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r300g: cleanup the emission of framebuffer state
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_inlines.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300, void* state)
39 {
40 struct r300_blend_state* blend = (struct r300_blend_state*)state;
41 struct pipe_framebuffer_state* fb =
42 (struct pipe_framebuffer_state*)r300->fb_state.state;
43 CS_LOCALS(r300);
44
45 BEGIN_CS(8);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
48 if (fb->nr_cbufs) {
49 OUT_CS(blend->blend_control);
50 OUT_CS(blend->alpha_blend_control);
51 OUT_CS(blend->color_channel_mask);
52 } else {
53 OUT_CS(0);
54 OUT_CS(0);
55 OUT_CS(0);
56 /* XXX also disable fastfill here once it's supported */
57 }
58 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
59 END_CS;
60 }
61
62 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
63 {
64 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
65 struct r300_screen* r300screen = r300_screen(r300->context.screen);
66 CS_LOCALS(r300);
67
68 if (r300screen->caps->is_r500) {
69 BEGIN_CS(3);
70 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
71 OUT_CS(bc->blend_color_red_alpha);
72 OUT_CS(bc->blend_color_green_blue);
73 END_CS;
74 } else {
75 BEGIN_CS(2);
76 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
77 END_CS;
78 }
79 }
80
81 void r300_emit_clip_state(struct r300_context* r300, void* state)
82 {
83 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
84 int i;
85 struct r300_screen* r300screen = r300_screen(r300->context.screen);
86 CS_LOCALS(r300);
87
88 if (r300screen->caps->has_tcl) {
89 BEGIN_CS(5 + (6 * 4));
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
91 (r300screen->caps->is_r500 ?
92 R500_PVS_UCP_START : R300_PVS_UCP_START));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
94 for (i = 0; i < 6; i++) {
95 OUT_CS_32F(clip->ucp[i][0]);
96 OUT_CS_32F(clip->ucp[i][1]);
97 OUT_CS_32F(clip->ucp[i][2]);
98 OUT_CS_32F(clip->ucp[i][3]);
99 }
100 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
101 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
102 END_CS;
103 } else {
104 BEGIN_CS(2);
105 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
106 END_CS;
107 }
108
109 }
110
111 void r300_emit_dsa_state(struct r300_context* r300, void* state)
112 {
113 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
114 struct r300_screen* r300screen = r300_screen(r300->context.screen);
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
118 CS_LOCALS(r300);
119
120 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
121 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
123
124 if (fb->zsbuf) {
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 } else {
128 OUT_CS(0);
129 OUT_CS(0);
130 }
131
132 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
133
134 if (r300screen->caps->is_r500) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
136 }
137 END_CS;
138 }
139
140 static const float * get_shader_constant(
141 struct r300_context * r300,
142 struct rc_constant * constant,
143 struct r300_constant_buffer * externals)
144 {
145 struct r300_viewport_state* viewport =
146 (struct r300_viewport_state*)r300->viewport_state.state;
147 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
148 struct pipe_texture *tex;
149
150 switch(constant->Type) {
151 case RC_CONSTANT_EXTERNAL:
152 return externals->constants[constant->u.External];
153
154 case RC_CONSTANT_IMMEDIATE:
155 return constant->u.Immediate;
156
157 case RC_CONSTANT_STATE:
158 switch (constant->u.State[0]) {
159 /* Factor for converting rectangle coords to
160 * normalized coords. Should only show up on non-r500. */
161 case RC_STATE_R300_TEXRECT_FACTOR:
162 tex = &r300->textures[constant->u.State[1]]->tex;
163 vec[0] = 1.0 / tex->width0;
164 vec[1] = 1.0 / tex->height0;
165 break;
166
167 /* Texture compare-fail value. Shouldn't ever show up, but if
168 * it does, we'll be ready. */
169 case RC_STATE_SHADOW_AMBIENT:
170 vec[3] = 0;
171 break;
172
173 case RC_STATE_R300_VIEWPORT_SCALE:
174 if (r300->tcl_bypass) {
175 vec[0] = 1;
176 vec[1] = 1;
177 vec[2] = 1;
178 } else {
179 vec[0] = viewport->xscale;
180 vec[1] = viewport->yscale;
181 vec[2] = viewport->zscale;
182 }
183 break;
184
185 case RC_STATE_R300_VIEWPORT_OFFSET:
186 if (!r300->tcl_bypass) {
187 vec[0] = viewport->xoffset;
188 vec[1] = viewport->yoffset;
189 vec[2] = viewport->zoffset;
190 }
191 break;
192
193 default:
194 debug_printf("r300: Implementation error: "
195 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
196 }
197 break;
198
199 default:
200 debug_printf("r300: Implementation error: "
201 "Unhandled constant type %d\n", constant->Type);
202 }
203
204 /* This should either be (0, 0, 0, 1), which should be a relatively safe
205 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
206 * state factors. */
207 return vec;
208 }
209
210 /* Convert a normal single-precision float into the 7.16 format
211 * used by the R300 fragment shader.
212 */
213 static uint32_t pack_float24(float f)
214 {
215 union {
216 float fl;
217 uint32_t u;
218 } u;
219 float mantissa;
220 int exponent;
221 uint32_t float24 = 0;
222
223 if (f == 0.0)
224 return 0;
225
226 u.fl = f;
227
228 mantissa = frexpf(f, &exponent);
229
230 /* Handle -ve */
231 if (mantissa < 0) {
232 float24 |= (1 << 23);
233 mantissa = mantissa * -1.0;
234 }
235 /* Handle exponent, bias of 63 */
236 exponent += 62;
237 float24 |= (exponent << 16);
238 /* Kill 7 LSB of mantissa */
239 float24 |= (u.u & 0x7FFFFF) >> 7;
240
241 return float24;
242 }
243
244 void r300_emit_fragment_program_code(struct r300_context* r300,
245 struct rX00_fragment_program_code* generic_code)
246 {
247 struct r300_fragment_program_code * code = &generic_code->code.r300;
248 int i;
249 CS_LOCALS(r300);
250
251 BEGIN_CS(15 +
252 code->alu.length * 4 +
253 (code->tex.length ? (1 + code->tex.length) : 0));
254
255 OUT_CS_REG(R300_US_CONFIG, code->config);
256 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
257 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
258
259 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
260 for(i = 0; i < 4; ++i)
261 OUT_CS(code->code_addr[i]);
262
263 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
264 for (i = 0; i < code->alu.length; i++)
265 OUT_CS(code->alu.inst[i].rgb_inst);
266
267 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
268 for (i = 0; i < code->alu.length; i++)
269 OUT_CS(code->alu.inst[i].rgb_addr);
270
271 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
272 for (i = 0; i < code->alu.length; i++)
273 OUT_CS(code->alu.inst[i].alpha_inst);
274
275 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
276 for (i = 0; i < code->alu.length; i++)
277 OUT_CS(code->alu.inst[i].alpha_addr);
278
279 if (code->tex.length) {
280 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
281 for(i = 0; i < code->tex.length; ++i)
282 OUT_CS(code->tex.inst[i]);
283 }
284
285 END_CS;
286 }
287
288 void r300_emit_fs_constant_buffer(struct r300_context* r300,
289 struct rc_constant_list* constants)
290 {
291 int i;
292 CS_LOCALS(r300);
293
294 if (constants->Count == 0)
295 return;
296
297 BEGIN_CS(constants->Count * 4 + 1);
298 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
299 for(i = 0; i < constants->Count; ++i) {
300 const float * data = get_shader_constant(r300,
301 &constants->Constants[i],
302 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
303 OUT_CS(pack_float24(data[0]));
304 OUT_CS(pack_float24(data[1]));
305 OUT_CS(pack_float24(data[2]));
306 OUT_CS(pack_float24(data[3]));
307 }
308 END_CS;
309 }
310
311 static void r300_emit_fragment_depth_config(struct r300_context* r300,
312 struct r300_fragment_shader* fs)
313 {
314 CS_LOCALS(r300);
315
316 BEGIN_CS(4);
317 if (r300_fragment_shader_writes_depth(fs)) {
318 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
319 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
320 } else {
321 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
322 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
323 }
324 END_CS;
325 }
326
327 void r500_emit_fragment_program_code(struct r300_context* r300,
328 struct rX00_fragment_program_code* generic_code)
329 {
330 struct r500_fragment_program_code * code = &generic_code->code.r500;
331 int i;
332 CS_LOCALS(r300);
333
334 BEGIN_CS(13 +
335 ((code->inst_end + 1) * 6));
336 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
337 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
338 OUT_CS_REG(R500_US_CODE_RANGE,
339 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
340 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
341 OUT_CS_REG(R500_US_CODE_ADDR,
342 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
343
344 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
345 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
346 for (i = 0; i <= code->inst_end; i++) {
347 OUT_CS(code->inst[i].inst0);
348 OUT_CS(code->inst[i].inst1);
349 OUT_CS(code->inst[i].inst2);
350 OUT_CS(code->inst[i].inst3);
351 OUT_CS(code->inst[i].inst4);
352 OUT_CS(code->inst[i].inst5);
353 }
354
355 END_CS;
356 }
357
358 void r500_emit_fs_constant_buffer(struct r300_context* r300,
359 struct rc_constant_list* constants)
360 {
361 int i;
362 CS_LOCALS(r300);
363
364 if (constants->Count == 0)
365 return;
366
367 BEGIN_CS(constants->Count * 4 + 3);
368 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
369 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
370 for (i = 0; i < constants->Count; i++) {
371 const float * data = get_shader_constant(r300,
372 &constants->Constants[i],
373 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
374 OUT_CS_32F(data[0]);
375 OUT_CS_32F(data[1]);
376 OUT_CS_32F(data[2]);
377 OUT_CS_32F(data[3]);
378 }
379 END_CS;
380 }
381
382 void r300_emit_fb_state(struct r300_context* r300, void* state)
383 {
384 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
385 struct r300_screen* r300screen = r300_screen(r300->context.screen);
386 struct r300_texture* tex;
387 struct pipe_surface* surf;
388 int i;
389 CS_LOCALS(r300);
390
391 BEGIN_CS((10 * fb->nr_cbufs) + (fb->zsbuf ? 10 : 0) + 6);
392
393 /* Flush and free renderbuffer caches. */
394 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
395 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
396 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
397 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
398 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
399 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
400
401 /* Set the number of colorbuffers. */
402 if (fb->nr_cbufs > 1) {
403 if (r300screen->caps->is_r500) {
404 OUT_CS_REG(R300_RB3D_CCTL,
405 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
406 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
407 } else {
408 OUT_CS_REG(R300_RB3D_CCTL,
409 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
410 }
411 } else {
412 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
413 }
414
415 /* Set up colorbuffers. */
416 for (i = 0; i < fb->nr_cbufs; i++) {
417 surf = fb->cbufs[i];
418 tex = (struct r300_texture*)surf->texture;
419 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
420
421 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
422 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
423
424 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
425 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
426 r300_translate_colorformat(tex->tex.format) |
427 R300_COLOR_TILE(tex->macrotile) |
428 R300_COLOR_MICROTILE(tex->microtile),
429 0, RADEON_GEM_DOMAIN_VRAM, 0);
430
431 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
432 r300_translate_out_fmt(surf->format));
433 }
434
435 /* Set up a zbuffer. */
436 if (fb->zsbuf) {
437 surf = fb->zsbuf;
438 tex = (struct r300_texture*)surf->texture;
439 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
440
441 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
442 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
443
444 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
445
446 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
447 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
448 R300_DEPTHMACROTILE(tex->macrotile) |
449 R300_DEPTHMICROTILE(tex->microtile),
450 0, RADEON_GEM_DOMAIN_VRAM, 0);
451 }
452
453 END_CS;
454 }
455
456 static void r300_emit_query_start(struct r300_context *r300)
457 {
458 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
459 struct r300_query *query = r300->query_current;
460 CS_LOCALS(r300);
461
462 if (!query)
463 return;
464
465 BEGIN_CS(4);
466 if (caps->family == CHIP_FAMILY_RV530) {
467 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
468 } else {
469 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
470 }
471 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
472 END_CS;
473 query->begin_emitted = TRUE;
474 }
475
476
477 static void r300_emit_query_finish(struct r300_context *r300,
478 struct r300_query *query)
479 {
480 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
481 CS_LOCALS(r300);
482
483 assert(caps->num_frag_pipes);
484
485 BEGIN_CS(6 * caps->num_frag_pipes + 2);
486 /* I'm not so sure I like this switch, but it's hard to be elegant
487 * when there's so many special cases...
488 *
489 * So here's the basic idea. For each pipe, enable writes to it only,
490 * then put out the relocation for ZPASS_ADDR, taking into account a
491 * 4-byte offset for each pipe. RV380 and older are special; they have
492 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
493 * so there's a chipset cap for that. */
494 switch (caps->num_frag_pipes) {
495 case 4:
496 /* pipe 3 only */
497 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
498 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
499 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
500 0, RADEON_GEM_DOMAIN_GTT, 0);
501 case 3:
502 /* pipe 2 only */
503 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
504 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
505 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
506 0, RADEON_GEM_DOMAIN_GTT, 0);
507 case 2:
508 /* pipe 1 only */
509 /* As mentioned above, accomodate RV380 and older. */
510 OUT_CS_REG(R300_SU_REG_DEST,
511 1 << (caps->high_second_pipe ? 3 : 1));
512 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
513 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
514 0, RADEON_GEM_DOMAIN_GTT, 0);
515 case 1:
516 /* pipe 0 only */
517 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
518 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
519 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
520 0, RADEON_GEM_DOMAIN_GTT, 0);
521 break;
522 default:
523 debug_printf("r300: Implementation error: Chipset reports %d"
524 " pixel pipes!\n", caps->num_frag_pipes);
525 assert(0);
526 }
527
528 /* And, finally, reset it to normal... */
529 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
530 END_CS;
531 }
532
533 static void rv530_emit_query_single(struct r300_context *r300,
534 struct r300_query *query)
535 {
536 CS_LOCALS(r300);
537
538 BEGIN_CS(8);
539 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
540 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
541 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
542 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
543 END_CS;
544 }
545
546 static void rv530_emit_query_double(struct r300_context *r300,
547 struct r300_query *query)
548 {
549 CS_LOCALS(r300);
550
551 BEGIN_CS(14);
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
553 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
554 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
555 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
556 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
557 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
558 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
559 END_CS;
560 }
561
562 void r300_emit_query_end(struct r300_context* r300)
563 {
564 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
565 struct r300_query *query = r300->query_current;
566
567 if (!query)
568 return;
569
570 if (query->begin_emitted == FALSE)
571 return;
572
573 if (caps->family == CHIP_FAMILY_RV530) {
574 if (caps->num_z_pipes == 2)
575 rv530_emit_query_double(r300, query);
576 else
577 rv530_emit_query_single(r300, query);
578 } else
579 r300_emit_query_finish(r300, query);
580 }
581
582 void r300_emit_rs_state(struct r300_context* r300, void* state)
583 {
584 struct r300_rs_state* rs = (struct r300_rs_state*)state;
585 float scale, offset;
586 CS_LOCALS(r300);
587
588 BEGIN_CS(18 + (rs->polygon_offset_enable ? 5 : 0));
589 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
590
591 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
592
593 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
594 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
595 OUT_CS(rs->point_minmax);
596 OUT_CS(rs->line_control);
597
598 if (rs->polygon_offset_enable) {
599 scale = rs->depth_scale * 12;
600 offset = rs->depth_offset;
601
602 switch (r300->zbuffer_bpp) {
603 case 16:
604 offset *= 4;
605 break;
606 case 24:
607 offset *= 2;
608 break;
609 }
610
611 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
612 OUT_CS_32F(scale);
613 OUT_CS_32F(offset);
614 OUT_CS_32F(scale);
615 OUT_CS_32F(offset);
616 }
617
618 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
619 OUT_CS(rs->polygon_offset_enable);
620 OUT_CS(rs->cull_mode);
621 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
622 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
623 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
624 END_CS;
625 }
626
627 void r300_emit_rs_block_state(struct r300_context* r300, void* state)
628 {
629 struct r300_rs_block* rs = (struct r300_rs_block*)state;
630 unsigned i;
631 struct r300_screen* r300screen = r300_screen(r300->context.screen);
632 CS_LOCALS(r300);
633
634 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
635
636 BEGIN_CS(21);
637 if (r300screen->caps->is_r500) {
638 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
639 } else {
640 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
641 }
642 for (i = 0; i < 8; i++) {
643 OUT_CS(rs->ip[i]);
644 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
645 }
646
647 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
648 OUT_CS(rs->count);
649 OUT_CS(rs->inst_count);
650
651 if (r300screen->caps->is_r500) {
652 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
653 } else {
654 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
655 }
656 for (i = 0; i < 8; i++) {
657 OUT_CS(rs->inst[i]);
658 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
659 }
660
661 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
662 rs->count, rs->inst_count);
663
664 END_CS;
665 }
666
667 void r300_emit_scissor_state(struct r300_context* r300, void* state)
668 {
669 unsigned minx, miny, maxx, maxy;
670 uint32_t top_left, bottom_right;
671 struct r300_screen* r300screen = r300_screen(r300->context.screen);
672 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
673 struct pipe_framebuffer_state* fb =
674 (struct pipe_framebuffer_state*)r300->fb_state.state;
675 CS_LOCALS(r300);
676
677 minx = miny = 0;
678 maxx = fb->width;
679 maxy = fb->height;
680
681 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
682 minx = MAX2(minx, scissor->minx);
683 miny = MAX2(miny, scissor->miny);
684 maxx = MIN2(maxx, scissor->maxx);
685 maxy = MIN2(maxy, scissor->maxy);
686 }
687
688 /* Special case for zero-area scissor.
689 *
690 * We can't allow the variables maxx and maxy to be zero because they are
691 * subtracted from later in the code, which would cause emitting ~0 and
692 * making the kernel checker angry.
693 *
694 * Let's consider we change maxx and maxy to 1, which is effectively
695 * a one-pixel area. We must then change minx and miny to a number which is
696 * greater than 1 to get the zero area back. */
697 if (!maxx || !maxy) {
698 minx = 2;
699 miny = 2;
700 maxx = 1;
701 maxy = 1;
702 }
703
704 if (r300screen->caps->is_r500) {
705 top_left =
706 (minx << R300_SCISSORS_X_SHIFT) |
707 (miny << R300_SCISSORS_Y_SHIFT);
708 bottom_right =
709 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
710 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
711 } else {
712 /* Offset of 1440 in non-R500 chipsets. */
713 top_left =
714 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
715 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
716 bottom_right =
717 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
718 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
719 }
720
721 BEGIN_CS(3);
722 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
723 OUT_CS(top_left);
724 OUT_CS(bottom_right);
725 END_CS;
726 }
727
728 void r300_emit_texture(struct r300_context* r300,
729 struct r300_sampler_state* sampler,
730 struct r300_texture* tex,
731 unsigned offset)
732 {
733 uint32_t filter0 = sampler->filter0;
734 uint32_t format0 = tex->state.format0;
735 unsigned min_level, max_level;
736 CS_LOCALS(r300);
737
738 /* to emulate 1D textures through 2D ones correctly */
739 if (tex->tex.target == PIPE_TEXTURE_1D) {
740 filter0 &= ~R300_TX_WRAP_T_MASK;
741 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
742 }
743
744 if (tex->is_npot) {
745 /* NPOT textures don't support mip filter, unfortunately.
746 * This prevents incorrect rendering. */
747 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
748 } else {
749 /* determine min/max levels */
750 /* the MAX_MIP level is the largest (finest) one */
751 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
752 min_level = MIN2(sampler->min_lod, max_level);
753 format0 |= R300_TX_NUM_LEVELS(max_level);
754 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
755 }
756
757 BEGIN_CS(16);
758 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
759 (offset << 28));
760 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
761 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
762
763 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
764 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
765 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
766 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
767 OUT_CS_RELOC(tex->buffer,
768 R300_TXO_MACRO_TILE(tex->macrotile) |
769 R300_TXO_MICRO_TILE(tex->microtile),
770 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
771 END_CS;
772 }
773
774 void r300_emit_aos(struct r300_context* r300, unsigned offset)
775 {
776 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
777 struct pipe_vertex_element *velem = r300->vertex_element;
778 int i;
779 unsigned size1, size2, aos_count = r300->vertex_element_count;
780 unsigned packet_size = (aos_count * 3 + 1) / 2;
781 CS_LOCALS(r300);
782
783 BEGIN_CS(2 + packet_size + aos_count * 2);
784 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
785 OUT_CS(aos_count);
786
787 for (i = 0; i < aos_count - 1; i += 2) {
788 vb1 = &vbuf[velem[i].vertex_buffer_index];
789 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
790 size1 = util_format_get_blocksize(velem[i].src_format);
791 size2 = util_format_get_blocksize(velem[i+1].src_format);
792
793 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
794 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
795 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
796 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
797 }
798
799 if (aos_count & 1) {
800 vb1 = &vbuf[velem[i].vertex_buffer_index];
801 size1 = util_format_get_blocksize(velem[i].src_format);
802
803 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
804 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
805 }
806
807 for (i = 0; i < aos_count; i++) {
808 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
809 RADEON_GEM_DOMAIN_GTT, 0, 0);
810 }
811 END_CS;
812 }
813
814 void r300_emit_vertex_format_state(struct r300_context* r300, void* state)
815 {
816 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
817 unsigned i;
818 CS_LOCALS(r300);
819
820 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
821
822 BEGIN_CS(26);
823 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
824
825 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
826 OUT_CS(vertex_info->vinfo.hwfmt[0]);
827 OUT_CS(vertex_info->vinfo.hwfmt[1]);
828 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
829 OUT_CS(vertex_info->vinfo.hwfmt[2]);
830 OUT_CS(vertex_info->vinfo.hwfmt[3]);
831 for (i = 0; i < 4; i++) {
832 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
833 vertex_info->vinfo.hwfmt[i]);
834 }
835
836 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
837 for (i = 0; i < 8; i++) {
838 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
839 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
840 vertex_info->vap_prog_stream_cntl[i]);
841 }
842 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
843 for (i = 0; i < 8; i++) {
844 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
845 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
846 vertex_info->vap_prog_stream_cntl_ext[i]);
847 }
848 END_CS;
849 }
850
851
852 void r300_emit_vertex_program_code(struct r300_context* r300,
853 struct r300_vertex_program_code* code)
854 {
855 int i;
856 struct r300_screen* r300screen = r300_screen(r300->context.screen);
857 unsigned instruction_count = code->length / 4;
858
859 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
860 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
861 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
862 int temp_count = MAX2(code->num_temporaries, 1);
863 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
864 vtx_mem_size / output_count, 10);
865 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
866
867 CS_LOCALS(r300);
868
869 if (!r300screen->caps->has_tcl) {
870 debug_printf("r300: Implementation error: emit_vertex_shader called,"
871 " but has_tcl is FALSE!\n");
872 return;
873 }
874
875 BEGIN_CS(9 + code->length);
876 /* R300_VAP_PVS_CODE_CNTL_0
877 * R300_VAP_PVS_CONST_CNTL
878 * R300_VAP_PVS_CODE_CNTL_1
879 * See the r5xx docs for instructions on how to use these. */
880 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
881 OUT_CS(R300_PVS_FIRST_INST(0) |
882 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
883 R300_PVS_LAST_INST(instruction_count - 1));
884 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
885 OUT_CS(instruction_count - 1);
886
887 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
888 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
889 for (i = 0; i < code->length; i++)
890 OUT_CS(code->body.d[i]);
891
892 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
893 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
894 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
895 R300_PVS_VF_MAX_VTX_NUM(12) |
896 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
897 END_CS;
898 }
899
900 void r300_emit_vertex_shader(struct r300_context* r300,
901 struct r300_vertex_shader* vs)
902 {
903 r300_emit_vertex_program_code(r300, &vs->code);
904 }
905
906 void r300_emit_vs_constant_buffer(struct r300_context* r300,
907 struct rc_constant_list* constants)
908 {
909 int i;
910 struct r300_screen* r300screen = r300_screen(r300->context.screen);
911 CS_LOCALS(r300);
912
913 if (!r300screen->caps->has_tcl) {
914 debug_printf("r300: Implementation error: emit_vertex_shader called,"
915 " but has_tcl is FALSE!\n");
916 return;
917 }
918
919 if (constants->Count == 0)
920 return;
921
922 BEGIN_CS(constants->Count * 4 + 3);
923 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
924 (r300screen->caps->is_r500 ?
925 R500_PVS_CONST_START : R300_PVS_CONST_START));
926 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
927 for (i = 0; i < constants->Count; i++) {
928 const float * data = get_shader_constant(r300,
929 &constants->Constants[i],
930 &r300->shader_constants[PIPE_SHADER_VERTEX]);
931 OUT_CS_32F(data[0]);
932 OUT_CS_32F(data[1]);
933 OUT_CS_32F(data[2]);
934 OUT_CS_32F(data[3]);
935 }
936 END_CS;
937 }
938
939 void r300_emit_viewport_state(struct r300_context* r300, void* state)
940 {
941 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
942 CS_LOCALS(r300);
943
944 if (r300->tcl_bypass) {
945 BEGIN_CS(2);
946 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
947 END_CS;
948 } else {
949 BEGIN_CS(9);
950 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
951 OUT_CS_32F(viewport->xscale);
952 OUT_CS_32F(viewport->xoffset);
953 OUT_CS_32F(viewport->yscale);
954 OUT_CS_32F(viewport->yoffset);
955 OUT_CS_32F(viewport->zscale);
956 OUT_CS_32F(viewport->zoffset);
957 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
958 END_CS;
959 }
960 }
961
962 void r300_emit_texture_count(struct r300_context* r300)
963 {
964 uint32_t tx_enable = 0;
965 int i;
966 CS_LOCALS(r300);
967
968 /* Notice that texture_count and sampler_count are just sizes
969 * of the respective arrays. We still have to check for the individual
970 * elements. */
971 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
972 if (r300->textures[i]) {
973 tx_enable |= 1 << i;
974 }
975 }
976
977 BEGIN_CS(2);
978 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
979 END_CS;
980
981 }
982
983 void r300_emit_ztop_state(struct r300_context* r300, void* state)
984 {
985 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
986 CS_LOCALS(r300);
987
988 BEGIN_CS(2);
989 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
990 END_CS;
991 }
992
993 void r300_flush_textures(struct r300_context* r300)
994 {
995 CS_LOCALS(r300);
996
997 BEGIN_CS(2);
998 OUT_CS_REG(R300_TX_INVALTAGS, 0);
999 END_CS;
1000 }
1001
1002 static void r300_flush_pvs(struct r300_context* r300)
1003 {
1004 CS_LOCALS(r300);
1005
1006 BEGIN_CS(2);
1007 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1008 END_CS;
1009 }
1010
1011 void r300_emit_buffer_validate(struct r300_context *r300)
1012 {
1013 struct pipe_framebuffer_state* fb =
1014 (struct pipe_framebuffer_state*)r300->fb_state.state;
1015 struct r300_texture* tex;
1016 unsigned i;
1017 boolean invalid = FALSE;
1018
1019 /* Clean out BOs. */
1020 r300->winsys->reset_bos(r300->winsys);
1021
1022 validate:
1023 /* Color buffers... */
1024 for (i = 0; i < fb->nr_cbufs; i++) {
1025 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1026 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1027 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1028 0, RADEON_GEM_DOMAIN_VRAM)) {
1029 r300->context.flush(&r300->context, 0, NULL);
1030 goto validate;
1031 }
1032 }
1033 /* ...depth buffer... */
1034 if (fb->zsbuf) {
1035 tex = (struct r300_texture*)fb->zsbuf->texture;
1036 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1037 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1038 0, RADEON_GEM_DOMAIN_VRAM)) {
1039 r300->context.flush(&r300->context, 0, NULL);
1040 goto validate;
1041 }
1042 }
1043 /* ...textures... */
1044 for (i = 0; i < r300->texture_count; i++) {
1045 tex = r300->textures[i];
1046 if (!tex)
1047 continue;
1048 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1049 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1050 r300->context.flush(&r300->context, 0, NULL);
1051 goto validate;
1052 }
1053 }
1054 /* ...occlusion query buffer... */
1055 if (r300->dirty_state & R300_NEW_QUERY) {
1056 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1057 0, RADEON_GEM_DOMAIN_GTT)) {
1058 r300->context.flush(&r300->context, 0, NULL);
1059 goto validate;
1060 }
1061 }
1062 /* ...and vertex buffer. */
1063 if (r300->vbo) {
1064 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1065 RADEON_GEM_DOMAIN_GTT, 0)) {
1066 r300->context.flush(&r300->context, 0, NULL);
1067 goto validate;
1068 }
1069 } else {
1070 /* debug_printf("No VBO while emitting dirty state!\n"); */
1071 }
1072 if (!r300->winsys->validate(r300->winsys)) {
1073 r300->context.flush(&r300->context, 0, NULL);
1074 if (invalid) {
1075 /* Well, hell. */
1076 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1077 exit(1);
1078 }
1079 invalid = TRUE;
1080 goto validate;
1081 }
1082 }
1083
1084 /* Emit all dirty state. */
1085 void r300_emit_dirty_state(struct r300_context* r300)
1086 {
1087 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1088 struct r300_atom* atom;
1089 unsigned i, dwords = 1024;
1090 int dirty_tex = 0;
1091
1092 /* Check the required number of dwords against the space remaining in the
1093 * current CS object. If we need more, then flush. */
1094
1095 foreach(atom, &r300->atom_list) {
1096 if (atom->dirty || atom->always_dirty) {
1097 dwords += atom->size;
1098 }
1099 }
1100
1101 /* Make sure we have at least 2*1024 spare dwords. */
1102 /* XXX It would be nice to know the number of dwords we really need to
1103 * XXX emit. */
1104 while (!r300->winsys->check_cs(r300->winsys, dwords)) {
1105 r300->context.flush(&r300->context, 0, NULL);
1106 }
1107
1108 if (r300->dirty_state & R300_NEW_QUERY) {
1109 r300_emit_query_start(r300);
1110 r300->dirty_state &= ~R300_NEW_QUERY;
1111 }
1112
1113 foreach(atom, &r300->atom_list) {
1114 if (atom->dirty || atom->always_dirty) {
1115 atom->emit(r300, atom->state);
1116 atom->dirty = FALSE;
1117 }
1118 }
1119
1120 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1121 r300_emit_fragment_depth_config(r300, r300->fs);
1122 if (r300screen->caps->is_r500) {
1123 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1124 } else {
1125 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1126 }
1127 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1128 }
1129
1130 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1131 if (r300screen->caps->is_r500) {
1132 r500_emit_fs_constant_buffer(r300,
1133 &r300->fs->shader->code.constants);
1134 } else {
1135 r300_emit_fs_constant_buffer(r300,
1136 &r300->fs->shader->code.constants);
1137 }
1138 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1139 }
1140
1141 /* Samplers and textures are tracked separately but emitted together. */
1142 if (r300->dirty_state &
1143 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1144 r300_emit_texture_count(r300);
1145
1146 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1147 if (r300->dirty_state &
1148 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1149 if (r300->textures[i])
1150 r300_emit_texture(r300,
1151 r300->sampler_states[i],
1152 r300->textures[i],
1153 i);
1154 r300->dirty_state &=
1155 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1156 dirty_tex++;
1157 }
1158 }
1159 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1160 }
1161
1162 if (dirty_tex) {
1163 r300_flush_textures(r300);
1164 }
1165
1166 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1167 r300_flush_pvs(r300);
1168 }
1169
1170 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1171 r300_emit_vertex_shader(r300, r300->vs);
1172 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1173 }
1174
1175 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1176 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1177 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1178 }
1179
1180 /* XXX
1181 assert(r300->dirty_state == 0);
1182 */
1183
1184 /* Finally, emit the VBO. */
1185 /* r300_emit_vertex_buffer(r300); */
1186
1187 r300->dirty_hw++;
1188 }