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Merge branch '7.8'
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 CS_LOCALS(r300);
68
69 if (r300->screen->caps.is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 int i;
87 CS_LOCALS(r300);
88
89 if (r300->screen->caps.has_tcl) {
90 BEGIN_CS(size);
91 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
92 (r300->screen->caps.is_r500 ?
93 R500_PVS_UCP_START : R300_PVS_UCP_START));
94 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
95 for (i = 0; i < 6; i++) {
96 OUT_CS_32F(clip->ucp[i][0]);
97 OUT_CS_32F(clip->ucp[i][1]);
98 OUT_CS_32F(clip->ucp[i][2]);
99 OUT_CS_32F(clip->ucp[i][3]);
100 }
101 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
102 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
103 END_CS;
104 } else {
105 BEGIN_CS(size);
106 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
107 END_CS;
108 }
109
110 }
111
112 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
113 {
114 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
118 CS_LOCALS(r300);
119
120 BEGIN_CS(size);
121 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
123
124 if (fb->zsbuf) {
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 } else {
128 OUT_CS(0);
129 OUT_CS(0);
130 }
131
132 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
133
134 if (r300->screen->caps.is_r500) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
136 }
137 END_CS;
138 }
139
140 static const float * get_rc_constant_state(
141 struct r300_context * r300,
142 struct rc_constant * constant)
143 {
144 struct r300_viewport_state* viewport = r300->viewport_state.state;
145 struct r300_textures_state* texstate = r300->textures_state.state;
146 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
147 struct pipe_resource *tex;
148
149 assert(constant->Type == RC_CONSTANT_STATE);
150
151 switch (constant->u.State[0]) {
152 /* Factor for converting rectangle coords to
153 * normalized coords. Should only show up on non-r500. */
154 case RC_STATE_R300_TEXRECT_FACTOR:
155 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
156 vec[0] = 1.0 / tex->width0;
157 vec[1] = 1.0 / tex->height0;
158 break;
159
160 case RC_STATE_R300_VIEWPORT_SCALE:
161 vec[0] = viewport->xscale;
162 vec[1] = viewport->yscale;
163 vec[2] = viewport->zscale;
164 break;
165
166 case RC_STATE_R300_VIEWPORT_OFFSET:
167 vec[0] = viewport->xoffset;
168 vec[1] = viewport->yoffset;
169 vec[2] = viewport->zoffset;
170 break;
171
172 default:
173 fprintf(stderr, "r300: Implementation error: "
174 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
175 }
176
177 /* This should either be (0, 0, 0, 1), which should be a relatively safe
178 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
179 * state factors. */
180 return vec;
181 }
182
183 /* Convert a normal single-precision float into the 7.16 format
184 * used by the R300 fragment shader.
185 */
186 static uint32_t pack_float24(float f)
187 {
188 union {
189 float fl;
190 uint32_t u;
191 } u;
192 float mantissa;
193 int exponent;
194 uint32_t float24 = 0;
195
196 if (f == 0.0)
197 return 0;
198
199 u.fl = f;
200
201 mantissa = frexpf(f, &exponent);
202
203 /* Handle -ve */
204 if (mantissa < 0) {
205 float24 |= (1 << 23);
206 mantissa = mantissa * -1.0;
207 }
208 /* Handle exponent, bias of 63 */
209 exponent += 62;
210 float24 |= (exponent << 16);
211 /* Kill 7 LSB of mantissa */
212 float24 |= (u.u & 0x7FFFFF) >> 7;
213
214 return float24;
215 }
216
217 unsigned r300_get_fs_atom_size(struct r300_context *r300)
218 {
219 struct r300_fragment_shader *fs = r300_fs(r300);
220 unsigned imm_count = fs->shader->immediates_count;
221 struct r300_fragment_program_code *code = &fs->shader->code.code.r300;
222
223 return 19 +
224 code->alu.length * 4 +
225 (code->tex.length ? (1 + code->tex.length) : 0) +
226 (imm_count ? imm_count * 5 : 0);
227 }
228
229 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
230 {
231 struct r300_fragment_shader *fs = r300_fs(r300);
232 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
233 struct r300_fragment_program_code * code = &generic_code->code.r300;
234 unsigned i;
235 unsigned imm_count = fs->shader->immediates_count;
236 unsigned imm_first = fs->shader->externals_count;
237 unsigned imm_end = generic_code->constants.Count;
238 struct rc_constant *constants = generic_code->constants.Constants;
239 CS_LOCALS(r300);
240
241 BEGIN_CS(size);
242 OUT_CS_REG(R300_US_CONFIG, code->config);
243 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
244 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
245
246 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
247 for(i = 0; i < 4; ++i)
248 OUT_CS(code->code_addr[i]);
249
250 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
251 for (i = 0; i < code->alu.length; i++)
252 OUT_CS(code->alu.inst[i].rgb_inst);
253
254 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
255 for (i = 0; i < code->alu.length; i++)
256 OUT_CS(code->alu.inst[i].rgb_addr);
257
258 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
259 for (i = 0; i < code->alu.length; i++)
260 OUT_CS(code->alu.inst[i].alpha_inst);
261
262 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
263 for (i = 0; i < code->alu.length; i++)
264 OUT_CS(code->alu.inst[i].alpha_addr);
265
266 if (code->tex.length) {
267 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
268 for(i = 0; i < code->tex.length; ++i)
269 OUT_CS(code->tex.inst[i]);
270 }
271
272 /* Emit immediates. */
273 if (imm_count) {
274 for(i = imm_first; i < imm_end; ++i) {
275 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
276 const float *data = constants[i].u.Immediate;
277
278 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
279 OUT_CS(pack_float24(data[0]));
280 OUT_CS(pack_float24(data[1]));
281 OUT_CS(pack_float24(data[2]));
282 OUT_CS(pack_float24(data[3]));
283 }
284 }
285 }
286
287 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
288 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
289 END_CS;
290 }
291
292 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
293 {
294 struct r300_fragment_shader *fs = r300_fs(r300);
295 struct rc_constant_list *constants = &fs->shader->code.constants;
296 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
297 unsigned i, count = fs->shader->externals_count;
298 CS_LOCALS(r300);
299
300 if (count == 0)
301 return;
302
303 BEGIN_CS(size);
304 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
305 for(i = 0; i < count; ++i) {
306 const float *data;
307 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
308 data = buf->constants[i];
309 OUT_CS(pack_float24(data[0]));
310 OUT_CS(pack_float24(data[1]));
311 OUT_CS(pack_float24(data[2]));
312 OUT_CS(pack_float24(data[3]));
313 }
314 END_CS;
315 }
316
317 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
318 {
319 struct r300_fragment_shader *fs = r300_fs(r300);
320 struct rc_constant_list *constants = &fs->shader->code.constants;
321 unsigned i;
322 unsigned count = fs->shader->rc_state_count;
323 unsigned first = fs->shader->externals_count;
324 unsigned end = constants->Count;
325 CS_LOCALS(r300);
326
327 if (count == 0)
328 return;
329
330 BEGIN_CS(size);
331 for(i = first; i < end; ++i) {
332 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
333 const float *data =
334 get_rc_constant_state(r300, &constants->Constants[i]);
335
336 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
337 OUT_CS(pack_float24(data[0]));
338 OUT_CS(pack_float24(data[1]));
339 OUT_CS(pack_float24(data[2]));
340 OUT_CS(pack_float24(data[3]));
341 }
342 }
343 END_CS;
344 }
345
346 unsigned r500_get_fs_atom_size(struct r300_context *r300)
347 {
348 struct r300_fragment_shader *fs = r300_fs(r300);
349 unsigned imm_count = fs->shader->immediates_count;
350 struct r500_fragment_program_code *code = &fs->shader->code.code.r500;
351
352 return 17 +
353 ((code->inst_end + 1) * 6) +
354 (imm_count ? imm_count * 7 : 0);
355 }
356
357 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
358 {
359 struct r300_fragment_shader *fs = r300_fs(r300);
360 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
361 struct r500_fragment_program_code * code = &generic_code->code.r500;
362 unsigned i;
363 unsigned imm_count = fs->shader->immediates_count;
364 unsigned imm_first = fs->shader->externals_count;
365 unsigned imm_end = generic_code->constants.Count;
366 struct rc_constant *constants = generic_code->constants.Constants;
367 CS_LOCALS(r300);
368
369 BEGIN_CS(size);
370 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
371 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
372 OUT_CS_REG(R500_US_CODE_RANGE,
373 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
374 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
375 OUT_CS_REG(R500_US_CODE_ADDR,
376 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
377
378 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
379 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
380 for (i = 0; i <= code->inst_end; i++) {
381 OUT_CS(code->inst[i].inst0);
382 OUT_CS(code->inst[i].inst1);
383 OUT_CS(code->inst[i].inst2);
384 OUT_CS(code->inst[i].inst3);
385 OUT_CS(code->inst[i].inst4);
386 OUT_CS(code->inst[i].inst5);
387 }
388
389 /* Emit immediates. */
390 if (imm_count) {
391 for(i = imm_first; i < imm_end; ++i) {
392 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
393 const float *data = constants[i].u.Immediate;
394
395 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
396 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
397 (i & R500_GA_US_VECTOR_INDEX_MASK));
398 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
399 OUT_CS_32F(data[0]);
400 OUT_CS_32F(data[1]);
401 OUT_CS_32F(data[2]);
402 OUT_CS_32F(data[3]);
403 }
404 }
405 }
406
407 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
408 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
409 END_CS;
410 }
411
412 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
413 {
414 struct r300_fragment_shader *fs = r300_fs(r300);
415 struct rc_constant_list *constants = &fs->shader->code.constants;
416 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
417 unsigned i, count = fs->shader->externals_count;
418 CS_LOCALS(r300);
419
420 if (count == 0)
421 return;
422
423 BEGIN_CS(size);
424 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
425 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
426 for(i = 0; i < count; ++i) {
427 const float *data;
428 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
429 data = buf->constants[i];
430
431 OUT_CS_32F(data[0]);
432 OUT_CS_32F(data[1]);
433 OUT_CS_32F(data[2]);
434 OUT_CS_32F(data[3]);
435 }
436 END_CS;
437 }
438
439 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
440 {
441 struct r300_fragment_shader *fs = r300_fs(r300);
442 struct rc_constant_list *constants = &fs->shader->code.constants;
443 unsigned i;
444 unsigned count = fs->shader->rc_state_count;
445 unsigned first = fs->shader->externals_count;
446 unsigned end = constants->Count;
447 CS_LOCALS(r300);
448
449 if (count == 0)
450 return;
451
452 BEGIN_CS(size);
453 for(i = first; i < end; ++i) {
454 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
455 const float *data =
456 get_rc_constant_state(r300, &constants->Constants[i]);
457
458 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
459 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
460 (i & R500_GA_US_VECTOR_INDEX_MASK));
461 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
462 OUT_CS_32F(data[0]);
463 OUT_CS_32F(data[1]);
464 OUT_CS_32F(data[2]);
465 OUT_CS_32F(data[3]);
466 }
467 }
468 END_CS;
469 }
470
471 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
472 {
473 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
474 struct r300_texture* tex;
475 struct pipe_surface* surf;
476 int i;
477 CS_LOCALS(r300);
478
479 BEGIN_CS(size);
480
481 /* Flush and free renderbuffer caches. */
482 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
483 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
484 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
485 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
486 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
487 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
488
489 /* Set the number of colorbuffers. */
490 if (fb->nr_cbufs > 1) {
491 if (r300->screen->caps.is_r500) {
492 OUT_CS_REG(R300_RB3D_CCTL,
493 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
494 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
495 } else {
496 OUT_CS_REG(R300_RB3D_CCTL,
497 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
498 }
499 } else {
500 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
501 }
502
503 /* Set up colorbuffers. */
504 for (i = 0; i < fb->nr_cbufs; i++) {
505 surf = fb->cbufs[i];
506 tex = r300_texture(surf->texture);
507 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
508
509 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
510 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
511
512 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
513 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
514 0, RADEON_GEM_DOMAIN_VRAM, 0);
515
516 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
517 }
518 for (; i < 4; i++) {
519 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
520 }
521
522 /* Set up a zbuffer. */
523 if (fb->zsbuf) {
524 surf = fb->zsbuf;
525 tex = r300_texture(surf->texture);
526 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
527
528 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
529 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
530
531 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
532
533 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
534 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
535 0, RADEON_GEM_DOMAIN_VRAM, 0);
536 }
537
538 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
539 if (r300->screen->caps.is_r500) {
540 OUT_CS(0);
541 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
542 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
543 } else {
544 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
545 (1440 << R300_SCISSORS_Y_SHIFT));
546 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
547 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
548 }
549 OUT_CS_REG(R300_GA_POINT_MINMAX,
550 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
551 END_CS;
552 }
553
554 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
555 {
556 struct r300_query *query = r300->query_current;
557 CS_LOCALS(r300);
558
559 if (!query)
560 return;
561
562 BEGIN_CS(size);
563 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
564 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
565 } else {
566 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
567 }
568 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
569 END_CS;
570 query->begin_emitted = TRUE;
571 }
572
573
574 static void r300_emit_query_finish(struct r300_context *r300,
575 struct r300_query *query)
576 {
577 struct r300_capabilities* caps = &r300->screen->caps;
578 CS_LOCALS(r300);
579
580 assert(caps->num_frag_pipes);
581
582 BEGIN_CS(6 * caps->num_frag_pipes + 2);
583 /* I'm not so sure I like this switch, but it's hard to be elegant
584 * when there's so many special cases...
585 *
586 * So here's the basic idea. For each pipe, enable writes to it only,
587 * then put out the relocation for ZPASS_ADDR, taking into account a
588 * 4-byte offset for each pipe. RV380 and older are special; they have
589 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
590 * so there's a chipset cap for that. */
591 switch (caps->num_frag_pipes) {
592 case 4:
593 /* pipe 3 only */
594 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
595 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
596 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
597 0, RADEON_GEM_DOMAIN_GTT, 0);
598 case 3:
599 /* pipe 2 only */
600 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
601 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
602 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
603 0, RADEON_GEM_DOMAIN_GTT, 0);
604 case 2:
605 /* pipe 1 only */
606 /* As mentioned above, accomodate RV380 and older. */
607 OUT_CS_REG(R300_SU_REG_DEST,
608 1 << (caps->high_second_pipe ? 3 : 1));
609 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
610 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
611 0, RADEON_GEM_DOMAIN_GTT, 0);
612 case 1:
613 /* pipe 0 only */
614 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
615 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
616 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
617 0, RADEON_GEM_DOMAIN_GTT, 0);
618 break;
619 default:
620 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
621 " pixel pipes!\n", caps->num_frag_pipes);
622 abort();
623 }
624
625 /* And, finally, reset it to normal... */
626 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
627 END_CS;
628 }
629
630 static void rv530_emit_query_single(struct r300_context *r300,
631 struct r300_query *query)
632 {
633 CS_LOCALS(r300);
634
635 BEGIN_CS(8);
636 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
637 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
638 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
639 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
640 END_CS;
641 }
642
643 static void rv530_emit_query_double(struct r300_context *r300,
644 struct r300_query *query)
645 {
646 CS_LOCALS(r300);
647
648 BEGIN_CS(14);
649 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
650 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
651 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
652 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
653 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
654 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
655 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
656 END_CS;
657 }
658
659 void r300_emit_query_end(struct r300_context* r300)
660 {
661 struct r300_capabilities *caps = &r300->screen->caps;
662 struct r300_query *query = r300->query_current;
663
664 if (!query)
665 return;
666
667 if (query->begin_emitted == FALSE)
668 return;
669
670 if (caps->family == CHIP_FAMILY_RV530) {
671 if (caps->num_z_pipes == 2)
672 rv530_emit_query_double(r300, query);
673 else
674 rv530_emit_query_single(r300, query);
675 } else
676 r300_emit_query_finish(r300, query);
677 }
678
679 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
680 {
681 struct r300_rs_state* rs = (struct r300_rs_state*)state;
682 float scale, offset;
683 CS_LOCALS(r300);
684
685 BEGIN_CS(size);
686 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
687
688 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
689
690 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
691 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
692
693 if (rs->polygon_offset_enable) {
694 scale = rs->depth_scale * 12;
695 offset = rs->depth_offset;
696
697 switch (r300->zbuffer_bpp) {
698 case 16:
699 offset *= 4;
700 break;
701 case 24:
702 offset *= 2;
703 break;
704 }
705
706 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
707 OUT_CS_32F(scale);
708 OUT_CS_32F(offset);
709 OUT_CS_32F(scale);
710 OUT_CS_32F(offset);
711 }
712
713 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
714 OUT_CS(rs->polygon_offset_enable);
715 OUT_CS(rs->cull_mode);
716 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
717 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
718 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
719 OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
720 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
721 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
722 OUT_CS_32F(rs->point_texcoord_left);
723 OUT_CS_32F(rs->point_texcoord_bottom);
724 OUT_CS_32F(rs->point_texcoord_right);
725 OUT_CS_32F(rs->point_texcoord_top);
726 END_CS;
727 }
728
729 void r300_emit_rs_block_state(struct r300_context* r300,
730 unsigned size, void* state)
731 {
732 struct r300_rs_block* rs = (struct r300_rs_block*)state;
733 unsigned i;
734 /* It's the same for both INST and IP tables */
735 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
736 CS_LOCALS(r300);
737
738 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
739
740 BEGIN_CS(size);
741 if (r300->screen->caps.is_r500) {
742 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
743 } else {
744 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
745 }
746 for (i = 0; i < count; i++) {
747 OUT_CS(rs->ip[i]);
748 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
749 }
750
751 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
752 OUT_CS(rs->count);
753 OUT_CS(rs->inst_count);
754
755 if (r300->screen->caps.is_r500) {
756 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
757 } else {
758 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
759 }
760 for (i = 0; i < count; i++) {
761 OUT_CS(rs->inst[i]);
762 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
763 }
764
765 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
766 rs->count, rs->inst_count);
767
768 END_CS;
769 }
770
771 void r300_emit_scissor_state(struct r300_context* r300,
772 unsigned size, void* state)
773 {
774 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
775 CS_LOCALS(r300);
776
777 BEGIN_CS(size);
778 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
779 if (r300->screen->caps.is_r500) {
780 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
781 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
782 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
783 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
784 } else {
785 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
786 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
787 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
788 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
789 }
790 END_CS;
791 }
792
793 void r300_emit_textures_state(struct r300_context *r300,
794 unsigned size, void *state)
795 {
796 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
797 struct r300_texture_sampler_state *texstate;
798 unsigned i;
799 CS_LOCALS(r300);
800
801 BEGIN_CS(size);
802 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
803
804 for (i = 0; i < allstate->count; i++) {
805 if ((1 << i) & allstate->tx_enable) {
806 texstate = &allstate->regs[i];
807
808 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
809 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
810 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
811 texstate->border_color);
812
813 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
814 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
815 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
816
817 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
818 OUT_CS_TEX_RELOC(r300_texture(allstate->sampler_views[i]->base.texture),
819 texstate->format.tile_config,
820 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
821 }
822 }
823 END_CS;
824 }
825
826 void r300_emit_aos(struct r300_context* r300, unsigned offset)
827 {
828 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
829 struct pipe_vertex_element *velem = r300->velems->velem;
830 int i;
831 unsigned size1, size2, aos_count = r300->velems->count;
832 unsigned packet_size = (aos_count * 3 + 1) / 2;
833 CS_LOCALS(r300);
834
835 BEGIN_CS(2 + packet_size + aos_count * 2);
836 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
837 OUT_CS(aos_count);
838
839 for (i = 0; i < aos_count - 1; i += 2) {
840 vb1 = &vbuf[velem[i].vertex_buffer_index];
841 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
842 size1 = util_format_get_blocksize(velem[i].src_format);
843 size2 = util_format_get_blocksize(velem[i+1].src_format);
844
845 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
846 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
847 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
848 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
849 }
850
851 if (aos_count & 1) {
852 vb1 = &vbuf[velem[i].vertex_buffer_index];
853 size1 = util_format_get_blocksize(velem[i].src_format);
854
855 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
856 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
857 }
858
859 for (i = 0; i < aos_count; i++) {
860 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
861 RADEON_GEM_DOMAIN_GTT, 0, 0);
862 }
863 END_CS;
864 }
865
866 void r300_emit_vertex_buffer(struct r300_context* r300)
867 {
868 CS_LOCALS(r300);
869
870 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
871 "vertex size %d\n", r300->vbo,
872 r300->vertex_info.size);
873 /* Set the pointer to our vertex buffer. The emitted values are this:
874 * PACKET3 [3D_LOAD_VBPNTR]
875 * COUNT [1]
876 * FORMAT [size | stride << 8]
877 * OFFSET [offset into BO]
878 * VBPNTR [relocated BO]
879 */
880 BEGIN_CS(7);
881 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
882 OUT_CS(1);
883 OUT_CS(r300->vertex_info.size |
884 (r300->vertex_info.size << 8));
885 OUT_CS(r300->vbo_offset);
886 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
887 END_CS;
888 }
889
890 void r300_emit_vertex_stream_state(struct r300_context* r300,
891 unsigned size, void* state)
892 {
893 struct r300_vertex_stream_state *streams =
894 (struct r300_vertex_stream_state*)state;
895 unsigned i;
896 CS_LOCALS(r300);
897
898 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
899
900 BEGIN_CS(size);
901 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
902 for (i = 0; i < streams->count; i++) {
903 OUT_CS(streams->vap_prog_stream_cntl[i]);
904 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
905 streams->vap_prog_stream_cntl[i]);
906 }
907 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
908 for (i = 0; i < streams->count; i++) {
909 OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
910 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
911 streams->vap_prog_stream_cntl_ext[i]);
912 }
913 END_CS;
914 }
915
916 void r300_emit_vap_output_state(struct r300_context* r300,
917 unsigned size, void* state)
918 {
919 struct r300_vap_output_state *vap_out_state =
920 (struct r300_vap_output_state*)state;
921 CS_LOCALS(r300);
922
923 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
924
925 BEGIN_CS(size);
926 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
927 OUT_CS(vap_out_state->vap_vtx_state_cntl);
928 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
929 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
930 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
931 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
932 END_CS;
933 }
934
935 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
936 {
937 CS_LOCALS(r300);
938
939 BEGIN_CS(size);
940 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
941 END_CS;
942 }
943
944 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
945 {
946 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
947 struct r300_vertex_program_code* code = &vs->code;
948 struct r300_screen* r300screen = r300->screen;
949 unsigned instruction_count = code->length / 4;
950 unsigned i;
951
952 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
953 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
954 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
955 unsigned temp_count = MAX2(code->num_temporaries, 1);
956
957 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
958 vtx_mem_size / output_count, 10);
959 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
960
961 unsigned imm_first = vs->externals_count;
962 unsigned imm_end = vs->code.constants.Count;
963 unsigned imm_count = vs->immediates_count;
964
965 CS_LOCALS(r300);
966
967 BEGIN_CS(size);
968 /* R300_VAP_PVS_CODE_CNTL_0
969 * R300_VAP_PVS_CONST_CNTL
970 * R300_VAP_PVS_CODE_CNTL_1
971 * See the r5xx docs for instructions on how to use these. */
972 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
973 OUT_CS(R300_PVS_FIRST_INST(0) |
974 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
975 R300_PVS_LAST_INST(instruction_count - 1));
976 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
977 OUT_CS(instruction_count - 1);
978
979 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
980 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
981 for (i = 0; i < code->length; i++) {
982 OUT_CS(code->body.d[i]);
983 }
984
985 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
986 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
987 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
988 R300_PVS_VF_MAX_VTX_NUM(12) |
989 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
990
991 /* Emit immediates. */
992 if (imm_count) {
993 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
994 (r300->screen->caps.is_r500 ?
995 R500_PVS_CONST_START : R300_PVS_CONST_START) +
996 imm_first);
997 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
998 for (i = imm_first; i < imm_end; i++) {
999 const float *data = vs->code.constants.Constants[i].u.Immediate;
1000 OUT_CS_32F(data[0]);
1001 OUT_CS_32F(data[1]);
1002 OUT_CS_32F(data[2]);
1003 OUT_CS_32F(data[3]);
1004 }
1005 }
1006 END_CS;
1007 }
1008
1009 void r300_emit_vs_constants(struct r300_context* r300,
1010 unsigned size, void *state)
1011 {
1012 unsigned i;
1013 unsigned count =
1014 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1015 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1016 CS_LOCALS(r300);
1017
1018 if (!count)
1019 return;
1020
1021 BEGIN_CS(size);
1022 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1023 (r300->screen->caps.is_r500 ?
1024 R500_PVS_CONST_START : R300_PVS_CONST_START));
1025 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1026 for (i = 0; i < count; i++) {
1027 const float *data = buf->constants[i];
1028 OUT_CS_32F(data[0]);
1029 OUT_CS_32F(data[1]);
1030 OUT_CS_32F(data[2]);
1031 OUT_CS_32F(data[3]);
1032 }
1033 END_CS;
1034 }
1035
1036 void r300_emit_viewport_state(struct r300_context* r300,
1037 unsigned size, void* state)
1038 {
1039 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1040 CS_LOCALS(r300);
1041
1042 BEGIN_CS(size);
1043 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1044 OUT_CS_32F(viewport->xscale);
1045 OUT_CS_32F(viewport->xoffset);
1046 OUT_CS_32F(viewport->yscale);
1047 OUT_CS_32F(viewport->yoffset);
1048 OUT_CS_32F(viewport->zscale);
1049 OUT_CS_32F(viewport->zoffset);
1050 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1051 END_CS;
1052 }
1053
1054 void r300_emit_ztop_state(struct r300_context* r300,
1055 unsigned size, void* state)
1056 {
1057 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1058 CS_LOCALS(r300);
1059
1060 BEGIN_CS(size);
1061 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1062 END_CS;
1063 }
1064
1065 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1066 {
1067 CS_LOCALS(r300);
1068
1069 BEGIN_CS(size);
1070 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1071 END_CS;
1072 }
1073
1074 void r300_emit_buffer_validate(struct r300_context *r300,
1075 boolean do_validate_vertex_buffers,
1076 struct pipe_resource *index_buffer)
1077 {
1078 struct pipe_framebuffer_state* fb =
1079 (struct pipe_framebuffer_state*)r300->fb_state.state;
1080 struct r300_textures_state *texstate =
1081 (struct r300_textures_state*)r300->textures_state.state;
1082 struct r300_texture* tex;
1083 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1084 struct pipe_vertex_element *velem = r300->velems->velem;
1085 struct pipe_resource *pbuf;
1086 unsigned i;
1087 boolean invalid = FALSE;
1088
1089 /* upload buffers first */
1090 if (r300->any_user_vbs) {
1091 r300_upload_user_buffers(r300);
1092 r300->any_user_vbs = false;
1093 }
1094
1095 /* Clean out BOs. */
1096 r300->rws->reset_bos(r300->rws);
1097
1098 validate:
1099 /* Color buffers... */
1100 for (i = 0; i < fb->nr_cbufs; i++) {
1101 tex = r300_texture(fb->cbufs[i]->texture);
1102 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1103 if (!r300_add_texture(r300->rws, tex,
1104 0, RADEON_GEM_DOMAIN_VRAM)) {
1105 r300->context.flush(&r300->context, 0, NULL);
1106 goto validate;
1107 }
1108 }
1109 /* ...depth buffer... */
1110 if (fb->zsbuf) {
1111 tex = r300_texture(fb->zsbuf->texture);
1112 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1113 if (!r300_add_texture(r300->rws, tex,
1114 0, RADEON_GEM_DOMAIN_VRAM)) {
1115 r300->context.flush(&r300->context, 0, NULL);
1116 goto validate;
1117 }
1118 }
1119 /* ...textures... */
1120 for (i = 0; i < texstate->count; i++) {
1121 if (!(texstate->tx_enable & (1 << i))) {
1122 continue;
1123 }
1124
1125 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1126 if (!r300_add_texture(r300->rws, tex,
1127 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1128 r300->context.flush(&r300->context, 0, NULL);
1129 goto validate;
1130 }
1131 }
1132 /* ...occlusion query buffer... */
1133 if (r300->query_start.dirty) {
1134 if (!r300_add_buffer(r300->rws, r300->oqbo,
1135 0, RADEON_GEM_DOMAIN_GTT)) {
1136 r300->context.flush(&r300->context, 0, NULL);
1137 goto validate;
1138 }
1139 }
1140 /* ...vertex buffer for SWTCL path... */
1141 if (r300->vbo) {
1142 if (!r300_add_buffer(r300->rws, r300->vbo,
1143 RADEON_GEM_DOMAIN_GTT, 0)) {
1144 r300->context.flush(&r300->context, 0, NULL);
1145 goto validate;
1146 }
1147 }
1148 /* ...vertex buffers for HWTCL path... */
1149 if (do_validate_vertex_buffers) {
1150 for (i = 0; i < r300->velems->count; i++) {
1151 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1152
1153 if (!r300_add_buffer(r300->rws, pbuf,
1154 RADEON_GEM_DOMAIN_GTT, 0)) {
1155 r300->context.flush(&r300->context, 0, NULL);
1156 goto validate;
1157 }
1158 }
1159 }
1160 /* ...and index buffer for HWTCL path. */
1161 if (index_buffer) {
1162 if (!r300_add_buffer(r300->rws, index_buffer,
1163 RADEON_GEM_DOMAIN_GTT, 0)) {
1164 r300->context.flush(&r300->context, 0, NULL);
1165 goto validate;
1166 }
1167 }
1168 if (!r300->rws->validate(r300->rws)) {
1169 r300->context.flush(&r300->context, 0, NULL);
1170 if (invalid) {
1171 /* Well, hell. */
1172 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1173 abort();
1174 }
1175 invalid = TRUE;
1176 goto validate;
1177 }
1178 }
1179
1180 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1181 {
1182 struct r300_atom* atom;
1183 unsigned dwords = 0;
1184
1185 foreach(atom, &r300->atom_list) {
1186 if (atom->dirty) {
1187 dwords += atom->size;
1188 }
1189 }
1190
1191 return dwords;
1192 }
1193
1194 /* Emit all dirty state. */
1195 void r300_emit_dirty_state(struct r300_context* r300)
1196 {
1197 struct r300_screen* r300screen = r300->screen;
1198 struct r300_atom* atom;
1199
1200 foreach(atom, &r300->atom_list) {
1201 if (atom->dirty) {
1202 atom->emit(r300, atom->size, atom->state);
1203 atom->dirty = FALSE;
1204 }
1205 }
1206
1207 /* Emit the VBO for SWTCL. */
1208 if (!r300screen->caps.has_tcl) {
1209 r300_emit_vertex_buffer(r300);
1210 }
1211
1212 r300->dirty_hw++;
1213 }