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Merge branch 'gallium-newclear'
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 CS_LOCALS(r300);
68
69 if (r300->screen->caps.is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 CS_LOCALS(r300);
87
88 if (r300->screen->caps.has_tcl) {
89 BEGIN_CS(size);
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
91 (r300->screen->caps.is_r500 ?
92 R500_PVS_UCP_START : R300_PVS_UCP_START));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
94 OUT_CS_TABLE(clip->ucp, 6 * 4);
95 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
96 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
97 END_CS;
98 } else {
99 BEGIN_CS(size);
100 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
101 END_CS;
102 }
103 }
104
105 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
106 {
107 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
108 struct pipe_framebuffer_state* fb =
109 (struct pipe_framebuffer_state*)r300->fb_state.state;
110 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
111 CS_LOCALS(r300);
112
113 BEGIN_CS(size);
114 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
115 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
116
117 if (fb->zsbuf) {
118 OUT_CS(dsa->z_buffer_control);
119 OUT_CS(dsa->z_stencil_control);
120 } else {
121 OUT_CS(0);
122 OUT_CS(0);
123 }
124
125 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
126
127 if (r300->screen->caps.is_r500) {
128 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
129 }
130 END_CS;
131 }
132
133 static const float * get_rc_constant_state(
134 struct r300_context * r300,
135 struct rc_constant * constant)
136 {
137 struct r300_textures_state* texstate = r300->textures_state.state;
138 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
139 struct pipe_resource *tex;
140
141 assert(constant->Type == RC_CONSTANT_STATE);
142
143 switch (constant->u.State[0]) {
144 /* Factor for converting rectangle coords to
145 * normalized coords. Should only show up on non-r500. */
146 case RC_STATE_R300_TEXRECT_FACTOR:
147 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
148 vec[0] = 1.0 / tex->width0;
149 vec[1] = 1.0 / tex->height0;
150 break;
151
152 case RC_STATE_R300_VIEWPORT_SCALE:
153 vec[0] = r300->viewport.scale[0];
154 vec[1] = r300->viewport.scale[1];
155 vec[2] = r300->viewport.scale[2];
156 break;
157
158 case RC_STATE_R300_VIEWPORT_OFFSET:
159 vec[0] = r300->viewport.translate[0];
160 vec[1] = r300->viewport.translate[1];
161 vec[2] = r300->viewport.translate[2];
162 break;
163
164 default:
165 fprintf(stderr, "r300: Implementation error: "
166 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
167 }
168
169 /* This should either be (0, 0, 0, 1), which should be a relatively safe
170 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
171 * state factors. */
172 return vec;
173 }
174
175 /* Convert a normal single-precision float into the 7.16 format
176 * used by the R300 fragment shader.
177 */
178 static uint32_t pack_float24(float f)
179 {
180 union {
181 float fl;
182 uint32_t u;
183 } u;
184 float mantissa;
185 int exponent;
186 uint32_t float24 = 0;
187
188 if (f == 0.0)
189 return 0;
190
191 u.fl = f;
192
193 mantissa = frexpf(f, &exponent);
194
195 /* Handle -ve */
196 if (mantissa < 0) {
197 float24 |= (1 << 23);
198 mantissa = mantissa * -1.0;
199 }
200 /* Handle exponent, bias of 63 */
201 exponent += 62;
202 float24 |= (exponent << 16);
203 /* Kill 7 LSB of mantissa */
204 float24 |= (u.u & 0x7FFFFF) >> 7;
205
206 return float24;
207 }
208
209 unsigned r300_get_fs_atom_size(struct r300_context *r300)
210 {
211 struct r300_fragment_shader *fs = r300_fs(r300);
212 unsigned imm_count = fs->shader->immediates_count;
213 struct r300_fragment_program_code *code = &fs->shader->code.code.r300;
214
215 return 19 +
216 code->alu.length * 4 +
217 (code->tex.length ? (1 + code->tex.length) : 0) +
218 (imm_count ? imm_count * 5 : 0);
219 }
220
221 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
222 {
223 struct r300_fragment_shader *fs = r300_fs(r300);
224 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
225 struct r300_fragment_program_code * code = &generic_code->code.r300;
226 unsigned i;
227 unsigned imm_count = fs->shader->immediates_count;
228 unsigned imm_first = fs->shader->externals_count;
229 unsigned imm_end = generic_code->constants.Count;
230 struct rc_constant *constants = generic_code->constants.Constants;
231 CS_LOCALS(r300);
232
233 BEGIN_CS(size);
234 OUT_CS_REG(R300_US_CONFIG, code->config);
235 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
236 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
237
238 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
239 OUT_CS_TABLE(code->code_addr, 4);
240
241 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
242 for (i = 0; i < code->alu.length; i++)
243 OUT_CS(code->alu.inst[i].rgb_inst);
244
245 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
246 for (i = 0; i < code->alu.length; i++)
247 OUT_CS(code->alu.inst[i].rgb_addr);
248
249 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
250 for (i = 0; i < code->alu.length; i++)
251 OUT_CS(code->alu.inst[i].alpha_inst);
252
253 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
254 for (i = 0; i < code->alu.length; i++)
255 OUT_CS(code->alu.inst[i].alpha_addr);
256
257 if (code->tex.length) {
258 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
259 OUT_CS_TABLE(code->tex.inst, code->tex.length);
260 }
261
262 /* Emit immediates. */
263 if (imm_count) {
264 for(i = imm_first; i < imm_end; ++i) {
265 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
266 const float *data = constants[i].u.Immediate;
267
268 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
269 OUT_CS(pack_float24(data[0]));
270 OUT_CS(pack_float24(data[1]));
271 OUT_CS(pack_float24(data[2]));
272 OUT_CS(pack_float24(data[3]));
273 }
274 }
275 }
276
277 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
278 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
279 END_CS;
280 }
281
282 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
283 {
284 struct r300_fragment_shader *fs = r300_fs(r300);
285 struct rc_constant_list *constants = &fs->shader->code.constants;
286 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
287 unsigned i, count = fs->shader->externals_count;
288 CS_LOCALS(r300);
289
290 if (count == 0)
291 return;
292
293 BEGIN_CS(size);
294 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
295 for(i = 0; i < count; ++i) {
296 const float *data;
297 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
298 data = buf->constants[i];
299 OUT_CS(pack_float24(data[0]));
300 OUT_CS(pack_float24(data[1]));
301 OUT_CS(pack_float24(data[2]));
302 OUT_CS(pack_float24(data[3]));
303 }
304 END_CS;
305 }
306
307 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
308 {
309 struct r300_fragment_shader *fs = r300_fs(r300);
310 struct rc_constant_list *constants = &fs->shader->code.constants;
311 unsigned i;
312 unsigned count = fs->shader->rc_state_count;
313 unsigned first = fs->shader->externals_count;
314 unsigned end = constants->Count;
315 CS_LOCALS(r300);
316
317 if (count == 0)
318 return;
319
320 BEGIN_CS(size);
321 for(i = first; i < end; ++i) {
322 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
323 const float *data =
324 get_rc_constant_state(r300, &constants->Constants[i]);
325
326 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
327 OUT_CS(pack_float24(data[0]));
328 OUT_CS(pack_float24(data[1]));
329 OUT_CS(pack_float24(data[2]));
330 OUT_CS(pack_float24(data[3]));
331 }
332 }
333 END_CS;
334 }
335
336 unsigned r500_get_fs_atom_size(struct r300_context *r300)
337 {
338 struct r300_fragment_shader *fs = r300_fs(r300);
339 unsigned imm_count = fs->shader->immediates_count;
340 struct r500_fragment_program_code *code = &fs->shader->code.code.r500;
341
342 return 17 +
343 ((code->inst_end + 1) * 6) +
344 (imm_count ? imm_count * 7 : 0);
345 }
346
347 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
348 {
349 struct r300_fragment_shader *fs = r300_fs(r300);
350 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
351 struct r500_fragment_program_code * code = &generic_code->code.r500;
352 unsigned i;
353 unsigned imm_count = fs->shader->immediates_count;
354 unsigned imm_first = fs->shader->externals_count;
355 unsigned imm_end = generic_code->constants.Count;
356 struct rc_constant *constants = generic_code->constants.Constants;
357 CS_LOCALS(r300);
358
359 BEGIN_CS(size);
360 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
361 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
362 OUT_CS_REG(R500_US_CODE_RANGE,
363 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
364 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
365 OUT_CS_REG(R500_US_CODE_ADDR,
366 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
367
368 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
369 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
370 for (i = 0; i <= code->inst_end; i++) {
371 OUT_CS(code->inst[i].inst0);
372 OUT_CS(code->inst[i].inst1);
373 OUT_CS(code->inst[i].inst2);
374 OUT_CS(code->inst[i].inst3);
375 OUT_CS(code->inst[i].inst4);
376 OUT_CS(code->inst[i].inst5);
377 }
378
379 /* Emit immediates. */
380 if (imm_count) {
381 for(i = imm_first; i < imm_end; ++i) {
382 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
383 const float *data = constants[i].u.Immediate;
384
385 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
386 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
387 (i & R500_GA_US_VECTOR_INDEX_MASK));
388 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
389 OUT_CS_TABLE(data, 4);
390 }
391 }
392 }
393
394 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
395 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
396 END_CS;
397 }
398
399 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
400 {
401 struct r300_fragment_shader *fs = r300_fs(r300);
402 struct rc_constant_list *constants = &fs->shader->code.constants;
403 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
404 unsigned i, count = fs->shader->externals_count;
405 CS_LOCALS(r300);
406
407 if (count == 0)
408 return;
409
410 BEGIN_CS(size);
411 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
412 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
413 for(i = 0; i < count; ++i) {
414 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
415 }
416 OUT_CS_TABLE(buf->constants, count * 4);
417 END_CS;
418 }
419
420 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
421 {
422 struct r300_fragment_shader *fs = r300_fs(r300);
423 struct rc_constant_list *constants = &fs->shader->code.constants;
424 unsigned i;
425 unsigned count = fs->shader->rc_state_count;
426 unsigned first = fs->shader->externals_count;
427 unsigned end = constants->Count;
428 CS_LOCALS(r300);
429
430 if (count == 0)
431 return;
432
433 BEGIN_CS(size);
434 for(i = first; i < end; ++i) {
435 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
436 const float *data =
437 get_rc_constant_state(r300, &constants->Constants[i]);
438
439 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
440 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
441 (i & R500_GA_US_VECTOR_INDEX_MASK));
442 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
443 OUT_CS_TABLE(data, 4);
444 }
445 }
446 END_CS;
447 }
448
449 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
450 {
451 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
452 struct r300_texture* tex;
453 struct pipe_surface* surf;
454 int i;
455 CS_LOCALS(r300);
456
457 BEGIN_CS(size);
458
459 /* Flush and free renderbuffer caches. */
460 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
461 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
462 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
463 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
464 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
465 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
466
467 /* Set the number of colorbuffers. */
468 if (fb->nr_cbufs > 1) {
469 if (r300->screen->caps.is_r500) {
470 OUT_CS_REG(R300_RB3D_CCTL,
471 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
472 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
473 } else {
474 OUT_CS_REG(R300_RB3D_CCTL,
475 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
476 }
477 } else {
478 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
479 }
480
481 /* Set up colorbuffers. */
482 for (i = 0; i < fb->nr_cbufs; i++) {
483 surf = fb->cbufs[i];
484 tex = r300_texture(surf->texture);
485 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
486
487 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
488 OUT_CS_TEX_RELOC(tex, surf->offset, 0, tex->domain, 0);
489
490 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
491 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
492 0, tex->domain, 0);
493
494 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
495 }
496 for (; i < 4; i++) {
497 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
498 }
499
500 /* Set up a zbuffer. */
501 if (fb->zsbuf) {
502 surf = fb->zsbuf;
503 tex = r300_texture(surf->texture);
504 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
505
506 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
507 OUT_CS_TEX_RELOC(tex, surf->offset, 0, tex->domain, 0);
508
509 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
510
511 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
512 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
513 0, tex->domain, 0);
514 }
515
516 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
517 if (r300->screen->caps.is_r500) {
518 OUT_CS(0);
519 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
520 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
521 } else {
522 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
523 (1440 << R300_SCISSORS_Y_SHIFT));
524 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
525 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
526 }
527 END_CS;
528 }
529
530 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
531 {
532 struct r300_query *query = r300->query_current;
533 CS_LOCALS(r300);
534
535 if (!query)
536 return;
537
538 BEGIN_CS(size);
539 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
540 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
541 } else {
542 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
543 }
544 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
545 END_CS;
546 query->begin_emitted = TRUE;
547 }
548
549
550 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
551 struct r300_query *query)
552 {
553 struct r300_capabilities* caps = &r300->screen->caps;
554 CS_LOCALS(r300);
555
556 assert(caps->num_frag_pipes);
557
558 BEGIN_CS(6 * caps->num_frag_pipes + 2);
559 /* I'm not so sure I like this switch, but it's hard to be elegant
560 * when there's so many special cases...
561 *
562 * So here's the basic idea. For each pipe, enable writes to it only,
563 * then put out the relocation for ZPASS_ADDR, taking into account a
564 * 4-byte offset for each pipe. RV380 and older are special; they have
565 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
566 * so there's a chipset cap for that. */
567 switch (caps->num_frag_pipes) {
568 case 4:
569 /* pipe 3 only */
570 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
571 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
572 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
573 0, r300_buffer(r300->oqbo)->domain, 0);
574 case 3:
575 /* pipe 2 only */
576 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
577 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
578 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
579 0, r300_buffer(r300->oqbo)->domain, 0);
580 case 2:
581 /* pipe 1 only */
582 /* As mentioned above, accomodate RV380 and older. */
583 OUT_CS_REG(R300_SU_REG_DEST,
584 1 << (caps->high_second_pipe ? 3 : 1));
585 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
586 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
587 0, r300_buffer(r300->oqbo)->domain, 0);
588 case 1:
589 /* pipe 0 only */
590 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
591 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
592 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
593 0, r300_buffer(r300->oqbo)->domain, 0);
594 break;
595 default:
596 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
597 " pixel pipes!\n", caps->num_frag_pipes);
598 abort();
599 }
600
601 /* And, finally, reset it to normal... */
602 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
603 END_CS;
604 }
605
606 static void rv530_emit_query_end_single_z(struct r300_context *r300,
607 struct r300_query *query)
608 {
609 CS_LOCALS(r300);
610
611 BEGIN_CS(8);
612 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
613 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
614 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, r300_buffer(r300->oqbo)->domain, 0);
615 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
616 END_CS;
617 }
618
619 static void rv530_emit_query_end_double_z(struct r300_context *r300,
620 struct r300_query *query)
621 {
622 CS_LOCALS(r300);
623
624 BEGIN_CS(14);
625 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
626 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
627 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, r300_buffer(r300->oqbo)->domain, 0);
628 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
629 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
630 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, r300_buffer(r300->oqbo)->domain, 0);
631 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
632 END_CS;
633 }
634
635 void r300_emit_query_end(struct r300_context* r300)
636 {
637 struct r300_capabilities *caps = &r300->screen->caps;
638 struct r300_query *query = r300->query_current;
639
640 if (!query)
641 return;
642
643 if (query->begin_emitted == FALSE)
644 return;
645
646 if (caps->family == CHIP_FAMILY_RV530) {
647 if (caps->num_z_pipes == 2)
648 rv530_emit_query_end_double_z(r300, query);
649 else
650 rv530_emit_query_end_single_z(r300, query);
651 } else
652 r300_emit_query_end_frag_pipes(r300, query);
653
654 query->begin_emitted = FALSE;
655 }
656
657 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
658 {
659 struct r300_rs_state* rs = (struct r300_rs_state*)state;
660 float scale, offset;
661 CS_LOCALS(r300);
662
663 BEGIN_CS(size);
664 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
665
666 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
667
668 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
669 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
670 OUT_CS(rs->point_minmax);
671 OUT_CS(rs->line_control);
672
673 if (rs->polygon_offset_enable) {
674 scale = rs->depth_scale * 12;
675 offset = rs->depth_offset;
676
677 switch (r300->zbuffer_bpp) {
678 case 16:
679 offset *= 4;
680 break;
681 case 24:
682 offset *= 2;
683 break;
684 }
685
686 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
687 OUT_CS_32F(scale);
688 OUT_CS_32F(offset);
689 OUT_CS_32F(scale);
690 OUT_CS_32F(offset);
691 }
692
693 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
694 OUT_CS(rs->polygon_offset_enable);
695 OUT_CS(rs->cull_mode);
696 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
697 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
698 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
699 OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
700 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
701 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
702 OUT_CS_32F(rs->point_texcoord_left);
703 OUT_CS_32F(rs->point_texcoord_bottom);
704 OUT_CS_32F(rs->point_texcoord_right);
705 OUT_CS_32F(rs->point_texcoord_top);
706 END_CS;
707 }
708
709 void r300_emit_rs_block_state(struct r300_context* r300,
710 unsigned size, void* state)
711 {
712 struct r300_rs_block* rs = (struct r300_rs_block*)state;
713 unsigned i;
714 /* It's the same for both INST and IP tables */
715 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
716 CS_LOCALS(r300);
717
718 if (SCREEN_DBG_ON(r300->screen, DBG_DRAW)) {
719 r500_dump_rs_block(rs);
720 }
721
722 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
723
724 BEGIN_CS(size);
725 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
726 OUT_CS(rs->vap_vtx_state_cntl);
727 OUT_CS(rs->vap_vsm_vtx_assm);
728 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
729 OUT_CS(rs->vap_out_vtx_fmt[0]);
730 OUT_CS(rs->vap_out_vtx_fmt[1]);
731
732 if (r300->screen->caps.is_r500) {
733 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
734 } else {
735 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
736 }
737 OUT_CS_TABLE(rs->ip, count);
738 for (i = 0; i < count; i++) {
739 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
740 }
741
742 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
743 OUT_CS(rs->count);
744 OUT_CS(rs->inst_count);
745
746 if (r300->screen->caps.is_r500) {
747 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
748 } else {
749 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
750 }
751 OUT_CS_TABLE(rs->inst, count);
752 for (i = 0; i < count; i++) {
753 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
754 }
755
756 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
757 rs->count, rs->inst_count);
758
759 END_CS;
760 }
761
762 void r300_emit_scissor_state(struct r300_context* r300,
763 unsigned size, void* state)
764 {
765 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
766 CS_LOCALS(r300);
767
768 BEGIN_CS(size);
769 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
770 if (r300->screen->caps.is_r500) {
771 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
772 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
773 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
774 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
775 } else {
776 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
777 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
778 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
779 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
780 }
781 END_CS;
782 }
783
784 void r300_emit_textures_state(struct r300_context *r300,
785 unsigned size, void *state)
786 {
787 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
788 struct r300_texture_sampler_state *texstate;
789 struct r300_texture *tex;
790 unsigned i;
791 CS_LOCALS(r300);
792
793 BEGIN_CS(size);
794 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
795
796 for (i = 0; i < allstate->count; i++) {
797 if ((1 << i) & allstate->tx_enable) {
798 texstate = &allstate->regs[i];
799 tex = r300_texture(allstate->sampler_views[i]->base.texture);
800
801 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
802 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
803 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
804 texstate->border_color);
805
806 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
807 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
808 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
809
810 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
811 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
812 0, 0);
813 }
814 }
815 END_CS;
816 }
817
818 void r300_emit_aos(struct r300_context* r300, unsigned offset, boolean indexed)
819 {
820 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
821 struct pipe_vertex_element *velem = r300->velems->velem;
822 struct r300_buffer *buf;
823 int i;
824 unsigned size1, size2, aos_count = r300->velems->count;
825 unsigned packet_size = (aos_count * 3 + 1) / 2;
826 CS_LOCALS(r300);
827
828 for (i = 0; i < aos_count; i++) {
829 if ((vbuf[velem[i].vertex_buffer_index].buffer_offset + velem[i].src_offset) % 4 != 0) {
830 /* XXX We must align the buffer. */
831 assert(0);
832 fprintf(stderr, "r300: Unaligned vertex buffer offsets aren't supported, aborting..\n");
833 abort();
834 }
835 }
836
837 BEGIN_CS(2 + packet_size + aos_count * 2);
838 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
839 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
840
841 for (i = 0; i < aos_count - 1; i += 2) {
842 vb1 = &vbuf[velem[i].vertex_buffer_index];
843 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
844 size1 = util_format_get_blocksize(velem[i].src_format);
845 size2 = util_format_get_blocksize(velem[i+1].src_format);
846
847 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
848 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
849 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
850 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
851 }
852
853 if (aos_count & 1) {
854 vb1 = &vbuf[velem[i].vertex_buffer_index];
855 size1 = util_format_get_blocksize(velem[i].src_format);
856
857 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
858 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
859 }
860
861 for (i = 0; i < aos_count; i++) {
862 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
863 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0, 0);
864 }
865 END_CS;
866 }
867
868 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
869 {
870 CS_LOCALS(r300);
871
872 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
873 "vertex size %d\n", r300->vbo,
874 r300->vertex_info.size);
875 /* Set the pointer to our vertex buffer. The emitted values are this:
876 * PACKET3 [3D_LOAD_VBPNTR]
877 * COUNT [1]
878 * FORMAT [size | stride << 8]
879 * OFFSET [offset into BO]
880 * VBPNTR [relocated BO]
881 */
882 BEGIN_CS(7);
883 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
884 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
885 OUT_CS(r300->vertex_info.size |
886 (r300->vertex_info.size << 8));
887 OUT_CS(r300->vbo_offset);
888 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0, 0);
889 END_CS;
890 }
891
892 void r300_emit_vertex_stream_state(struct r300_context* r300,
893 unsigned size, void* state)
894 {
895 struct r300_vertex_stream_state *streams =
896 (struct r300_vertex_stream_state*)state;
897 unsigned i;
898 CS_LOCALS(r300);
899
900 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
901
902 BEGIN_CS(size);
903 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
904 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
905 for (i = 0; i < streams->count; i++) {
906 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
907 streams->vap_prog_stream_cntl[i]);
908 }
909 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
910 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
911 for (i = 0; i < streams->count; i++) {
912 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
913 streams->vap_prog_stream_cntl_ext[i]);
914 }
915 END_CS;
916 }
917
918 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
919 {
920 CS_LOCALS(r300);
921
922 BEGIN_CS(size);
923 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
924 END_CS;
925 }
926
927 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
928 {
929 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
930 struct r300_vertex_program_code* code = &vs->code;
931 struct r300_screen* r300screen = r300->screen;
932 unsigned instruction_count = code->length / 4;
933 unsigned i;
934
935 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
936 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
937 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
938 unsigned temp_count = MAX2(code->num_temporaries, 1);
939
940 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
941 vtx_mem_size / output_count, 10);
942 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
943
944 unsigned imm_first = vs->externals_count;
945 unsigned imm_end = vs->code.constants.Count;
946 unsigned imm_count = vs->immediates_count;
947
948 CS_LOCALS(r300);
949
950 BEGIN_CS(size);
951 /* R300_VAP_PVS_CODE_CNTL_0
952 * R300_VAP_PVS_CONST_CNTL
953 * R300_VAP_PVS_CODE_CNTL_1
954 * See the r5xx docs for instructions on how to use these. */
955 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
956 OUT_CS(R300_PVS_FIRST_INST(0) |
957 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
958 R300_PVS_LAST_INST(instruction_count - 1));
959 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
960 OUT_CS(instruction_count - 1);
961
962 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
963 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
964 OUT_CS_TABLE(code->body.d, code->length);
965
966 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
967 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
968 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
969 R300_PVS_VF_MAX_VTX_NUM(12) |
970 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
971
972 /* Emit immediates. */
973 if (imm_count) {
974 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
975 (r300->screen->caps.is_r500 ?
976 R500_PVS_CONST_START : R300_PVS_CONST_START) +
977 imm_first);
978 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
979 for (i = imm_first; i < imm_end; i++) {
980 const float *data = vs->code.constants.Constants[i].u.Immediate;
981 OUT_CS_TABLE(data, 4);
982 }
983 }
984 END_CS;
985 }
986
987 void r300_emit_vs_constants(struct r300_context* r300,
988 unsigned size, void *state)
989 {
990 unsigned count =
991 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
992 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
993 CS_LOCALS(r300);
994
995 if (!count)
996 return;
997
998 BEGIN_CS(size);
999 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1000 (r300->screen->caps.is_r500 ?
1001 R500_PVS_CONST_START : R300_PVS_CONST_START));
1002 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1003 OUT_CS_TABLE(buf->constants, count * 4);
1004 END_CS;
1005 }
1006
1007 void r300_emit_viewport_state(struct r300_context* r300,
1008 unsigned size, void* state)
1009 {
1010 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1011 CS_LOCALS(r300);
1012
1013 BEGIN_CS(size);
1014 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1015 OUT_CS_32F(viewport->xscale);
1016 OUT_CS_32F(viewport->xoffset);
1017 OUT_CS_32F(viewport->yscale);
1018 OUT_CS_32F(viewport->yoffset);
1019 OUT_CS_32F(viewport->zscale);
1020 OUT_CS_32F(viewport->zoffset);
1021 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1022 END_CS;
1023 }
1024
1025 void r300_emit_ztop_state(struct r300_context* r300,
1026 unsigned size, void* state)
1027 {
1028 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1029 CS_LOCALS(r300);
1030
1031 BEGIN_CS(size);
1032 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1033 END_CS;
1034 }
1035
1036 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1037 {
1038 CS_LOCALS(r300);
1039
1040 BEGIN_CS(size);
1041 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1042 END_CS;
1043 }
1044
1045 void r300_emit_buffer_validate(struct r300_context *r300,
1046 boolean do_validate_vertex_buffers,
1047 struct pipe_resource *index_buffer)
1048 {
1049 struct pipe_framebuffer_state* fb =
1050 (struct pipe_framebuffer_state*)r300->fb_state.state;
1051 struct r300_textures_state *texstate =
1052 (struct r300_textures_state*)r300->textures_state.state;
1053 struct r300_texture* tex;
1054 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1055 struct pipe_vertex_element *velem = r300->velems->velem;
1056 struct pipe_resource *pbuf;
1057 unsigned i;
1058 boolean invalid = FALSE;
1059
1060 /* upload buffers first */
1061 if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
1062 r300_upload_user_buffers(r300);
1063 r300->any_user_vbs = false;
1064 }
1065
1066 /* Clean out BOs. */
1067 r300->rws->reset_bos(r300->rws);
1068
1069 validate:
1070 /* Color buffers... */
1071 for (i = 0; i < fb->nr_cbufs; i++) {
1072 tex = r300_texture(fb->cbufs[i]->texture);
1073 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1074 if (!r300_add_texture(r300->rws, tex, 0, tex->domain)) {
1075 r300->context.flush(&r300->context, 0, NULL);
1076 goto validate;
1077 }
1078 }
1079 /* ...depth buffer... */
1080 if (fb->zsbuf) {
1081 tex = r300_texture(fb->zsbuf->texture);
1082 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1083 if (!r300_add_texture(r300->rws, tex,
1084 0, tex->domain)) {
1085 r300->context.flush(&r300->context, 0, NULL);
1086 goto validate;
1087 }
1088 }
1089 /* ...textures... */
1090 for (i = 0; i < texstate->count; i++) {
1091 if (!(texstate->tx_enable & (1 << i))) {
1092 continue;
1093 }
1094
1095 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1096 if (!r300_add_texture(r300->rws, tex, tex->domain, 0)) {
1097 r300->context.flush(&r300->context, 0, NULL);
1098 goto validate;
1099 }
1100 }
1101 /* ...occlusion query buffer... */
1102 if (r300->query_start.dirty ||
1103 (r300->query_current && r300->query_current->begin_emitted)) {
1104 if (!r300_add_buffer(r300->rws, r300->oqbo,
1105 0, r300_buffer(r300->oqbo)->domain)) {
1106 r300->context.flush(&r300->context, 0, NULL);
1107 goto validate;
1108 }
1109 }
1110 /* ...vertex buffer for SWTCL path... */
1111 if (r300->vbo) {
1112 if (!r300_add_buffer(r300->rws, r300->vbo,
1113 r300_buffer(r300->vbo)->domain, 0)) {
1114 r300->context.flush(&r300->context, 0, NULL);
1115 goto validate;
1116 }
1117 }
1118 /* ...vertex buffers for HWTCL path... */
1119 if (do_validate_vertex_buffers) {
1120 for (i = 0; i < r300->velems->count; i++) {
1121 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1122
1123 if (!r300_add_buffer(r300->rws, pbuf,
1124 r300_buffer(pbuf)->domain, 0)) {
1125 r300->context.flush(&r300->context, 0, NULL);
1126 goto validate;
1127 }
1128 }
1129 }
1130 /* ...and index buffer for HWTCL path. */
1131 if (index_buffer) {
1132 if (!r300_add_buffer(r300->rws, index_buffer,
1133 r300_buffer(index_buffer)->domain, 0)) {
1134 r300->context.flush(&r300->context, 0, NULL);
1135 goto validate;
1136 }
1137 }
1138 if (!r300->rws->validate(r300->rws)) {
1139 r300->context.flush(&r300->context, 0, NULL);
1140 if (invalid) {
1141 /* Well, hell. */
1142 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1143 abort();
1144 }
1145 invalid = TRUE;
1146 goto validate;
1147 }
1148 }
1149
1150 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1151 {
1152 struct r300_atom* atom;
1153 unsigned dwords = 0;
1154
1155 foreach(atom, &r300->atom_list) {
1156 if (atom->dirty) {
1157 dwords += atom->size;
1158 }
1159 }
1160
1161 /* let's reserve some more, just in case */
1162 dwords += 32;
1163
1164 return dwords;
1165 }
1166
1167 /* Emit all dirty state. */
1168 void r300_emit_dirty_state(struct r300_context* r300)
1169 {
1170 struct r300_atom* atom;
1171
1172 foreach(atom, &r300->atom_list) {
1173 if (atom->dirty) {
1174 atom->emit(r300, atom->size, atom->state);
1175 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1176 atom->counter++;
1177 }
1178 atom->dirty = FALSE;
1179 }
1180 }
1181
1182 r300->dirty_hw++;
1183 }