src/gallium/drivers/r300/r300_emit.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2009 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 /* r300_emit: Functions for emitting state. */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_math.h"
  28 #include "util/u_simple_list.h"
  29
  30 #include "r300_context.h"
  31 #include "r300_cs.h"
  32 #include "r300_emit.h"
  33 #include "r300_fs.h"
  34 #include "r300_screen.h"
  35 #include "r300_screen_buffer.h"
  36 #include "r300_vs.h"
  37
  38 void r300_emit_blend_state(struct r300_context* r300,
  39                            unsigned size, void* state)
  40 {
  41     struct r300_blend_state* blend = (struct r300_blend_state*)state;
  42     struct pipe_framebuffer_state* fb =
  43         (struct pipe_framebuffer_state*)r300->fb_state.state;
  44     CS_LOCALS(r300);
  45
  46     if (fb->nr_cbufs) {
  47         WRITE_CS_TABLE(blend->cb, size);
  48     } else {
  49         WRITE_CS_TABLE(blend->cb_no_readwrite, size);
  50     }
  51 }
  52
  53 void r300_emit_blend_color_state(struct r300_context* r300,
  54                                  unsigned size, void* state)
  55 {
  56     struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
  57     CS_LOCALS(r300);
  58
  59     WRITE_CS_TABLE(bc->cb, size);
  60 }
  61
  62 void r300_emit_clip_state(struct r300_context* r300,
  63                           unsigned size, void* state)
  64 {
  65     struct r300_clip_state* clip = (struct r300_clip_state*)state;
  66     CS_LOCALS(r300);
  67
  68     WRITE_CS_TABLE(clip->cb, size);
  69 }
  70
  71 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
  72 {
  73     struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
  74     struct pipe_framebuffer_state* fb =
  75         (struct pipe_framebuffer_state*)r300->fb_state.state;
  76     CS_LOCALS(r300);
  77
  78     if (fb->zsbuf) {
  79         WRITE_CS_TABLE(&dsa->cb_begin, size);
  80     } else {
  81         WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
  82     }
  83 }
  84
  85 static const float * get_rc_constant_state(
  86     struct r300_context * r300,
  87     struct rc_constant * constant)
  88 {
  89     struct r300_textures_state* texstate = r300->textures_state.state;
  90     static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
  91     struct pipe_resource *tex;
  92
  93     assert(constant->Type == RC_CONSTANT_STATE);
  94
  95     switch (constant->u.State[0]) {
  96         /* Factor for converting rectangle coords to
  97          * normalized coords. Should only show up on non-r500. */
  98         case RC_STATE_R300_TEXRECT_FACTOR:
  99             tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
 100             vec[0] = 1.0 / tex->width0;
 101             vec[1] = 1.0 / tex->height0;
 102             break;
 103
 104         case RC_STATE_R300_VIEWPORT_SCALE:
 105             vec[0] = r300->viewport.scale[0];
 106             vec[1] = r300->viewport.scale[1];
 107             vec[2] = r300->viewport.scale[2];
 108             break;
 109
 110         case RC_STATE_R300_VIEWPORT_OFFSET:
 111             vec[0] = r300->viewport.translate[0];
 112             vec[1] = r300->viewport.translate[1];
 113             vec[2] = r300->viewport.translate[2];
 114             break;
 115
 116         default:
 117             fprintf(stderr, "r300: Implementation error: "
 118                 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
 119     }
 120
 121     /* This should either be (0, 0, 0, 1), which should be a relatively safe
 122      * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
 123      * state factors. */
 124     return vec;
 125 }
 126
 127 /* Convert a normal single-precision float into the 7.16 format
 128  * used by the R300 fragment shader.
 129  */
 130 uint32_t pack_float24(float f)
 131 {
 132     union {
 133         float fl;
 134         uint32_t u;
 135     } u;
 136     float mantissa;
 137     int exponent;
 138     uint32_t float24 = 0;
 139
 140     if (f == 0.0)
 141         return 0;
 142
 143     u.fl = f;
 144
 145     mantissa = frexpf(f, &exponent);
 146
 147     /* Handle -ve */
 148     if (mantissa < 0) {
 149         float24 |= (1 << 23);
 150         mantissa = mantissa * -1.0;
 151     }
 152     /* Handle exponent, bias of 63 */
 153     exponent += 62;
 154     float24 |= (exponent << 16);
 155     /* Kill 7 LSB of mantissa */
 156     float24 |= (u.u & 0x7FFFFF) >> 7;
 157
 158     return float24;
 159 }
 160
 161 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
 162 {
 163     struct r300_fragment_shader *fs = r300_fs(r300);
 164     CS_LOCALS(r300);
 165
 166     WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
 167 }
 168
 169 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
 170 {
 171     struct r300_fragment_shader *fs = r300_fs(r300);
 172     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
 173     unsigned count = fs->shader->externals_count * 4;
 174     CS_LOCALS(r300);
 175
 176     if (count == 0)
 177         return;
 178
 179     BEGIN_CS(size);
 180     OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count);
 181     OUT_CS_TABLE(buf->constants, count);
 182     END_CS;
 183 }
 184
 185 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
 186 {
 187     struct r300_fragment_shader *fs = r300_fs(r300);
 188     struct rc_constant_list *constants = &fs->shader->code.constants;
 189     unsigned i;
 190     unsigned count = fs->shader->rc_state_count;
 191     unsigned first = fs->shader->externals_count;
 192     unsigned end = constants->Count;
 193     uint32_t cdata[4];
 194     unsigned j;
 195     CS_LOCALS(r300);
 196
 197     if (count == 0)
 198         return;
 199
 200     BEGIN_CS(size);
 201     for(i = first; i < end; ++i) {
 202         if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
 203             const float *data =
 204                     get_rc_constant_state(r300, &constants->Constants[i]);
 205
 206             for (j = 0; j < 4; j++)
 207                 cdata[j] = pack_float24(data[j]);
 208
 209             OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
 210             OUT_CS_TABLE(cdata, 4);
 211         }
 212     }
 213     END_CS;
 214 }
 215
 216 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
 217 {
 218     struct r300_fragment_shader *fs = r300_fs(r300);
 219     CS_LOCALS(r300);
 220
 221     WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
 222 }
 223
 224 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
 225 {
 226     struct r300_fragment_shader *fs = r300_fs(r300);
 227     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
 228     unsigned count = fs->shader->externals_count * 4;
 229     CS_LOCALS(r300);
 230
 231     if (count == 0)
 232         return;
 233
 234     BEGIN_CS(size);
 235     OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
 236     OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count);
 237     OUT_CS_TABLE(buf->constants, count);
 238     END_CS;
 239 }
 240
 241 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
 242 {
 243     struct r300_fragment_shader *fs = r300_fs(r300);
 244     struct rc_constant_list *constants = &fs->shader->code.constants;
 245     unsigned i;
 246     unsigned count = fs->shader->rc_state_count;
 247     unsigned first = fs->shader->externals_count;
 248     unsigned end = constants->Count;
 249     CS_LOCALS(r300);
 250
 251     if (count == 0)
 252         return;
 253
 254     BEGIN_CS(size);
 255     for(i = first; i < end; ++i) {
 256         if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
 257             const float *data =
 258                     get_rc_constant_state(r300, &constants->Constants[i]);
 259
 260             OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
 261                        R500_GA_US_VECTOR_INDEX_TYPE_CONST |
 262                        (i & R500_GA_US_VECTOR_INDEX_MASK));
 263             OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
 264             OUT_CS_TABLE(data, 4);
 265         }
 266     }
 267     END_CS;
 268 }
 269
 270 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
 271 {
 272     struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
 273     struct pipe_framebuffer_state* fb =
 274             (struct pipe_framebuffer_state*)r300->fb_state.state;
 275     CS_LOCALS(r300);
 276
 277     BEGIN_CS(size);
 278
 279     /* Set up scissors.
 280      * By writing to the SC registers, SC & US assert idle. */
 281     OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
 282     if (r300->screen->caps.is_r500) {
 283         OUT_CS(0);
 284         OUT_CS(((fb->width  - 1) << R300_SCISSORS_X_SHIFT) |
 285                ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
 286     } else {
 287         OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
 288                (1440 << R300_SCISSORS_Y_SHIFT));
 289         OUT_CS(((fb->width  + 1440-1) << R300_SCISSORS_X_SHIFT) |
 290                ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
 291     }
 292
 293     /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
 294     OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
 295     END_CS;
 296 }
 297
 298 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
 299 {
 300     struct r300_aa_state *aa = (struct r300_aa_state*)state;
 301     CS_LOCALS(r300);
 302
 303     BEGIN_CS(size);
 304     OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
 305
 306     if (aa->dest) {
 307         OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
 308         OUT_CS_RELOC(aa->dest->buffer, aa->dest->offset, 0, aa->dest->domain, 0);
 309
 310         OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
 311         OUT_CS_RELOC(aa->dest->buffer, aa->dest->pitch, 0, aa->dest->domain, 0);
 312     }
 313
 314     OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
 315     END_CS;
 316 }
 317
 318 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
 319 {
 320     struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
 321     struct r300_surface* surf;
 322     unsigned i;
 323     CS_LOCALS(r300);
 324
 325     BEGIN_CS(size);
 326
 327     /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
 328      * what we usually want. */
 329     if (r300->screen->caps.is_r500) {
 330         OUT_CS_REG(R300_RB3D_CCTL,
 331             R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
 332     } else {
 333         OUT_CS_REG(R300_RB3D_CCTL, 0);
 334     }
 335
 336     /* Set up colorbuffers. */
 337     for (i = 0; i < fb->nr_cbufs; i++) {
 338         surf = r300_surface(fb->cbufs[i]);
 339
 340         OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
 341         OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
 342
 343         OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
 344         OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
 345     }
 346
 347     /* Set up a zbuffer. */
 348     if (fb->zsbuf) {
 349         surf = r300_surface(fb->zsbuf);
 350
 351         OUT_CS_REG(R300_ZB_FORMAT, surf->format);
 352         OUT_CS_REG(R300_ZB_BW_CNTL, 0);
 353
 354         OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
 355         OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
 356
 357         OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
 358         OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
 359
 360         OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0);
 361
 362         /* HiZ RAM. */
 363         if (r300->screen->caps.has_hiz) {
 364             OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
 365             OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
 366         }
 367
 368         /* Z Mask RAM. (compressed zbuffer) */
 369         OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
 370         OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
 371     }
 372
 373     /* Colorbuffer format in the US block.
 374      * (must be written after unpipelined regs) */
 375     OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
 376     for (i = 0; i < fb->nr_cbufs; i++) {
 377         OUT_CS(r300_surface(fb->cbufs[i])->format);
 378     }
 379     for (; i < 4; i++) {
 380         OUT_CS(R300_US_OUT_FMT_UNUSED);
 381     }
 382     END_CS;
 383 }
 384
 385 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
 386 {
 387     struct r300_query *query = r300->query_current;
 388     CS_LOCALS(r300);
 389
 390     if (!query)
 391         return;
 392
 393     BEGIN_CS(size);
 394     if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
 395         OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 396     } else {
 397         OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 398     }
 399     OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
 400     END_CS;
 401     query->begin_emitted = TRUE;
 402     query->flushed = FALSE;
 403 }
 404
 405 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
 406                                            struct r300_query *query)
 407 {
 408     struct r300_capabilities* caps = &r300->screen->caps;
 409     struct r300_winsys_buffer *buf = r300->query_current->buffer;
 410     CS_LOCALS(r300);
 411
 412     assert(caps->num_frag_pipes);
 413
 414     BEGIN_CS(6 * caps->num_frag_pipes + 2);
 415     /* I'm not so sure I like this switch, but it's hard to be elegant
 416      * when there's so many special cases...
 417      *
 418      * So here's the basic idea. For each pipe, enable writes to it only,
 419      * then put out the relocation for ZPASS_ADDR, taking into account a
 420      * 4-byte offset for each pipe. RV380 and older are special; they have
 421      * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
 422      * so there's a chipset cap for that. */
 423     switch (caps->num_frag_pipes) {
 424         case 4:
 425             /* pipe 3 only */
 426             OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
 427             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 428             OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
 429                     0, query->domain, 0);
 430         case 3:
 431             /* pipe 2 only */
 432             OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
 433             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 434             OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
 435                     0, query->domain, 0);
 436         case 2:
 437             /* pipe 1 only */
 438             /* As mentioned above, accomodate RV380 and older. */
 439             OUT_CS_REG(R300_SU_REG_DEST,
 440                     1 << (caps->high_second_pipe ? 3 : 1));
 441             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 442             OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
 443                     0, query->domain, 0);
 444         case 1:
 445             /* pipe 0 only */
 446             OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
 447             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 448             OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
 449                     0, query->domain, 0);
 450             break;
 451         default:
 452             fprintf(stderr, "r300: Implementation error: Chipset reports %d"
 453                     " pixel pipes!\n", caps->num_frag_pipes);
 454             abort();
 455     }
 456
 457     /* And, finally, reset it to normal... */
 458     OUT_CS_REG(R300_SU_REG_DEST, 0xF);
 459     END_CS;
 460 }
 461
 462 static void rv530_emit_query_end_single_z(struct r300_context *r300,
 463                                           struct r300_query *query)
 464 {
 465     struct r300_winsys_buffer *buf = r300->query_current->buffer;
 466     CS_LOCALS(r300);
 467
 468     BEGIN_CS(8);
 469     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 470     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 471     OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain, 0);
 472     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 473     END_CS;
 474 }
 475
 476 static void rv530_emit_query_end_double_z(struct r300_context *r300,
 477                                           struct r300_query *query)
 478 {
 479     struct r300_winsys_buffer *buf = r300->query_current->buffer;
 480     CS_LOCALS(r300);
 481
 482     BEGIN_CS(14);
 483     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 484     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 485     OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain, 0);
 486     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 487     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 488     OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain, 0);
 489     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 490     END_CS;
 491 }
 492
 493 void r300_emit_query_end(struct r300_context* r300)
 494 {
 495     struct r300_capabilities *caps = &r300->screen->caps;
 496     struct r300_query *query = r300->query_current;
 497
 498     if (!query)
 499         return;
 500
 501     if (query->begin_emitted == FALSE)
 502         return;
 503
 504     if (caps->family == CHIP_FAMILY_RV530) {
 505         if (caps->num_z_pipes == 2)
 506             rv530_emit_query_end_double_z(r300, query);
 507         else
 508             rv530_emit_query_end_single_z(r300, query);
 509     } else
 510         r300_emit_query_end_frag_pipes(r300, query);
 511
 512     query->begin_emitted = FALSE;
 513     query->num_results += query->num_pipes;
 514
 515     /* XXX grab all the results and reset the counter. */
 516     if (query->num_results >= query->buffer_size / 4 - 4) {
 517         query->num_results = (query->buffer_size / 4) / 2;
 518         fprintf(stderr, "r300: Rewinding OQBO...\n");
 519     }
 520 }
 521
 522 void r300_emit_invariant_state(struct r300_context *r300,
 523                                unsigned size, void *state)
 524 {
 525     CS_LOCALS(r300);
 526     WRITE_CS_TABLE(state, size);
 527 }
 528
 529 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
 530 {
 531     struct r300_rs_state* rs = state;
 532     struct pipe_framebuffer_state* fb = r300->fb_state.state;
 533     float scale, offset;
 534     unsigned mspos0, mspos1;
 535     CS_LOCALS(r300);
 536
 537     BEGIN_CS(size);
 538     OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
 539
 540     /* Multisampling. Depends on framebuffer sample count. */
 541     if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
 542         if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
 543             /* Subsample placement. These may not be optimal. */
 544             switch (fb->cbufs[0]->texture->nr_samples) {
 545                 case 2:
 546                     mspos0 = 0x33996633;
 547                     mspos1 = 0x6666663;
 548                     break;
 549                 case 3:
 550                     mspos0 = 0x33936933;
 551                     mspos1 = 0x6666663;
 552                     break;
 553                 case 4:
 554                     mspos0 = 0x33939933;
 555                     mspos1 = 0x3966663;
 556                     break;
 557                 case 6:
 558                     mspos0 = 0x22a2aa22;
 559                     mspos1 = 0x2a65672;
 560                     break;
 561                 default:
 562                     debug_printf("r300: Bad number of multisamples!\n");
 563                     mspos0 = rs->multisample_position_0;
 564                     mspos1 = rs->multisample_position_1;
 565                     break;
 566             }
 567
 568             OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
 569             OUT_CS(mspos0);
 570             OUT_CS(mspos1);
 571         } else {
 572             OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
 573             OUT_CS(rs->multisample_position_0);
 574             OUT_CS(rs->multisample_position_1);
 575         }
 576     }
 577
 578     OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
 579     OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
 580     OUT_CS(rs->point_minmax);
 581     OUT_CS(rs->line_control);
 582
 583     if (rs->polygon_offset_enable) {
 584         scale = rs->depth_scale * 12;
 585         offset = rs->depth_offset;
 586
 587         switch (r300->zbuffer_bpp) {
 588             case 16:
 589                 offset *= 4;
 590                 break;
 591             case 24:
 592                 offset *= 2;
 593                 break;
 594         }
 595
 596         OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 597         OUT_CS_32F(scale);
 598         OUT_CS_32F(offset);
 599         OUT_CS_32F(scale);
 600         OUT_CS_32F(offset);
 601     }
 602
 603     OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
 604     OUT_CS(rs->polygon_offset_enable);
 605     OUT_CS(rs->cull_mode);
 606     OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
 607     OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
 608     OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
 609     OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
 610     OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
 611     OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
 612     OUT_CS_32F(rs->point_texcoord_left);
 613     OUT_CS_32F(rs->point_texcoord_bottom);
 614     OUT_CS_32F(rs->point_texcoord_right);
 615     OUT_CS_32F(rs->point_texcoord_top);
 616     END_CS;
 617 }
 618
 619 void r300_emit_rs_block_state(struct r300_context* r300,
 620                               unsigned size, void* state)
 621 {
 622     struct r300_rs_block* rs = (struct r300_rs_block*)state;
 623     unsigned i;
 624     /* It's the same for both INST and IP tables */
 625     unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
 626     CS_LOCALS(r300);
 627
 628     if (SCREEN_DBG_ON(r300->screen, DBG_DRAW)) {
 629         r500_dump_rs_block(rs);
 630     }
 631
 632     DBG(r300, DBG_DRAW, "r300: RS emit:\n");
 633
 634     BEGIN_CS(size);
 635     OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
 636     OUT_CS(rs->vap_vtx_state_cntl);
 637     OUT_CS(rs->vap_vsm_vtx_assm);
 638     OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 639     OUT_CS(rs->vap_out_vtx_fmt[0]);
 640     OUT_CS(rs->vap_out_vtx_fmt[1]);
 641
 642     if (r300->screen->caps.is_r500) {
 643         OUT_CS_REG_SEQ(R500_RS_IP_0, count);
 644     } else {
 645         OUT_CS_REG_SEQ(R300_RS_IP_0, count);
 646     }
 647     OUT_CS_TABLE(rs->ip, count);
 648     for (i = 0; i < count; i++) {
 649         DBG(r300, DBG_DRAW, "    : ip %d: 0x%08x\n", i, rs->ip[i]);
 650     }
 651
 652     OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 653     OUT_CS(rs->count);
 654     OUT_CS(rs->inst_count);
 655
 656     if (r300->screen->caps.is_r500) {
 657         OUT_CS_REG_SEQ(R500_RS_INST_0, count);
 658     } else {
 659         OUT_CS_REG_SEQ(R300_RS_INST_0, count);
 660     }
 661     OUT_CS_TABLE(rs->inst, count);
 662     for (i = 0; i < count; i++) {
 663         DBG(r300, DBG_DRAW, "    : inst %d: 0x%08x\n", i, rs->inst[i]);
 664     }
 665
 666     DBG(r300, DBG_DRAW, "    : count: 0x%08x inst_count: 0x%08x\n",
 667         rs->count, rs->inst_count);
 668
 669     END_CS;
 670 }
 671
 672 void r300_emit_scissor_state(struct r300_context* r300,
 673                              unsigned size, void* state)
 674 {
 675     struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
 676     CS_LOCALS(r300);
 677
 678     BEGIN_CS(size);
 679     OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
 680     if (r300->screen->caps.is_r500) {
 681         OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
 682                (scissor->miny << R300_CLIPRECT_Y_SHIFT));
 683         OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
 684                ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
 685     } else {
 686         OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
 687                ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
 688         OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
 689                ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
 690     }
 691     END_CS;
 692 }
 693
 694 void r300_emit_textures_state(struct r300_context *r300,
 695                               unsigned size, void *state)
 696 {
 697     struct r300_textures_state *allstate = (struct r300_textures_state*)state;
 698     struct r300_texture_sampler_state *texstate;
 699     struct r300_texture *tex;
 700     unsigned i;
 701     CS_LOCALS(r300);
 702
 703     BEGIN_CS(size);
 704     OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
 705
 706     for (i = 0; i < allstate->count; i++) {
 707         if ((1 << i) & allstate->tx_enable) {
 708             texstate = &allstate->regs[i];
 709             tex = r300_texture(allstate->sampler_views[i]->base.texture);
 710
 711             OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
 712             OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
 713             OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
 714                        texstate->border_color);
 715
 716             OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
 717             OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
 718             OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
 719
 720             OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 721             OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
 722                              0, 0);
 723         }
 724     }
 725     END_CS;
 726 }
 727
 728 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
 729 {
 730     struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
 731     struct pipe_vertex_element *velem = r300->velems->velem;
 732     struct r300_buffer *buf;
 733     int i;
 734     unsigned *hw_format_size = r300->velems->hw_format_size;
 735     unsigned size1, size2, aos_count = r300->velems->count;
 736     unsigned packet_size = (aos_count * 3 + 1) / 2;
 737     CS_LOCALS(r300);
 738
 739     BEGIN_CS(2 + packet_size + aos_count * 2);
 740     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
 741     OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
 742
 743     for (i = 0; i < aos_count - 1; i += 2) {
 744         vb1 = &vbuf[velem[i].vertex_buffer_index];
 745         vb2 = &vbuf[velem[i+1].vertex_buffer_index];
 746         size1 = hw_format_size[i];
 747         size2 = hw_format_size[i+1];
 748
 749         OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
 750                R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
 751         OUT_CS(vb1->buffer_offset + velem[i].src_offset   + offset * vb1->stride);
 752         OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
 753     }
 754
 755     if (aos_count & 1) {
 756         vb1 = &vbuf[velem[i].vertex_buffer_index];
 757         size1 = hw_format_size[i];
 758
 759         OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
 760         OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
 761     }
 762
 763     for (i = 0; i < aos_count; i++) {
 764         buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
 765         OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0, 0);
 766     }
 767     END_CS;
 768 }
 769
 770 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
 771 {
 772     CS_LOCALS(r300);
 773
 774     DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
 775             "vertex size %d\n", r300->vbo,
 776             r300->vertex_info.size);
 777     /* Set the pointer to our vertex buffer. The emitted values are this:
 778      * PACKET3 [3D_LOAD_VBPNTR]
 779      * COUNT   [1]
 780      * FORMAT  [size | stride << 8]
 781      * OFFSET  [offset into BO]
 782      * VBPNTR  [relocated BO]
 783      */
 784     BEGIN_CS(7);
 785     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
 786     OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
 787     OUT_CS(r300->vertex_info.size |
 788             (r300->vertex_info.size << 8));
 789     OUT_CS(r300->vbo_offset);
 790     OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0, 0);
 791     END_CS;
 792 }
 793
 794 void r300_emit_vertex_stream_state(struct r300_context* r300,
 795                                    unsigned size, void* state)
 796 {
 797     struct r300_vertex_stream_state *streams =
 798         (struct r300_vertex_stream_state*)state;
 799     unsigned i;
 800     CS_LOCALS(r300);
 801
 802     DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
 803
 804     BEGIN_CS(size);
 805     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
 806     OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
 807     for (i = 0; i < streams->count; i++) {
 808         DBG(r300, DBG_DRAW, "    : prog_stream_cntl%d: 0x%08x\n", i,
 809                streams->vap_prog_stream_cntl[i]);
 810     }
 811     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
 812     OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
 813     for (i = 0; i < streams->count; i++) {
 814         DBG(r300, DBG_DRAW, "    : prog_stream_cntl_ext%d: 0x%08x\n", i,
 815                streams->vap_prog_stream_cntl_ext[i]);
 816     }
 817     END_CS;
 818 }
 819
 820 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
 821 {
 822     CS_LOCALS(r300);
 823
 824     BEGIN_CS(size);
 825     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
 826     END_CS;
 827 }
 828
 829 void r300_emit_vap_invariant_state(struct r300_context *r300,
 830                                    unsigned size, void *state)
 831 {
 832     CS_LOCALS(r300);
 833     WRITE_CS_TABLE(state, size);
 834 }
 835
 836 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
 837 {
 838     struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
 839     struct r300_vertex_program_code* code = &vs->code;
 840     struct r300_screen* r300screen = r300->screen;
 841     unsigned instruction_count = code->length / 4;
 842     unsigned i;
 843
 844     unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
 845     unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
 846     unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
 847     unsigned temp_count = MAX2(code->num_temporaries, 1);
 848
 849     unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
 850                                   vtx_mem_size / output_count, 10);
 851     unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
 852
 853     unsigned imm_first = vs->externals_count;
 854     unsigned imm_end = vs->code.constants.Count;
 855     unsigned imm_count = vs->immediates_count;
 856
 857     CS_LOCALS(r300);
 858
 859     BEGIN_CS(size);
 860
 861     /* R300_VAP_PVS_CODE_CNTL_0
 862      * R300_VAP_PVS_CONST_CNTL
 863      * R300_VAP_PVS_CODE_CNTL_1
 864      * See the r5xx docs for instructions on how to use these. */
 865     OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
 866     OUT_CS(R300_PVS_FIRST_INST(0) |
 867             R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
 868             R300_PVS_LAST_INST(instruction_count - 1));
 869     OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
 870     OUT_CS(instruction_count - 1);
 871
 872     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
 873     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
 874     OUT_CS_TABLE(code->body.d, code->length);
 875
 876     OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
 877             R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
 878             R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
 879             R300_PVS_VF_MAX_VTX_NUM(12) |
 880             (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
 881
 882     /* Emit immediates. */
 883     if (imm_count) {
 884         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
 885                    (r300->screen->caps.is_r500 ?
 886                    R500_PVS_CONST_START : R300_PVS_CONST_START) +
 887                    imm_first);
 888         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
 889         for (i = imm_first; i < imm_end; i++) {
 890             const float *data = vs->code.constants.Constants[i].u.Immediate;
 891             OUT_CS_TABLE(data, 4);
 892         }
 893     }
 894     END_CS;
 895 }
 896
 897 void r300_emit_vs_constants(struct r300_context* r300,
 898                             unsigned size, void *state)
 899 {
 900     unsigned count =
 901         ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
 902     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
 903     CS_LOCALS(r300);
 904
 905     if (!count)
 906         return;
 907
 908     BEGIN_CS(size);
 909     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
 910                (r300->screen->caps.is_r500 ?
 911                R500_PVS_CONST_START : R300_PVS_CONST_START));
 912     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
 913     OUT_CS_TABLE(buf->constants, count * 4);
 914     END_CS;
 915 }
 916
 917 void r300_emit_viewport_state(struct r300_context* r300,
 918                               unsigned size, void* state)
 919 {
 920     struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
 921     CS_LOCALS(r300);
 922
 923     BEGIN_CS(size);
 924     OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
 925     OUT_CS_TABLE(&viewport->xscale, 6);
 926     OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
 927     END_CS;
 928 }
 929
 930 void r300_emit_ztop_state(struct r300_context* r300,
 931                           unsigned size, void* state)
 932 {
 933     struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
 934     CS_LOCALS(r300);
 935
 936     BEGIN_CS(size);
 937     OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
 938     END_CS;
 939 }
 940
 941 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
 942 {
 943     CS_LOCALS(r300);
 944
 945     BEGIN_CS(size);
 946     OUT_CS_REG(R300_TX_INVALTAGS, 0);
 947     END_CS;
 948 }
 949
 950 void r300_emit_buffer_validate(struct r300_context *r300,
 951                                boolean do_validate_vertex_buffers,
 952                                struct pipe_resource *index_buffer)
 953 {
 954     struct pipe_framebuffer_state* fb =
 955         (struct pipe_framebuffer_state*)r300->fb_state.state;
 956     struct r300_textures_state *texstate =
 957         (struct r300_textures_state*)r300->textures_state.state;
 958     struct r300_texture* tex;
 959     struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
 960     struct pipe_vertex_element *velem = r300->velems->velem;
 961     struct pipe_resource *pbuf;
 962     unsigned i;
 963     boolean invalid = FALSE;
 964
 965     /* upload buffers first */
 966     if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
 967         r300_upload_user_buffers(r300);
 968         r300->any_user_vbs = false;
 969     }
 970
 971     /* Clean out BOs. */
 972     r300->rws->reset_bos(r300->rws);
 973
 974 validate:
 975     /* Color buffers... */
 976     for (i = 0; i < fb->nr_cbufs; i++) {
 977         tex = r300_texture(fb->cbufs[i]->texture);
 978         assert(tex && tex->buffer && "cbuf is marked, but NULL!");
 979         if (!r300_add_texture(r300->rws, tex, 0, tex->domain)) {
 980             r300->context.flush(&r300->context, 0, NULL);
 981             goto validate;
 982         }
 983     }
 984     /* ...depth buffer... */
 985     if (fb->zsbuf) {
 986         tex = r300_texture(fb->zsbuf->texture);
 987         assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
 988         if (!r300_add_texture(r300->rws, tex,
 989                               0, tex->domain)) {
 990             r300->context.flush(&r300->context, 0, NULL);
 991             goto validate;
 992         }
 993     }
 994     /* ...textures... */
 995     for (i = 0; i < texstate->count; i++) {
 996         if (!(texstate->tx_enable & (1 << i))) {
 997             continue;
 998         }
 999
1000         tex = r300_texture(texstate->sampler_views[i]->base.texture);
1001         if (!r300_add_texture(r300->rws, tex, tex->domain, 0)) {
1002             r300->context.flush(&r300->context, 0, NULL);
1003             goto validate;
1004         }
1005     }
1006     /* ...occlusion query buffer... */
1007     if (r300->query_current) {
1008         if (!r300->rws->add_buffer(r300->rws, r300->query_current->buffer,
1009                                    0, r300->query_current->domain)) {
1010             r300->context.flush(&r300->context, 0, NULL);
1011             goto validate;
1012         }
1013     }
1014     /* ...vertex buffer for SWTCL path... */
1015     if (r300->vbo) {
1016         if (!r300_add_buffer(r300->rws, r300->vbo,
1017                              r300_buffer(r300->vbo)->domain, 0)) {
1018             r300->context.flush(&r300->context, 0, NULL);
1019             goto validate;
1020         }
1021     }
1022     /* ...vertex buffers for HWTCL path... */
1023     if (do_validate_vertex_buffers) {
1024         for (i = 0; i < r300->velems->count; i++) {
1025             pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1026
1027             if (!r300_add_buffer(r300->rws, pbuf,
1028                                  r300_buffer(pbuf)->domain, 0)) {
1029                 r300->context.flush(&r300->context, 0, NULL);
1030                 goto validate;
1031             }
1032         }
1033     }
1034     /* ...and index buffer for HWTCL path. */
1035     if (index_buffer) {
1036         if (!r300_add_buffer(r300->rws, index_buffer,
1037                              r300_buffer(index_buffer)->domain, 0)) {
1038             r300->context.flush(&r300->context, 0, NULL);
1039             goto validate;
1040         }
1041     }
1042     if (!r300->rws->validate(r300->rws)) {
1043         r300->context.flush(&r300->context, 0, NULL);
1044         if (invalid) {
1045             /* Well, hell. */
1046             fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1047             abort();
1048         }
1049         invalid = TRUE;
1050         goto validate;
1051     }
1052 }
1053
1054 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1055 {
1056     struct r300_atom* atom;
1057     unsigned dwords = 0;
1058
1059     foreach(atom, &r300->atom_list) {
1060         if (atom->dirty) {
1061             dwords += atom->size;
1062         }
1063     }
1064
1065     /* let's reserve some more, just in case */
1066     dwords += 32;
1067
1068     return dwords;
1069 }
1070
1071 /* Emit all dirty state. */
1072 void r300_emit_dirty_state(struct r300_context* r300)
1073 {
1074     struct r300_atom* atom;
1075
1076     foreach(atom, &r300->atom_list) {
1077         if (atom->dirty) {
1078             atom->emit(r300, atom->size, atom->state);
1079             if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1080                 atom->counter++;
1081             }
1082             atom->dirty = FALSE;
1083         }
1084     }
1085
1086     r300->dirty_hw++;
1087 }