2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_simple_list.h"
31 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
48 WRITE_CS_TABLE(blend
->cb
, size
);
50 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
54 void r300_emit_blend_color_state(struct r300_context
* r300
,
55 unsigned size
, void* state
)
57 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
60 WRITE_CS_TABLE(bc
->cb
, size
);
63 void r300_emit_clip_state(struct r300_context
* r300
,
64 unsigned size
, void* state
)
66 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
69 WRITE_CS_TABLE(clip
->cb
, size
);
72 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
74 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
75 struct pipe_framebuffer_state
* fb
=
76 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
80 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
82 WRITE_CS_TABLE(dsa
->cb_no_readwrite
, size
);
86 static const float * get_rc_constant_state(
87 struct r300_context
* r300
,
88 struct rc_constant
* constant
)
90 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
91 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
92 struct pipe_resource
*tex
;
94 assert(constant
->Type
== RC_CONSTANT_STATE
);
96 switch (constant
->u
.State
[0]) {
97 /* Factor for converting rectangle coords to
98 * normalized coords. Should only show up on non-r500. */
99 case RC_STATE_R300_TEXRECT_FACTOR
:
100 tex
= texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
;
101 vec
[0] = 1.0 / tex
->width0
;
102 vec
[1] = 1.0 / tex
->height0
;
105 case RC_STATE_R300_VIEWPORT_SCALE
:
106 vec
[0] = r300
->viewport
.scale
[0];
107 vec
[1] = r300
->viewport
.scale
[1];
108 vec
[2] = r300
->viewport
.scale
[2];
111 case RC_STATE_R300_VIEWPORT_OFFSET
:
112 vec
[0] = r300
->viewport
.translate
[0];
113 vec
[1] = r300
->viewport
.translate
[1];
114 vec
[2] = r300
->viewport
.translate
[2];
118 fprintf(stderr
, "r300: Implementation error: "
119 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
122 /* This should either be (0, 0, 0, 1), which should be a relatively safe
123 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
128 /* Convert a normal single-precision float into the 7.16 format
129 * used by the R300 fragment shader.
131 uint32_t pack_float24(float f
)
139 uint32_t float24
= 0;
146 mantissa
= frexpf(f
, &exponent
);
150 float24
|= (1 << 23);
151 mantissa
= mantissa
* -1.0;
153 /* Handle exponent, bias of 63 */
155 float24
|= (exponent
<< 16);
156 /* Kill 7 LSB of mantissa */
157 float24
|= (u
.u
& 0x7FFFFF) >> 7;
162 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
164 struct r300_fragment_shader
*fs
= r300_fs(r300
);
167 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
170 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
172 struct r300_fragment_shader
*fs
= r300_fs(r300
);
173 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
174 unsigned count
= fs
->shader
->externals_count
;
182 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
183 for (i
= 0; i
< count
; i
++)
184 for (j
= 0; j
< 4; j
++)
185 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
189 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
191 struct r300_fragment_shader
*fs
= r300_fs(r300
);
192 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
194 unsigned count
= fs
->shader
->rc_state_count
;
195 unsigned first
= fs
->shader
->externals_count
;
196 unsigned end
= constants
->Count
;
204 for(i
= first
; i
< end
; ++i
) {
205 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
207 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
209 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
210 for (j
= 0; j
< 4; j
++)
211 OUT_CS(pack_float24(data
[j
]));
217 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
219 struct r300_fragment_shader
*fs
= r300_fs(r300
);
222 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
225 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
227 struct r300_fragment_shader
*fs
= r300_fs(r300
);
228 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
229 unsigned count
= fs
->shader
->externals_count
* 4;
236 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
237 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
);
238 OUT_CS_TABLE(buf
->ptr
, count
);
242 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
244 struct r300_fragment_shader
*fs
= r300_fs(r300
);
245 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
247 unsigned count
= fs
->shader
->rc_state_count
;
248 unsigned first
= fs
->shader
->externals_count
;
249 unsigned end
= constants
->Count
;
256 for(i
= first
; i
< end
; ++i
) {
257 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
259 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
261 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
262 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
263 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
264 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
265 OUT_CS_TABLE(data
, 4);
271 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
273 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
274 struct pipe_framebuffer_state
* fb
=
275 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
276 uint32_t height
= fb
->height
;
277 uint32_t width
= fb
->width
;
280 if (r300
->cbzb_clear
) {
281 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
283 height
= surf
->cbzb_height
;
284 width
= surf
->cbzb_width
;
290 * By writing to the SC registers, SC & US assert idle. */
291 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
292 if (r300
->screen
->caps
.is_r500
) {
294 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
295 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
297 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
298 (1440 << R300_SCISSORS_Y_SHIFT
));
299 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
300 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
303 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
304 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
308 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
310 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
314 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
317 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 1);
318 OUT_CS_RELOC(aa
->dest
->buffer
, aa
->dest
->offset
, 0, aa
->dest
->domain
);
320 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH
, 1);
321 OUT_CS_RELOC(aa
->dest
->buffer
, aa
->dest
->pitch
, 0, aa
->dest
->domain
);
324 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, aa
->aaresolve_ctl
);
328 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
330 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
331 struct r300_surface
* surf
;
333 boolean has_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
338 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
339 * what we usually want. */
340 if (r300
->screen
->caps
.is_r500
) {
341 OUT_CS_REG(R300_RB3D_CCTL
,
342 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
344 OUT_CS_REG(R300_RB3D_CCTL
, 0);
347 /* Set up colorbuffers. */
348 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
349 surf
= r300_surface(fb
->cbufs
[i
]);
351 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
352 OUT_CS_RELOC(surf
->buffer
, surf
->offset
, 0, surf
->domain
);
354 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
355 OUT_CS_RELOC(surf
->buffer
, surf
->pitch
, 0, surf
->domain
);
358 /* Set up the ZB part of the CBZB clear. */
359 if (r300
->cbzb_clear
) {
360 surf
= r300_surface(fb
->cbufs
[0]);
362 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
364 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
365 OUT_CS_RELOC(surf
->buffer
, surf
->cbzb_midpoint_offset
, 0, surf
->domain
);
367 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
368 OUT_CS_RELOC(surf
->buffer
, surf
->cbzb_pitch
, 0, surf
->domain
);
371 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
374 /* Set up a zbuffer. */
375 else if (fb
->zsbuf
) {
376 surf
= r300_surface(fb
->zsbuf
);
378 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
380 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
381 OUT_CS_RELOC(surf
->buffer
, surf
->offset
, 0, surf
->domain
);
383 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
384 OUT_CS_RELOC(surf
->buffer
, surf
->pitch
, 0, surf
->domain
);
388 struct r300_texture
*tex
;
389 int level
= surf
->base
.level
;
390 tex
= r300_texture(surf
->base
.texture
);
392 surf_pitch
= surf
->pitch
& R300_DEPTHPITCH_MASK
;
394 if (r300
->screen
->caps
.hiz_ram
) {
395 if (tex
->hiz_mem
[level
]) {
396 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, tex
->hiz_mem
[level
]->ofs
<< 2);
397 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf_pitch
);
399 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
400 OUT_CS_REG(R300_ZB_HIZ_PITCH
, 0);
403 /* Z Mask RAM. (compressed zbuffer) */
404 if (tex
->zmask_mem
[level
]) {
405 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, tex
->zmask_mem
[level
]->ofs
<< 2);
406 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf_pitch
);
408 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
409 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, 0);
417 void r300_emit_hyperz_state(struct r300_context
*r300
,
418 unsigned size
, void *state
)
420 struct r300_hyperz_state
*z
= state
;
423 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
425 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
428 void r300_emit_hyperz_end(struct r300_context
*r300
)
430 struct r300_hyperz_state z
=
431 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
435 z
.zb_depthclearvalue
= 0;
436 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
437 z
.gb_z_peq_config
= 0;
439 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
442 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
443 unsigned size
, void *state
)
445 struct pipe_framebuffer_state
* fb
=
446 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
452 /* Colorbuffer format in the US block.
453 * (must be written after unpipelined regs) */
454 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
455 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
456 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
459 OUT_CS(R300_US_OUT_FMT_UNUSED
);
462 /* Multisampling. Depends on framebuffer sample count.
463 * These are pipelined regs and as such cannot be moved
464 * to the AA state. */
465 if (r300
->rws
->get_value(r300
->rws
, R300_VID_DRM_2_3_0
)) {
466 unsigned mspos0
= 0x66666666;
467 unsigned mspos1
= 0x6666666;
469 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->texture
->nr_samples
> 1) {
470 /* Subsample placement. These may not be optimal. */
471 switch (fb
->cbufs
[0]->texture
->nr_samples
) {
489 debug_printf("r300: Bad number of multisamples!\n");
493 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
500 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
502 struct r300_query
*query
= r300
->query_current
;
509 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
510 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
512 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
514 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
516 query
->begin_emitted
= TRUE
;
517 query
->flushed
= FALSE
;
520 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
521 struct r300_query
*query
)
523 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
524 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
527 assert(caps
->num_frag_pipes
);
529 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
530 /* I'm not so sure I like this switch, but it's hard to be elegant
531 * when there's so many special cases...
533 * So here's the basic idea. For each pipe, enable writes to it only,
534 * then put out the relocation for ZPASS_ADDR, taking into account a
535 * 4-byte offset for each pipe. RV380 and older are special; they have
536 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
537 * so there's a chipset cap for that. */
538 switch (caps
->num_frag_pipes
) {
541 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
542 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
543 OUT_CS_RELOC(buf
, (query
->num_results
+ 3) * 4,
547 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
548 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
549 OUT_CS_RELOC(buf
, (query
->num_results
+ 2) * 4,
553 /* As mentioned above, accomodate RV380 and older. */
554 OUT_CS_REG(R300_SU_REG_DEST
,
555 1 << (caps
->high_second_pipe
? 3 : 1));
556 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
557 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4,
561 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
562 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
563 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4,
567 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
568 " pixel pipes!\n", caps
->num_frag_pipes
);
572 /* And, finally, reset it to normal... */
573 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
577 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
578 struct r300_query
*query
)
580 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
584 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
585 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
586 OUT_CS_RELOC(buf
, query
->num_results
* 4, 0, query
->domain
);
587 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
591 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
592 struct r300_query
*query
)
594 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
598 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
599 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
600 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4, 0, query
->domain
);
601 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
602 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
603 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4, 0, query
->domain
);
604 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
608 void r300_emit_query_end(struct r300_context
* r300
)
610 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
611 struct r300_query
*query
= r300
->query_current
;
616 if (query
->begin_emitted
== FALSE
)
619 if (caps
->family
== CHIP_FAMILY_RV530
) {
620 if (caps
->num_z_pipes
== 2)
621 rv530_emit_query_end_double_z(r300
, query
);
623 rv530_emit_query_end_single_z(r300
, query
);
625 r300_emit_query_end_frag_pipes(r300
, query
);
627 query
->begin_emitted
= FALSE
;
628 query
->num_results
+= query
->num_pipes
;
630 /* XXX grab all the results and reset the counter. */
631 if (query
->num_results
>= query
->buffer_size
/ 4 - 4) {
632 query
->num_results
= (query
->buffer_size
/ 4) / 2;
633 fprintf(stderr
, "r300: Rewinding OQBO...\n");
637 void r300_emit_invariant_state(struct r300_context
*r300
,
638 unsigned size
, void *state
)
641 WRITE_CS_TABLE(state
, size
);
644 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
646 struct r300_rs_state
* rs
= state
;
650 OUT_CS_TABLE(rs
->cb_main
, 25);
651 if (rs
->polygon_offset_enable
) {
652 if (r300
->zbuffer_bpp
== 16) {
653 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
655 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
661 void r300_emit_rs_block_state(struct r300_context
* r300
,
662 unsigned size
, void* state
)
664 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
666 /* It's the same for both INST and IP tables */
667 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
670 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
671 r500_dump_rs_block(rs
);
673 fprintf(stderr
, "r300: RS emit:\n");
675 for (i
= 0; i
< count
; i
++)
676 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
678 for (i
= 0; i
< count
; i
++)
679 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
681 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
682 rs
->count
, rs
->inst_count
);
686 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
687 OUT_CS(rs
->vap_vtx_state_cntl
);
688 OUT_CS(rs
->vap_vsm_vtx_assm
);
689 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
690 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
691 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
693 if (r300
->screen
->caps
.is_r500
) {
694 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
696 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
698 OUT_CS_TABLE(rs
->ip
, count
);
700 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
702 OUT_CS(rs
->inst_count
);
704 if (r300
->screen
->caps
.is_r500
) {
705 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
707 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
709 OUT_CS_TABLE(rs
->inst
, count
);
713 void r300_emit_scissor_state(struct r300_context
* r300
,
714 unsigned size
, void* state
)
716 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
720 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
721 if (r300
->screen
->caps
.is_r500
) {
722 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
723 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
724 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
725 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
727 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
728 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
729 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
730 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
735 void r300_emit_textures_state(struct r300_context
*r300
,
736 unsigned size
, void *state
)
738 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
739 struct r300_texture_sampler_state
*texstate
;
740 struct r300_texture
*tex
;
745 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
747 for (i
= 0; i
< allstate
->count
; i
++) {
748 if ((1 << i
) & allstate
->tx_enable
) {
749 texstate
= &allstate
->regs
[i
];
750 tex
= r300_texture(allstate
->sampler_views
[i
]->base
.texture
);
752 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
753 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
754 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
755 texstate
->border_color
);
757 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
758 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
759 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
761 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
762 OUT_CS_TEX_RELOC(tex
, texstate
->format
.tile_config
, tex
->domain
,
769 void r300_emit_aos(struct r300_context
* r300
, int offset
, boolean indexed
)
771 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
772 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
773 struct r300_buffer
*buf
;
775 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
776 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
777 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
780 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
781 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
782 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
784 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
785 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
786 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
787 size1
= hw_format_size
[i
];
788 size2
= hw_format_size
[i
+1];
790 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
791 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
792 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
793 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
797 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
798 size1
= hw_format_size
[i
];
800 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
801 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
804 for (i
= 0; i
< aos_count
; i
++) {
805 buf
= r300_buffer(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
806 OUT_CS_BUF_RELOC_NO_OFFSET(&buf
->b
.b
, buf
->domain
, 0);
811 void r300_emit_aos_swtcl(struct r300_context
*r300
, boolean indexed
)
815 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
816 "vertex size %d\n", r300
->vbo
,
817 r300
->vertex_info
.size
);
818 /* Set the pointer to our vertex buffer. The emitted values are this:
819 * PACKET3 [3D_LOAD_VBPNTR]
821 * FORMAT [size | stride << 8]
822 * OFFSET [offset into BO]
823 * VBPNTR [relocated BO]
826 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
827 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
828 OUT_CS(r300
->vertex_info
.size
|
829 (r300
->vertex_info
.size
<< 8));
830 OUT_CS(r300
->vbo_offset
);
831 OUT_CS_BUF_RELOC(r300
->vbo
, 0, r300_buffer(r300
->vbo
)->domain
, 0);
835 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
836 unsigned size
, void* state
)
838 struct r300_vertex_stream_state
*streams
=
839 (struct r300_vertex_stream_state
*)state
;
843 if (DBG_ON(r300
, DBG_PSC
)) {
844 fprintf(stderr
, "r300: PSC emit:\n");
846 for (i
= 0; i
< streams
->count
; i
++) {
847 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
848 streams
->vap_prog_stream_cntl
[i
]);
851 for (i
= 0; i
< streams
->count
; i
++) {
852 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
853 streams
->vap_prog_stream_cntl_ext
[i
]);
858 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
859 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
860 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
861 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
865 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
870 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
874 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
875 unsigned size
, void *state
)
878 WRITE_CS_TABLE(state
, size
);
881 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
883 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
884 struct r300_vertex_program_code
* code
= &vs
->code
;
885 struct r300_screen
* r300screen
= r300
->screen
;
886 unsigned instruction_count
= code
->length
/ 4;
889 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
890 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
891 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
892 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
894 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
895 vtx_mem_size
/ output_count
, 10);
896 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
898 unsigned imm_first
= vs
->externals_count
;
899 unsigned imm_end
= vs
->code
.constants
.Count
;
900 unsigned imm_count
= vs
->immediates_count
;
906 /* R300_VAP_PVS_CODE_CNTL_0
907 * R300_VAP_PVS_CONST_CNTL
908 * R300_VAP_PVS_CODE_CNTL_1
909 * See the r5xx docs for instructions on how to use these. */
910 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
911 OUT_CS(R300_PVS_FIRST_INST(0) |
912 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
913 R300_PVS_LAST_INST(instruction_count
- 1));
914 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
915 OUT_CS(instruction_count
- 1);
917 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
918 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
919 OUT_CS_TABLE(code
->body
.d
, code
->length
);
921 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
922 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
923 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
924 R300_PVS_VF_MAX_VTX_NUM(12) |
925 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
927 /* Emit immediates. */
929 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
930 (r300
->screen
->caps
.is_r500
?
931 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
933 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
934 for (i
= imm_first
; i
< imm_end
; i
++) {
935 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
936 OUT_CS_TABLE(data
, 4);
940 /* Emit flow control instructions. */
941 if (code
->num_fc_ops
) {
943 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
944 if (r300screen
->caps
.is_r500
) {
945 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, code
->num_fc_ops
* 2);
946 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, code
->num_fc_ops
* 2);
948 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, code
->num_fc_ops
);
949 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, code
->num_fc_ops
);
951 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, code
->num_fc_ops
);
952 OUT_CS_TABLE(code
->fc_loop_index
, code
->num_fc_ops
);
958 void r300_emit_vs_constants(struct r300_context
* r300
,
959 unsigned size
, void *state
)
962 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
963 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
970 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
971 (r300
->screen
->caps
.is_r500
?
972 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
973 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
974 OUT_CS_TABLE(buf
->ptr
, count
* 4);
978 void r300_emit_viewport_state(struct r300_context
* r300
,
979 unsigned size
, void* state
)
981 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
985 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
986 OUT_CS_TABLE(&viewport
->xscale
, 6);
987 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
991 static void r300_emit_hiz_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
995 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1002 static void r300_emit_zmask_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
1006 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1013 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1015 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1017 struct pipe_framebuffer_state
*fb
=
1018 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1019 struct r300_hyperz_state
*z
=
1020 (struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
1021 struct r300_screen
* r300screen
= r300
->screen
;
1022 uint32_t stride
, offset
= 0, height
, offset_shift
;
1023 struct r300_texture
* tex
;
1026 tex
= r300_texture(fb
->zsbuf
->texture
);
1028 offset
= tex
->hiz_mem
[fb
->zsbuf
->level
]->ofs
;
1029 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->level
];
1031 /* convert from pixels to 4x4 blocks */
1032 stride
= ALIGN_DIVUP(stride
, 4);
1034 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1035 /* there are 4 blocks per dwords */
1036 stride
= ALIGN_DIVUP(stride
, 4);
1038 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, 4);
1041 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1043 for (i
= 0; i
< height
; i
++) {
1044 offset
= i
* stride
;
1045 offset
<<= offset_shift
;
1046 r300_emit_hiz_line_clear(r300
, offset
, stride
, 0xffffffff);
1048 z
->current_func
= -1;
1050 /* Mark the current zbuffer's hiz ram as in use. */
1051 tex
->hiz_in_use
[fb
->zsbuf
->level
] = TRUE
;
1054 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1056 struct pipe_framebuffer_state
*fb
=
1057 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1058 struct r300_screen
* r300screen
= r300
->screen
;
1059 uint32_t stride
, offset
= 0;
1060 struct r300_texture
* tex
;
1062 int mult
, offset_shift
;
1064 tex
= r300_texture(fb
->zsbuf
->texture
);
1065 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->level
];
1067 offset
= tex
->zmask_mem
[fb
->zsbuf
->level
]->ofs
;
1069 if (r300
->z_compression
== RV350_Z_COMPRESS_88
)
1074 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, mult
);
1077 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1078 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1080 /* okay have width in pixels - divide by block width */
1081 stride
= ALIGN_DIVUP(stride
, mult
);
1082 /* have width in blocks - divide by number of fragment pipes screen width */
1083 /* 16 blocks per dword */
1084 stride
= ALIGN_DIVUP(stride
, 16);
1086 for (i
= 0; i
< height
; i
++) {
1087 offset
= i
* stride
;
1088 offset
<<= offset_shift
;
1089 r300_emit_zmask_line_clear(r300
, offset
, stride
, 0x0);//0xffffffff);
1092 /* Mark the current zbuffer's zmask as in use. */
1093 tex
->zmask_in_use
[fb
->zsbuf
->level
] = TRUE
;
1096 void r300_emit_ztop_state(struct r300_context
* r300
,
1097 unsigned size
, void* state
)
1099 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1103 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1107 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1112 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1116 void r300_emit_buffer_validate(struct r300_context
*r300
,
1117 boolean do_validate_vertex_buffers
,
1118 struct pipe_resource
*index_buffer
)
1120 struct pipe_framebuffer_state
* fb
=
1121 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1122 struct r300_textures_state
*texstate
=
1123 (struct r300_textures_state
*)r300
->textures_state
.state
;
1124 struct r300_texture
* tex
;
1125 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1126 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
1127 struct pipe_resource
*pbuf
;
1129 boolean invalid
= FALSE
;
1131 /* upload buffers first */
1132 if (r300
->screen
->caps
.has_tcl
&& r300
->any_user_vbs
) {
1133 r300_upload_user_buffers(r300
);
1134 r300
->any_user_vbs
= false;
1137 /* Clean out BOs. */
1138 r300
->rws
->cs_reset_buffers(r300
->cs
);
1141 /* Color buffers... */
1142 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1143 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
1144 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
1145 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buffer
, 0,
1146 r300_surface(fb
->cbufs
[i
])->domain
);
1148 /* ...depth buffer... */
1150 tex
= r300_texture(fb
->zsbuf
->texture
);
1151 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
1152 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buffer
, 0,
1153 r300_surface(fb
->zsbuf
)->domain
);
1155 /* ...textures... */
1156 for (i
= 0; i
< texstate
->count
; i
++) {
1157 if (!(texstate
->tx_enable
& (1 << i
))) {
1161 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
1162 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buffer
, tex
->domain
, 0);
1164 /* ...occlusion query buffer... */
1165 if (r300
->query_current
)
1166 r300
->rws
->cs_add_buffer(r300
->cs
, r300
->query_current
->buffer
,
1167 0, r300
->query_current
->domain
);
1168 /* ...vertex buffer for SWTCL path... */
1170 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(r300
->vbo
)->buf
,
1171 r300_buffer(r300
->vbo
)->domain
, 0);
1172 /* ...vertex buffers for HWTCL path... */
1173 if (do_validate_vertex_buffers
) {
1174 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1175 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1177 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(pbuf
)->buf
,
1178 r300_buffer(pbuf
)->domain
, 0);
1181 /* ...and index buffer for HWTCL path. */
1183 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(index_buffer
)->buf
,
1184 r300_buffer(index_buffer
)->domain
, 0);
1186 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1187 r300
->context
.flush(&r300
->context
, 0, NULL
);
1190 fprintf(stderr
, "r300: Stuck in validation loop, gonna quit now.\n");
1198 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1200 struct r300_atom
* atom
;
1201 unsigned dwords
= 0;
1203 foreach(atom
, &r300
->atom_list
) {
1205 dwords
+= atom
->size
;
1209 /* let's reserve some more, just in case */
1215 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1217 unsigned dwords
= 0;
1219 /* Emitted in flush. */
1220 dwords
+= 26; /* emit_query_end */
1221 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1226 /* Emit all dirty state. */
1227 void r300_emit_dirty_state(struct r300_context
* r300
)
1229 struct r300_atom
* atom
;
1231 foreach(atom
, &r300
->atom_list
) {
1233 atom
->emit(r300
, atom
->size
, atom
->state
);
1234 if (SCREEN_DBG_ON(r300
->screen
, DBG_STATS
)) {
1237 atom
->dirty
= FALSE
;