2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
30 #include "r300_context.h"
32 #include "r300_emit.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
38 void r300_emit_blend_state(struct r300_context
* r300
,
39 unsigned size
, void* state
)
41 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
42 struct pipe_framebuffer_state
* fb
=
43 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
47 WRITE_CS_TABLE(blend
->cb
, size
);
49 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
53 void r300_emit_blend_color_state(struct r300_context
* r300
,
54 unsigned size
, void* state
)
56 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
59 WRITE_CS_TABLE(bc
->cb
, size
);
62 void r300_emit_clip_state(struct r300_context
* r300
,
63 unsigned size
, void* state
)
65 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
68 WRITE_CS_TABLE(clip
->cb
, size
);
71 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
73 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
74 struct pipe_framebuffer_state
* fb
=
75 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
79 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
81 WRITE_CS_TABLE(dsa
->cb_no_readwrite
, size
);
85 static const float * get_rc_constant_state(
86 struct r300_context
* r300
,
87 struct rc_constant
* constant
)
89 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
90 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
91 struct pipe_resource
*tex
;
93 assert(constant
->Type
== RC_CONSTANT_STATE
);
95 switch (constant
->u
.State
[0]) {
96 /* Factor for converting rectangle coords to
97 * normalized coords. Should only show up on non-r500. */
98 case RC_STATE_R300_TEXRECT_FACTOR
:
99 tex
= texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
;
100 vec
[0] = 1.0 / tex
->width0
;
101 vec
[1] = 1.0 / tex
->height0
;
104 case RC_STATE_R300_VIEWPORT_SCALE
:
105 vec
[0] = r300
->viewport
.scale
[0];
106 vec
[1] = r300
->viewport
.scale
[1];
107 vec
[2] = r300
->viewport
.scale
[2];
110 case RC_STATE_R300_VIEWPORT_OFFSET
:
111 vec
[0] = r300
->viewport
.translate
[0];
112 vec
[1] = r300
->viewport
.translate
[1];
113 vec
[2] = r300
->viewport
.translate
[2];
117 fprintf(stderr
, "r300: Implementation error: "
118 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
121 /* This should either be (0, 0, 0, 1), which should be a relatively safe
122 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
127 /* Convert a normal single-precision float into the 7.16 format
128 * used by the R300 fragment shader.
130 uint32_t pack_float24(float f
)
138 uint32_t float24
= 0;
145 mantissa
= frexpf(f
, &exponent
);
149 float24
|= (1 << 23);
150 mantissa
= mantissa
* -1.0;
152 /* Handle exponent, bias of 63 */
154 float24
|= (exponent
<< 16);
155 /* Kill 7 LSB of mantissa */
156 float24
|= (u
.u
& 0x7FFFFF) >> 7;
161 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
163 struct r300_fragment_shader
*fs
= r300_fs(r300
);
166 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
169 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
171 struct r300_fragment_shader
*fs
= r300_fs(r300
);
172 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
173 unsigned count
= fs
->shader
->externals_count
* 4;
180 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
);
181 OUT_CS_TABLE(buf
->constants
, count
);
185 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
187 struct r300_fragment_shader
*fs
= r300_fs(r300
);
188 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
190 unsigned count
= fs
->shader
->rc_state_count
;
191 unsigned first
= fs
->shader
->externals_count
;
192 unsigned end
= constants
->Count
;
201 for(i
= first
; i
< end
; ++i
) {
202 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
204 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
206 for (j
= 0; j
< 4; j
++)
207 cdata
[j
] = pack_float24(data
[j
]);
209 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
210 OUT_CS_TABLE(cdata
, 4);
216 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
218 struct r300_fragment_shader
*fs
= r300_fs(r300
);
221 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
224 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
226 struct r300_fragment_shader
*fs
= r300_fs(r300
);
227 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
228 unsigned count
= fs
->shader
->externals_count
* 4;
235 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
236 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
);
237 OUT_CS_TABLE(buf
->constants
, count
);
241 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
243 struct r300_fragment_shader
*fs
= r300_fs(r300
);
244 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
246 unsigned count
= fs
->shader
->rc_state_count
;
247 unsigned first
= fs
->shader
->externals_count
;
248 unsigned end
= constants
->Count
;
255 for(i
= first
; i
< end
; ++i
) {
256 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
258 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
260 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
261 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
262 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
264 OUT_CS_TABLE(data
, 4);
270 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
272 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
273 struct pipe_framebuffer_state
* fb
=
274 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
280 * By writing to the SC registers, SC & US assert idle. */
281 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
282 if (r300
->screen
->caps
.is_r500
) {
284 OUT_CS(((fb
->width
- 1) << R300_SCISSORS_X_SHIFT
) |
285 ((fb
->height
- 1) << R300_SCISSORS_Y_SHIFT
));
287 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
288 (1440 << R300_SCISSORS_Y_SHIFT
));
289 OUT_CS(((fb
->width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
290 ((fb
->height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
293 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
294 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
298 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
300 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
304 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
307 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 1);
308 OUT_CS_RELOC(aa
->dest
->buffer
, aa
->dest
->offset
, 0, aa
->dest
->domain
, 0);
310 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH
, 1);
311 OUT_CS_RELOC(aa
->dest
->buffer
, aa
->dest
->pitch
, 0, aa
->dest
->domain
, 0);
314 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, aa
->aaresolve_ctl
);
318 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
320 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
321 struct r300_surface
* surf
;
327 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
328 * what we usually want. */
329 if (r300
->screen
->caps
.is_r500
) {
330 OUT_CS_REG(R300_RB3D_CCTL
,
331 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
333 OUT_CS_REG(R300_RB3D_CCTL
, 0);
336 /* Set up colorbuffers. */
337 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
338 surf
= r300_surface(fb
->cbufs
[i
]);
340 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
341 OUT_CS_RELOC(surf
->buffer
, surf
->offset
, 0, surf
->domain
, 0);
343 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
344 OUT_CS_RELOC(surf
->buffer
, surf
->pitch
, 0, surf
->domain
, 0);
347 /* Set up a zbuffer. */
349 surf
= r300_surface(fb
->zsbuf
);
351 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
352 OUT_CS_REG(R300_ZB_BW_CNTL
, 0);
354 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
355 OUT_CS_RELOC(surf
->buffer
, surf
->offset
, 0, surf
->domain
, 0);
357 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
358 OUT_CS_RELOC(surf
->buffer
, surf
->pitch
, 0, surf
->domain
, 0);
360 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE
, 0);
363 if (r300
->screen
->caps
.has_hiz
) {
364 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
365 OUT_CS_REG(R300_ZB_HIZ_PITCH
, 0);
368 /* Z Mask RAM. (compressed zbuffer) */
369 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
370 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, 0);
373 /* Colorbuffer format in the US block.
374 * (must be written after unpipelined regs) */
375 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
376 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
377 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
380 OUT_CS(R300_US_OUT_FMT_UNUSED
);
385 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
387 struct r300_query
*query
= r300
->query_current
;
394 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
395 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
397 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
399 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
401 query
->begin_emitted
= TRUE
;
402 query
->flushed
= FALSE
;
405 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
406 struct r300_query
*query
)
408 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
409 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
412 assert(caps
->num_frag_pipes
);
414 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
415 /* I'm not so sure I like this switch, but it's hard to be elegant
416 * when there's so many special cases...
418 * So here's the basic idea. For each pipe, enable writes to it only,
419 * then put out the relocation for ZPASS_ADDR, taking into account a
420 * 4-byte offset for each pipe. RV380 and older are special; they have
421 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
422 * so there's a chipset cap for that. */
423 switch (caps
->num_frag_pipes
) {
426 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
427 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
428 OUT_CS_RELOC(buf
, (query
->num_results
+ 3) * 4,
429 0, query
->domain
, 0);
432 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
433 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
434 OUT_CS_RELOC(buf
, (query
->num_results
+ 2) * 4,
435 0, query
->domain
, 0);
438 /* As mentioned above, accomodate RV380 and older. */
439 OUT_CS_REG(R300_SU_REG_DEST
,
440 1 << (caps
->high_second_pipe
? 3 : 1));
441 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
442 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4,
443 0, query
->domain
, 0);
446 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
447 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
448 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4,
449 0, query
->domain
, 0);
452 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
453 " pixel pipes!\n", caps
->num_frag_pipes
);
457 /* And, finally, reset it to normal... */
458 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
462 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
463 struct r300_query
*query
)
465 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
469 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
470 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
471 OUT_CS_RELOC(buf
, query
->num_results
* 4, 0, query
->domain
, 0);
472 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
476 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
477 struct r300_query
*query
)
479 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
483 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
484 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
485 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4, 0, query
->domain
, 0);
486 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
487 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
488 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4, 0, query
->domain
, 0);
489 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
493 void r300_emit_query_end(struct r300_context
* r300
)
495 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
496 struct r300_query
*query
= r300
->query_current
;
501 if (query
->begin_emitted
== FALSE
)
504 if (caps
->family
== CHIP_FAMILY_RV530
) {
505 if (caps
->num_z_pipes
== 2)
506 rv530_emit_query_end_double_z(r300
, query
);
508 rv530_emit_query_end_single_z(r300
, query
);
510 r300_emit_query_end_frag_pipes(r300
, query
);
512 query
->begin_emitted
= FALSE
;
513 query
->num_results
+= query
->num_pipes
;
515 /* XXX grab all the results and reset the counter. */
516 if (query
->num_results
>= query
->buffer_size
/ 4 - 4) {
517 query
->num_results
= (query
->buffer_size
/ 4) / 2;
518 fprintf(stderr
, "r300: Rewinding OQBO...\n");
522 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
524 struct r300_rs_state
* rs
= state
;
525 struct pipe_framebuffer_state
* fb
= r300
->fb_state
.state
;
527 unsigned mspos0
, mspos1
;
531 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
533 /* Multisampling. Depends on framebuffer sample count. */
534 if (r300
->rws
->get_value(r300
->rws
, R300_VID_DRM_2_3_0
)) {
535 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->texture
->nr_samples
> 1) {
536 /* Subsample placement. These may not be optimal. */
537 switch (fb
->cbufs
[0]->texture
->nr_samples
) {
555 debug_printf("r300: Bad number of multisamples!\n");
556 mspos0
= rs
->multisample_position_0
;
557 mspos1
= rs
->multisample_position_1
;
561 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
565 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
566 OUT_CS(rs
->multisample_position_0
);
567 OUT_CS(rs
->multisample_position_1
);
571 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
572 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
573 OUT_CS(rs
->point_minmax
);
574 OUT_CS(rs
->line_control
);
576 if (rs
->polygon_offset_enable
) {
577 scale
= rs
->depth_scale
* 12;
578 offset
= rs
->depth_offset
;
580 switch (r300
->zbuffer_bpp
) {
589 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
596 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE
, 2);
597 OUT_CS(rs
->polygon_offset_enable
);
598 OUT_CS(rs
->cull_mode
);
599 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
600 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
601 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
602 OUT_CS_REG(R300_SC_CLIP_RULE
, rs
->clip_rule
);
603 OUT_CS_REG(R300_GB_ENABLE
, rs
->stuffing_enable
);
604 OUT_CS_REG_SEQ(R300_GA_POINT_S0
, 4);
605 OUT_CS_32F(rs
->point_texcoord_left
);
606 OUT_CS_32F(rs
->point_texcoord_bottom
);
607 OUT_CS_32F(rs
->point_texcoord_right
);
608 OUT_CS_32F(rs
->point_texcoord_top
);
612 void r300_emit_rs_block_state(struct r300_context
* r300
,
613 unsigned size
, void* state
)
615 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
617 /* It's the same for both INST and IP tables */
618 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
621 if (SCREEN_DBG_ON(r300
->screen
, DBG_DRAW
)) {
622 r500_dump_rs_block(rs
);
625 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
628 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
629 OUT_CS(rs
->vap_vtx_state_cntl
);
630 OUT_CS(rs
->vap_vsm_vtx_assm
);
631 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
632 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
633 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
635 if (r300
->screen
->caps
.is_r500
) {
636 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
638 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
640 OUT_CS_TABLE(rs
->ip
, count
);
641 for (i
= 0; i
< count
; i
++) {
642 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
645 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
647 OUT_CS(rs
->inst_count
);
649 if (r300
->screen
->caps
.is_r500
) {
650 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
652 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
654 OUT_CS_TABLE(rs
->inst
, count
);
655 for (i
= 0; i
< count
; i
++) {
656 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
659 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
660 rs
->count
, rs
->inst_count
);
665 void r300_emit_scissor_state(struct r300_context
* r300
,
666 unsigned size
, void* state
)
668 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
672 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
673 if (r300
->screen
->caps
.is_r500
) {
674 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
675 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
676 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
677 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
679 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
680 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
681 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
682 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
687 void r300_emit_textures_state(struct r300_context
*r300
,
688 unsigned size
, void *state
)
690 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
691 struct r300_texture_sampler_state
*texstate
;
692 struct r300_texture
*tex
;
697 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
699 for (i
= 0; i
< allstate
->count
; i
++) {
700 if ((1 << i
) & allstate
->tx_enable
) {
701 texstate
= &allstate
->regs
[i
];
702 tex
= r300_texture(allstate
->sampler_views
[i
]->base
.texture
);
704 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
705 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
706 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
707 texstate
->border_color
);
709 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
710 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
711 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
713 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
714 OUT_CS_TEX_RELOC(tex
, texstate
->format
.tile_config
, tex
->domain
,
721 void r300_emit_aos(struct r300_context
* r300
, int offset
, boolean indexed
)
723 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
724 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
725 struct r300_buffer
*buf
;
727 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
728 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
729 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
732 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
733 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
734 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
736 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
737 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
738 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
739 size1
= hw_format_size
[i
];
740 size2
= hw_format_size
[i
+1];
742 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
743 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
744 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
745 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
749 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
750 size1
= hw_format_size
[i
];
752 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
753 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
756 for (i
= 0; i
< aos_count
; i
++) {
757 buf
= r300_buffer(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
758 OUT_CS_BUF_RELOC_NO_OFFSET(&buf
->b
.b
, buf
->domain
, 0, 0);
763 void r300_emit_aos_swtcl(struct r300_context
*r300
, boolean indexed
)
767 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
768 "vertex size %d\n", r300
->vbo
,
769 r300
->vertex_info
.size
);
770 /* Set the pointer to our vertex buffer. The emitted values are this:
771 * PACKET3 [3D_LOAD_VBPNTR]
773 * FORMAT [size | stride << 8]
774 * OFFSET [offset into BO]
775 * VBPNTR [relocated BO]
778 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
779 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
780 OUT_CS(r300
->vertex_info
.size
|
781 (r300
->vertex_info
.size
<< 8));
782 OUT_CS(r300
->vbo_offset
);
783 OUT_CS_BUF_RELOC(r300
->vbo
, 0, r300_buffer(r300
->vbo
)->domain
, 0, 0);
787 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
788 unsigned size
, void* state
)
790 struct r300_vertex_stream_state
*streams
=
791 (struct r300_vertex_stream_state
*)state
;
795 DBG(r300
, DBG_DRAW
, "r300: PSC emit:\n");
798 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
799 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
800 for (i
= 0; i
< streams
->count
; i
++) {
801 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
802 streams
->vap_prog_stream_cntl
[i
]);
804 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
805 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
806 for (i
= 0; i
< streams
->count
; i
++) {
807 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
808 streams
->vap_prog_stream_cntl_ext
[i
]);
813 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
818 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
822 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
824 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
825 struct r300_vertex_program_code
* code
= &vs
->code
;
826 struct r300_screen
* r300screen
= r300
->screen
;
827 unsigned instruction_count
= code
->length
/ 4;
830 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
831 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
832 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
833 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
835 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
836 vtx_mem_size
/ output_count
, 10);
837 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
839 unsigned imm_first
= vs
->externals_count
;
840 unsigned imm_end
= vs
->code
.constants
.Count
;
841 unsigned imm_count
= vs
->immediates_count
;
846 /* Amount of time to wait for vertex fetches in PVS */
847 OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG
, 0xffff);
849 OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ
, 4);
855 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL
, R300_SGN_NORM_NO_ZERO
);
857 /* R300_VAP_PVS_CODE_CNTL_0
858 * R300_VAP_PVS_CONST_CNTL
859 * R300_VAP_PVS_CODE_CNTL_1
860 * See the r5xx docs for instructions on how to use these. */
861 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
862 OUT_CS(R300_PVS_FIRST_INST(0) |
863 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
864 R300_PVS_LAST_INST(instruction_count
- 1));
865 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
866 OUT_CS(instruction_count
- 1);
868 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
869 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
870 OUT_CS_TABLE(code
->body
.d
, code
->length
);
872 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
873 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
874 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
875 R300_PVS_VF_MAX_VTX_NUM(12) |
876 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
878 /* Emit immediates. */
880 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
881 (r300
->screen
->caps
.is_r500
?
882 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
884 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
885 for (i
= imm_first
; i
< imm_end
; i
++) {
886 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
887 OUT_CS_TABLE(data
, 4);
893 void r300_emit_vs_constants(struct r300_context
* r300
,
894 unsigned size
, void *state
)
897 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
898 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
905 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
906 (r300
->screen
->caps
.is_r500
?
907 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
908 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
909 OUT_CS_TABLE(buf
->constants
, count
* 4);
913 void r300_emit_viewport_state(struct r300_context
* r300
,
914 unsigned size
, void* state
)
916 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
920 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
921 OUT_CS_TABLE(&viewport
->xscale
, 6);
922 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
926 void r300_emit_ztop_state(struct r300_context
* r300
,
927 unsigned size
, void* state
)
929 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
933 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
937 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
942 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
946 void r300_emit_buffer_validate(struct r300_context
*r300
,
947 boolean do_validate_vertex_buffers
,
948 struct pipe_resource
*index_buffer
)
950 struct pipe_framebuffer_state
* fb
=
951 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
952 struct r300_textures_state
*texstate
=
953 (struct r300_textures_state
*)r300
->textures_state
.state
;
954 struct r300_texture
* tex
;
955 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
956 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
957 struct pipe_resource
*pbuf
;
959 boolean invalid
= FALSE
;
961 /* upload buffers first */
962 if (r300
->screen
->caps
.has_tcl
&& r300
->any_user_vbs
) {
963 r300_upload_user_buffers(r300
);
964 r300
->any_user_vbs
= false;
968 r300
->rws
->reset_bos(r300
->rws
);
971 /* Color buffers... */
972 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
973 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
974 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
975 if (!r300_add_texture(r300
->rws
, tex
, 0, tex
->domain
)) {
976 r300
->context
.flush(&r300
->context
, 0, NULL
);
980 /* ...depth buffer... */
982 tex
= r300_texture(fb
->zsbuf
->texture
);
983 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
984 if (!r300_add_texture(r300
->rws
, tex
,
986 r300
->context
.flush(&r300
->context
, 0, NULL
);
991 for (i
= 0; i
< texstate
->count
; i
++) {
992 if (!(texstate
->tx_enable
& (1 << i
))) {
996 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
997 if (!r300_add_texture(r300
->rws
, tex
, tex
->domain
, 0)) {
998 r300
->context
.flush(&r300
->context
, 0, NULL
);
1002 /* ...occlusion query buffer... */
1003 if (r300
->query_current
) {
1004 if (!r300
->rws
->add_buffer(r300
->rws
, r300
->query_current
->buffer
,
1005 0, r300
->query_current
->domain
)) {
1006 r300
->context
.flush(&r300
->context
, 0, NULL
);
1010 /* ...vertex buffer for SWTCL path... */
1012 if (!r300_add_buffer(r300
->rws
, r300
->vbo
,
1013 r300_buffer(r300
->vbo
)->domain
, 0)) {
1014 r300
->context
.flush(&r300
->context
, 0, NULL
);
1018 /* ...vertex buffers for HWTCL path... */
1019 if (do_validate_vertex_buffers
) {
1020 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1021 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1023 if (!r300_add_buffer(r300
->rws
, pbuf
,
1024 r300_buffer(pbuf
)->domain
, 0)) {
1025 r300
->context
.flush(&r300
->context
, 0, NULL
);
1030 /* ...and index buffer for HWTCL path. */
1032 if (!r300_add_buffer(r300
->rws
, index_buffer
,
1033 r300_buffer(index_buffer
)->domain
, 0)) {
1034 r300
->context
.flush(&r300
->context
, 0, NULL
);
1038 if (!r300
->rws
->validate(r300
->rws
)) {
1039 r300
->context
.flush(&r300
->context
, 0, NULL
);
1042 fprintf(stderr
, "r300: Stuck in validation loop, gonna quit now.\n");
1050 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1052 struct r300_atom
* atom
;
1053 unsigned dwords
= 0;
1055 foreach(atom
, &r300
->atom_list
) {
1057 dwords
+= atom
->size
;
1061 /* let's reserve some more, just in case */
1067 /* Emit all dirty state. */
1068 void r300_emit_dirty_state(struct r300_context
* r300
)
1070 struct r300_atom
* atom
;
1072 foreach(atom
, &r300
->atom_list
) {
1074 atom
->emit(r300
, atom
->size
, atom
->state
);
1075 if (SCREEN_DBG_ON(r300
->screen
, DBG_STATS
)) {
1078 atom
->dirty
= FALSE
;