src/gallium/drivers/r300/r300_emit.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 /* r300_emit: Functions for emitting state. */
  24
  25 #include "util/u_math.h"
  26
  27 #include "r300_context.h"
  28 #include "r300_cs.h"
  29 #include "r300_emit.h"
  30 #include "r300_fs.h"
  31 #include "r300_screen.h"
  32 #include "r300_state_derived.h"
  33 #include "r300_state_inlines.h"
  34 #include "r300_texture.h"
  35 #include "r300_vs.h"
  36
  37 void r300_emit_blend_state(struct r300_context* r300,
  38                            struct r300_blend_state* blend)
  39 {
  40     CS_LOCALS(r300);
  41     BEGIN_CS(8);
  42     OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
  43     OUT_CS(blend->blend_control);
  44     OUT_CS(blend->alpha_blend_control);
  45     OUT_CS(blend->color_channel_mask);
  46     OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
  47     OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
  48     END_CS;
  49 }
  50
  51 void r300_emit_blend_color_state(struct r300_context* r300,
  52                                  struct r300_blend_color_state* bc)
  53 {
  54     struct r300_screen* r300screen = r300_screen(r300->context.screen);
  55     CS_LOCALS(r300);
  56
  57     if (r300screen->caps->is_r500) {
  58         BEGIN_CS(3);
  59         OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
  60         OUT_CS(bc->blend_color_red_alpha);
  61         OUT_CS(bc->blend_color_green_blue);
  62         END_CS;
  63     } else {
  64         BEGIN_CS(2);
  65         OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
  66         END_CS;
  67     }
  68 }
  69
  70 void r300_emit_clip_state(struct r300_context* r300,
  71                           struct pipe_clip_state* clip)
  72 {
  73     int i;
  74     struct r300_screen* r300screen = r300_screen(r300->context.screen);
  75     CS_LOCALS(r300);
  76
  77     if (r300screen->caps->has_tcl) {
  78         BEGIN_CS(5 + (6 * 4));
  79         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
  80                 (r300screen->caps->is_r500 ?
  81                  R500_PVS_UCP_START : R300_PVS_UCP_START));
  82         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
  83         for (i = 0; i < 6; i++) {
  84             OUT_CS_32F(clip->ucp[i][0]);
  85             OUT_CS_32F(clip->ucp[i][1]);
  86             OUT_CS_32F(clip->ucp[i][2]);
  87             OUT_CS_32F(clip->ucp[i][3]);
  88         }
  89         OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
  90                 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
  91         END_CS;
  92     } else {
  93         BEGIN_CS(2);
  94         OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
  95         END_CS;
  96     }
  97
  98 }
  99
 100 void r300_emit_dsa_state(struct r300_context* r300,
 101                            struct r300_dsa_state* dsa)
 102 {
 103     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 104     CS_LOCALS(r300);
 105
 106     BEGIN_CS(r300screen->caps->is_r500 ? 10 : 8);
 107     OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
 108
 109     /* not needed since we use the 8bit alpha ref */
 110     /*if (r300screen->caps->is_r500) {
 111         OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
 112     }*/
 113
 114     OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
 115     OUT_CS(dsa->z_buffer_control);
 116     OUT_CS(dsa->z_stencil_control);
 117     OUT_CS(dsa->stencil_ref_mask);
 118     OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
 119
 120     /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
 121     if (r300screen->caps->is_r500) {
 122         OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
 123     }
 124     END_CS;
 125 }
 126
 127 static const float * get_shader_constant(
 128     struct r300_context * r300,
 129     struct rc_constant * constant,
 130     struct r300_constant_buffer * externals)
 131 {
 132     static float vec[4] = { 0.0, 0.0, 0.0, 0.0 };
 133     struct pipe_texture *tex;
 134
 135     switch(constant->Type) {
 136         case RC_CONSTANT_EXTERNAL:
 137             return externals->constants[constant->u.External];
 138
 139         case RC_CONSTANT_IMMEDIATE:
 140             return constant->u.Immediate;
 141
 142         case RC_CONSTANT_STATE:
 143             switch (constant->u.State[0])
 144             {
 145                 /* R3xx-specific */
 146                 case RC_STATE_R300_TEXRECT_FACTOR:
 147                     tex = &r300->textures[constant->u.State[1]]->tex;
 148                     vec[0] = 1.0 / tex->width[0];
 149                     vec[1] = 1.0 / tex->height[0];
 150                     vec[2] = vec[3] = 1;
 151                     break;
 152
 153                 default:
 154                     assert(0);
 155             }
 156             return vec;
 157
 158         default:
 159             debug_printf("r300: Implementation error: Unhandled constant type %i\n",
 160                 constant->Type);
 161             return vec;
 162     }
 163 }
 164
 165 /* Convert a normal single-precision float into the 7.16 format
 166  * used by the R300 fragment shader.
 167  */
 168 static uint32_t pack_float24(float f)
 169 {
 170     union {
 171         float fl;
 172         uint32_t u;
 173     } u;
 174     float mantissa;
 175     int exponent;
 176     uint32_t float24 = 0;
 177
 178     if (f == 0.0)
 179         return 0;
 180
 181     u.fl = f;
 182
 183     mantissa = frexpf(f, &exponent);
 184
 185     /* Handle -ve */
 186     if (mantissa < 0) {
 187         float24 |= (1 << 23);
 188         mantissa = mantissa * -1.0;
 189     }
 190     /* Handle exponent, bias of 63 */
 191     exponent += 62;
 192     float24 |= (exponent << 16);
 193     /* Kill 7 LSB of mantissa */
 194     float24 |= (u.u & 0x7FFFFF) >> 7;
 195
 196     return float24;
 197 }
 198
 199 void r300_emit_fragment_program_code(struct r300_context* r300,
 200                                      struct rX00_fragment_program_code* generic_code)
 201 {
 202     struct r300_fragment_program_code * code = &generic_code->code.r300;
 203     int i;
 204     CS_LOCALS(r300);
 205
 206     BEGIN_CS(15 +
 207              code->alu.length * 4 +
 208              (code->tex.length ? (1 + code->tex.length) : 0));
 209
 210     OUT_CS_REG(R300_US_CONFIG, code->config);
 211     OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
 212     OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
 213
 214     OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
 215     for(i = 0; i < 4; ++i)
 216         OUT_CS(code->code_addr[i]);
 217
 218     OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
 219     for (i = 0; i < code->alu.length; i++)
 220         OUT_CS(code->alu.inst[i].rgb_inst);
 221
 222     OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
 223     for (i = 0; i < code->alu.length; i++)
 224         OUT_CS(code->alu.inst[i].rgb_addr);
 225
 226     OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
 227     for (i = 0; i < code->alu.length; i++)
 228         OUT_CS(code->alu.inst[i].alpha_inst);
 229
 230     OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
 231     for (i = 0; i < code->alu.length; i++)
 232         OUT_CS(code->alu.inst[i].alpha_addr);
 233
 234     if (code->tex.length) {
 235         OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
 236         for(i = 0; i < code->tex.length; ++i)
 237             OUT_CS(code->tex.inst[i]);
 238     }
 239
 240     END_CS;
 241 }
 242
 243 void r300_emit_fs_constant_buffer(struct r300_context* r300,
 244                                   struct rc_constant_list* constants)
 245 {
 246     int i;
 247     CS_LOCALS(r300);
 248
 249     if (constants->Count == 0)
 250         return;
 251
 252     BEGIN_CS(constants->Count * 4 + 1);
 253     OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
 254     for(i = 0; i < constants->Count; ++i) {
 255         const float * data = get_shader_constant(r300,
 256                                                  &constants->Constants[i],
 257                                                  &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
 258         OUT_CS(pack_float24(data[0]));
 259         OUT_CS(pack_float24(data[1]));
 260         OUT_CS(pack_float24(data[2]));
 261         OUT_CS(pack_float24(data[3]));
 262     }
 263     END_CS;
 264 }
 265
 266 void r500_emit_fragment_program_code(struct r300_context* r300,
 267                                      struct rX00_fragment_program_code* generic_code)
 268 {
 269     struct r500_fragment_program_code * code = &generic_code->code.r500;
 270     int i;
 271     CS_LOCALS(r300);
 272
 273     BEGIN_CS(13 +
 274              ((code->inst_end + 1) * 6));
 275     OUT_CS_REG(R500_US_CONFIG, 0);
 276     OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
 277     OUT_CS_REG(R500_US_CODE_RANGE,
 278                R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
 279     OUT_CS_REG(R500_US_CODE_OFFSET, 0);
 280     OUT_CS_REG(R500_US_CODE_ADDR,
 281                R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
 282
 283     OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
 284     OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
 285     for (i = 0; i <= code->inst_end; i++) {
 286         OUT_CS(code->inst[i].inst0);
 287         OUT_CS(code->inst[i].inst1);
 288         OUT_CS(code->inst[i].inst2);
 289         OUT_CS(code->inst[i].inst3);
 290         OUT_CS(code->inst[i].inst4);
 291         OUT_CS(code->inst[i].inst5);
 292     }
 293
 294     END_CS;
 295 }
 296
 297 void r500_emit_fs_constant_buffer(struct r300_context* r300,
 298                                   struct rc_constant_list* constants)
 299 {
 300     int i;
 301     CS_LOCALS(r300);
 302
 303     if (constants->Count == 0)
 304         return;
 305
 306     BEGIN_CS(constants->Count * 4 + 3);
 307     OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
 308     OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
 309     for (i = 0; i < constants->Count; i++) {
 310         const float * data = get_shader_constant(r300,
 311                                                  &constants->Constants[i],
 312                                                  &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
 313         OUT_CS_32F(data[0]);
 314         OUT_CS_32F(data[1]);
 315         OUT_CS_32F(data[2]);
 316         OUT_CS_32F(data[3]);
 317     }
 318     END_CS;
 319 }
 320
 321 void r300_emit_fb_state(struct r300_context* r300,
 322                         struct pipe_framebuffer_state* fb)
 323 {
 324     struct r300_texture* tex;
 325     struct pipe_surface* surf;
 326     int i;
 327     CS_LOCALS(r300);
 328
 329     BEGIN_CS((10 * fb->nr_cbufs) + (fb->zsbuf ? 10 : 0) + 4);
 330     OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 331         R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 332         R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 333     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 334         R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 335         R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 336
 337     for (i = 0; i < fb->nr_cbufs; i++) {
 338         surf = fb->cbufs[i];
 339         tex = (struct r300_texture*)surf->texture;
 340         assert(tex && tex->buffer && "cbuf is marked, but NULL!");
 341
 342         OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
 343         OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 344
 345         OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
 346         OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
 347                      r300_translate_colorformat(tex->tex.format), 0,
 348                      RADEON_GEM_DOMAIN_VRAM, 0);
 349
 350         OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
 351             r300_translate_out_fmt(surf->format));
 352     }
 353
 354     if (fb->zsbuf) {
 355         surf = fb->zsbuf;
 356         tex = (struct r300_texture*)surf->texture;
 357         assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
 358
 359         OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
 360         OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 361
 362         OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
 363
 364         OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
 365         OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
 366                      RADEON_GEM_DOMAIN_VRAM, 0);
 367     }
 368
 369     END_CS;
 370 }
 371
 372 static void r300_emit_query_start(struct r300_context *r300)
 373 {
 374     struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
 375     struct r300_query *query = r300->query_current;
 376     CS_LOCALS(r300);
 377
 378     if (!query)
 379         return;
 380
 381     /* XXX This will almost certainly not return good results
 382      * for overlapping queries. */
 383     BEGIN_CS(4);
 384     if (caps->family == CHIP_FAMILY_RV530) {
 385         OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 386     } else {
 387         OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 388     }
 389     OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
 390     END_CS;
 391     query->begin_emitted = TRUE;
 392 }
 393
 394
 395 static void r300_emit_query_finish(struct r300_context *r300,
 396                                    struct r300_query *query)
 397 {
 398     struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
 399     CS_LOCALS(r300);
 400
 401     assert(caps->num_frag_pipes);
 402
 403     BEGIN_CS(6 * caps->num_frag_pipes + 2);
 404     /* I'm not so sure I like this switch, but it's hard to be elegant
 405      * when there's so many special cases...
 406      *
 407      * So here's the basic idea. For each pipe, enable writes to it only,
 408      * then put out the relocation for ZPASS_ADDR, taking into account a
 409      * 4-byte offset for each pipe. RV380 and older are special; they have
 410      * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
 411      * so there's a chipset cap for that. */
 412     switch (caps->num_frag_pipes) {
 413         case 4:
 414             /* pipe 3 only */
 415             OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
 416             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 417             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
 418                     0, RADEON_GEM_DOMAIN_GTT, 0);
 419         case 3:
 420             /* pipe 2 only */
 421             OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
 422             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 423             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
 424                     0, RADEON_GEM_DOMAIN_GTT, 0);
 425         case 2:
 426             /* pipe 1 only */
 427             /* As mentioned above, accomodate RV380 and older. */
 428             OUT_CS_REG(R300_SU_REG_DEST,
 429                     1 << (caps->high_second_pipe ? 3 : 1));
 430             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 431             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
 432                     0, RADEON_GEM_DOMAIN_GTT, 0);
 433         case 1:
 434             /* pipe 0 only */
 435             OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
 436             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 437             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
 438                     0, RADEON_GEM_DOMAIN_GTT, 0);
 439             break;
 440         default:
 441             debug_printf("r300: Implementation error: Chipset reports %d"
 442                     " pixel pipes!\n", caps->num_frag_pipes);
 443             assert(0);
 444     }
 445
 446     /* And, finally, reset it to normal... */
 447     OUT_CS_REG(R300_SU_REG_DEST, 0xF);
 448     END_CS;
 449 }
 450
 451 static void rv530_emit_query_single(struct r300_context *r300,
 452                                     struct r300_query *query)
 453 {
 454     CS_LOCALS(r300);
 455
 456     BEGIN_CS(8);
 457     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 458     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 459     OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 460     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 461     END_CS;
 462 }
 463
 464 static void rv530_emit_query_double(struct r300_context *r300,
 465                                     struct r300_query *query)
 466 {
 467     CS_LOCALS(r300);
 468
 469     BEGIN_CS(14);
 470     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 471     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 472     OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 473     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 474     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 475     OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 476     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 477     END_CS;
 478 }
 479
 480 void r300_emit_query_end(struct r300_context* r300)
 481 {
 482     struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
 483     struct r300_query *query = r300->query_current;
 484
 485     if (!query)
 486         return;
 487
 488     if (query->begin_emitted == FALSE)
 489         return;
 490
 491     if (caps->family == CHIP_FAMILY_RV530) {
 492         if (caps->num_z_pipes == 2)
 493             rv530_emit_query_double(r300, query);
 494         else
 495             rv530_emit_query_single(r300, query);
 496     } else
 497         r300_emit_query_finish(r300, query);
 498 }
 499
 500 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
 501 {
 502     CS_LOCALS(r300);
 503
 504     BEGIN_CS(22);
 505     OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
 506     OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
 507     OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
 508     OUT_CS(rs->point_minmax);
 509     OUT_CS(rs->line_control);
 510     OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
 511     OUT_CS(rs->depth_scale_front);
 512     OUT_CS(rs->depth_offset_front);
 513     OUT_CS(rs->depth_scale_back);
 514     OUT_CS(rs->depth_offset_back);
 515     OUT_CS(rs->polygon_offset_enable);
 516     OUT_CS(rs->cull_mode);
 517     OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
 518     OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
 519     OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
 520     OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
 521     END_CS;
 522 }
 523
 524 void r300_emit_rs_block_state(struct r300_context* r300,
 525                               struct r300_rs_block* rs)
 526 {
 527     int i;
 528     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 529     CS_LOCALS(r300);
 530
 531     DBG(r300, DBG_DRAW, "r300: RS emit:\n");
 532
 533     BEGIN_CS(21);
 534     if (r300screen->caps->is_r500) {
 535         OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
 536     } else {
 537         OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
 538     }
 539     for (i = 0; i < 8; i++) {
 540         OUT_CS(rs->ip[i]);
 541         DBG(r300, DBG_DRAW, "    : ip %d: 0x%08x\n", i, rs->ip[i]);
 542     }
 543
 544     OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 545     OUT_CS(rs->count);
 546     OUT_CS(rs->inst_count);
 547
 548     if (r300screen->caps->is_r500) {
 549         OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
 550     } else {
 551         OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
 552     }
 553     for (i = 0; i < 8; i++) {
 554         OUT_CS(rs->inst[i]);
 555         DBG(r300, DBG_DRAW, "    : inst %d: 0x%08x\n", i, rs->inst[i]);
 556     }
 557
 558     DBG(r300, DBG_DRAW, "    : count: 0x%08x inst_count: 0x%08x\n",
 559         rs->count, rs->inst_count);
 560
 561     END_CS;
 562 }
 563
 564 void r300_emit_scissor_state(struct r300_context* r300,
 565                              struct r300_scissor_state* scissor)
 566 {
 567     CS_LOCALS(r300);
 568
 569     BEGIN_CS(3);
 570     OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
 571     OUT_CS(scissor->scissor_top_left);
 572     OUT_CS(scissor->scissor_bottom_right);
 573     END_CS;
 574 }
 575
 576 void r300_emit_texture(struct r300_context* r300,
 577                        struct r300_sampler_state* sampler,
 578                        struct r300_texture* tex,
 579                        unsigned offset)
 580 {
 581     uint32_t filter0 = sampler->filter0;
 582     CS_LOCALS(r300);
 583
 584     /* to emulate 1D textures through 2D ones correctly */
 585     if (tex->tex.target == PIPE_TEXTURE_1D) {
 586         filter0 &= ~R300_TX_WRAP_T_MASK;
 587         filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
 588     }
 589
 590     BEGIN_CS(16);
 591     OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
 592         (offset << 28));
 593     OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
 594     OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
 595
 596     OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), tex->state.format0);
 597     OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
 598     OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
 599     OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
 600     OUT_CS_RELOC(tex->buffer, 0,
 601             RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
 602     END_CS;
 603 }
 604
 605 /* XXX I can't read this and that's not good */
 606 void r300_emit_aos(struct r300_context* r300, unsigned offset)
 607 {
 608     struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
 609     struct pipe_vertex_element *velem = r300->vertex_element;
 610     CS_LOCALS(r300);
 611     int i;
 612     unsigned aos_count = r300->vertex_element_count;
 613
 614     unsigned packet_size = (aos_count * 3 + 1) / 2;
 615     BEGIN_CS(2 + packet_size + aos_count * 2);
 616     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
 617     OUT_CS(aos_count);
 618     for (i = 0; i < aos_count - 1; i += 2) {
 619         int buf_num1 = velem[i].vertex_buffer_index;
 620         int buf_num2 = velem[i+1].vertex_buffer_index;
 621         assert(vbuf[buf_num1].stride % 4 == 0 && pf_get_size(velem[i].src_format) % 4 == 0);
 622         assert(vbuf[buf_num2].stride % 4 == 0 && pf_get_size(velem[i+1].src_format) % 4 == 0);
 623         OUT_CS((pf_get_size(velem[i].src_format) >> 2) | (vbuf[buf_num1].stride << 6) |
 624                (pf_get_size(velem[i+1].src_format) << 14) | (vbuf[buf_num2].stride << 22));
 625         OUT_CS(vbuf[buf_num1].buffer_offset + velem[i].src_offset +
 626                offset * vbuf[buf_num1].stride);
 627         OUT_CS(vbuf[buf_num2].buffer_offset + velem[i+1].src_offset +
 628                offset * vbuf[buf_num2].stride);
 629     }
 630     if (aos_count & 1) {
 631         int buf_num = velem[i].vertex_buffer_index;
 632         assert(vbuf[buf_num].stride % 4 == 0 && pf_get_size(velem[i].src_format) % 4 == 0);
 633         OUT_CS((pf_get_size(velem[i].src_format) >> 2) | (vbuf[buf_num].stride << 6));
 634         OUT_CS(vbuf[buf_num].buffer_offset + velem[i].src_offset +
 635                offset * vbuf[buf_num].stride);
 636     }
 637
 638     /* XXX bare CS reloc */
 639     for (i = 0; i < aos_count; i++) {
 640         cs_winsys->write_cs_reloc(cs_winsys,
 641                                   vbuf[velem[i].vertex_buffer_index].buffer,
 642                                   RADEON_GEM_DOMAIN_GTT,
 643                                   0,
 644                                   0);
 645         cs_count -= 2;
 646     }
 647     END_CS;
 648 }
 649 #if 0
 650 void r300_emit_draw_packet(struct r300_context* r300)
 651 {
 652     CS_LOCALS(r300);
 653
 654     DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
 655             "vertex size %d\n", r300->vbo,
 656             r300->vertex_info->vinfo.size);
 657     /* Set the pointer to our vertex buffer. The emitted values are this:
 658      * PACKET3 [3D_LOAD_VBPNTR]
 659      * COUNT   [1]
 660      * FORMAT  [size | stride << 8]
 661      * OFFSET  [offset into BO]
 662      * VBPNTR  [relocated BO]
 663      */
 664     BEGIN_CS(7);
 665     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
 666     OUT_CS(1);
 667     OUT_CS(r300->vertex_info->vinfo.size |
 668             (r300->vertex_info->vinfo.size << 8));
 669     OUT_CS(r300->vbo_offset);
 670     OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
 671     END_CS;
 672 }
 673 #endif
 674
 675 void r300_emit_vertex_format_state(struct r300_context* r300)
 676 {
 677     int i;
 678     CS_LOCALS(r300);
 679
 680     DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
 681
 682     BEGIN_CS(26);
 683     OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
 684
 685     OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
 686     OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
 687     OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
 688     OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 689     OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
 690     OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
 691     for (i = 0; i < 4; i++) {
 692        DBG(r300, DBG_DRAW, "    : hwfmt%d: 0x%08x\n", i,
 693                r300->vertex_info->vinfo.hwfmt[i]);
 694     }
 695
 696     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
 697     for (i = 0; i < 8; i++) {
 698         OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
 699         DBG(r300, DBG_DRAW, "    : prog_stream_cntl%d: 0x%08x\n", i,
 700                r300->vertex_info->vap_prog_stream_cntl[i]);
 701     }
 702     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
 703     for (i = 0; i < 8; i++) {
 704         OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
 705         DBG(r300, DBG_DRAW, "    : prog_stream_cntl_ext%d: 0x%08x\n", i,
 706                r300->vertex_info->vap_prog_stream_cntl_ext[i]);
 707     }
 708     END_CS;
 709 }
 710
 711 /* XXX This should go to util ... */
 712 /* Return the number of bits set in the given number. */
 713 static unsigned bitcount(unsigned n)
 714 {
 715     unsigned bits = 0;
 716
 717     while (n) {
 718         if (n & 1) {
 719             bits++;
 720         }
 721         n >>= 1;
 722     }
 723
 724     return bits;
 725 }
 726
 727 void r300_emit_vertex_program_code(struct r300_context* r300,
 728                                    struct r300_vertex_program_code* code)
 729 {
 730     int i;
 731     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 732     unsigned instruction_count = code->length / 4;
 733
 734     int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
 735     int input_count = MAX2(bitcount(code->InputsRead), 1);
 736     int output_count = MAX2(bitcount(code->OutputsWritten), 1);
 737     int temp_count = MAX2(code->num_temporaries, 1);
 738     int pvs_num_slots = MIN3(vtx_mem_size / input_count,
 739                              vtx_mem_size / output_count, 10);
 740     int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
 741
 742     CS_LOCALS(r300);
 743
 744     if (!r300screen->caps->has_tcl) {
 745         debug_printf("r300: Implementation error: emit_vertex_shader called,"
 746                 " but has_tcl is FALSE!\n");
 747         return;
 748     }
 749
 750     BEGIN_CS(9 + code->length);
 751     /* R300_VAP_PVS_CODE_CNTL_0
 752      * R300_VAP_PVS_CONST_CNTL
 753      * R300_VAP_PVS_CODE_CNTL_1
 754      * See the r5xx docs for instructions on how to use these. */
 755     OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
 756     OUT_CS(R300_PVS_FIRST_INST(0) |
 757             R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
 758             R300_PVS_LAST_INST(instruction_count - 1));
 759     OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
 760     OUT_CS(instruction_count - 1);
 761
 762     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
 763     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
 764     for (i = 0; i < code->length; i++)
 765         OUT_CS(code->body.d[i]);
 766
 767     OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
 768             R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
 769             R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
 770             R300_PVS_VF_MAX_VTX_NUM(12) |
 771             (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
 772     END_CS;
 773 }
 774
 775 void r300_emit_vertex_shader(struct r300_context* r300,
 776                              struct r300_vertex_shader* vs)
 777 {
 778     r300_emit_vertex_program_code(r300, &vs->code);
 779 }
 780
 781 void r300_emit_vs_constant_buffer(struct r300_context* r300,
 782                                   struct rc_constant_list* constants)
 783 {
 784     int i;
 785     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 786     CS_LOCALS(r300);
 787
 788     if (!r300screen->caps->has_tcl) {
 789         debug_printf("r300: Implementation error: emit_vertex_shader called,"
 790         " but has_tcl is FALSE!\n");
 791         return;
 792     }
 793
 794     if (constants->Count == 0)
 795         return;
 796
 797     BEGIN_CS(constants->Count * 4 + 3);
 798     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
 799                (r300screen->caps->is_r500 ?
 800                R500_PVS_CONST_START : R300_PVS_CONST_START));
 801     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
 802     for (i = 0; i < constants->Count; i++) {
 803         const float * data = get_shader_constant(r300,
 804                                                  &constants->Constants[i],
 805                                                  &r300->shader_constants[PIPE_SHADER_VERTEX]);
 806         OUT_CS_32F(data[0]);
 807         OUT_CS_32F(data[1]);
 808         OUT_CS_32F(data[2]);
 809         OUT_CS_32F(data[3]);
 810     }
 811     END_CS;
 812 }
 813
 814 void r300_emit_viewport_state(struct r300_context* r300,
 815                               struct r300_viewport_state* viewport)
 816 {
 817     CS_LOCALS(r300);
 818
 819     BEGIN_CS(9);
 820     OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
 821     OUT_CS_32F(viewport->xscale);
 822     OUT_CS_32F(viewport->xoffset);
 823     OUT_CS_32F(viewport->yscale);
 824     OUT_CS_32F(viewport->yoffset);
 825     OUT_CS_32F(viewport->zscale);
 826     OUT_CS_32F(viewport->zoffset);
 827
 828     if (r300->rs_state->enable_vte) {
 829         OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
 830     } else {
 831         OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
 832     }
 833     END_CS;
 834 }
 835
 836 void r300_flush_textures(struct r300_context* r300)
 837 {
 838     CS_LOCALS(r300);
 839
 840     BEGIN_CS(4);
 841     OUT_CS_REG(R300_TX_INVALTAGS, 0);
 842     OUT_CS_REG(R300_TX_ENABLE, (1 << r300->texture_count) - 1);
 843     END_CS;
 844 }
 845
 846 static void r300_flush_pvs(struct r300_context* r300)
 847 {
 848     CS_LOCALS(r300);
 849
 850     BEGIN_CS(2);
 851     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
 852     END_CS;
 853 }
 854
 855 /* Emit all dirty state. */
 856 void r300_emit_dirty_state(struct r300_context* r300)
 857 {
 858     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 859     struct r300_texture* tex;
 860     int i, dirty_tex = 0;
 861     boolean invalid = FALSE;
 862
 863     if (!(r300->dirty_state)) {
 864         return;
 865     }
 866
 867     /* Clean out BOs. */
 868     r300->winsys->reset_bos(r300->winsys);
 869
 870     /* XXX check size */
 871 validate:
 872     /* Color buffers... */
 873     for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
 874         tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
 875         assert(tex && tex->buffer && "cbuf is marked, but NULL!");
 876         if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
 877                     0, RADEON_GEM_DOMAIN_VRAM)) {
 878             r300->context.flush(&r300->context, 0, NULL);
 879             goto validate;
 880         }
 881     }
 882     /* ...depth buffer... */
 883     if (r300->framebuffer_state.zsbuf) {
 884         tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
 885         assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
 886         if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
 887                     0, RADEON_GEM_DOMAIN_VRAM)) {
 888             r300->context.flush(&r300->context, 0, NULL);
 889             goto validate;
 890         }
 891     }
 892     /* ...textures... */
 893     for (i = 0; i < r300->texture_count; i++) {
 894         tex = r300->textures[i];
 895         if (!tex)
 896             continue;
 897         if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
 898                     RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
 899             r300->context.flush(&r300->context, 0, NULL);
 900             goto validate;
 901         }
 902     }
 903     /* ...occlusion query buffer... */
 904     if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
 905                 0, RADEON_GEM_DOMAIN_GTT)) {
 906         r300->context.flush(&r300->context, 0, NULL);
 907         goto validate;
 908     }
 909     /* ...and vertex buffer. */
 910     if (r300->vbo) {
 911         if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
 912                     RADEON_GEM_DOMAIN_GTT, 0)) {
 913             r300->context.flush(&r300->context, 0, NULL);
 914             goto validate;
 915         }
 916     } else {
 917         // debug_printf("No VBO while emitting dirty state!\n");
 918     }
 919     if (!r300->winsys->validate(r300->winsys)) {
 920         r300->context.flush(&r300->context, 0, NULL);
 921         if (invalid) {
 922             /* Well, hell. */
 923             debug_printf("r300: Stuck in validation loop, gonna quit now.");
 924             exit(1);
 925         }
 926         invalid = TRUE;
 927         goto validate;
 928     }
 929
 930     if (r300->dirty_state & R300_NEW_QUERY) {
 931         r300_emit_query_start(r300);
 932         r300->dirty_state &= ~R300_NEW_QUERY;
 933     }
 934
 935     if (r300->dirty_state & R300_NEW_BLEND) {
 936         r300_emit_blend_state(r300, r300->blend_state);
 937         r300->dirty_state &= ~R300_NEW_BLEND;
 938     }
 939
 940     if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
 941         r300_emit_blend_color_state(r300, r300->blend_color_state);
 942         r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
 943     }
 944
 945     if (r300->dirty_state & R300_NEW_CLIP) {
 946         r300_emit_clip_state(r300, &r300->clip_state);
 947         r300->dirty_state &= ~R300_NEW_CLIP;
 948     }
 949
 950     if (r300->dirty_state & R300_NEW_DSA) {
 951         r300_emit_dsa_state(r300, r300->dsa_state);
 952         r300->dirty_state &= ~R300_NEW_DSA;
 953     }
 954
 955     if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
 956         if (r300screen->caps->is_r500) {
 957             r500_emit_fragment_program_code(r300, &r300->fs->code);
 958         } else {
 959             r300_emit_fragment_program_code(r300, &r300->fs->code);
 960         }
 961         r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
 962     }
 963
 964     if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
 965         if (r300screen->caps->is_r500) {
 966             r500_emit_fs_constant_buffer(r300, &r300->fs->code.constants);
 967         } else {
 968             r300_emit_fs_constant_buffer(r300, &r300->fs->code.constants);
 969         }
 970         r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
 971     }
 972
 973     if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
 974         r300_emit_fb_state(r300, &r300->framebuffer_state);
 975         r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
 976     }
 977
 978     if (r300->dirty_state & R300_NEW_RASTERIZER) {
 979         r300_emit_rs_state(r300, r300->rs_state);
 980         r300->dirty_state &= ~R300_NEW_RASTERIZER;
 981     }
 982
 983     if (r300->dirty_state & R300_NEW_RS_BLOCK) {
 984         r300_emit_rs_block_state(r300, r300->rs_block);
 985         r300->dirty_state &= ~R300_NEW_RS_BLOCK;
 986     }
 987
 988     if (r300->dirty_state & R300_NEW_SCISSOR) {
 989         r300_emit_scissor_state(r300, r300->scissor_state);
 990         r300->dirty_state &= ~R300_NEW_SCISSOR;
 991     }
 992
 993     /* Samplers and textures are tracked separately but emitted together. */
 994     if (r300->dirty_state &
 995             (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
 996         for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
 997             if (r300->dirty_state &
 998                 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
 999                 if (r300->textures[i])
1000                     r300_emit_texture(r300,
1001                                       r300->sampler_states[i],
1002                                       r300->textures[i],
1003                                       i);
1004                 r300->dirty_state &=
1005                     ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1006                 dirty_tex++;
1007             }
1008         }
1009         r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1010     }
1011
1012     if (r300->dirty_state & R300_NEW_VIEWPORT) {
1013         r300_emit_viewport_state(r300, r300->viewport_state);
1014         r300->dirty_state &= ~R300_NEW_VIEWPORT;
1015     }
1016
1017     if (dirty_tex) {
1018         r300_flush_textures(r300);
1019     }
1020
1021     if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1022         r300_emit_vertex_format_state(r300);
1023         r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1024     }
1025
1026     if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1027         r300_flush_pvs(r300);
1028     }
1029
1030     if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1031         r300_emit_vertex_shader(r300, r300->vs);
1032         r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1033     }
1034
1035     if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1036         r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1037         r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1038     }
1039
1040     /* XXX
1041     assert(r300->dirty_state == 0);
1042     */
1043
1044     /* Finally, emit the VBO. */
1045     //r300_emit_vertex_buffer(r300);
1046
1047     r300->dirty_hw++;
1048 }