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r300g: atomize PVS flush
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_vs.h"
36
37 void r300_emit_blend_state(struct r300_context* r300,
38 unsigned size, void* state)
39 {
40 struct r300_blend_state* blend = (struct r300_blend_state*)state;
41 struct pipe_framebuffer_state* fb =
42 (struct pipe_framebuffer_state*)r300->fb_state.state;
43 CS_LOCALS(r300);
44
45 BEGIN_CS(8);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
48 if (fb->nr_cbufs) {
49 OUT_CS(blend->blend_control);
50 OUT_CS(blend->alpha_blend_control);
51 OUT_CS(blend->color_channel_mask);
52 } else {
53 OUT_CS(0);
54 OUT_CS(0);
55 OUT_CS(0);
56 /* XXX also disable fastfill here once it's supported */
57 }
58 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
59 END_CS;
60 }
61
62 void r300_emit_blend_color_state(struct r300_context* r300,
63 unsigned size, void* state)
64 {
65 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
66 struct r300_screen* r300screen = r300_screen(r300->context.screen);
67 CS_LOCALS(r300);
68
69 if (r300screen->caps->is_r500) {
70 BEGIN_CS(3);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(2);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 int i;
87 struct r300_screen* r300screen = r300_screen(r300->context.screen);
88 CS_LOCALS(r300);
89
90 if (r300screen->caps->has_tcl) {
91 BEGIN_CS(5 + (6 * 4));
92 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
93 (r300screen->caps->is_r500 ?
94 R500_PVS_UCP_START : R300_PVS_UCP_START));
95 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
96 for (i = 0; i < 6; i++) {
97 OUT_CS_32F(clip->ucp[i][0]);
98 OUT_CS_32F(clip->ucp[i][1]);
99 OUT_CS_32F(clip->ucp[i][2]);
100 OUT_CS_32F(clip->ucp[i][3]);
101 }
102 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
103 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
104 END_CS;
105 } else {
106 BEGIN_CS(2);
107 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
108 END_CS;
109 }
110
111 }
112
113 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
114 {
115 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
116 struct r300_screen* r300screen = r300_screen(r300->context.screen);
117 struct pipe_framebuffer_state* fb =
118 (struct pipe_framebuffer_state*)r300->fb_state.state;
119 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
120 CS_LOCALS(r300);
121
122 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
123 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
124 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
125
126 if (fb->zsbuf) {
127 OUT_CS(dsa->z_buffer_control);
128 OUT_CS(dsa->z_stencil_control);
129 } else {
130 OUT_CS(0);
131 OUT_CS(0);
132 }
133
134 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
135
136 if (r300screen->caps->is_r500) {
137 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
138 }
139 END_CS;
140 }
141
142 static const float * get_shader_constant(
143 struct r300_context * r300,
144 struct rc_constant * constant,
145 struct r300_constant_buffer * externals)
146 {
147 struct r300_viewport_state* viewport =
148 (struct r300_viewport_state*)r300->viewport_state.state;
149 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
150 struct pipe_texture *tex;
151
152 switch(constant->Type) {
153 case RC_CONSTANT_EXTERNAL:
154 return externals->constants[constant->u.External];
155
156 case RC_CONSTANT_IMMEDIATE:
157 return constant->u.Immediate;
158
159 case RC_CONSTANT_STATE:
160 switch (constant->u.State[0]) {
161 /* Factor for converting rectangle coords to
162 * normalized coords. Should only show up on non-r500. */
163 case RC_STATE_R300_TEXRECT_FACTOR:
164 tex = &r300->textures[constant->u.State[1]]->tex;
165 vec[0] = 1.0 / tex->width0;
166 vec[1] = 1.0 / tex->height0;
167 break;
168
169 /* Texture compare-fail value. Shouldn't ever show up, but if
170 * it does, we'll be ready. */
171 case RC_STATE_SHADOW_AMBIENT:
172 vec[3] = 0;
173 break;
174
175 case RC_STATE_R300_VIEWPORT_SCALE:
176 if (r300->tcl_bypass) {
177 vec[0] = 1;
178 vec[1] = 1;
179 vec[2] = 1;
180 } else {
181 vec[0] = viewport->xscale;
182 vec[1] = viewport->yscale;
183 vec[2] = viewport->zscale;
184 }
185 break;
186
187 case RC_STATE_R300_VIEWPORT_OFFSET:
188 if (!r300->tcl_bypass) {
189 vec[0] = viewport->xoffset;
190 vec[1] = viewport->yoffset;
191 vec[2] = viewport->zoffset;
192 }
193 break;
194
195 default:
196 debug_printf("r300: Implementation error: "
197 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
198 }
199 break;
200
201 default:
202 debug_printf("r300: Implementation error: "
203 "Unhandled constant type %d\n", constant->Type);
204 }
205
206 /* This should either be (0, 0, 0, 1), which should be a relatively safe
207 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
208 * state factors. */
209 return vec;
210 }
211
212 /* Convert a normal single-precision float into the 7.16 format
213 * used by the R300 fragment shader.
214 */
215 static uint32_t pack_float24(float f)
216 {
217 union {
218 float fl;
219 uint32_t u;
220 } u;
221 float mantissa;
222 int exponent;
223 uint32_t float24 = 0;
224
225 if (f == 0.0)
226 return 0;
227
228 u.fl = f;
229
230 mantissa = frexpf(f, &exponent);
231
232 /* Handle -ve */
233 if (mantissa < 0) {
234 float24 |= (1 << 23);
235 mantissa = mantissa * -1.0;
236 }
237 /* Handle exponent, bias of 63 */
238 exponent += 62;
239 float24 |= (exponent << 16);
240 /* Kill 7 LSB of mantissa */
241 float24 |= (u.u & 0x7FFFFF) >> 7;
242
243 return float24;
244 }
245
246 void r300_emit_fragment_program_code(struct r300_context* r300,
247 struct rX00_fragment_program_code* generic_code)
248 {
249 struct r300_fragment_program_code * code = &generic_code->code.r300;
250 int i;
251 CS_LOCALS(r300);
252
253 BEGIN_CS(15 +
254 code->alu.length * 4 +
255 (code->tex.length ? (1 + code->tex.length) : 0));
256
257 OUT_CS_REG(R300_US_CONFIG, code->config);
258 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
259 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
260
261 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
262 for(i = 0; i < 4; ++i)
263 OUT_CS(code->code_addr[i]);
264
265 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
266 for (i = 0; i < code->alu.length; i++)
267 OUT_CS(code->alu.inst[i].rgb_inst);
268
269 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
270 for (i = 0; i < code->alu.length; i++)
271 OUT_CS(code->alu.inst[i].rgb_addr);
272
273 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
274 for (i = 0; i < code->alu.length; i++)
275 OUT_CS(code->alu.inst[i].alpha_inst);
276
277 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
278 for (i = 0; i < code->alu.length; i++)
279 OUT_CS(code->alu.inst[i].alpha_addr);
280
281 if (code->tex.length) {
282 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
283 for(i = 0; i < code->tex.length; ++i)
284 OUT_CS(code->tex.inst[i]);
285 }
286
287 END_CS;
288 }
289
290 void r300_emit_fs_constant_buffer(struct r300_context* r300,
291 struct rc_constant_list* constants)
292 {
293 int i;
294 CS_LOCALS(r300);
295
296 if (constants->Count == 0)
297 return;
298
299 BEGIN_CS(constants->Count * 4 + 1);
300 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
301 for(i = 0; i < constants->Count; ++i) {
302 const float * data = get_shader_constant(r300,
303 &constants->Constants[i],
304 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
305 OUT_CS(pack_float24(data[0]));
306 OUT_CS(pack_float24(data[1]));
307 OUT_CS(pack_float24(data[2]));
308 OUT_CS(pack_float24(data[3]));
309 }
310 END_CS;
311 }
312
313 static void r300_emit_fragment_depth_config(struct r300_context* r300,
314 struct r300_fragment_shader* fs)
315 {
316 CS_LOCALS(r300);
317
318 BEGIN_CS(4);
319 if (r300_fragment_shader_writes_depth(fs)) {
320 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
321 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
322 } else {
323 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
324 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
325 }
326 END_CS;
327 }
328
329 void r500_emit_fragment_program_code(struct r300_context* r300,
330 struct rX00_fragment_program_code* generic_code)
331 {
332 struct r500_fragment_program_code * code = &generic_code->code.r500;
333 int i;
334 CS_LOCALS(r300);
335
336 BEGIN_CS(13 +
337 ((code->inst_end + 1) * 6));
338 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
339 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
340 OUT_CS_REG(R500_US_CODE_RANGE,
341 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
342 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
343 OUT_CS_REG(R500_US_CODE_ADDR,
344 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
345
346 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
347 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
348 for (i = 0; i <= code->inst_end; i++) {
349 OUT_CS(code->inst[i].inst0);
350 OUT_CS(code->inst[i].inst1);
351 OUT_CS(code->inst[i].inst2);
352 OUT_CS(code->inst[i].inst3);
353 OUT_CS(code->inst[i].inst4);
354 OUT_CS(code->inst[i].inst5);
355 }
356
357 END_CS;
358 }
359
360 void r500_emit_fs_constant_buffer(struct r300_context* r300,
361 struct rc_constant_list* constants)
362 {
363 int i;
364 CS_LOCALS(r300);
365
366 if (constants->Count == 0)
367 return;
368
369 BEGIN_CS(constants->Count * 4 + 3);
370 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
371 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
372 for (i = 0; i < constants->Count; i++) {
373 const float * data = get_shader_constant(r300,
374 &constants->Constants[i],
375 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
376 OUT_CS_32F(data[0]);
377 OUT_CS_32F(data[1]);
378 OUT_CS_32F(data[2]);
379 OUT_CS_32F(data[3]);
380 }
381 END_CS;
382 }
383
384 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
385 {
386 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
387 struct r300_screen* r300screen = r300_screen(r300->context.screen);
388 struct r300_texture* tex;
389 struct pipe_surface* surf;
390 int i;
391 CS_LOCALS(r300);
392
393 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
394 (fb->zsbuf ? 10 : 0) + 8);
395
396 /* Flush and free renderbuffer caches. */
397 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
398 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
399 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
400 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
401 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
402 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
403
404 /* Set the number of colorbuffers. */
405 if (fb->nr_cbufs > 1) {
406 if (r300screen->caps->is_r500) {
407 OUT_CS_REG(R300_RB3D_CCTL,
408 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
409 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
410 } else {
411 OUT_CS_REG(R300_RB3D_CCTL,
412 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
413 }
414 } else {
415 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
416 }
417
418 /* Set up colorbuffers. */
419 for (i = 0; i < fb->nr_cbufs; i++) {
420 surf = fb->cbufs[i];
421 tex = (struct r300_texture*)surf->texture;
422 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
423
424 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
425 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
426
427 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
428 OUT_CS_RELOC(tex->buffer, tex->fb_state.colorpitch[surf->level],
429 0, RADEON_GEM_DOMAIN_VRAM, 0);
430
431 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
432 }
433 for (; i < 4; i++) {
434 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
435 }
436
437 /* Set up a zbuffer. */
438 if (fb->zsbuf) {
439 surf = fb->zsbuf;
440 tex = (struct r300_texture*)surf->texture;
441 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
442
443 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
444 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
445
446 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
447
448 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
449 OUT_CS_RELOC(tex->buffer, tex->fb_state.depthpitch[surf->level],
450 0, RADEON_GEM_DOMAIN_VRAM, 0);
451 }
452
453 OUT_CS_REG(R300_GA_POINT_MINMAX,
454 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
455 END_CS;
456 }
457
458 static void r300_emit_query_start(struct r300_context *r300)
459 {
460 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
461 struct r300_query *query = r300->query_current;
462 CS_LOCALS(r300);
463
464 if (!query)
465 return;
466
467 BEGIN_CS(4);
468 if (caps->family == CHIP_FAMILY_RV530) {
469 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
470 } else {
471 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
472 }
473 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
474 END_CS;
475 query->begin_emitted = TRUE;
476 }
477
478
479 static void r300_emit_query_finish(struct r300_context *r300,
480 struct r300_query *query)
481 {
482 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
483 CS_LOCALS(r300);
484
485 assert(caps->num_frag_pipes);
486
487 BEGIN_CS(6 * caps->num_frag_pipes + 2);
488 /* I'm not so sure I like this switch, but it's hard to be elegant
489 * when there's so many special cases...
490 *
491 * So here's the basic idea. For each pipe, enable writes to it only,
492 * then put out the relocation for ZPASS_ADDR, taking into account a
493 * 4-byte offset for each pipe. RV380 and older are special; they have
494 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
495 * so there's a chipset cap for that. */
496 switch (caps->num_frag_pipes) {
497 case 4:
498 /* pipe 3 only */
499 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
500 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
501 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
502 0, RADEON_GEM_DOMAIN_GTT, 0);
503 case 3:
504 /* pipe 2 only */
505 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
506 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
507 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
508 0, RADEON_GEM_DOMAIN_GTT, 0);
509 case 2:
510 /* pipe 1 only */
511 /* As mentioned above, accomodate RV380 and older. */
512 OUT_CS_REG(R300_SU_REG_DEST,
513 1 << (caps->high_second_pipe ? 3 : 1));
514 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
515 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
516 0, RADEON_GEM_DOMAIN_GTT, 0);
517 case 1:
518 /* pipe 0 only */
519 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
520 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
521 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
522 0, RADEON_GEM_DOMAIN_GTT, 0);
523 break;
524 default:
525 debug_printf("r300: Implementation error: Chipset reports %d"
526 " pixel pipes!\n", caps->num_frag_pipes);
527 assert(0);
528 }
529
530 /* And, finally, reset it to normal... */
531 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
532 END_CS;
533 }
534
535 static void rv530_emit_query_single(struct r300_context *r300,
536 struct r300_query *query)
537 {
538 CS_LOCALS(r300);
539
540 BEGIN_CS(8);
541 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
542 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
543 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
544 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
545 END_CS;
546 }
547
548 static void rv530_emit_query_double(struct r300_context *r300,
549 struct r300_query *query)
550 {
551 CS_LOCALS(r300);
552
553 BEGIN_CS(14);
554 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
555 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
556 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
557 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
558 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
559 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
560 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
561 END_CS;
562 }
563
564 void r300_emit_query_end(struct r300_context* r300)
565 {
566 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
567 struct r300_query *query = r300->query_current;
568
569 if (!query)
570 return;
571
572 if (query->begin_emitted == FALSE)
573 return;
574
575 if (caps->family == CHIP_FAMILY_RV530) {
576 if (caps->num_z_pipes == 2)
577 rv530_emit_query_double(r300, query);
578 else
579 rv530_emit_query_single(r300, query);
580 } else
581 r300_emit_query_finish(r300, query);
582 }
583
584 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
585 {
586 struct r300_rs_state* rs = (struct r300_rs_state*)state;
587 float scale, offset;
588 CS_LOCALS(r300);
589
590 BEGIN_CS(17 + (rs->polygon_offset_enable ? 5 : 0));
591 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
592
593 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
594
595 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
596 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
597
598 if (rs->polygon_offset_enable) {
599 scale = rs->depth_scale * 12;
600 offset = rs->depth_offset;
601
602 switch (r300->zbuffer_bpp) {
603 case 16:
604 offset *= 4;
605 break;
606 case 24:
607 offset *= 2;
608 break;
609 }
610
611 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
612 OUT_CS_32F(scale);
613 OUT_CS_32F(offset);
614 OUT_CS_32F(scale);
615 OUT_CS_32F(offset);
616 }
617
618 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
619 OUT_CS(rs->polygon_offset_enable);
620 OUT_CS(rs->cull_mode);
621 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
622 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
623 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
624 END_CS;
625 }
626
627 void r300_emit_rs_block_state(struct r300_context* r300,
628 unsigned size, void* state)
629 {
630 struct r300_rs_block* rs = (struct r300_rs_block*)state;
631 unsigned i;
632 struct r300_screen* r300screen = r300_screen(r300->context.screen);
633 /* It's the same for both INST and IP tables */
634 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
635 CS_LOCALS(r300);
636
637 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
638
639 BEGIN_CS(5 + count*2);
640 if (r300screen->caps->is_r500) {
641 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
642 } else {
643 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
644 }
645 for (i = 0; i < count; i++) {
646 OUT_CS(rs->ip[i]);
647 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
648 }
649
650 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
651 OUT_CS(rs->count);
652 OUT_CS(rs->inst_count);
653
654 if (r300screen->caps->is_r500) {
655 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
656 } else {
657 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
658 }
659 for (i = 0; i < count; i++) {
660 OUT_CS(rs->inst[i]);
661 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
662 }
663
664 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
665 rs->count, rs->inst_count);
666
667 END_CS;
668 }
669
670 void r300_emit_scissor_state(struct r300_context* r300,
671 unsigned size, void* state)
672 {
673 unsigned minx, miny, maxx, maxy;
674 uint32_t top_left, bottom_right;
675 struct r300_screen* r300screen = r300_screen(r300->context.screen);
676 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
677 struct pipe_framebuffer_state* fb =
678 (struct pipe_framebuffer_state*)r300->fb_state.state;
679 CS_LOCALS(r300);
680
681 minx = miny = 0;
682 maxx = fb->width;
683 maxy = fb->height;
684
685 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
686 minx = MAX2(minx, scissor->minx);
687 miny = MAX2(miny, scissor->miny);
688 maxx = MIN2(maxx, scissor->maxx);
689 maxy = MIN2(maxy, scissor->maxy);
690 }
691
692 /* Special case for zero-area scissor.
693 *
694 * We can't allow the variables maxx and maxy to be zero because they are
695 * subtracted from later in the code, which would cause emitting ~0 and
696 * making the kernel checker angry.
697 *
698 * Let's consider we change maxx and maxy to 1, which is effectively
699 * a one-pixel area. We must then change minx and miny to a number which is
700 * greater than 1 to get the zero area back. */
701 if (!maxx || !maxy) {
702 minx = 2;
703 miny = 2;
704 maxx = 1;
705 maxy = 1;
706 }
707
708 if (r300screen->caps->is_r500) {
709 top_left =
710 (minx << R300_SCISSORS_X_SHIFT) |
711 (miny << R300_SCISSORS_Y_SHIFT);
712 bottom_right =
713 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
714 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
715 } else {
716 /* Offset of 1440 in non-R500 chipsets. */
717 top_left =
718 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
719 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
720 bottom_right =
721 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
722 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
723 }
724
725 BEGIN_CS(3);
726 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
727 OUT_CS(top_left);
728 OUT_CS(bottom_right);
729 END_CS;
730 }
731
732 void r300_emit_texture(struct r300_context* r300,
733 struct r300_sampler_state* sampler,
734 struct r300_texture* tex,
735 unsigned offset)
736 {
737 uint32_t filter0 = sampler->filter0;
738 uint32_t format0 = tex->state.format0;
739 unsigned min_level, max_level;
740 CS_LOCALS(r300);
741
742 /* to emulate 1D textures through 2D ones correctly */
743 if (tex->tex.target == PIPE_TEXTURE_1D) {
744 filter0 &= ~R300_TX_WRAP_T_MASK;
745 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
746 }
747
748 if (tex->is_npot) {
749 /* NPOT textures don't support mip filter, unfortunately.
750 * This prevents incorrect rendering. */
751 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
752 } else {
753 /* determine min/max levels */
754 /* the MAX_MIP level is the largest (finest) one */
755 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
756 min_level = MIN2(sampler->min_lod, max_level);
757 format0 |= R300_TX_NUM_LEVELS(max_level);
758 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
759 }
760
761 BEGIN_CS(16);
762 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
763 (offset << 28));
764 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
765 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
766
767 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
768 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
769 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
770 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
771 OUT_CS_RELOC(tex->buffer,
772 R300_TXO_MACRO_TILE(tex->macrotile) |
773 R300_TXO_MICRO_TILE(tex->microtile),
774 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
775 END_CS;
776 }
777
778 void r300_emit_aos(struct r300_context* r300, unsigned offset)
779 {
780 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
781 struct pipe_vertex_element *velem = r300->vertex_element;
782 int i;
783 unsigned size1, size2, aos_count = r300->vertex_element_count;
784 unsigned packet_size = (aos_count * 3 + 1) / 2;
785 CS_LOCALS(r300);
786
787 BEGIN_CS(2 + packet_size + aos_count * 2);
788 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
789 OUT_CS(aos_count);
790
791 for (i = 0; i < aos_count - 1; i += 2) {
792 vb1 = &vbuf[velem[i].vertex_buffer_index];
793 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
794 size1 = util_format_get_blocksize(velem[i].src_format);
795 size2 = util_format_get_blocksize(velem[i+1].src_format);
796
797 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
798 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
799 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
800 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
801 }
802
803 if (aos_count & 1) {
804 vb1 = &vbuf[velem[i].vertex_buffer_index];
805 size1 = util_format_get_blocksize(velem[i].src_format);
806
807 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
808 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
809 }
810
811 for (i = 0; i < aos_count; i++) {
812 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
813 RADEON_GEM_DOMAIN_GTT, 0, 0);
814 }
815 END_CS;
816 }
817
818 void r300_emit_vertex_format_state(struct r300_context* r300,
819 unsigned size, void* state)
820 {
821 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
822 unsigned i;
823 CS_LOCALS(r300);
824
825 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
826
827 BEGIN_CS(26);
828 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
829
830 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
831 OUT_CS(vertex_info->vinfo.hwfmt[0]);
832 OUT_CS(vertex_info->vinfo.hwfmt[1]);
833 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
834 OUT_CS(vertex_info->vinfo.hwfmt[2]);
835 OUT_CS(vertex_info->vinfo.hwfmt[3]);
836 for (i = 0; i < 4; i++) {
837 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
838 vertex_info->vinfo.hwfmt[i]);
839 }
840
841 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
842 for (i = 0; i < 8; i++) {
843 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
844 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
845 vertex_info->vap_prog_stream_cntl[i]);
846 }
847 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
848 for (i = 0; i < 8; i++) {
849 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
850 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
851 vertex_info->vap_prog_stream_cntl_ext[i]);
852 }
853 END_CS;
854 }
855
856 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
857 {
858 CS_LOCALS(r300);
859
860 BEGIN_CS(2);
861 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
862 END_CS;
863 }
864
865 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
866 {
867 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
868 struct r300_vertex_program_code* code = &vs->code;
869 struct r300_screen* r300screen = r300_screen(r300->context.screen);
870 unsigned instruction_count = code->length / 4;
871 unsigned i;
872
873 unsigned vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
874 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
875 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
876 unsigned temp_count = MAX2(code->num_temporaries, 1);
877
878 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
879 vtx_mem_size / output_count, 10);
880 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
881
882 CS_LOCALS(r300);
883
884 if (!r300screen->caps->has_tcl) {
885 debug_printf("r300: Implementation error: emit_vertex_shader called,"
886 " but has_tcl is FALSE!\n");
887 return;
888 }
889
890 BEGIN_CS(9 + code->length);
891 /* R300_VAP_PVS_CODE_CNTL_0
892 * R300_VAP_PVS_CONST_CNTL
893 * R300_VAP_PVS_CODE_CNTL_1
894 * See the r5xx docs for instructions on how to use these. */
895 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
896 OUT_CS(R300_PVS_FIRST_INST(0) |
897 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
898 R300_PVS_LAST_INST(instruction_count - 1));
899 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
900 OUT_CS(instruction_count - 1);
901
902 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
903 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
904 for (i = 0; i < code->length; i++) {
905 OUT_CS(code->body.d[i]);
906 }
907
908 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
909 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
910 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
911 R300_PVS_VF_MAX_VTX_NUM(12) |
912 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
913 END_CS;
914 }
915
916 void r300_emit_vs_constant_buffer(struct r300_context* r300,
917 struct rc_constant_list* constants)
918 {
919 int i;
920 struct r300_screen* r300screen = r300_screen(r300->context.screen);
921 CS_LOCALS(r300);
922
923 if (!r300screen->caps->has_tcl) {
924 debug_printf("r300: Implementation error: emit_vertex_shader called,"
925 " but has_tcl is FALSE!\n");
926 return;
927 }
928
929 if (constants->Count == 0)
930 return;
931
932 BEGIN_CS(constants->Count * 4 + 3);
933 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
934 (r300screen->caps->is_r500 ?
935 R500_PVS_CONST_START : R300_PVS_CONST_START));
936 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
937 for (i = 0; i < constants->Count; i++) {
938 const float * data = get_shader_constant(r300,
939 &constants->Constants[i],
940 &r300->shader_constants[PIPE_SHADER_VERTEX]);
941 OUT_CS_32F(data[0]);
942 OUT_CS_32F(data[1]);
943 OUT_CS_32F(data[2]);
944 OUT_CS_32F(data[3]);
945 }
946 END_CS;
947 }
948
949 void r300_emit_viewport_state(struct r300_context* r300,
950 unsigned size, void* state)
951 {
952 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
953 CS_LOCALS(r300);
954
955 if (r300->tcl_bypass) {
956 BEGIN_CS(2);
957 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
958 END_CS;
959 } else {
960 BEGIN_CS(9);
961 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
962 OUT_CS_32F(viewport->xscale);
963 OUT_CS_32F(viewport->xoffset);
964 OUT_CS_32F(viewport->yscale);
965 OUT_CS_32F(viewport->yoffset);
966 OUT_CS_32F(viewport->zscale);
967 OUT_CS_32F(viewport->zoffset);
968 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
969 END_CS;
970 }
971 }
972
973 void r300_emit_texture_count(struct r300_context* r300)
974 {
975 uint32_t tx_enable = 0;
976 int i;
977 CS_LOCALS(r300);
978
979 /* Notice that texture_count and sampler_count are just sizes
980 * of the respective arrays. We still have to check for the individual
981 * elements. */
982 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
983 if (r300->textures[i]) {
984 tx_enable |= 1 << i;
985 }
986 }
987
988 BEGIN_CS(2);
989 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
990 END_CS;
991
992 }
993
994 void r300_emit_ztop_state(struct r300_context* r300,
995 unsigned size, void* state)
996 {
997 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
998 CS_LOCALS(r300);
999
1000 BEGIN_CS(2);
1001 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1002 END_CS;
1003 }
1004
1005 void r300_flush_textures(struct r300_context* r300)
1006 {
1007 CS_LOCALS(r300);
1008
1009 BEGIN_CS(2);
1010 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1011 END_CS;
1012 }
1013
1014 void r300_emit_buffer_validate(struct r300_context *r300)
1015 {
1016 struct pipe_framebuffer_state* fb =
1017 (struct pipe_framebuffer_state*)r300->fb_state.state;
1018 struct r300_texture* tex;
1019 unsigned i;
1020 boolean invalid = FALSE;
1021
1022 /* Clean out BOs. */
1023 r300->winsys->reset_bos(r300->winsys);
1024
1025 validate:
1026 /* Color buffers... */
1027 for (i = 0; i < fb->nr_cbufs; i++) {
1028 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1029 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1030 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1031 0, RADEON_GEM_DOMAIN_VRAM)) {
1032 r300->context.flush(&r300->context, 0, NULL);
1033 goto validate;
1034 }
1035 }
1036 /* ...depth buffer... */
1037 if (fb->zsbuf) {
1038 tex = (struct r300_texture*)fb->zsbuf->texture;
1039 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1040 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1041 0, RADEON_GEM_DOMAIN_VRAM)) {
1042 r300->context.flush(&r300->context, 0, NULL);
1043 goto validate;
1044 }
1045 }
1046 /* ...textures... */
1047 for (i = 0; i < r300->texture_count; i++) {
1048 tex = r300->textures[i];
1049 if (!tex)
1050 continue;
1051 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1052 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1053 r300->context.flush(&r300->context, 0, NULL);
1054 goto validate;
1055 }
1056 }
1057 /* ...occlusion query buffer... */
1058 if (r300->dirty_state & R300_NEW_QUERY) {
1059 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1060 0, RADEON_GEM_DOMAIN_GTT)) {
1061 r300->context.flush(&r300->context, 0, NULL);
1062 goto validate;
1063 }
1064 }
1065 /* ...and vertex buffer. */
1066 if (r300->vbo) {
1067 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1068 RADEON_GEM_DOMAIN_GTT, 0)) {
1069 r300->context.flush(&r300->context, 0, NULL);
1070 goto validate;
1071 }
1072 } else {
1073 /* debug_printf("No VBO while emitting dirty state!\n"); */
1074 }
1075 if (!r300->winsys->validate(r300->winsys)) {
1076 r300->context.flush(&r300->context, 0, NULL);
1077 if (invalid) {
1078 /* Well, hell. */
1079 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1080 exit(1);
1081 }
1082 invalid = TRUE;
1083 goto validate;
1084 }
1085 }
1086
1087 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1088 {
1089 struct r300_atom* atom;
1090 unsigned dwords = 0;
1091
1092 foreach(atom, &r300->atom_list) {
1093 if (atom->dirty || atom->always_dirty) {
1094 dwords += atom->size;
1095 }
1096 }
1097
1098 /* XXX This is the compensation for the non-atomized states. */
1099 dwords += 1024;
1100
1101 return dwords;
1102 }
1103
1104 /* Emit all dirty state. */
1105 void r300_emit_dirty_state(struct r300_context* r300)
1106 {
1107 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1108 struct r300_atom* atom;
1109 unsigned i;
1110 int dirty_tex = 0;
1111
1112 if (r300->dirty_state & R300_NEW_QUERY) {
1113 r300_emit_query_start(r300);
1114 r300->dirty_state &= ~R300_NEW_QUERY;
1115 }
1116
1117 foreach(atom, &r300->atom_list) {
1118 if (atom->dirty || atom->always_dirty) {
1119 atom->emit(r300, atom->size, atom->state);
1120 atom->dirty = FALSE;
1121 }
1122 }
1123
1124 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1125 r300_emit_fragment_depth_config(r300, r300->fs);
1126 if (r300screen->caps->is_r500) {
1127 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1128 } else {
1129 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1130 }
1131 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1132 }
1133
1134 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1135 if (r300screen->caps->is_r500) {
1136 r500_emit_fs_constant_buffer(r300,
1137 &r300->fs->shader->code.constants);
1138 } else {
1139 r300_emit_fs_constant_buffer(r300,
1140 &r300->fs->shader->code.constants);
1141 }
1142 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1143 }
1144
1145 /* Samplers and textures are tracked separately but emitted together. */
1146 if (r300->dirty_state &
1147 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1148 r300_emit_texture_count(r300);
1149
1150 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1151 if (r300->dirty_state &
1152 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1153 if (r300->textures[i]) {
1154 r300_emit_texture(r300,
1155 r300->sampler_states[i],
1156 r300->textures[i],
1157 i);
1158 dirty_tex |= r300->dirty_state & (R300_NEW_TEXTURE << i);
1159 }
1160 r300->dirty_state &=
1161 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1162 }
1163 }
1164 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1165 }
1166
1167 if (dirty_tex) {
1168 r300_flush_textures(r300);
1169 }
1170
1171 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1172 struct r300_vertex_shader* vs = r300->vs_state.state;
1173 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1174 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1175 }
1176
1177 /* XXX
1178 assert(r300->dirty_state == 0);
1179 */
1180
1181 /* Finally, emit the VBO. */
1182 /* r300_emit_vertex_buffer(r300); */
1183
1184 r300->dirty_hw++;
1185 }