src/gallium/drivers/r300/r300_screen.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "util/u_format.h"
  25 #include "util/u_format_s3tc.h"
  26 #include "util/u_memory.h"
  27 #include "os/os_time.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30
  31 #include "r300_context.h"
  32 #include "r300_texture.h"
  33 #include "r300_screen_buffer.h"
  34 #include "r300_state_inlines.h"
  35 #include "r300_public.h"
  36
  37 #include "draw/draw_context.h"
  38
  39 /* Return the identifier behind whom the brave coders responsible for this
  40  * amalgamation of code, sweat, and duct tape, routinely obscure their names.
  41  *
  42  * ...I should have just put "Corbin Simpson", but I'm not that cool.
  43  *
  44  * (Or egotistical. Yet.) */
  45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
  46 {
  47     return "X.Org R300 Project";
  48 }
  49
  50 static const char* chip_families[] = {
  51     "unknown",
  52     "ATI R300",
  53     "ATI R350",
  54     "ATI RV350",
  55     "ATI RV370",
  56     "ATI RV380",
  57     "ATI RS400",
  58     "ATI RC410",
  59     "ATI RS480",
  60     "ATI R420",
  61     "ATI R423",
  62     "ATI R430",
  63     "ATI R480",
  64     "ATI R481",
  65     "ATI RV410",
  66     "ATI RS600",
  67     "ATI RS690",
  68     "ATI RS740",
  69     "ATI RV515",
  70     "ATI R520",
  71     "ATI RV530",
  72     "ATI R580",
  73     "ATI RV560",
  74     "ATI RV570"
  75 };
  76
  77 static const char* r300_get_name(struct pipe_screen* pscreen)
  78 {
  79     struct r300_screen* r300screen = r300_screen(pscreen);
  80
  81     return chip_families[r300screen->caps.family];
  82 }
  83
  84 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
  85 {
  86     struct r300_screen* r300screen = r300_screen(pscreen);
  87     boolean is_r500 = r300screen->caps.is_r500;
  88
  89     switch (param) {
  90         /* Supported features (boolean caps). */
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_TWO_SIDED_STENCIL:
  93         case PIPE_CAP_ANISOTROPIC_FILTER:
  94         case PIPE_CAP_POINT_SPRITE:
  95         case PIPE_CAP_OCCLUSION_QUERY:
  96         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  97         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  99         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 100         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 101         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 102         case PIPE_CAP_CONDITIONAL_RENDER:
 103         case PIPE_CAP_TEXTURE_BARRIER:
 104         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 105         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 106         case PIPE_CAP_USER_INDEX_BUFFERS:
 107         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 108         case PIPE_CAP_DEPTH_CLIP_DISABLE: /* XXX implemented, but breaks Regnum Online */
 109         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 110             return 1;
 111
 112         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 113             return R300_BUFFER_ALIGNMENT;
 114
 115         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 116             return 16;
 117
 118         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 119             return 120;
 120
 121         /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
 122         case PIPE_CAP_TEXTURE_SWIZZLE:
 123             return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
 124
 125         /* We don't support color clamping on r500, so that we can use color
 126          * intepolators for generic varyings. */
 127         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 128             return !is_r500;
 129
 130         /* Supported on r500 only. */
 131         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 132         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 133         case PIPE_CAP_SM3:
 134             return is_r500 ? 1 : 0;
 135
 136         /* Unsupported features. */
 137         case PIPE_CAP_QUERY_TIME_ELAPSED:
 138         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 139         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 140         case PIPE_CAP_INDEP_BLEND_ENABLE:
 141         case PIPE_CAP_INDEP_BLEND_FUNC:
 142         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 143         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 144         case PIPE_CAP_TGSI_INSTANCEID:
 145         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 146         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 147         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 148         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 149         case PIPE_CAP_SCALED_RESOLVE:
 150         case PIPE_CAP_MIN_TEXEL_OFFSET:
 151         case PIPE_CAP_MAX_TEXEL_OFFSET:
 152         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 153         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 154         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 155         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 156         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 157         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 158         case PIPE_CAP_COMPUTE:
 159         case PIPE_CAP_START_INSTANCE:
 160         case PIPE_CAP_QUERY_TIMESTAMP:
 161         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 162         case PIPE_CAP_CUBE_MAP_ARRAY:
 163         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 164         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 165             return 0;
 166
 167         /* SWTCL-only features. */
 168         case PIPE_CAP_PRIMITIVE_RESTART:
 169         case PIPE_CAP_USER_VERTEX_BUFFERS:
 170             return !r300screen->caps.has_tcl;
 171
 172         /* HWTCL-only features / limitations. */
 173         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 174         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 175         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 176             return r300screen->caps.has_tcl;
 177         case PIPE_CAP_TGSI_TEXCOORD:
 178             return 0;
 179
 180         /* Texturing. */
 181         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 182             return r300screen->caps.num_tex_units;
 183         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 184         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 185         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 186             /* 13 == 4096, 12 == 2048 */
 187             return is_r500 ? 13 : 12;
 188
 189         /* Render targets. */
 190         case PIPE_CAP_MAX_RENDER_TARGETS:
 191             return 4;
 192     }
 193     return 0;
 194 }
 195
 196 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 197 {
 198    struct r300_screen* r300screen = r300_screen(pscreen);
 199    boolean is_r400 = r300screen->caps.is_r400;
 200    boolean is_r500 = r300screen->caps.is_r500;
 201
 202    switch (shader) {
 203     case PIPE_SHADER_FRAGMENT:
 204         switch (param)
 205         {
 206         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 207             return is_r500 || is_r400 ? 512 : 96;
 208         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 209             return is_r500 || is_r400 ? 512 : 64;
 210         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 211             return is_r500 || is_r400 ? 512 : 32;
 212         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 213             return is_r500 ? 511 : 4;
 214         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 215             return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
 216             /* Fragment shader limits. */
 217         case PIPE_SHADER_CAP_MAX_INPUTS:
 218             /* 2 colors + 8 texcoords are always supported
 219              * (minus fog and wpos).
 220              *
 221              * R500 has the ability to turn 3rd and 4th color into
 222              * additional texcoords but there is no two-sided color
 223              * selection then. However the facing bit can be used instead. */
 224             return 10;
 225         case PIPE_SHADER_CAP_MAX_CONSTS:
 226             return is_r500 ? 256 : 32;
 227         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 228             return 1;
 229         case PIPE_SHADER_CAP_MAX_TEMPS:
 230             return is_r500 ? 128 : is_r400 ? 64 : 32;
 231         case PIPE_SHADER_CAP_MAX_PREDS:
 232             return is_r500 ? 1 : 0;
 233         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 234            return r300screen->caps.num_tex_units;
 235         case PIPE_SHADER_CAP_MAX_ADDRS:
 236         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 237         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 238         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 239         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 240         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 241         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 242         case PIPE_SHADER_CAP_SUBROUTINES:
 243         case PIPE_SHADER_CAP_INTEGERS:
 244             return 0;
 245         case PIPE_SHADER_CAP_PREFERRED_IR:
 246             return PIPE_SHADER_IR_TGSI;
 247         }
 248         break;
 249     case PIPE_SHADER_VERTEX:
 250         switch (param)
 251         {
 252         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 253         case PIPE_SHADER_CAP_SUBROUTINES:
 254             return 0;
 255         default:;
 256         }
 257
 258         if (!r300screen->caps.has_tcl) {
 259             return draw_get_shader_param(shader, param);
 260         }
 261
 262         switch (param)
 263         {
 264         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 265         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 266             return is_r500 ? 1024 : 256;
 267         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 268             return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
 269         case PIPE_SHADER_CAP_MAX_INPUTS:
 270             return 16;
 271         case PIPE_SHADER_CAP_MAX_CONSTS:
 272             return 256;
 273         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 274             return 1;
 275         case PIPE_SHADER_CAP_MAX_TEMPS:
 276             return 32;
 277         case PIPE_SHADER_CAP_MAX_ADDRS:
 278             return 1; /* XXX guessed */
 279         case PIPE_SHADER_CAP_MAX_PREDS:
 280             return is_r500 ? 4 : 0; /* XXX guessed. */
 281         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 282             return 1;
 283         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 284         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 285         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 286         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 287         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 288         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 289         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 290         case PIPE_SHADER_CAP_SUBROUTINES:
 291         case PIPE_SHADER_CAP_INTEGERS:
 292         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 293             return 0;
 294         case PIPE_SHADER_CAP_PREFERRED_IR:
 295             return PIPE_SHADER_IR_TGSI;
 296         }
 297         break;
 298     }
 299     return 0;
 300 }
 301
 302 static float r300_get_paramf(struct pipe_screen* pscreen,
 303                              enum pipe_capf param)
 304 {
 305     struct r300_screen* r300screen = r300_screen(pscreen);
 306
 307     switch (param) {
 308         case PIPE_CAPF_MAX_LINE_WIDTH:
 309         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 310         case PIPE_CAPF_MAX_POINT_WIDTH:
 311         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 312             /* The maximum dimensions of the colorbuffer are our practical
 313              * rendering limits. 2048 pixels should be enough for anybody. */
 314             if (r300screen->caps.is_r500) {
 315                 return 4096.0f;
 316             } else if (r300screen->caps.is_r400) {
 317                 return 4021.0f;
 318             } else {
 319                 return 2560.0f;
 320             }
 321         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 322             return 16.0f;
 323         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 324             return 16.0f;
 325         case PIPE_CAPF_GUARD_BAND_LEFT:
 326         case PIPE_CAPF_GUARD_BAND_TOP:
 327         case PIPE_CAPF_GUARD_BAND_RIGHT:
 328         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 329             /* XXX I don't know what these should be but the least we can do is
 330              * silence the potential error message */
 331             return 0.0f;
 332         default:
 333             debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
 334                          param);
 335             return 0.0f;
 336     }
 337 }
 338
 339 static int r300_get_video_param(struct pipe_screen *screen,
 340                                 enum pipe_video_profile profile,
 341                                 enum pipe_video_cap param)
 342 {
 343    switch (param) {
 344       case PIPE_VIDEO_CAP_SUPPORTED:
 345          return vl_profile_supported(screen, profile);
 346       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 347          return 0;
 348       case PIPE_VIDEO_CAP_MAX_WIDTH:
 349       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 350          return vl_video_buffer_max_size(screen);
 351       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 352          return PIPE_FORMAT_NV12;
 353       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 354          return false;
 355       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 356          return false;
 357       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 358          return true;
 359       default:
 360          return 0;
 361    }
 362 }
 363
 364 /**
 365  * Whether the format matches:
 366  *   PIPE_FORMAT_?10?10?10?2_UNORM
 367  */
 368 static INLINE boolean
 369 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
 370 {
 371    static const unsigned size[4] = {10, 10, 10, 2};
 372    unsigned chan;
 373
 374    if (desc->block.width != 1 ||
 375        desc->block.height != 1 ||
 376        desc->block.bits != 32)
 377       return FALSE;
 378
 379    for (chan = 0; chan < 4; ++chan) {
 380       if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
 381          desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
 382          return FALSE;
 383       if (desc->channel[chan].size != size[chan])
 384          return FALSE;
 385    }
 386
 387    return TRUE;
 388 }
 389
 390 static boolean r300_is_format_supported(struct pipe_screen* screen,
 391                                         enum pipe_format format,
 392                                         enum pipe_texture_target target,
 393                                         unsigned sample_count,
 394                                         unsigned usage)
 395 {
 396     uint32_t retval = 0;
 397     boolean drm_2_8_0 = r300_screen(screen)->info.drm_minor >= 8;
 398     boolean is_r500 = r300_screen(screen)->caps.is_r500;
 399     boolean is_r400 = r300_screen(screen)->caps.is_r400;
 400     boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
 401                               format == PIPE_FORMAT_R10G10B10X2_SNORM ||
 402                               format == PIPE_FORMAT_B10G10R10A2_UNORM ||
 403                               format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
 404     boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
 405                        format == PIPE_FORMAT_RGTC1_SNORM ||
 406                        format == PIPE_FORMAT_LATC1_UNORM ||
 407                        format == PIPE_FORMAT_LATC1_SNORM;
 408     boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
 409                        format == PIPE_FORMAT_RGTC2_SNORM ||
 410                        format == PIPE_FORMAT_LATC2_UNORM ||
 411                        format == PIPE_FORMAT_LATC2_SNORM;
 412     boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
 413                             format == PIPE_FORMAT_R16G16_FLOAT ||
 414                             format == PIPE_FORMAT_A16_FLOAT ||
 415                             format == PIPE_FORMAT_L16_FLOAT ||
 416                             format == PIPE_FORMAT_L16A16_FLOAT ||
 417                             format == PIPE_FORMAT_R16A16_FLOAT ||
 418                             format == PIPE_FORMAT_I16_FLOAT;
 419     boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
 420                             format == PIPE_FORMAT_R16G16_FLOAT ||
 421                             format == PIPE_FORMAT_R16G16B16_FLOAT ||
 422                             format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
 423                             format == PIPE_FORMAT_R16G16B16X16_FLOAT;
 424     const struct util_format_description *desc;
 425
 426     if (!util_format_is_supported(format, usage))
 427        return FALSE;
 428
 429     /* Check multisampling support. */
 430     switch (sample_count) {
 431         case 0:
 432         case 1:
 433             break;
 434         case 2:
 435         case 4:
 436         case 6:
 437             /* We need DRM 2.8.0. */
 438             if (!drm_2_8_0) {
 439                 return FALSE;
 440             }
 441             /* Only support R500, because I didn't test older chipsets,
 442              * but MSAA should work there too. */
 443             if (!is_r500 && !debug_get_bool_option("RADEON_MSAA", FALSE)) {
 444                 return FALSE;
 445             }
 446             /* No texturing and scanout. */
 447             if (usage & (PIPE_BIND_SAMPLER_VIEW |
 448                          PIPE_BIND_DISPLAY_TARGET |
 449                          PIPE_BIND_SCANOUT)) {
 450                 return FALSE;
 451             }
 452
 453             desc = util_format_description(format);
 454
 455             if (is_r500) {
 456                 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
 457                 if (!util_format_is_depth_or_stencil(format) &&
 458                     !util_format_is_rgba8_variant(desc) &&
 459                     !util_format_is_rgba1010102_variant(desc) &&
 460                     format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
 461                     format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
 462                     return FALSE;
 463                 }
 464             } else {
 465                 /* Only allow depth/stencil, RGBA8. */
 466                 if (!util_format_is_depth_or_stencil(format) &&
 467                     !util_format_is_rgba8_variant(desc)) {
 468                     return FALSE;
 469                 }
 470             }
 471             break;
 472         default:
 473             return FALSE;
 474     }
 475
 476     /* Check sampler format support. */
 477     if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 478         /* these two are broken for an unknown reason */
 479         format != PIPE_FORMAT_R8G8B8X8_SNORM &&
 480         format != PIPE_FORMAT_R16G16B16X16_SNORM &&
 481         /* ATI1N is r5xx-only. */
 482         (is_r500 || !is_ati1n) &&
 483         /* ATI2N is supported on r4xx-r5xx. */
 484         (is_r400 || is_r500 || !is_ati2n) &&
 485         /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
 486         (drm_2_8_0 || !is_x16f_xy16f) &&
 487         r300_is_sampler_format_supported(format)) {
 488         retval |= PIPE_BIND_SAMPLER_VIEW;
 489     }
 490
 491     /* Check colorbuffer format support. */
 492     if ((usage & (PIPE_BIND_RENDER_TARGET |
 493                   PIPE_BIND_DISPLAY_TARGET |
 494                   PIPE_BIND_SCANOUT |
 495                   PIPE_BIND_SHARED)) &&
 496         /* 2101010 cannot be rendered to on non-r5xx. */
 497         (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
 498         r300_is_colorbuffer_format_supported(format)) {
 499         retval |= usage &
 500             (PIPE_BIND_RENDER_TARGET |
 501              PIPE_BIND_DISPLAY_TARGET |
 502              PIPE_BIND_SCANOUT |
 503              PIPE_BIND_SHARED);
 504     }
 505
 506     /* Check depth-stencil format support. */
 507     if (usage & PIPE_BIND_DEPTH_STENCIL &&
 508         r300_is_zs_format_supported(format)) {
 509         retval |= PIPE_BIND_DEPTH_STENCIL;
 510     }
 511
 512     /* Check vertex buffer format support. */
 513     if (usage & PIPE_BIND_VERTEX_BUFFER) {
 514         if (r300_screen(screen)->caps.has_tcl) {
 515             /* Half float is supported on >= R400. */
 516             if ((is_r400 || is_r500 || !is_half_float) &&
 517                 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
 518                 retval |= PIPE_BIND_VERTEX_BUFFER;
 519             }
 520         } else {
 521             /* SW TCL */
 522             if (!util_format_is_pure_integer(format)) {
 523                 retval |= PIPE_BIND_VERTEX_BUFFER;
 524             }
 525         }
 526     }
 527
 528     /* Transfers are always supported. */
 529     if (usage & PIPE_BIND_TRANSFER_READ)
 530         retval |= PIPE_BIND_TRANSFER_READ;
 531     if (usage & PIPE_BIND_TRANSFER_WRITE)
 532         retval |= PIPE_BIND_TRANSFER_WRITE;
 533
 534     return retval == usage;
 535 }
 536
 537 static void r300_destroy_screen(struct pipe_screen* pscreen)
 538 {
 539     struct r300_screen* r300screen = r300_screen(pscreen);
 540     struct radeon_winsys *rws = radeon_winsys(pscreen);
 541
 542     pipe_mutex_destroy(r300screen->cmask_mutex);
 543
 544     if (rws)
 545       rws->destroy(rws);
 546
 547     FREE(r300screen);
 548 }
 549
 550 static void r300_fence_reference(struct pipe_screen *screen,
 551                                  struct pipe_fence_handle **ptr,
 552                                  struct pipe_fence_handle *fence)
 553 {
 554     pb_reference((struct pb_buffer**)ptr,
 555                              (struct pb_buffer*)fence);
 556 }
 557
 558 static boolean r300_fence_signalled(struct pipe_screen *screen,
 559                                     struct pipe_fence_handle *fence)
 560 {
 561     struct radeon_winsys *rws = r300_screen(screen)->rws;
 562     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 563
 564     return !rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE);
 565 }
 566
 567 static boolean r300_fence_finish(struct pipe_screen *screen,
 568                                  struct pipe_fence_handle *fence,
 569                                  uint64_t timeout)
 570 {
 571     struct radeon_winsys *rws = r300_screen(screen)->rws;
 572     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 573
 574     if (timeout != PIPE_TIMEOUT_INFINITE) {
 575         int64_t start_time = os_time_get();
 576
 577         /* Convert to microseconds. */
 578         timeout /= 1000;
 579
 580         /* Wait in a loop. */
 581         while (rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) {
 582             if (os_time_get() - start_time >= timeout) {
 583                 return FALSE;
 584             }
 585             os_time_sleep(10);
 586         }
 587         return TRUE;
 588     }
 589
 590     rws->buffer_wait(rfence, RADEON_USAGE_READWRITE);
 591     return TRUE;
 592 }
 593
 594 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
 595 {
 596     struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
 597
 598     if (!r300screen) {
 599         FREE(r300screen);
 600         return NULL;
 601     }
 602
 603     rws->query_info(rws, &r300screen->info);
 604
 605     r300_init_debug(r300screen);
 606     r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
 607
 608     if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
 609         r300screen->caps.zmask_ram = 0;
 610     if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
 611         r300screen->caps.hiz_ram = 0;
 612
 613     if (r300screen->info.drm_minor < 8)
 614         r300screen->caps.has_us_format = FALSE;
 615
 616     r300screen->rws = rws;
 617     r300screen->screen.destroy = r300_destroy_screen;
 618     r300screen->screen.get_name = r300_get_name;
 619     r300screen->screen.get_vendor = r300_get_vendor;
 620     r300screen->screen.get_param = r300_get_param;
 621     r300screen->screen.get_shader_param = r300_get_shader_param;
 622     r300screen->screen.get_paramf = r300_get_paramf;
 623     r300screen->screen.get_video_param = r300_get_video_param;
 624     r300screen->screen.is_format_supported = r300_is_format_supported;
 625     r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 626     r300screen->screen.context_create = r300_create_context;
 627     r300screen->screen.fence_reference = r300_fence_reference;
 628     r300screen->screen.fence_signalled = r300_fence_signalled;
 629     r300screen->screen.fence_finish = r300_fence_finish;
 630
 631     r300_init_screen_resource_functions(r300screen);
 632
 633     util_format_s3tc_init();
 634     pipe_mutex_init(r300screen->cmask_mutex);
 635
 636     return &r300screen->screen;
 637 }