2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static INLINE
unsigned evergreen_array_mode(unsigned mode
)
38 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
40 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
42 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
44 case RADEON_SURF_MODE_LINEAR
: return V_028C70_ARRAY_LINEAR_GENERAL
;
48 static uint32_t eg_num_banks(uint32_t nbanks
)
64 static unsigned eg_tile_split(unsigned tile_split
)
67 case 64: tile_split
= 0; break;
68 case 128: tile_split
= 1; break;
69 case 256: tile_split
= 2; break;
70 case 512: tile_split
= 3; break;
72 case 1024: tile_split
= 4; break;
73 case 2048: tile_split
= 5; break;
74 case 4096: tile_split
= 6; break;
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
81 switch (macro_tile_aspect
) {
83 case 1: macro_tile_aspect
= 0; break;
84 case 2: macro_tile_aspect
= 1; break;
85 case 4: macro_tile_aspect
= 2; break;
86 case 8: macro_tile_aspect
= 3; break;
88 return macro_tile_aspect
;
91 static unsigned eg_bank_wh(unsigned bankwh
)
95 case 1: bankwh
= 0; break;
96 case 2: bankwh
= 1; break;
97 case 4: bankwh
= 2; break;
98 case 8: bankwh
= 3; break;
103 static uint32_t r600_translate_blend_function(int blend_func
)
105 switch (blend_func
) {
107 return V_028780_COMB_DST_PLUS_SRC
;
108 case PIPE_BLEND_SUBTRACT
:
109 return V_028780_COMB_SRC_MINUS_DST
;
110 case PIPE_BLEND_REVERSE_SUBTRACT
:
111 return V_028780_COMB_DST_MINUS_SRC
;
113 return V_028780_COMB_MIN_DST_SRC
;
115 return V_028780_COMB_MAX_DST_SRC
;
117 R600_ERR("Unknown blend function %d\n", blend_func
);
124 static uint32_t r600_translate_blend_factor(int blend_fact
)
126 switch (blend_fact
) {
127 case PIPE_BLENDFACTOR_ONE
:
128 return V_028780_BLEND_ONE
;
129 case PIPE_BLENDFACTOR_SRC_COLOR
:
130 return V_028780_BLEND_SRC_COLOR
;
131 case PIPE_BLENDFACTOR_SRC_ALPHA
:
132 return V_028780_BLEND_SRC_ALPHA
;
133 case PIPE_BLENDFACTOR_DST_ALPHA
:
134 return V_028780_BLEND_DST_ALPHA
;
135 case PIPE_BLENDFACTOR_DST_COLOR
:
136 return V_028780_BLEND_DST_COLOR
;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
139 case PIPE_BLENDFACTOR_CONST_COLOR
:
140 return V_028780_BLEND_CONST_COLOR
;
141 case PIPE_BLENDFACTOR_CONST_ALPHA
:
142 return V_028780_BLEND_CONST_ALPHA
;
143 case PIPE_BLENDFACTOR_ZERO
:
144 return V_028780_BLEND_ZERO
;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
157 case PIPE_BLENDFACTOR_SRC1_COLOR
:
158 return V_028780_BLEND_SRC1_COLOR
;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
160 return V_028780_BLEND_SRC1_ALPHA
;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
162 return V_028780_BLEND_INV_SRC1_COLOR
;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
164 return V_028780_BLEND_INV_SRC1_ALPHA
;
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
173 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
177 case PIPE_TEXTURE_1D
:
178 return V_030000_SQ_TEX_DIM_1D
;
179 case PIPE_TEXTURE_1D_ARRAY
:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
181 case PIPE_TEXTURE_2D
:
182 case PIPE_TEXTURE_RECT
:
183 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
184 V_030000_SQ_TEX_DIM_2D
;
185 case PIPE_TEXTURE_2D_ARRAY
:
186 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
187 V_030000_SQ_TEX_DIM_2D_ARRAY
;
188 case PIPE_TEXTURE_3D
:
189 return V_030000_SQ_TEX_DIM_3D
;
190 case PIPE_TEXTURE_CUBE
:
191 case PIPE_TEXTURE_CUBE_ARRAY
:
192 return V_030000_SQ_TEX_DIM_CUBEMAP
;
196 static uint32_t r600_translate_dbformat(enum pipe_format format
)
199 case PIPE_FORMAT_Z16_UNORM
:
200 return V_028040_Z_16
;
201 case PIPE_FORMAT_Z24X8_UNORM
:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
203 case PIPE_FORMAT_X8Z24_UNORM
:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
205 return V_028040_Z_24
;
206 case PIPE_FORMAT_Z32_FLOAT
:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
208 return V_028040_Z_32_FLOAT
;
214 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
216 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
221 return r600_translate_colorformat(chip
, format
) != ~0U &&
222 r600_translate_colorswap(format
) != ~0U;
225 static bool r600_is_zs_format_supported(enum pipe_format format
)
227 return r600_translate_dbformat(format
) != ~0U;
230 static inline bool r600_is_blending_supported(enum pipe_format format
)
232 return !(util_format_is_pure_integer(format
) || util_format_is_depth_or_stencil(format
));
235 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
236 enum pipe_format format
,
237 enum pipe_texture_target target
,
238 unsigned sample_count
,
241 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
244 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
245 R600_ERR("r600: unsupported texture type %d\n", target
);
249 if (!util_format_is_supported(format
, usage
))
252 if (sample_count
> 1) {
253 if (!rscreen
->has_msaa
)
256 switch (sample_count
) {
266 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
267 if (target
== PIPE_BUFFER
) {
268 if (r600_is_vertex_format_supported(format
))
269 retval
|= PIPE_BIND_SAMPLER_VIEW
;
271 if (r600_is_sampler_format_supported(screen
, format
))
272 retval
|= PIPE_BIND_SAMPLER_VIEW
;
276 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
277 PIPE_BIND_DISPLAY_TARGET
|
279 PIPE_BIND_SHARED
)) &&
280 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
282 (PIPE_BIND_RENDER_TARGET
|
283 PIPE_BIND_DISPLAY_TARGET
|
288 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
289 r600_is_zs_format_supported(format
)) {
290 retval
|= PIPE_BIND_DEPTH_STENCIL
;
293 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
294 r600_is_vertex_format_supported(format
)) {
295 retval
|= PIPE_BIND_VERTEX_BUFFER
;
298 if (usage
& PIPE_BIND_TRANSFER_READ
)
299 retval
|= PIPE_BIND_TRANSFER_READ
;
300 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
301 retval
|= PIPE_BIND_TRANSFER_WRITE
;
303 if ((usage
& PIPE_BIND_BLENDABLE
) &&
304 r600_is_blending_supported(format
))
305 retval
|= PIPE_BIND_BLENDABLE
;
307 return retval
== usage
;
310 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
311 const struct pipe_blend_state
*state
, int mode
)
313 uint32_t color_control
= 0, target_mask
= 0;
314 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
320 r600_init_command_buffer(&blend
->buffer
, 20);
321 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
323 if (state
->logicop_enable
) {
324 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
326 color_control
|= (0xcc << 16);
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state
->independent_blend_enable
) {
330 for (int i
= 0; i
< 8; i
++) {
331 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
334 for (int i
= 0; i
< 8; i
++) {
335 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
339 /* only have dual source on MRT0 */
340 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
341 blend
->cb_target_mask
= target_mask
;
342 blend
->alpha_to_one
= state
->alpha_to_one
;
345 color_control
|= S_028808_MODE(mode
);
347 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
350 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
351 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
362 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
364 for (int i
= 0; i
< 8; i
++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j
= state
->independent_blend_enable
? i
: 0;
368 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
369 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
370 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
371 unsigned eqA
= state
->rt
[j
].alpha_func
;
372 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
373 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
376 r600_store_value(&blend
->buffer_no_blend
, 0);
378 if (!state
->rt
[j
].blend_enable
) {
379 r600_store_value(&blend
->buffer
, 0);
383 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
385 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
386 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
388 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
389 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
391 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
392 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
394 r600_store_value(&blend
->buffer
, bc
);
399 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
400 const struct pipe_blend_state
*state
)
403 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
406 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
407 const struct pipe_depth_stencil_alpha_state
*state
)
409 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
410 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
416 r600_init_command_buffer(&dsa
->buffer
, 3);
418 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
419 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
420 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
421 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
422 dsa
->zwritemask
= state
->depth
.writemask
;
424 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
425 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
426 S_028800_ZFUNC(state
->depth
.func
);
429 if (state
->stencil
[0].enabled
) {
430 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
431 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
432 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
433 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
434 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
436 if (state
->stencil
[1].enabled
) {
437 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
439 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
440 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
441 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
446 alpha_test_control
= 0;
448 if (state
->alpha
.enabled
) {
449 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
450 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref
= fui(state
->alpha
.ref_value
);
453 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
454 dsa
->alpha_ref
= alpha_ref
;
457 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
461 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
462 const struct pipe_rasterizer_state
*state
)
464 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
465 unsigned tmp
, spi_interp
;
466 float psize_min
, psize_max
;
467 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
473 r600_init_command_buffer(&rs
->buffer
, 30);
475 rs
->flatshade
= state
->flatshade
;
476 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
477 rs
->two_side
= state
->light_twoside
;
478 rs
->clip_plane_enable
= state
->clip_plane_enable
;
479 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
480 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
481 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
482 rs
->pa_cl_clip_cntl
=
483 S_028810_PS_UCP_MODE(3) |
484 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
485 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
486 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
487 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
488 rs
->multisample_enable
= state
->multisample
;
491 rs
->offset_units
= state
->offset_units
;
492 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
493 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
495 if (state
->point_size_per_vertex
) {
496 psize_min
= util_get_min_point_size(state
);
499 /* Force the point size to be as if the vertex output was disabled. */
500 psize_min
= state
->point_size
;
501 psize_max
= state
->point_size
;
504 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
505 if (state
->sprite_coord_enable
) {
506 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
507 S_0286D4_PNT_SPRITE_OVRD_X(2) |
508 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
509 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
510 S_0286D4_PNT_SPRITE_OVRD_W(1);
511 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
512 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
516 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
517 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
518 tmp
= r600_pack_float_12p4(state
->point_size
/2);
519 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
520 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
521 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
522 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
523 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
524 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
525 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
527 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
528 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
529 S_028A48_MSAA_ENABLE(state
->multisample
) |
530 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
531 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
533 if (rctx
->b
.chip_class
== CAYMAN
) {
534 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
535 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
536 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
538 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
539 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
540 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
543 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
544 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
545 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
546 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
547 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
548 S_028814_FACE(!state
->front_ccw
) |
549 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
550 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
551 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
552 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
553 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
554 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
555 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
559 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
560 const struct pipe_sampler_state
*state
)
562 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
563 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
569 ss
->border_color_use
= sampler_state_needs_border_color(state
);
571 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
572 ss
->tex_sampler_words
[0] =
573 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
574 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
575 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
576 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
577 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
578 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
579 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
580 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
581 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
582 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
583 ss
->tex_sampler_words
[1] =
584 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
585 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
586 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
587 ss
->tex_sampler_words
[2] =
588 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
589 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
592 if (ss
->border_color_use
) {
593 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
598 static struct pipe_sampler_view
*
599 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
600 unsigned width0
, unsigned height0
)
603 struct pipe_context
*ctx
= view
->base
.context
;
604 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
606 int stride
= util_format_get_blocksize(view
->base
.format
);
607 unsigned format
, num_format
, format_comp
, endian
;
608 unsigned swizzle_res
;
609 unsigned char swizzle
[4];
610 const struct util_format_description
*desc
;
611 unsigned offset
= view
->base
.u
.buf
.first_element
* stride
;
612 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
614 swizzle
[0] = view
->base
.swizzle_r
;
615 swizzle
[1] = view
->base
.swizzle_g
;
616 swizzle
[2] = view
->base
.swizzle_b
;
617 swizzle
[3] = view
->base
.swizzle_a
;
619 r600_vertex_data_type(view
->base
.format
,
620 &format
, &num_format
, &format_comp
,
623 desc
= util_format_description(view
->base
.format
);
625 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, swizzle
, TRUE
);
627 va
= r600_resource_va(ctx
->screen
, view
->base
.texture
) + offset
;
628 view
->tex_resource
= &tmp
->resource
;
630 view
->skip_mip_address_reloc
= true;
631 view
->tex_resource_words
[0] = va
;
632 view
->tex_resource_words
[1] = size
- 1;
633 view
->tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
634 S_030008_STRIDE(stride
) |
635 S_030008_DATA_FORMAT(format
) |
636 S_030008_NUM_FORMAT_ALL(num_format
) |
637 S_030008_FORMAT_COMP_ALL(format_comp
) |
638 S_030008_SRF_MODE_ALL(1) |
639 S_030008_ENDIAN_SWAP(endian
);
640 view
->tex_resource_words
[3] = swizzle_res
;
642 * in theory dword 4 is for number of elements, for use with resinfo,
643 * but it seems to utterly fail to work, the amd gpu shader analyser
644 * uses a const buffer to store the element sizes for buffer txq
646 view
->tex_resource_words
[4] = 0;
647 view
->tex_resource_words
[5] = view
->tex_resource_words
[6] = 0;
648 view
->tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
652 struct pipe_sampler_view
*
653 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
654 struct pipe_resource
*texture
,
655 const struct pipe_sampler_view
*state
,
656 unsigned width0
, unsigned height0
,
657 unsigned force_level
)
659 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
660 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
661 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
662 unsigned format
, endian
;
663 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
664 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
665 unsigned height
, depth
, width
;
666 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
667 enum pipe_format pipe_format
= state
->format
;
668 struct radeon_surface_level
*surflevel
;
669 unsigned base_level
, first_level
, last_level
;
675 /* initialize base object */
677 view
->base
.texture
= NULL
;
678 pipe_reference(NULL
, &texture
->reference
);
679 view
->base
.texture
= texture
;
680 view
->base
.reference
.count
= 1;
681 view
->base
.context
= ctx
;
683 if (texture
->target
== PIPE_BUFFER
)
684 return texture_buffer_sampler_view(view
, width0
, height0
);
686 swizzle
[0] = state
->swizzle_r
;
687 swizzle
[1] = state
->swizzle_g
;
688 swizzle
[2] = state
->swizzle_b
;
689 swizzle
[3] = state
->swizzle_a
;
691 tile_split
= tmp
->surface
.tile_split
;
692 surflevel
= tmp
->surface
.level
;
694 /* Texturing with separate depth and stencil. */
695 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
696 switch (pipe_format
) {
697 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
698 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
700 case PIPE_FORMAT_X8Z24_UNORM
:
701 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
702 /* Z24 is always stored like this. */
703 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
705 case PIPE_FORMAT_X24S8_UINT
:
706 case PIPE_FORMAT_S8X24_UINT
:
707 case PIPE_FORMAT_X32_S8X24_UINT
:
708 pipe_format
= PIPE_FORMAT_S8_UINT
;
709 tile_split
= tmp
->surface
.stencil_tile_split
;
710 surflevel
= tmp
->surface
.stencil_level
;
716 format
= r600_translate_texformat(ctx
->screen
, pipe_format
,
718 &word4
, &yuv_format
);
719 assert(format
!= ~0);
725 endian
= r600_colorformat_endian_swap(format
);
728 first_level
= state
->u
.tex
.first_level
;
729 last_level
= state
->u
.tex
.last_level
;
732 depth
= texture
->depth0
;
735 base_level
= force_level
;
738 width
= u_minify(width
, force_level
);
739 height
= u_minify(height
, force_level
);
740 depth
= u_minify(depth
, force_level
);
743 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(pipe_format
);
744 non_disp_tiling
= tmp
->non_disp_tiling
;
746 switch (surflevel
[base_level
].mode
) {
747 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
748 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
750 case RADEON_SURF_MODE_2D
:
751 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
753 case RADEON_SURF_MODE_1D
:
754 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
756 case RADEON_SURF_MODE_LINEAR
:
758 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
761 macro_aspect
= tmp
->surface
.mtilea
;
762 bankw
= tmp
->surface
.bankw
;
763 bankh
= tmp
->surface
.bankh
;
764 tile_split
= eg_tile_split(tile_split
);
765 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
766 bankw
= eg_bank_wh(bankw
);
767 bankh
= eg_bank_wh(bankh
);
768 fmask_bankh
= eg_bank_wh(tmp
->fmask
.bank_height
);
770 /* 128 bit formats require tile type = 1 */
771 if (rscreen
->b
.chip_class
== CAYMAN
) {
772 if (util_format_get_blocksize(pipe_format
) >= 16)
775 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
777 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
779 depth
= texture
->array_size
;
780 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
781 depth
= texture
->array_size
;
782 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
783 depth
= texture
->array_size
/ 6;
785 va
= r600_resource_va(ctx
->screen
, texture
);
787 view
->tex_resource
= &tmp
->resource
;
788 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
789 S_030000_PITCH((pitch
/ 8) - 1) |
790 S_030000_TEX_WIDTH(width
- 1));
791 if (rscreen
->b
.chip_class
== CAYMAN
)
792 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
794 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
795 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
796 S_030004_TEX_DEPTH(depth
- 1) |
797 S_030004_ARRAY_MODE(array_mode
));
798 view
->tex_resource_words
[2] = (surflevel
[base_level
].offset
+ va
) >> 8;
800 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
801 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
803 /* disable FMASK (0 = disabled) */
804 view
->tex_resource_words
[3] = 0;
805 view
->skip_mip_address_reloc
= true;
807 /* FMASK should be in MIP_ADDRESS for multisample textures */
808 view
->tex_resource_words
[3] = (tmp
->fmask
.offset
+ va
) >> 8;
810 } else if (last_level
&& texture
->nr_samples
<= 1) {
811 view
->tex_resource_words
[3] = (surflevel
[1].offset
+ va
) >> 8;
813 view
->tex_resource_words
[3] = (surflevel
[base_level
].offset
+ va
) >> 8;
816 view
->tex_resource_words
[4] = (word4
|
817 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
818 S_030010_ENDIAN_SWAP(endian
));
819 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
820 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
821 view
->tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
823 if (texture
->nr_samples
> 1) {
824 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
825 if (rscreen
->b
.chip_class
== CAYMAN
) {
826 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
828 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
829 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
830 view
->tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
832 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(first_level
);
833 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(last_level
);
834 /* aniso max 16 samples */
835 view
->tex_resource_words
[6] |= S_030018_MAX_ANISO(4);
838 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
839 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
840 S_03001C_BANK_WIDTH(bankw
) |
841 S_03001C_BANK_HEIGHT(bankh
) |
842 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
843 S_03001C_NUM_BANKS(nbanks
) |
844 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
848 static struct pipe_sampler_view
*
849 evergreen_create_sampler_view(struct pipe_context
*ctx
,
850 struct pipe_resource
*tex
,
851 const struct pipe_sampler_view
*state
)
853 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
854 tex
->width0
, tex
->height0
, 0);
857 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
859 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
860 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
862 r600_write_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
863 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
866 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
867 const struct pipe_poly_stipple
*state
)
871 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
872 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
873 uint32_t *tl
, uint32_t *br
)
875 /* EG hw workaround */
881 /* cayman hw workaround */
882 if (rctx
->b
.chip_class
== CAYMAN
) {
883 if (br_x
== 1 && br_y
== 1)
887 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
888 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
891 static void evergreen_set_scissor_states(struct pipe_context
*ctx
,
893 unsigned num_scissors
,
894 const struct pipe_scissor_state
*state
)
896 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
899 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
900 rctx
->scissor
[i
].scissor
= state
[i
- start_slot
];
901 rctx
->scissor
[i
].atom
.dirty
= true;
905 static void evergreen_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
907 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
908 struct r600_scissor_state
*rstate
= (struct r600_scissor_state
*)atom
;
909 struct pipe_scissor_state
*state
= &rstate
->scissor
;
910 unsigned offset
= rstate
->idx
* 4 * 2;
913 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
915 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ offset
, 2);
921 * This function intializes the CB* register values for RATs. It is meant
922 * to be used for 1D aligned buffers that do not have an associated
925 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
926 struct r600_surface
*surf
)
928 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
929 unsigned format
= r600_translate_colorformat(rctx
->b
.chip_class
,
931 unsigned endian
= r600_colorformat_endian_swap(format
);
932 unsigned swap
= r600_translate_colorswap(surf
->base
.format
);
933 unsigned block_size
=
934 align(util_format_get_blocksize(pipe_buffer
->format
), 4);
935 unsigned pitch_alignment
=
936 MAX2(64, rctx
->screen
->b
.tiling_info
.group_bytes
/ block_size
);
937 unsigned pitch
= align(pipe_buffer
->width0
, pitch_alignment
);
939 /* XXX: This is copied from evergreen_init_color_surface(). I don't
940 * know why this is necessary.
942 if (pipe_buffer
->usage
== PIPE_USAGE_STAGING
) {
943 endian
= ENDIAN_NONE
;
946 surf
->cb_color_base
=
947 r600_resource_va(rctx
->b
.b
.screen
, pipe_buffer
) >> 8;
949 surf
->cb_color_pitch
= (pitch
/ 8) - 1;
951 surf
->cb_color_slice
= 0;
953 surf
->cb_color_view
= 0;
955 surf
->cb_color_info
=
956 S_028C70_ENDIAN(endian
)
957 | S_028C70_FORMAT(format
)
958 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
)
959 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT
)
960 | S_028C70_COMP_SWAP(swap
)
961 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
962 * are using NUMBER_UINT */
966 surf
->cb_color_attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
968 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
970 surf
->cb_color_dim
= pipe_buffer
->width0
;
972 /* Set the buffer range the GPU will have access to: */
973 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
974 0, pipe_buffer
->width0
);
976 surf
->cb_color_fmask
= surf
->cb_color_base
;
977 surf
->cb_color_fmask_slice
= 0;
980 void evergreen_init_color_surface(struct r600_context
*rctx
,
981 struct r600_surface
*surf
)
983 struct r600_screen
*rscreen
= rctx
->screen
;
984 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
985 struct pipe_resource
*pipe_tex
= surf
->base
.texture
;
986 unsigned level
= surf
->base
.u
.tex
.level
;
987 unsigned pitch
, slice
;
988 unsigned color_info
, color_attrib
, color_dim
= 0, color_view
;
989 unsigned format
, swap
, ntype
, endian
;
990 uint64_t offset
, base_offset
;
991 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
992 const struct util_format_description
*desc
;
994 bool blend_clamp
= 0, blend_bypass
= 0;
996 offset
= rtex
->surface
.level
[level
].offset
;
997 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
998 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
999 offset
+= rtex
->surface
.level
[level
].slice_size
*
1000 surf
->base
.u
.tex
.first_layer
;
1003 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1004 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1006 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1007 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1012 switch (rtex
->surface
.level
[level
].mode
) {
1013 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1014 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1015 non_disp_tiling
= 1;
1017 case RADEON_SURF_MODE_1D
:
1018 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1019 non_disp_tiling
= rtex
->non_disp_tiling
;
1021 case RADEON_SURF_MODE_2D
:
1022 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1023 non_disp_tiling
= rtex
->non_disp_tiling
;
1025 case RADEON_SURF_MODE_LINEAR
:
1027 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1028 non_disp_tiling
= 1;
1031 tile_split
= rtex
->surface
.tile_split
;
1032 macro_aspect
= rtex
->surface
.mtilea
;
1033 bankw
= rtex
->surface
.bankw
;
1034 bankh
= rtex
->surface
.bankh
;
1035 fmask_bankh
= rtex
->fmask
.bank_height
;
1036 tile_split
= eg_tile_split(tile_split
);
1037 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1038 bankw
= eg_bank_wh(bankw
);
1039 bankh
= eg_bank_wh(bankh
);
1040 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1042 /* 128 bit formats require tile type = 1 */
1043 if (rscreen
->b
.chip_class
== CAYMAN
) {
1044 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1045 non_disp_tiling
= 1;
1047 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
1048 desc
= util_format_description(surf
->base
.format
);
1049 for (i
= 0; i
< 4; i
++) {
1050 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1055 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1056 S_028C74_NUM_BANKS(nbanks
) |
1057 S_028C74_BANK_WIDTH(bankw
) |
1058 S_028C74_BANK_HEIGHT(bankh
) |
1059 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1060 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1061 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1063 if (rctx
->b
.chip_class
== CAYMAN
) {
1064 color_attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1065 UTIL_FORMAT_SWIZZLE_1
);
1067 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1068 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1069 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1070 S_028C74_NUM_FRAGMENTS(log_samples
);
1074 ntype
= V_028C70_NUMBER_UNORM
;
1075 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1076 ntype
= V_028C70_NUMBER_SRGB
;
1077 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1078 if (desc
->channel
[i
].normalized
)
1079 ntype
= V_028C70_NUMBER_SNORM
;
1080 else if (desc
->channel
[i
].pure_integer
)
1081 ntype
= V_028C70_NUMBER_SINT
;
1082 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1083 if (desc
->channel
[i
].normalized
)
1084 ntype
= V_028C70_NUMBER_UNORM
;
1085 else if (desc
->channel
[i
].pure_integer
)
1086 ntype
= V_028C70_NUMBER_UINT
;
1089 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
);
1090 assert(format
!= ~0);
1092 swap
= r600_translate_colorswap(surf
->base
.format
);
1095 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1096 endian
= ENDIAN_NONE
;
1098 endian
= r600_colorformat_endian_swap(format
);
1101 /* blend clamp should be set for all NORM/SRGB types */
1102 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1103 ntype
== V_028C70_NUMBER_SRGB
)
1106 /* set blend bypass according to docs if SINT/UINT or
1107 8/24 COLOR variants */
1108 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1109 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1110 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1115 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1117 color_info
|= S_028C70_FORMAT(format
) |
1118 S_028C70_COMP_SWAP(swap
) |
1119 S_028C70_BLEND_CLAMP(blend_clamp
) |
1120 S_028C70_BLEND_BYPASS(blend_bypass
) |
1121 S_028C70_NUMBER_TYPE(ntype
) |
1122 S_028C70_ENDIAN(endian
);
1124 /* EXPORT_NORM is an optimzation that can be enabled for better
1125 * performance in certain cases.
1126 * EXPORT_NORM can be enabled if:
1127 * - 11-bit or smaller UNORM/SNORM/SRGB
1128 * - 16-bit or smaller FLOAT
1130 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1131 ((desc
->channel
[i
].size
< 12 &&
1132 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1133 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1134 (desc
->channel
[i
].size
< 17 &&
1135 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1136 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1137 surf
->export_16bpc
= true;
1140 if (rtex
->fmask
.size
) {
1141 color_info
|= S_028C70_COMPRESSION(1);
1144 base_offset
= r600_resource_va(rctx
->b
.b
.screen
, pipe_tex
);
1146 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1147 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1148 surf
->cb_color_dim
= color_dim
;
1149 surf
->cb_color_info
= color_info
;
1150 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1151 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1152 surf
->cb_color_view
= color_view
;
1153 surf
->cb_color_attrib
= color_attrib
;
1154 if (rtex
->fmask
.size
) {
1155 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask
.offset
) >> 8;
1157 surf
->cb_color_fmask
= surf
->cb_color_base
;
1159 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1161 surf
->color_initialized
= true;
1164 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1165 struct r600_surface
*surf
)
1167 struct r600_screen
*rscreen
= rctx
->screen
;
1168 struct pipe_screen
*screen
= &rscreen
->b
.b
;
1169 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1171 unsigned level
, pitch
, slice
, format
, array_mode
;
1172 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1174 level
= surf
->base
.u
.tex
.level
;
1175 format
= r600_translate_dbformat(surf
->base
.format
);
1176 assert(format
!= ~0);
1178 offset
= r600_resource_va(screen
, surf
->base
.texture
);
1179 offset
+= rtex
->surface
.level
[level
].offset
;
1180 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1181 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1185 switch (rtex
->surface
.level
[level
].mode
) {
1186 case RADEON_SURF_MODE_2D
:
1187 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1189 case RADEON_SURF_MODE_1D
:
1190 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1191 case RADEON_SURF_MODE_LINEAR
:
1193 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1196 tile_split
= rtex
->surface
.tile_split
;
1197 macro_aspect
= rtex
->surface
.mtilea
;
1198 bankw
= rtex
->surface
.bankw
;
1199 bankh
= rtex
->surface
.bankh
;
1200 tile_split
= eg_tile_split(tile_split
);
1201 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1202 bankw
= eg_bank_wh(bankw
);
1203 bankh
= eg_bank_wh(bankh
);
1204 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
1207 surf
->db_z_info
= S_028040_ARRAY_MODE(array_mode
) |
1208 S_028040_FORMAT(format
) |
1209 S_028040_TILE_SPLIT(tile_split
)|
1210 S_028040_NUM_BANKS(nbanks
) |
1211 S_028040_BANK_WIDTH(bankw
) |
1212 S_028040_BANK_HEIGHT(bankh
) |
1213 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1214 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1215 surf
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1217 surf
->db_depth_base
= offset
;
1218 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1219 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1220 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1221 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1223 switch (surf
->base
.format
) {
1224 case PIPE_FORMAT_Z24X8_UNORM
:
1225 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1226 case PIPE_FORMAT_X8Z24_UNORM
:
1227 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1228 surf
->pa_su_poly_offset_db_fmt_cntl
=
1229 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1231 case PIPE_FORMAT_Z32_FLOAT
:
1232 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1233 surf
->pa_su_poly_offset_db_fmt_cntl
=
1234 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1235 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1237 case PIPE_FORMAT_Z16_UNORM
:
1238 surf
->pa_su_poly_offset_db_fmt_cntl
=
1239 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1244 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1245 uint64_t stencil_offset
;
1246 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1248 stile_split
= eg_tile_split(stile_split
);
1250 stencil_offset
= rtex
->surface
.stencil_level
[level
].offset
;
1251 stencil_offset
+= r600_resource_va(screen
, surf
->base
.texture
);
1253 surf
->db_stencil_base
= stencil_offset
>> 8;
1254 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1255 S_028044_TILE_SPLIT(stile_split
);
1257 surf
->db_stencil_base
= offset
;
1258 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1259 * Older kernels are out of luck. */
1260 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1261 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1262 S_028044_FORMAT(V_028044_STENCIL_8
);
1265 /* use htile only for first level */
1266 if (rtex
->htile_buffer
&& !level
) {
1267 uint64_t va
= r600_resource_va(&rctx
->screen
->b
.b
, &rtex
->htile_buffer
->b
.b
);
1268 surf
->db_htile_data_base
= va
>> 8;
1269 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1270 S_028ABC_HTILE_HEIGHT(1) |
1271 S_028ABC_FULL_CACHE(1) |
1273 surf
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1274 surf
->db_preload_control
= 0;
1277 surf
->depth_initialized
= true;
1280 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1281 const struct pipe_framebuffer_state
*state
)
1283 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1284 struct r600_surface
*surf
;
1285 struct r600_texture
*rtex
;
1286 uint32_t i
, log_samples
;
1288 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1289 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1290 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
1291 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1293 if (rctx
->framebuffer
.state
.zsbuf
) {
1294 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1295 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
1297 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1298 if (rtex
->htile_buffer
) {
1299 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1303 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1306 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1307 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1308 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1309 rctx
->framebuffer
.compressed_cb_mask
= 0;
1310 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1312 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1313 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1317 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1319 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1321 if (!surf
->color_initialized
) {
1322 evergreen_init_color_surface(rctx
, surf
);
1325 if (!surf
->export_16bpc
) {
1326 rctx
->framebuffer
.export_16bpc
= false;
1329 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1330 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1334 /* Update alpha-test state dependencies.
1335 * Alpha-test is done on the first colorbuffer only. */
1336 if (state
->nr_cbufs
) {
1337 bool alphatest_bypass
= false;
1338 bool export_16bpc
= true;
1340 surf
= (struct r600_surface
*)state
->cbufs
[0];
1342 alphatest_bypass
= surf
->alphatest_bypass
;
1343 export_16bpc
= surf
->export_16bpc
;
1346 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1347 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1348 rctx
->alphatest_state
.atom
.dirty
= true;
1350 if (rctx
->alphatest_state
.cb0_export_16bpc
!= export_16bpc
) {
1351 rctx
->alphatest_state
.cb0_export_16bpc
= export_16bpc
;
1352 rctx
->alphatest_state
.atom
.dirty
= true;
1358 surf
= (struct r600_surface
*)state
->zsbuf
;
1360 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1362 if (!surf
->depth_initialized
) {
1363 evergreen_init_depth_surface(rctx
, surf
);
1366 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1367 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1368 rctx
->poly_offset_state
.atom
.dirty
= true;
1371 if (rctx
->db_state
.rsurf
!= surf
) {
1372 rctx
->db_state
.rsurf
= surf
;
1373 rctx
->db_state
.atom
.dirty
= true;
1374 rctx
->db_misc_state
.atom
.dirty
= true;
1376 } else if (rctx
->db_state
.rsurf
) {
1377 rctx
->db_state
.rsurf
= NULL
;
1378 rctx
->db_state
.atom
.dirty
= true;
1379 rctx
->db_misc_state
.atom
.dirty
= true;
1382 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1383 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1384 rctx
->cb_misc_state
.atom
.dirty
= true;
1387 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1388 rctx
->alphatest_state
.bypass
= false;
1389 rctx
->alphatest_state
.atom
.dirty
= true;
1392 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1393 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1394 if ((rctx
->b
.chip_class
== CAYMAN
||
1395 rctx
->b
.family
== CHIP_RV770
) &&
1396 rctx
->db_misc_state
.log_samples
!= log_samples
) {
1397 rctx
->db_misc_state
.log_samples
= log_samples
;
1398 rctx
->db_misc_state
.atom
.dirty
= true;
1402 /* Calculate the CS size. */
1403 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1406 if (rctx
->b
.chip_class
== EVERGREEN
)
1407 rctx
->framebuffer
.atom
.num_dw
+= 14; /* Evergreen */
1409 rctx
->framebuffer
.atom
.num_dw
+= 25; /* Cayman */
1412 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1413 if (rctx
->keep_tiling_flags
)
1414 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1415 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1419 rctx
->framebuffer
.atom
.num_dw
+= 24;
1420 if (rctx
->keep_tiling_flags
)
1421 rctx
->framebuffer
.atom
.num_dw
+= 2;
1422 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1423 rctx
->framebuffer
.atom
.num_dw
+= 4;
1426 rctx
->framebuffer
.atom
.dirty
= true;
1431 static uint32_t sample_locs_8x
[] = {
1432 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1433 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1434 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1435 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1436 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1437 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1438 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1439 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1441 static unsigned max_dist_8x
= 7;
1443 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1444 unsigned sample_count
,
1445 unsigned sample_index
,
1452 switch (sample_count
) {
1455 out_value
[0] = out_value
[1] = 0.5;
1458 offset
= 4 * (sample_index
* 2);
1459 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1460 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1461 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1462 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1465 offset
= 4 * (sample_index
* 2);
1466 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1467 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1468 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1469 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1472 offset
= 4 * (sample_index
% 4 * 2);
1473 index
= (sample_index
/ 4);
1474 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1475 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1476 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1477 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1482 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1485 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1486 unsigned max_dist
= 0;
1488 switch (nr_samples
) {
1493 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(eg_sample_locs_2x
));
1494 radeon_emit_array(cs
, eg_sample_locs_2x
, Elements(eg_sample_locs_2x
));
1495 max_dist
= eg_max_dist_2x
;
1498 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(eg_sample_locs_4x
));
1499 radeon_emit_array(cs
, eg_sample_locs_4x
, Elements(eg_sample_locs_4x
));
1500 max_dist
= eg_max_dist_4x
;
1503 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_8x
));
1504 radeon_emit_array(cs
, sample_locs_8x
, Elements(sample_locs_8x
));
1505 max_dist
= max_dist_8x
;
1509 if (nr_samples
> 1) {
1510 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1511 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1512 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1513 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1514 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1516 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1517 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1518 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1522 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1524 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1525 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1526 unsigned nr_cbufs
= state
->nr_cbufs
;
1528 struct r600_texture
*tex
= NULL
;
1529 struct r600_surface
*cb
= NULL
;
1531 /* XXX support more colorbuffers once we need them */
1532 assert(nr_cbufs
<= 8);
1537 for (i
= 0; i
< nr_cbufs
; i
++) {
1538 unsigned reloc
, cmask_reloc
;
1540 cb
= (struct r600_surface
*)state
->cbufs
[i
];
1542 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1543 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1547 tex
= (struct r600_texture
*)cb
->base
.texture
;
1548 reloc
= r600_context_bo_reloc(&rctx
->b
,
1550 (struct r600_resource
*)cb
->base
.texture
,
1551 RADEON_USAGE_READWRITE
,
1552 tex
->surface
.nsamples
> 1 ?
1553 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1554 RADEON_PRIO_COLOR_BUFFER
);
1556 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
1557 cmask_reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1558 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
1559 RADEON_PRIO_COLOR_META
);
1561 cmask_reloc
= reloc
;
1564 r600_write_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
1565 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1566 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1567 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1568 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1569 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1570 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1571 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1572 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
1573 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1574 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1575 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1576 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1577 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1579 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1580 radeon_emit(cs
, reloc
);
1582 if (!rctx
->keep_tiling_flags
) {
1583 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1584 radeon_emit(cs
, reloc
);
1587 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1588 radeon_emit(cs
, reloc
);
1590 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1591 radeon_emit(cs
, cmask_reloc
);
1593 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1594 radeon_emit(cs
, reloc
);
1596 /* set CB_COLOR1_INFO for possible dual-src blending */
1597 if (i
== 1 && state
->cbufs
[0]) {
1598 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1599 cb
->cb_color_info
| tex
->cb_color_info
);
1601 if (!rctx
->keep_tiling_flags
) {
1602 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1604 (struct r600_resource
*)state
->cbufs
[0]->texture
,
1605 RADEON_USAGE_READWRITE
,
1606 RADEON_PRIO_COLOR_BUFFER
);
1608 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1609 radeon_emit(cs
, reloc
);
1613 if (rctx
->keep_tiling_flags
) {
1614 for (; i
< 8 ; i
++) {
1615 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1617 for (; i
< 12; i
++) {
1618 r600_write_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
1624 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
1625 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1627 (struct r600_resource
*)state
->zsbuf
->texture
,
1628 RADEON_USAGE_READWRITE
,
1629 zb
->base
.texture
->nr_samples
> 1 ?
1630 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1631 RADEON_PRIO_DEPTH_BUFFER
);
1633 r600_write_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1634 zb
->pa_su_poly_offset_db_fmt_cntl
);
1635 r600_write_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
1637 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
1638 radeon_emit(cs
, zb
->db_z_info
); /* R_028040_DB_Z_INFO */
1639 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1640 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
1641 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1642 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
1643 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1644 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1645 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1647 if (!rctx
->keep_tiling_flags
) {
1648 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028040_DB_Z_INFO */
1649 radeon_emit(cs
, reloc
);
1652 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1653 radeon_emit(cs
, reloc
);
1655 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1656 radeon_emit(cs
, reloc
);
1658 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1659 radeon_emit(cs
, reloc
);
1661 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1662 radeon_emit(cs
, reloc
);
1663 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1664 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1665 * Older kernels are out of luck. */
1666 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
1667 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1668 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1671 /* Framebuffer dimensions. */
1672 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1674 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1675 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1676 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1678 if (rctx
->b
.chip_class
== EVERGREEN
) {
1679 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1681 cayman_emit_msaa_state(cs
, rctx
->framebuffer
.nr_samples
);
1685 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
1687 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1688 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
1689 float offset_units
= state
->offset_units
;
1690 float offset_scale
= state
->offset_scale
;
1692 switch (state
->zs_format
) {
1693 case PIPE_FORMAT_Z24X8_UNORM
:
1694 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1695 case PIPE_FORMAT_X8Z24_UNORM
:
1696 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1697 offset_units
*= 2.0f
;
1699 case PIPE_FORMAT_Z16_UNORM
:
1700 offset_units
*= 4.0f
;
1705 r600_write_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1706 radeon_emit(cs
, fui(offset_scale
));
1707 radeon_emit(cs
, fui(offset_units
));
1708 radeon_emit(cs
, fui(offset_scale
));
1709 radeon_emit(cs
, fui(offset_units
));
1712 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1714 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1715 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1716 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1717 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1719 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1720 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1721 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1722 * will assure that the alpha-test will work even if there is
1723 * no colorbuffer bound. */
1724 radeon_emit(cs
, 0xf | (a
->dual_src_blend
? ps_colormask
: 0) | fb_colormask
); /* R_02823C_CB_SHADER_MASK */
1727 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1729 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1730 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1732 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1733 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1736 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1737 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1738 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
1739 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1740 reloc_idx
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rtex
->htile_buffer
,
1741 RADEON_USAGE_READWRITE
, RADEON_PRIO_DEPTH_META
);
1742 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1743 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1745 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
1746 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
1750 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1752 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1753 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1754 unsigned db_render_control
= 0;
1755 unsigned db_count_control
= 0;
1756 unsigned db_render_override
=
1757 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1758 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1760 if (a
->occlusion_query_enabled
) {
1761 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1762 if (rctx
->b
.chip_class
== CAYMAN
) {
1763 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
1765 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1767 /* FIXME we should be able to use hyperz even if we are not writing to
1768 * zbuffer but somehow this trigger GPU lockup. See :
1770 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
1772 * Disable hyperz for now if not writing to zbuffer.
1774 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->db_htile_surface
&& rctx
->zwritemask
) {
1775 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1776 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF
);
1777 /* This is to fix a lockup when hyperz and alpha test are enabled at
1778 * the same time somehow GPU get confuse on which order to pick for
1781 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1782 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
1785 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
);
1787 if (a
->flush_depthstencil_through_cb
) {
1788 assert(a
->copy_depth
|| a
->copy_stencil
);
1790 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1791 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1792 S_028000_COPY_CENTROID(1) |
1793 S_028000_COPY_SAMPLE(a
->copy_sample
);
1794 } else if (a
->flush_depthstencil_in_place
) {
1795 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(1) |
1796 S_028000_STENCIL_COMPRESS_DISABLE(1);
1797 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1799 if (a
->htile_clear
) {
1800 /* FIXME we might want to disable cliprect here */
1801 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
1804 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1805 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
1806 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
1807 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1808 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1811 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
1812 struct r600_vertexbuf_state
*state
,
1813 unsigned resource_offset
,
1816 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1817 uint32_t dirty_mask
= state
->dirty_mask
;
1819 while (dirty_mask
) {
1820 struct pipe_vertex_buffer
*vb
;
1821 struct r600_resource
*rbuffer
;
1823 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1825 vb
= &state
->vb
[buffer_index
];
1826 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1829 va
= r600_resource_va(&rctx
->screen
->b
.b
, &rbuffer
->b
.b
);
1830 va
+= vb
->buffer_offset
;
1832 /* fetch resources start at index 992 */
1833 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1834 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
1835 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1836 radeon_emit(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1837 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1838 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1839 S_030008_STRIDE(vb
->stride
) |
1840 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1841 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1842 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1843 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1844 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1845 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1846 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1847 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1848 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1849 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1851 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1852 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1853 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1855 state
->dirty_mask
= 0;
1858 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1860 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
1863 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1865 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
1866 RADEON_CP_PACKET3_COMPUTE_MODE
);
1869 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
1870 struct r600_constbuf_state
*state
,
1871 unsigned buffer_id_base
,
1872 unsigned reg_alu_constbuf_size
,
1873 unsigned reg_alu_const_cache
,
1876 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1877 uint32_t dirty_mask
= state
->dirty_mask
;
1879 while (dirty_mask
) {
1880 struct pipe_constant_buffer
*cb
;
1881 struct r600_resource
*rbuffer
;
1883 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1884 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1886 cb
= &state
->cb
[buffer_index
];
1887 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1890 va
= r600_resource_va(&rctx
->screen
->b
.b
, &rbuffer
->b
.b
);
1891 va
+= cb
->buffer_offset
;
1893 if (!gs_ring_buffer
) {
1894 r600_write_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1895 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16), pkt_flags
);
1896 r600_write_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
1900 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1901 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1902 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1904 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1905 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
1906 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1907 radeon_emit(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1908 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1909 S_030008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1910 S_030008_STRIDE(gs_ring_buffer
? 4 : 16) |
1911 S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
1912 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT
));
1913 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1914 S_03000C_UNCACHED(gs_ring_buffer
? 1 : 0) |
1915 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1916 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1917 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1918 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1919 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1920 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1921 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1922 radeon_emit(cs
, /* RESOURCEi_WORD7 */
1923 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
));
1925 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1926 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1927 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1929 dirty_mask
&= ~(1 << buffer_index
);
1931 state
->dirty_mask
= 0;
1934 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1936 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 176,
1937 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1938 R_028980_ALU_CONST_CACHE_VS_0
,
1939 0 /* PKT3 flags */);
1942 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1944 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1945 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1946 R_0289C0_ALU_CONST_CACHE_GS_0
,
1947 0 /* PKT3 flags */);
1950 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1952 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1953 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1954 R_028940_ALU_CONST_CACHE_PS_0
,
1955 0 /* PKT3 flags */);
1958 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1960 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
], 816,
1961 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
1962 R_028F40_ALU_CONST_CACHE_LS_0
,
1963 RADEON_CP_PACKET3_COMPUTE_MODE
);
1966 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
1967 struct r600_samplerview_state
*state
,
1968 unsigned resource_id_base
)
1970 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1971 uint32_t dirty_mask
= state
->dirty_mask
;
1973 while (dirty_mask
) {
1974 struct r600_pipe_sampler_view
*rview
;
1975 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1978 rview
= state
->views
[resource_index
];
1981 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
1982 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
1983 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
1985 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rview
->tex_resource
,
1987 rview
->tex_resource
->b
.b
.nr_samples
> 1 ?
1988 RADEON_PRIO_SHADER_TEXTURE_MSAA
:
1989 RADEON_PRIO_SHADER_TEXTURE_RO
);
1990 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1991 radeon_emit(cs
, reloc
);
1993 if (!rview
->skip_mip_address_reloc
) {
1994 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1995 radeon_emit(cs
, reloc
);
1998 state
->dirty_mask
= 0;
2001 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2003 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 176 + R600_MAX_CONST_BUFFERS
);
2006 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2008 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2011 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2013 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2016 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2017 struct r600_textures_info
*texinfo
,
2018 unsigned resource_id_base
,
2019 unsigned border_index_reg
)
2021 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2022 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2024 while (dirty_mask
) {
2025 struct r600_pipe_sampler_state
*rstate
;
2026 unsigned i
= u_bit_scan(&dirty_mask
);
2028 rstate
= texinfo
->states
.states
[i
];
2031 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2032 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2033 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2035 if (rstate
->border_color_use
) {
2036 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2038 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2041 texinfo
->states
.dirty_mask
= 0;
2044 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2046 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
);
2049 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2051 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
);
2054 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2056 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
);
2059 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2061 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2062 uint8_t mask
= s
->sample_mask
;
2064 r600_write_context_reg(rctx
->b
.rings
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2065 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2068 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2070 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2071 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2072 uint16_t mask
= s
->sample_mask
;
2074 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2075 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2076 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2079 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2081 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2082 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2083 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2085 r600_write_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2086 (r600_resource_va(rctx
->b
.b
.screen
, &shader
->buffer
->b
.b
) + shader
->offset
) >> 8);
2087 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2088 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->buffer
,
2089 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
2092 static void evergreen_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
2094 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2095 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
2097 uint32_t v
= 0, v2
= 0, primid
= 0;
2099 if (state
->geom_enable
) {
2102 if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 128)
2103 cut_val
= V_028A40_GS_CUT_128
;
2104 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 256)
2105 cut_val
= V_028A40_GS_CUT_256
;
2106 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 512)
2107 cut_val
= V_028A40_GS_CUT_512
;
2109 cut_val
= V_028A40_GS_CUT_1024
;
2110 v
= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2112 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2114 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
2115 S_028A40_CUT_MODE(cut_val
);
2117 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2121 r600_write_context_reg(cs
, R_028B54_VGT_SHADER_STAGES_EN
, v
);
2122 r600_write_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2123 r600_write_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2126 static void evergreen_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2128 struct pipe_screen
*screen
= rctx
->b
.b
.screen
;
2129 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2130 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2131 struct r600_resource
*rbuffer
;
2133 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2134 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2135 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2137 if (state
->enable
) {
2138 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2139 r600_write_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
2140 (r600_resource_va(screen
, &rbuffer
->b
.b
)) >> 8);
2141 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2142 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
2143 RADEON_USAGE_READWRITE
,
2144 RADEON_PRIO_SHADER_RESOURCE_RW
));
2145 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2146 state
->esgs_ring
.buffer_size
>> 8);
2148 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2149 r600_write_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
2150 (r600_resource_va(screen
, &rbuffer
->b
.b
)) >> 8);
2151 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2152 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
2153 RADEON_USAGE_READWRITE
,
2154 RADEON_PRIO_SHADER_RESOURCE_RW
));
2155 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2156 state
->gsvs_ring
.buffer_size
>> 8);
2158 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2159 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2162 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2163 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2164 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2167 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2168 enum chip_class ctx_chip_class
,
2169 enum radeon_family ctx_family
,
2172 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2173 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2174 /* always set the temp clauses */
2175 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2177 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2178 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2179 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2181 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2183 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2185 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2186 r600_store_value(cb
, 0);
2187 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2189 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2192 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2194 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2197 r600_init_command_buffer(cb
, 256);
2199 /* This must be first. */
2200 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2201 r600_store_value(cb
, 0x80000000);
2202 r600_store_value(cb
, 0x80000000);
2204 /* We're setting config registers here. */
2205 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2206 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2208 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2209 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2211 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2212 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2214 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2215 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2216 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2217 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2218 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2219 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2220 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2222 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2223 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2224 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2225 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2226 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2228 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2229 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2230 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2231 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2232 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2233 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2234 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2235 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2236 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2237 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2238 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2239 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2240 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2241 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2243 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2245 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2246 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2247 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2249 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2251 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2253 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2254 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2255 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2257 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2258 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2259 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2261 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2263 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2264 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2265 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2267 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2269 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2271 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2273 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2274 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2275 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2276 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2278 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2279 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2281 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * 16);
2282 for (tmp
= 0; tmp
< 16; tmp
++) {
2283 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2284 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2287 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2288 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2289 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2291 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2292 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2293 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2294 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2295 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2297 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2298 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2299 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2301 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2302 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2303 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2305 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2306 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2307 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2309 /* to avoid GPU doing any preloading of constant from random address */
2310 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2311 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2312 r600_store_value(cb
, 0);
2313 r600_store_value(cb
, 0);
2314 r600_store_value(cb
, 0);
2315 r600_store_value(cb
, 0);
2316 r600_store_value(cb
, 0);
2317 r600_store_value(cb
, 0);
2318 r600_store_value(cb
, 0);
2319 r600_store_value(cb
, 0);
2320 r600_store_value(cb
, 0);
2321 r600_store_value(cb
, 0);
2322 r600_store_value(cb
, 0);
2323 r600_store_value(cb
, 0);
2324 r600_store_value(cb
, 0);
2325 r600_store_value(cb
, 0);
2326 r600_store_value(cb
, 0);
2328 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2329 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2330 r600_store_value(cb
, 0);
2331 r600_store_value(cb
, 0);
2332 r600_store_value(cb
, 0);
2333 r600_store_value(cb
, 0);
2334 r600_store_value(cb
, 0);
2335 r600_store_value(cb
, 0);
2336 r600_store_value(cb
, 0);
2337 r600_store_value(cb
, 0);
2338 r600_store_value(cb
, 0);
2339 r600_store_value(cb
, 0);
2340 r600_store_value(cb
, 0);
2341 r600_store_value(cb
, 0);
2342 r600_store_value(cb
, 0);
2343 r600_store_value(cb
, 0);
2344 r600_store_value(cb
, 0);
2346 if (rctx
->screen
->b
.has_streamout
) {
2347 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2350 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2351 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2352 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2353 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2354 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2355 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2356 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2358 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2359 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2360 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2363 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
2364 enum chip_class ctx_chip_class
,
2365 enum radeon_family ctx_family
,
2404 switch (ctx_family
) {
2412 tmp
|= S_008C00_VC_ENABLE(1);
2415 tmp
|= S_008C00_EXPORT_SRC_C(1);
2416 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2417 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2418 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2419 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2420 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2421 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2422 tmp
|= S_008C00_ES_PRIO(es_prio
);
2424 /* enable dynamic GPR resource management */
2425 if (ctx_drm_minor
>= 7) {
2426 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2427 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2428 /* always set temp clauses */
2429 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2430 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2431 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2432 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2433 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2434 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2435 S_028838_PS_GPRS(0x1e) |
2436 S_028838_VS_GPRS(0x1e) |
2437 S_028838_GS_GPRS(0x1e) |
2438 S_028838_ES_GPRS(0x1e) |
2439 S_028838_HS_GPRS(0x1e) |
2440 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2442 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2443 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2445 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2446 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2447 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2448 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2450 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2451 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2452 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2454 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2455 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2456 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2459 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2461 /* The cs checker requires this register to be set. */
2462 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2464 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2465 r600_store_value(cb
, 0);
2466 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2471 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2473 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2481 int num_ps_stack_entries
;
2482 int num_vs_stack_entries
;
2483 int num_gs_stack_entries
;
2484 int num_es_stack_entries
;
2485 int num_hs_stack_entries
;
2486 int num_ls_stack_entries
;
2487 enum radeon_family family
;
2490 if (rctx
->b
.chip_class
== CAYMAN
) {
2491 cayman_init_atom_start_cs(rctx
);
2495 r600_init_command_buffer(cb
, 256);
2497 /* This must be first. */
2498 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2499 r600_store_value(cb
, 0x80000000);
2500 r600_store_value(cb
, 0x80000000);
2502 /* We're setting config registers here. */
2503 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2504 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2506 evergreen_init_common_regs(cb
, rctx
->b
.chip_class
,
2507 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2509 family
= rctx
->b
.family
;
2513 num_ps_threads
= 96;
2514 num_vs_threads
= 16;
2515 num_gs_threads
= 16;
2516 num_es_threads
= 16;
2517 num_hs_threads
= 16;
2518 num_ls_threads
= 16;
2519 num_ps_stack_entries
= 42;
2520 num_vs_stack_entries
= 42;
2521 num_gs_stack_entries
= 42;
2522 num_es_stack_entries
= 42;
2523 num_hs_stack_entries
= 42;
2524 num_ls_stack_entries
= 42;
2527 num_ps_threads
= 128;
2528 num_vs_threads
= 20;
2529 num_gs_threads
= 20;
2530 num_es_threads
= 20;
2531 num_hs_threads
= 20;
2532 num_ls_threads
= 20;
2533 num_ps_stack_entries
= 42;
2534 num_vs_stack_entries
= 42;
2535 num_gs_stack_entries
= 42;
2536 num_es_stack_entries
= 42;
2537 num_hs_stack_entries
= 42;
2538 num_ls_stack_entries
= 42;
2541 num_ps_threads
= 128;
2542 num_vs_threads
= 20;
2543 num_gs_threads
= 20;
2544 num_es_threads
= 20;
2545 num_hs_threads
= 20;
2546 num_ls_threads
= 20;
2547 num_ps_stack_entries
= 85;
2548 num_vs_stack_entries
= 85;
2549 num_gs_stack_entries
= 85;
2550 num_es_stack_entries
= 85;
2551 num_hs_stack_entries
= 85;
2552 num_ls_stack_entries
= 85;
2556 num_ps_threads
= 128;
2557 num_vs_threads
= 20;
2558 num_gs_threads
= 20;
2559 num_es_threads
= 20;
2560 num_hs_threads
= 20;
2561 num_ls_threads
= 20;
2562 num_ps_stack_entries
= 85;
2563 num_vs_stack_entries
= 85;
2564 num_gs_stack_entries
= 85;
2565 num_es_stack_entries
= 85;
2566 num_hs_stack_entries
= 85;
2567 num_ls_stack_entries
= 85;
2570 num_ps_threads
= 96;
2571 num_vs_threads
= 16;
2572 num_gs_threads
= 16;
2573 num_es_threads
= 16;
2574 num_hs_threads
= 16;
2575 num_ls_threads
= 16;
2576 num_ps_stack_entries
= 42;
2577 num_vs_stack_entries
= 42;
2578 num_gs_stack_entries
= 42;
2579 num_es_stack_entries
= 42;
2580 num_hs_stack_entries
= 42;
2581 num_ls_stack_entries
= 42;
2584 num_ps_threads
= 96;
2585 num_vs_threads
= 25;
2586 num_gs_threads
= 25;
2587 num_es_threads
= 25;
2588 num_hs_threads
= 25;
2589 num_ls_threads
= 25;
2590 num_ps_stack_entries
= 42;
2591 num_vs_stack_entries
= 42;
2592 num_gs_stack_entries
= 42;
2593 num_es_stack_entries
= 42;
2594 num_hs_stack_entries
= 42;
2595 num_ls_stack_entries
= 42;
2598 num_ps_threads
= 96;
2599 num_vs_threads
= 25;
2600 num_gs_threads
= 25;
2601 num_es_threads
= 25;
2602 num_hs_threads
= 25;
2603 num_ls_threads
= 25;
2604 num_ps_stack_entries
= 85;
2605 num_vs_stack_entries
= 85;
2606 num_gs_stack_entries
= 85;
2607 num_es_stack_entries
= 85;
2608 num_hs_stack_entries
= 85;
2609 num_ls_stack_entries
= 85;
2612 num_ps_threads
= 128;
2613 num_vs_threads
= 20;
2614 num_gs_threads
= 20;
2615 num_es_threads
= 20;
2616 num_hs_threads
= 20;
2617 num_ls_threads
= 20;
2618 num_ps_stack_entries
= 85;
2619 num_vs_stack_entries
= 85;
2620 num_gs_stack_entries
= 85;
2621 num_es_stack_entries
= 85;
2622 num_hs_stack_entries
= 85;
2623 num_ls_stack_entries
= 85;
2626 num_ps_threads
= 128;
2627 num_vs_threads
= 20;
2628 num_gs_threads
= 20;
2629 num_es_threads
= 20;
2630 num_hs_threads
= 20;
2631 num_ls_threads
= 20;
2632 num_ps_stack_entries
= 42;
2633 num_vs_stack_entries
= 42;
2634 num_gs_stack_entries
= 42;
2635 num_es_stack_entries
= 42;
2636 num_hs_stack_entries
= 42;
2637 num_ls_stack_entries
= 42;
2640 num_ps_threads
= 128;
2641 num_vs_threads
= 10;
2642 num_gs_threads
= 10;
2643 num_es_threads
= 10;
2644 num_hs_threads
= 10;
2645 num_ls_threads
= 10;
2646 num_ps_stack_entries
= 42;
2647 num_vs_stack_entries
= 42;
2648 num_gs_stack_entries
= 42;
2649 num_es_stack_entries
= 42;
2650 num_hs_stack_entries
= 42;
2651 num_ls_stack_entries
= 42;
2655 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2656 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2657 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2658 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2660 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2661 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2663 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2664 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2665 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2667 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2668 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2669 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2671 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2672 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2673 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2675 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2676 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2677 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2679 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2680 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2682 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2683 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2685 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2686 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2687 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2688 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2689 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2690 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2691 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2693 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2694 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2695 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2696 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2697 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2699 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2700 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2701 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2702 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2703 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2704 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2705 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2706 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2707 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2708 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2709 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2710 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2711 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2712 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2714 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2715 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2716 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2718 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2720 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2722 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2723 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2724 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2726 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2728 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2730 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2731 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2732 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2734 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * 16);
2735 for (tmp
= 0; tmp
< 16; tmp
++) {
2736 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2737 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2740 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2741 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2742 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2744 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2745 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2746 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2747 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2749 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2750 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2751 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2752 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2753 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2755 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2756 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2757 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2759 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2760 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2761 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2763 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2764 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2765 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2767 /* to avoid GPU doing any preloading of constant from random address */
2768 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2769 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2770 r600_store_value(cb
, 0);
2771 r600_store_value(cb
, 0);
2772 r600_store_value(cb
, 0);
2773 r600_store_value(cb
, 0);
2774 r600_store_value(cb
, 0);
2775 r600_store_value(cb
, 0);
2776 r600_store_value(cb
, 0);
2777 r600_store_value(cb
, 0);
2778 r600_store_value(cb
, 0);
2779 r600_store_value(cb
, 0);
2780 r600_store_value(cb
, 0);
2781 r600_store_value(cb
, 0);
2782 r600_store_value(cb
, 0);
2783 r600_store_value(cb
, 0);
2784 r600_store_value(cb
, 0);
2786 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2787 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2788 r600_store_value(cb
, 0);
2789 r600_store_value(cb
, 0);
2790 r600_store_value(cb
, 0);
2791 r600_store_value(cb
, 0);
2792 r600_store_value(cb
, 0);
2793 r600_store_value(cb
, 0);
2794 r600_store_value(cb
, 0);
2795 r600_store_value(cb
, 0);
2796 r600_store_value(cb
, 0);
2797 r600_store_value(cb
, 0);
2798 r600_store_value(cb
, 0);
2799 r600_store_value(cb
, 0);
2800 r600_store_value(cb
, 0);
2801 r600_store_value(cb
, 0);
2802 r600_store_value(cb
, 0);
2804 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2806 if (rctx
->screen
->b
.has_streamout
) {
2807 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2810 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2811 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2812 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2813 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2814 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2815 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2816 r600_store_context_reg(cb
, R_0288EC_SQ_LDS_ALLOC_PS
, 0);
2817 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2819 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2820 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2821 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2824 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2826 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2827 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2828 struct r600_shader
*rshader
= &shader
->shader
;
2829 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
2830 int pos_index
= -1, face_index
= -1;
2832 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2833 unsigned spi_baryc_cntl
, sid
, tmp
, num
= 0;
2834 unsigned z_export
= 0, stencil_export
= 0;
2835 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2836 uint32_t spi_ps_input_cntl
[32];
2839 r600_init_command_buffer(cb
, 64);
2844 for (i
= 0; i
< rshader
->ninput
; i
++) {
2845 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2846 POSITION goes via GPRs from the SC so isn't counted */
2847 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2849 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2853 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2855 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2856 have_perspective
= TRUE
;
2857 if (rshader
->input
[i
].centroid
)
2858 have_centroid
= TRUE
;
2861 sid
= rshader
->input
[i
].spi_sid
;
2864 tmp
= S_028644_SEMANTIC(sid
);
2866 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2867 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2868 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2869 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
2870 tmp
|= S_028644_FLAT_SHADE(1);
2873 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2874 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
2875 tmp
|= S_028644_PT_SPRITE_TEX(1);
2878 spi_ps_input_cntl
[num
++] = tmp
;
2882 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
2883 r600_store_array(cb
, num
, spi_ps_input_cntl
);
2885 for (i
= 0; i
< rshader
->noutput
; i
++) {
2886 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2888 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2891 if (rshader
->uses_kill
)
2892 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2894 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2895 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
2898 for (i
= 0; i
< rshader
->noutput
; i
++) {
2899 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2900 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2904 num_cout
= rshader
->nr_ps_color_exports
;
2906 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2908 /* always at least export 1 component per pixel */
2911 shader
->nr_ps_color_outputs
= num_cout
;
2914 have_perspective
= TRUE
;
2917 if (!have_perspective
&& !have_linear
)
2918 have_perspective
= TRUE
;
2920 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2921 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2922 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2924 if (pos_index
!= -1) {
2925 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2926 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2927 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2928 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
2931 spi_ps_in_control_1
= 0;
2932 if (face_index
!= -1) {
2933 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2934 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2938 if (have_perspective
)
2939 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
2940 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
2942 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
2943 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
2945 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
2946 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2947 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2949 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
2950 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2951 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
2953 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
2954 r600_store_value(cb
, r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
2955 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
2956 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2957 S_028844_PRIME_CACHE_ON_DRAW(1) |
2958 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
2959 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2961 shader
->db_shader_control
= db_shader_control
;
2962 shader
->ps_depth_export
= z_export
| stencil_export
;
2964 shader
->sprite_coord_enable
= sprite_coord_enable
;
2965 if (rctx
->rasterizer
)
2966 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2969 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2971 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2972 struct r600_shader
*rshader
= &shader
->shader
;
2974 r600_init_command_buffer(cb
, 32);
2976 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
2977 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
2978 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
2979 r600_store_context_reg(cb
, R_02888C_SQ_PGM_START_ES
,
2980 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
2981 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2984 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2986 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2987 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2988 struct r600_shader
*rshader
= &shader
->shader
;
2989 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
2990 unsigned gsvs_itemsize
=
2991 (cp_shader
->ring_item_size
* rshader
->gs_max_out_vertices
) >> 2;
2993 r600_init_command_buffer(cb
, 64);
2995 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
2997 r600_store_context_reg(cb
, R_028AB8_VGT_VTX_CNT_EN
, 1);
2999 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
3000 S_028B38_MAX_VERT_OUT(rshader
->gs_max_out_vertices
));
3001 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
3002 r600_conv_prim_to_gs_out(rshader
->gs_output_prim
));
3004 if (rctx
->screen
->b
.info
.drm_minor
>= 35) {
3005 r600_store_context_reg(cb
, R_028B90_VGT_GS_INSTANCE_CNT
,
3007 S_028B90_ENABLE(0));
3009 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3010 r600_store_value(cb
, cp_shader
->ring_item_size
>> 2);
3011 r600_store_value(cb
, 0);
3012 r600_store_value(cb
, 0);
3013 r600_store_value(cb
, 0);
3015 r600_store_context_reg(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
,
3016 (rshader
->ring_item_size
) >> 2);
3018 r600_store_context_reg(cb
, R_028904_SQ_GSVS_RING_ITEMSIZE
,
3021 r600_store_context_reg_seq(cb
, R_02892C_SQ_GSVS_RING_OFFSET_1
, 3);
3022 r600_store_value(cb
, gsvs_itemsize
);
3023 r600_store_value(cb
, gsvs_itemsize
);
3024 r600_store_value(cb
, gsvs_itemsize
);
3026 /* FIXME calculate these values somehow ??? */
3027 r600_store_context_reg_seq(cb
, R_028A54_GS_PER_ES
, 3);
3028 r600_store_value(cb
, 0x80); /* GS_PER_ES */
3029 r600_store_value(cb
, 0x100); /* ES_PER_GS */
3030 r600_store_value(cb
, 0x2); /* GS_PER_VS */
3032 r600_store_context_reg(cb
, R_028878_SQ_PGM_RESOURCES_GS
,
3033 S_028878_NUM_GPRS(rshader
->bc
.ngpr
) |
3034 S_028878_STACK_SIZE(rshader
->bc
.nstack
));
3035 r600_store_context_reg(cb
, R_028874_SQ_PGM_START_GS
,
3036 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3037 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3041 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3043 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3044 struct r600_shader
*rshader
= &shader
->shader
;
3045 unsigned spi_vs_out_id
[10] = {};
3046 unsigned i
, tmp
, nparams
= 0;
3048 for (i
= 0; i
< rshader
->noutput
; i
++) {
3049 if (rshader
->output
[i
].spi_sid
) {
3050 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3051 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3056 r600_init_command_buffer(cb
, 32);
3058 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3059 for (i
= 0; i
< 10; i
++) {
3060 r600_store_value(cb
, spi_vs_out_id
[i
]);
3063 /* Certain attributes (position, psize, etc.) don't count as params.
3064 * VS is required to export at least one param and r600_shader_from_tgsi()
3065 * takes care of adding a dummy export.
3070 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3071 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3072 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3073 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3074 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3075 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3076 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3077 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3079 shader
->pa_cl_vs_out_cntl
=
3080 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3081 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3082 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3083 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
3084 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
3085 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
) |
3086 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
);
3089 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3091 struct pipe_blend_state blend
;
3093 memset(&blend
, 0, sizeof(blend
));
3094 blend
.independent_blend_enable
= true;
3095 blend
.rt
[0].colormask
= 0xf;
3096 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3099 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3101 struct pipe_blend_state blend
;
3102 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3103 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3105 memset(&blend
, 0, sizeof(blend
));
3106 blend
.independent_blend_enable
= true;
3107 blend
.rt
[0].colormask
= 0xf;
3108 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3111 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3113 struct pipe_blend_state blend
;
3114 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3116 memset(&blend
, 0, sizeof(blend
));
3117 blend
.independent_blend_enable
= true;
3118 blend
.rt
[0].colormask
= 0xf;
3119 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3122 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3124 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3126 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3129 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3132 unsigned db_shader_control
;
3134 if (!rctx
->ps_shader
) {
3138 dual_export
= rctx
->framebuffer
.export_16bpc
&&
3139 !rctx
->ps_shader
->current
->ps_depth_export
;
3141 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3142 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3143 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3144 V_02880C_EXPORT_DB_FULL
) |
3145 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3147 /* When alpha test is enabled we can't trust the hw to make the proper
3148 * decision on the order in which ztest should be run related to fragment
3151 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3152 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3153 * execution and thus after alpha test so if discarded by the alpha test
3154 * the z value is not written.
3155 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3156 * get a hang unless you flush the DB in between. For now just use
3159 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3160 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3162 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3165 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3166 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3167 rctx
->db_misc_state
.atom
.dirty
= true;
3171 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3172 struct pipe_resource
*dst
,
3177 struct pipe_resource
*src
,
3182 unsigned copy_height
,
3186 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
3187 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3188 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3189 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3190 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3191 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3192 uint64_t base
, addr
;
3194 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3195 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3196 /* downcast linear aligned to linear to simplify test */
3197 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3198 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3199 assert(dst_mode
!= src_mode
);
3201 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3202 if (util_format_has_depth(util_format_description(src
->format
)))
3203 non_disp_tiling
= 1;
3206 sub_cmd
= EG_DMA_COPY_TILED
;
3207 lbpp
= util_logbase2(bpp
);
3208 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
3209 nbanks
= eg_num_banks(rctx
->screen
->b
.tiling_info
.num_banks
);
3211 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
3213 array_mode
= evergreen_array_mode(src_mode
);
3214 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
3215 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3216 /* linear height must be the same as the slice tile max height, it's ok even
3217 * if the linear destination/source have smaller heigh as the size of the
3218 * dma packet will be using the copy_height which is always smaller or equal
3219 * to the linear height
3221 height
= rsrc
->surface
.level
[src_level
].npix_y
;
3226 base
= rsrc
->surface
.level
[src_level
].offset
;
3227 addr
= rdst
->surface
.level
[dst_level
].offset
;
3228 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3229 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3230 bank_h
= eg_bank_wh(rsrc
->surface
.bankh
);
3231 bank_w
= eg_bank_wh(rsrc
->surface
.bankw
);
3232 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.mtilea
);
3233 tile_split
= eg_tile_split(rsrc
->surface
.tile_split
);
3234 base
+= r600_resource_va(&rctx
->screen
->b
.b
, src
);
3235 addr
+= r600_resource_va(&rctx
->screen
->b
.b
, dst
);
3238 array_mode
= evergreen_array_mode(dst_mode
);
3239 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
3240 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3241 /* linear height must be the same as the slice tile max height, it's ok even
3242 * if the linear destination/source have smaller heigh as the size of the
3243 * dma packet will be using the copy_height which is always smaller or equal
3244 * to the linear height
3246 height
= rdst
->surface
.level
[dst_level
].npix_y
;
3251 base
= rdst
->surface
.level
[dst_level
].offset
;
3252 addr
= rsrc
->surface
.level
[src_level
].offset
;
3253 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
3254 addr
+= src_y
* pitch
+ src_x
* bpp
;
3255 bank_h
= eg_bank_wh(rdst
->surface
.bankh
);
3256 bank_w
= eg_bank_wh(rdst
->surface
.bankw
);
3257 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.mtilea
);
3258 tile_split
= eg_tile_split(rdst
->surface
.tile_split
);
3259 base
+= r600_resource_va(&rctx
->screen
->b
.b
, dst
);
3260 addr
+= r600_resource_va(&rctx
->screen
->b
.b
, src
);
3263 size
= (copy_height
* pitch
) / 4;
3264 ncopy
= (size
/ EG_DMA_COPY_MAX_SIZE
) + !!(size
% EG_DMA_COPY_MAX_SIZE
);
3265 r600_need_dma_space(&rctx
->b
, ncopy
* 9);
3267 for (i
= 0; i
< ncopy
; i
++) {
3268 cheight
= copy_height
;
3269 if (((cheight
* pitch
) / 4) > EG_DMA_COPY_MAX_SIZE
) {
3270 cheight
= (EG_DMA_COPY_MAX_SIZE
* 4) / pitch
;
3272 size
= (cheight
* pitch
) / 4;
3273 /* emit reloc before writting cs so that cs is always in consistent state */
3274 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rsrc
->resource
,
3275 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
3276 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rdst
->resource
,
3277 RADEON_USAGE_WRITE
, RADEON_PRIO_MIN
);
3278 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
);
3279 cs
->buf
[cs
->cdw
++] = base
>> 8;
3280 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
3281 (lbpp
<< 24) | (bank_h
<< 21) |
3282 (bank_w
<< 18) | (mt_aspect
<< 16);
3283 cs
->buf
[cs
->cdw
++] = (pitch_tile_max
<< 0) | ((height
- 1) << 16);
3284 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 0);
3285 cs
->buf
[cs
->cdw
++] = (x
<< 0) | (z
<< 18);
3286 cs
->buf
[cs
->cdw
++] = (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28);
3287 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
3288 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
3289 copy_height
-= cheight
;
3290 addr
+= cheight
* pitch
;
3295 static void evergreen_dma_copy(struct pipe_context
*ctx
,
3296 struct pipe_resource
*dst
,
3298 unsigned dstx
, unsigned dsty
, unsigned dstz
,
3299 struct pipe_resource
*src
,
3301 const struct pipe_box
*src_box
)
3303 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3304 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3305 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3306 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3307 unsigned src_w
, dst_w
;
3308 unsigned src_x
, src_y
;
3309 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3311 if (rctx
->b
.rings
.dma
.cs
== NULL
) {
3315 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3316 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3320 if (src
->format
!= dst
->format
|| src_box
->depth
> 1 ||
3321 rdst
->dirty_level_mask
!= 0) {
3325 if (rsrc
->dirty_level_mask
) {
3326 ctx
->flush_resource(ctx
, src
);
3329 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3330 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3331 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3332 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3334 bpp
= rdst
->surface
.bpe
;
3335 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3336 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3337 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3338 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3339 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3341 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3342 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3343 /* downcast linear aligned to linear to simplify test */
3344 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3345 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3347 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3348 /* FIXME evergreen can do partial blit */
3351 /* the x test here are currently useless (because we don't support partial blit)
3352 * but keep them around so we don't forget about those
3354 if (src_pitch
% 8 || src_box
->x
% 8 || dst_x
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3358 /* 128 bpp surfaces require non_disp_tiling for both
3359 * tiled and linear buffers on cayman. However, async
3360 * DMA only supports it on the tiled side. As such
3361 * the tile order is backwards after a L2T/T2L packet.
3363 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3364 (src_mode
!= dst_mode
) &&
3365 (util_format_get_blocksize(src
->format
) >= 16)) {
3369 if (src_mode
== dst_mode
) {
3370 uint64_t dst_offset
, src_offset
;
3371 /* simple dma blit would do NOTE code here assume :
3374 * dst_pitch == src_pitch
3376 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3377 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3378 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3379 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3380 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3381 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3382 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
,
3383 src_box
->height
* src_pitch
);
3385 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3386 src
, src_level
, src_x
, src_y
, src_box
->z
,
3387 copy_height
, dst_pitch
, bpp
);
3392 ctx
->resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3393 src
, src_level
, src_box
);
3396 void evergreen_init_state_functions(struct r600_context
*rctx
)
3401 * To avoid GPU lockup registers must be emited in a specific order
3402 * (no kidding ...). The order below is important and have been
3403 * partialy infered from analyzing fglrx command stream.
3405 * Don't reorder atom without carefully checking the effect (GPU lockup
3406 * or piglit regression).
3410 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
3412 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
3413 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
3414 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
3415 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
3416 /* shader program */
3417 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
3419 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
3420 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
3421 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
3423 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
3424 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
3425 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
3426 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
3427 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
3429 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 7);
3431 if (rctx
->b
.chip_class
== EVERGREEN
) {
3432 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
3434 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
3436 rctx
->sample_mask
.sample_mask
= ~0;
3438 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3439 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3440 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3441 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
3442 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3443 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
3444 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
3445 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
3446 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3447 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 6);
3448 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3449 for (i
= 0; i
< 16; i
++) {
3450 r600_init_atom(rctx
, &rctx
->viewport
[i
].atom
, id
++, r600_emit_viewport_state
, 8);
3451 r600_init_atom(rctx
, &rctx
->scissor
[i
].atom
, id
++, evergreen_emit_scissor_state
, 4);
3452 rctx
->viewport
[i
].idx
= i
;
3453 rctx
->scissor
[i
].idx
= i
;
3455 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3456 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
3457 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.begin_atom
;
3458 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.enable_atom
;
3459 r600_init_atom(rctx
, &rctx
->vertex_shader
.atom
, id
++, r600_emit_shader
, 23);
3460 r600_init_atom(rctx
, &rctx
->pixel_shader
.atom
, id
++, r600_emit_shader
, 0);
3461 r600_init_atom(rctx
, &rctx
->geometry_shader
.atom
, id
++, r600_emit_shader
, 0);
3462 r600_init_atom(rctx
, &rctx
->export_shader
.atom
, id
++, r600_emit_shader
, 0);
3463 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, evergreen_emit_shader_stages
, 6);
3464 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, evergreen_emit_gs_rings
, 26);
3466 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
3467 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
3468 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
3469 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
3470 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
3471 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
3472 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
3473 rctx
->b
.b
.set_scissor_states
= evergreen_set_scissor_states
;
3475 if (rctx
->b
.chip_class
== EVERGREEN
)
3476 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
3478 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3479 rctx
->b
.dma_copy
= evergreen_dma_copy
;
3481 evergreen_init_compute_state_functions(rctx
);