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r600g: initial evergreen support in new path
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "evergreend.h"
45 struct radeon_state {
46 unsigned dummy;
47 };
48 #include "r600_resource.h"
49 #include "r600_shader.h"
50 #include "r600_pipe.h"
51 #include "eg_state_inlines.h"
52
53 static void evergreen_set_blend_color(struct pipe_context *ctx,
54 const struct pipe_blend_color *state)
55 {
56 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
57 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
58
59 if (rstate == NULL)
60 return;
61
62 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
63 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
65 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
66 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
67 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
68 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
69 r600_context_pipe_state_set(&rctx->ctx, rstate);
70 }
71
72 static void *evergreen_create_blend_state(struct pipe_context *ctx,
73 const struct pipe_blend_state *state)
74 {
75 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
76 struct r600_pipe_state *rstate;
77 u32 color_control, target_mask;
78
79 if (blend == NULL) {
80 return NULL;
81 }
82 rstate = &blend->rstate;
83
84 rstate->id = R600_PIPE_STATE_BLEND;
85
86 target_mask = 0;
87 color_control = S_028808_MODE(1);
88 if (state->logicop_enable) {
89 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
90 } else {
91 color_control |= (0xcc << 16);
92 }
93 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
94 if (state->independent_blend_enable) {
95 for (int i = 0; i < 8; i++) {
96 target_mask |= (state->rt[i].colormask << (4 * i));
97 }
98 } else {
99 for (int i = 0; i < 8; i++) {
100 target_mask |= (state->rt[0].colormask << (4 * i));
101 }
102 }
103 blend->cb_target_mask = target_mask;
104 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
105 color_control, 0xFFFFFFFF, NULL);
106 return rstate;
107 }
108
109 static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
110 {
111 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
112 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
113 struct r600_pipe_state *rstate;
114
115 if (state == NULL)
116 return;
117 rstate = &blend->rstate;
118 rctx->states[rstate->id] = rstate;
119 rctx->cb_target_mask = blend->cb_target_mask;
120 r600_context_pipe_state_set(&rctx->ctx, rstate);
121 }
122
123 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
124 const struct pipe_depth_stencil_alpha_state *state)
125 {
126 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
127 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
128 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
129
130 if (rstate == NULL) {
131 return NULL;
132 }
133
134 rstate->id = R600_PIPE_STATE_DSA;
135 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
136 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
137 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
138 * be set if shader use texkill instruction
139 */
140 db_shader_control = 0x210;
141 stencil_ref_mask = 0;
142 stencil_ref_mask_bf = 0;
143 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
144 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
145 S_028800_ZFUNC(state->depth.func);
146
147 /* stencil */
148 if (state->stencil[0].enabled) {
149 db_depth_control |= S_028800_STENCIL_ENABLE(1);
150 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
151 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
152 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
153 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
154
155
156 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
157 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
158 if (state->stencil[1].enabled) {
159 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
160 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
161 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
162 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
163 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
164 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
165 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
166 }
167 }
168
169 /* alpha */
170 alpha_test_control = 0;
171 alpha_ref = 0;
172 if (state->alpha.enabled) {
173 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
174 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
175 alpha_ref = fui(state->alpha.ref_value);
176 }
177
178 /* misc */
179 db_render_control = 0;
180 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
181 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
182 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
183 /* TODO db_render_override depends on query */
184 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
185 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
186 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
187 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
188 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
189 0xFFFFFFFF & C_028430_STENCILREF, NULL);
190 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
191 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
192 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
193 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
194 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
195 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
196 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
197 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
198 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
199
200 return rstate;
201 }
202
203 static void *evergreen_create_rs_state(struct pipe_context *ctx,
204 const struct pipe_rasterizer_state *state)
205 {
206 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
207 struct r600_pipe_state *rstate;
208 float offset_units = 0, offset_scale = 0;
209 unsigned offset_db_fmt_cntl = 0;
210 unsigned tmp;
211 unsigned prov_vtx = 1;
212
213 if (rs == NULL) {
214 return NULL;
215 }
216
217 rstate = &rs->rstate;
218 rs->flatshade = state->flatshade;
219 rs->sprite_coord_enable = state->sprite_coord_enable;
220
221 rstate->id = R600_PIPE_STATE_RASTERIZER;
222 if (state->flatshade_first)
223 prov_vtx = 0;
224 tmp = 0x00000001;
225 if (state->sprite_coord_enable) {
226 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
227 S_0286D4_PNT_SPRITE_OVRD_X(2) |
228 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
229 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
230 S_0286D4_PNT_SPRITE_OVRD_W(1);
231 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
232 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
233 }
234 }
235 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
236
237 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
238 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
239 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
240 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
241 S_028814_FACE(!state->front_ccw) |
242 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
243 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
244 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
245 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
246 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
247 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
248 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
249 /* point size 12.4 fixed point */
250 tmp = (unsigned)(state->point_size * 8.0);
251 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
252 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
253 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
254 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
255 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
256 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
257 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
258 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
259 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
260 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
261 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
262 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
264 return rstate;
265 }
266
267 static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
268 {
269 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
270 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
271
272 if (state == NULL)
273 return;
274
275 if (rctx->flatshade != rs->flatshade) {
276 // rctx->ps_rebuild = TRUE;
277 }
278 if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
279 // rctx->ps_rebuild = TRUE;
280 }
281 rctx->flatshade = rs->flatshade;
282 rctx->sprite_coord_enable = rs->sprite_coord_enable;
283
284 rctx->states[rs->rstate.id] = &rs->rstate;
285 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
286 }
287
288 static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
289 {
290 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
291 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
292
293 if (rctx->states[rs->rstate.id] == &rs->rstate) {
294 rctx->states[rs->rstate.id] = NULL;
295 }
296 free(rs);
297 }
298
299 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
300 const struct pipe_sampler_state *state)
301 {
302 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
303 union util_color uc;
304
305 if (rstate == NULL) {
306 return NULL;
307 }
308
309 rstate->id = R600_PIPE_STATE_SAMPLER;
310 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
311 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
312 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
313 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
314 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
315 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
316 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
317 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
318 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
319 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
320 /* FIXME LOD it depends on texture base level ... */
321 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
322 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
323 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
324 0xFFFFFFFF, NULL);
325 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
326 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
327 S_03C008_TYPE(1),
328 0xFFFFFFFF, NULL);
329
330 if (uc.ui) {
331 /* TODO border color */
332 }
333 return rstate;
334 }
335
336 static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
337 unsigned count,
338 const struct pipe_vertex_element *elements)
339 {
340 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
341
342 assert(count < 32);
343 v->count = count;
344 v->refcount = 1;
345 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
346 return v;
347 }
348
349 static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
350 struct pipe_sampler_view *state)
351 {
352 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
353
354 pipe_resource_reference(&state->texture, NULL);
355 FREE(resource);
356 }
357
358 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
359 struct pipe_resource *texture,
360 const struct pipe_sampler_view *state)
361 {
362 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
363 struct r600_pipe_state *rstate;
364 const struct util_format_description *desc;
365 struct r600_resource_texture *tmp;
366 struct r600_resource *rbuffer;
367 unsigned format;
368 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
369 unsigned char swizzle[4];
370 struct radeon_ws_bo *bo[2];
371
372 if (resource == NULL)
373 return NULL;
374 rstate = &resource->state;
375
376 /* initialize base object */
377 resource->base = *state;
378 resource->base.texture = NULL;
379 pipe_reference(NULL, &texture->reference);
380 resource->base.texture = texture;
381 resource->base.reference.count = 1;
382 resource->base.context = ctx;
383
384 swizzle[0] = state->swizzle_r;
385 swizzle[1] = state->swizzle_g;
386 swizzle[2] = state->swizzle_b;
387 swizzle[3] = state->swizzle_a;
388 format = r600_translate_texformat(texture->format,
389 swizzle,
390 &word4, &yuv_format);
391 if (format == ~0) {
392 format = 0;
393 }
394 desc = util_format_description(texture->format);
395 if (desc == NULL) {
396 R600_ERR("unknow format %d\n", texture->format);
397 }
398 tmp = (struct r600_resource_texture*)texture;
399 rbuffer = &tmp->resource;
400 bo[0] = rbuffer->bo;
401 bo[1] = rbuffer->bo;
402 /* FIXME depth texture decompression */
403 if (tmp->depth) {
404 #if 0
405 r = evergreen_texture_from_depth(ctx, tmp, view->first_level);
406 if (r) {
407 return;
408 }
409 bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
410 bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
411 #endif
412 }
413 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
414
415 /* FIXME properly handle first level != 0 */
416 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030000_RESOURCE0_WORD0,
417 S_030000_DIM(r600_tex_dim(texture->target)) |
418 S_030000_PITCH((pitch / 8) - 1) |
419 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
420 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030004_RESOURCE0_WORD1,
421 S_030004_TEX_HEIGHT(texture->height0 - 1) |
422 S_030004_TEX_DEPTH(texture->depth0 - 1),
423 0xFFFFFFFF, NULL);
424 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030008_RESOURCE0_WORD2,
425 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
426 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03000C_RESOURCE0_WORD3,
427 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
428 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030010_RESOURCE0_WORD4,
429 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
430 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
431 S_030010_REQUEST_SIZE(1) |
432 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
433 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030014_RESOURCE0_WORD5,
434 S_030014_LAST_LEVEL(state->last_level) |
435 S_030014_BASE_ARRAY(0) |
436 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
437 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
438 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03001C_RESOURCE0_WORD7,
439 S_03001C_DATA_FORMAT(format) |
440 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
441
442 return &resource->base;
443 }
444
445 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
446 struct pipe_sampler_view **views)
447 {
448 /* TODO */
449 assert(1);
450 }
451
452 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
453 struct pipe_sampler_view **views)
454 {
455 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
456 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
457
458 for (int i = 0; i < count; i++) {
459 if (resource[i]) {
460 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
461 }
462 }
463 }
464
465 static void evergreen_bind_state(struct pipe_context *ctx, void *state)
466 {
467 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
468 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
469
470 if (state == NULL)
471 return;
472 rctx->states[rstate->id] = rstate;
473 r600_context_pipe_state_set(&rctx->ctx, rstate);
474 }
475
476 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
477 {
478 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
479 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
480
481 for (int i = 0; i < count; i++) {
482 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
483 }
484 }
485
486 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
487 {
488 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
489 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
490
491 /* TODO implement */
492 for (int i = 0; i < count; i++) {
493 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
494 }
495 }
496
497 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
498 {
499 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
500 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
501
502 if (rctx->states[rstate->id] == rstate) {
503 rctx->states[rstate->id] = NULL;
504 }
505 for (int i = 0; i < rstate->nregs; i++) {
506 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
507 }
508 free(rstate);
509 }
510
511 static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
512 {
513 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
514
515 if (v == NULL)
516 return;
517 if (--v->refcount)
518 return;
519 free(v);
520 }
521
522 static void evergreen_set_clip_state(struct pipe_context *ctx,
523 const struct pipe_clip_state *state)
524 {
525 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
526 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
527
528 if (rstate == NULL)
529 return;
530
531 rctx->clip = *state;
532 rstate->id = R600_PIPE_STATE_CLIP;
533 for (int i = 0; i < state->nr; i++) {
534 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
535 R_0285BC_PA_CL_UCP0_X + i * 4,
536 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
537 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
538 R_0285C0_PA_CL_UCP0_Y + i * 4,
539 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
540 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
541 R_0285C4_PA_CL_UCP0_Z + i * 4,
542 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
543 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
544 R_0285C8_PA_CL_UCP0_W + i * 4,
545 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
546 }
547 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
548 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
549 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
550 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
551
552 free(rctx->states[R600_PIPE_STATE_CLIP]);
553 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
554 r600_context_pipe_state_set(&rctx->ctx, rstate);
555 }
556
557 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
558 {
559 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
560 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
561
562 evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
563 rctx->vertex_elements = v;
564 if (v) {
565 v->refcount++;
566 // rctx->vs_rebuild = TRUE;
567 }
568 }
569
570 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
571 const struct pipe_poly_stipple *state)
572 {
573 }
574
575 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
576 {
577 }
578
579 static void evergreen_set_scissor_state(struct pipe_context *ctx,
580 const struct pipe_scissor_state *state)
581 {
582 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
583 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
584 u32 tl, br;
585
586 if (rstate == NULL)
587 return;
588
589 rstate->id = R600_PIPE_STATE_SCISSOR;
590 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
591 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
592 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
593 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
594 0xFFFFFFFF, NULL);
595 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
596 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
597 0xFFFFFFFF, NULL);
598 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
599 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
600 0xFFFFFFFF, NULL);
601 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
602 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
603 0xFFFFFFFF, NULL);
604 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
605 R_028210_PA_SC_CLIPRECT_0_TL, tl,
606 0xFFFFFFFF, NULL);
607 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
608 R_028214_PA_SC_CLIPRECT_0_BR, br,
609 0xFFFFFFFF, NULL);
610 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
611 R_028218_PA_SC_CLIPRECT_1_TL, tl,
612 0xFFFFFFFF, NULL);
613 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
614 R_02821C_PA_SC_CLIPRECT_1_BR, br,
615 0xFFFFFFFF, NULL);
616 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
617 R_028220_PA_SC_CLIPRECT_2_TL, tl,
618 0xFFFFFFFF, NULL);
619 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
620 R_028224_PA_SC_CLIPRECT_2_BR, br,
621 0xFFFFFFFF, NULL);
622 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
623 R_028228_PA_SC_CLIPRECT_3_TL, tl,
624 0xFFFFFFFF, NULL);
625 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
626 R_02822C_PA_SC_CLIPRECT_3_BR, br,
627 0xFFFFFFFF, NULL);
628 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
629 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
630 0xFFFFFFFF, NULL);
631 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
632 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
633 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
635 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
636 0xFFFFFFFF, NULL);
637
638 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
639 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
640 r600_context_pipe_state_set(&rctx->ctx, rstate);
641 }
642
643 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
644 const struct pipe_stencil_ref *state)
645 {
646 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
647 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
648 u32 tmp;
649
650 if (rstate == NULL)
651 return;
652
653 rctx->stencil_ref = *state;
654 rstate->id = R600_PIPE_STATE_STENCIL_REF;
655 tmp = S_028430_STENCILREF(state->ref_value[0]);
656 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
657 R_028430_DB_STENCILREFMASK, tmp,
658 ~C_028430_STENCILREF, NULL);
659 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
660 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
661 R_028434_DB_STENCILREFMASK_BF, tmp,
662 ~C_028434_STENCILREF_BF, NULL);
663
664 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
665 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
666 r600_context_pipe_state_set(&rctx->ctx, rstate);
667 }
668
669 static void evergreen_set_viewport_state(struct pipe_context *ctx,
670 const struct pipe_viewport_state *state)
671 {
672 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
673 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
674
675 if (rstate == NULL)
676 return;
677
678 rctx->viewport = *state;
679 rstate->id = R600_PIPE_STATE_VIEWPORT;
680 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
681 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
682 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
683 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
684 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
685 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
686 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
687 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
688 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
689
690 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
691 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
692 r600_context_pipe_state_set(&rctx->ctx, rstate);
693 }
694
695 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
696 const struct pipe_framebuffer_state *state, int cb)
697 {
698 struct r600_resource_texture *rtex;
699 struct r600_resource *rbuffer;
700 unsigned level = state->cbufs[cb]->level;
701 unsigned pitch, slice;
702 unsigned color_info;
703 unsigned format, swap, ntype;
704 const struct util_format_description *desc;
705 struct radeon_ws_bo *bo[3];
706
707 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
708 rbuffer = &rtex->resource;
709 bo[0] = rbuffer->bo;
710 bo[1] = rbuffer->bo;
711 bo[2] = rbuffer->bo;
712
713 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
714 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
715 ntype = 0;
716 desc = util_format_description(rtex->resource.base.b.format);
717 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
718 ntype = V_028C70_NUMBER_SRGB;
719
720 format = r600_translate_colorformat(rtex->resource.base.b.format);
721 swap = r600_translate_colorswap(rtex->resource.base.b.format);
722 color_info = S_028C70_FORMAT(format) |
723 S_028C70_COMP_SWAP(swap) |
724 S_028C70_BLEND_CLAMP(1) |
725 S_028C70_SOURCE_FORMAT(1) |
726 S_028C70_NUMBER_TYPE(ntype);
727
728 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
729 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
730 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
731 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
732 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
733 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
734 color_info, 0xFFFFFFFF, NULL);
735 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
736 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
737 S_028C64_PITCH_TILE_MAX(pitch),
738 0xFFFFFFFF, NULL);
739 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
740 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
741 S_028C68_SLICE_TILE_MAX(slice),
742 0xFFFFFFFF, NULL);
743 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
744 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
745 0x00000000, 0xFFFFFFFF, NULL);
746 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
747 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
748 S_028C74_NON_DISP_TILING_ORDER(1),
749 0xFFFFFFFF, NULL);
750 }
751
752 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
753 const struct pipe_framebuffer_state *state)
754 {
755 struct r600_resource_texture *rtex;
756 struct r600_resource *rbuffer;
757 unsigned level;
758 unsigned pitch, slice, format;
759
760 if (state->zsbuf == NULL)
761 return;
762
763 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
764 rtex->tiled = 1;
765 rtex->array_mode = 2;
766 rtex->tile_type = 1;
767 rtex->depth = 1;
768 rbuffer = &rtex->resource;
769
770 level = state->zsbuf->level;
771 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
772 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
773 format = r600_translate_dbformat(state->zsbuf->texture->format);
774
775 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028048_DB_Z_READ_BASE,
776 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
777 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028050_DB_Z_WRITE_BASE,
778 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
779 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
780 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028040_DB_Z_INFO,
781 S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
782 0xFFFFFFFF, NULL);
783 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028058_DB_DEPTH_SIZE,
784 S_028058_PITCH_TILE_MAX(pitch),
785 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02805C_DB_DEPTH_SLICE,
787 S_02805C_SLICE_TILE_MAX(slice),
788 0xFFFFFFFF, NULL);
789 }
790
791 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
792 const struct pipe_framebuffer_state *state)
793 {
794 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
795 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
796 u32 shader_mask, tl, br, target_mask;
797
798 if (rstate == NULL)
799 return;
800
801 /* unreference old buffer and reference new one */
802 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
803 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
804 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
805 }
806 for (int i = 0; i < state->nr_cbufs; i++) {
807 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
808 }
809 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
810 rctx->framebuffer = *state;
811
812 /* build states */
813 for (int i = 0; i < state->nr_cbufs; i++) {
814 evergreen_cb(rctx, rstate, state, i);
815 }
816 if (state->zsbuf) {
817 evergreen_db(rctx, rstate, state);
818 }
819
820 target_mask = 0x00000000;
821 target_mask = 0xFFFFFFFF;
822 shader_mask = 0;
823 for (int i = 0; i < state->nr_cbufs; i++) {
824 target_mask ^= 0xf << (i * 4);
825 shader_mask |= 0xf << (i * 4);
826 }
827 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
828 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
829
830 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
831 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
832 0xFFFFFFFF, NULL);
833 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
834 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
835 0xFFFFFFFF, NULL);
836 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
837 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
838 0xFFFFFFFF, NULL);
839 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
840 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
841 0xFFFFFFFF, NULL);
842
843 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
844 0x00000000, target_mask, NULL);
845 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
846 shader_mask, 0xFFFFFFFF, NULL);
847 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
848 0x00000000, 0xFFFFFFFF, NULL);
849 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
850 0x00000000, 0xFFFFFFFF, NULL);
851
852 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
853 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
854 r600_context_pipe_state_set(&rctx->ctx, rstate);
855 }
856
857 static void evergreen_set_index_buffer(struct pipe_context *ctx,
858 const struct pipe_index_buffer *ib)
859 {
860 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
861
862 if (ib) {
863 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
864 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
865 } else {
866 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
867 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
868 }
869
870 /* TODO make this more like a state */
871 }
872
873 static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
874 const struct pipe_vertex_buffer *buffers)
875 {
876 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
877
878 for (int i = 0; i < rctx->nvertex_buffer; i++) {
879 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
880 }
881 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
882 for (int i = 0; i < count; i++) {
883 rctx->vertex_buffer[i].buffer = NULL;
884 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
885 }
886 rctx->nvertex_buffer = count;
887 }
888
889 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
890 struct pipe_resource *buffer)
891 {
892 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
893 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
894
895 switch (shader) {
896 case PIPE_SHADER_VERTEX:
897 rctx->vs_const_buffer.nregs = 0;
898 r600_pipe_state_add_reg(&rctx->vs_const_buffer, R600_GROUP_ALU_CONST,
899 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
900 ALIGN_DIVUP(buffer->width0 >> 4, 16),
901 0xFFFFFFFF, NULL);
902 r600_pipe_state_add_reg(&rctx->vs_const_buffer, R600_GROUP_ALU_CONST,
903 R_028980_ALU_CONST_CACHE_VS_0,
904 0, 0xFFFFFFFF, rbuffer->bo);
905 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
906 break;
907 case PIPE_SHADER_FRAGMENT:
908 rctx->ps_const_buffer.nregs = 0;
909 r600_pipe_state_add_reg(&rctx->ps_const_buffer, R600_GROUP_ALU_CONST,
910 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
911 ALIGN_DIVUP(buffer->width0 >> 4, 16),
912 0xFFFFFFFF, NULL);
913 r600_pipe_state_add_reg(&rctx->ps_const_buffer, R600_GROUP_ALU_CONST,
914 R_028940_ALU_CONST_CACHE_PS_0,
915 0, 0xFFFFFFFF, rbuffer->bo);
916 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
917 break;
918 default:
919 R600_ERR("unsupported %d\n", shader);
920 return;
921 }
922 }
923
924 static void *evergreen_create_shader_state(struct pipe_context *ctx,
925 const struct pipe_shader_state *state)
926 {
927 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
928 int r;
929
930 r = r600_pipe_shader_create2(ctx, shader, state->tokens);
931 if (r) {
932 return NULL;
933 }
934 return shader;
935 }
936
937 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
938 {
939 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
940
941 /* TODO delete old shader */
942 rctx->ps_shader = (struct r600_pipe_shader *)state;
943 }
944
945 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
946 {
947 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
948
949 /* TODO delete old shader */
950 rctx->vs_shader = (struct r600_pipe_shader *)state;
951 }
952
953 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
954 {
955 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
956 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
957
958 if (rctx->ps_shader == shader) {
959 rctx->ps_shader = NULL;
960 }
961 /* TODO proper delete */
962 free(shader);
963 }
964
965 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
966 {
967 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
968 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
969
970 if (rctx->vs_shader == shader) {
971 rctx->vs_shader = NULL;
972 }
973 /* TODO proper delete */
974 free(shader);
975 }
976
977 void evergreen_init_state_functions2(struct r600_pipe_context *rctx)
978 {
979 rctx->context.create_blend_state = evergreen_create_blend_state;
980 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
981 rctx->context.create_fs_state = evergreen_create_shader_state;
982 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
983 rctx->context.create_sampler_state = evergreen_create_sampler_state;
984 rctx->context.create_sampler_view = evergreen_create_sampler_view;
985 rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
986 rctx->context.create_vs_state = evergreen_create_shader_state;
987 rctx->context.bind_blend_state = evergreen_bind_blend_state;
988 rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
989 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
990 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
991 rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
992 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
993 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
994 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
995 rctx->context.delete_blend_state = evergreen_delete_state;
996 rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
997 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
998 rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
999 rctx->context.delete_sampler_state = evergreen_delete_state;
1000 rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
1001 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
1002 rctx->context.set_blend_color = evergreen_set_blend_color;
1003 rctx->context.set_clip_state = evergreen_set_clip_state;
1004 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
1005 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1006 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1007 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1008 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1009 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1010 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1011 rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
1012 rctx->context.set_index_buffer = evergreen_set_index_buffer;
1013 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1014 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1015 rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
1016 }
1017
1018 void evergreen_init_config2(struct r600_pipe_context *rctx)
1019 {
1020 struct r600_pipe_state *rstate = &rctx->config;
1021 int ps_prio;
1022 int vs_prio;
1023 int gs_prio;
1024 int es_prio;
1025 int hs_prio, cs_prio, ls_prio;
1026 int num_ps_gprs;
1027 int num_vs_gprs;
1028 int num_gs_gprs;
1029 int num_es_gprs;
1030 int num_hs_gprs;
1031 int num_ls_gprs;
1032 int num_temp_gprs;
1033 int num_ps_threads;
1034 int num_vs_threads;
1035 int num_gs_threads;
1036 int num_es_threads;
1037 int num_hs_threads;
1038 int num_ls_threads;
1039 int num_ps_stack_entries;
1040 int num_vs_stack_entries;
1041 int num_gs_stack_entries;
1042 int num_es_stack_entries;
1043 int num_hs_stack_entries;
1044 int num_ls_stack_entries;
1045 enum radeon_family family;
1046 unsigned tmp;
1047
1048 family = r600_get_family(rctx->radeon);
1049 ps_prio = 0;
1050 vs_prio = 1;
1051 gs_prio = 2;
1052 es_prio = 3;
1053 hs_prio = 0;
1054 ls_prio = 0;
1055 cs_prio = 0;
1056
1057 switch (family) {
1058 case CHIP_CEDAR:
1059 default:
1060 num_ps_gprs = 93;
1061 num_vs_gprs = 46;
1062 num_temp_gprs = 4;
1063 num_gs_gprs = 31;
1064 num_es_gprs = 31;
1065 num_hs_gprs = 23;
1066 num_ls_gprs = 23;
1067 num_ps_threads = 96;
1068 num_vs_threads = 16;
1069 num_gs_threads = 16;
1070 num_es_threads = 16;
1071 num_hs_threads = 16;
1072 num_ls_threads = 16;
1073 num_ps_stack_entries = 42;
1074 num_vs_stack_entries = 42;
1075 num_gs_stack_entries = 42;
1076 num_es_stack_entries = 42;
1077 num_hs_stack_entries = 42;
1078 num_ls_stack_entries = 42;
1079 break;
1080 case CHIP_REDWOOD:
1081 num_ps_gprs = 93;
1082 num_vs_gprs = 46;
1083 num_temp_gprs = 4;
1084 num_gs_gprs = 31;
1085 num_es_gprs = 31;
1086 num_hs_gprs = 23;
1087 num_ls_gprs = 23;
1088 num_ps_threads = 128;
1089 num_vs_threads = 20;
1090 num_gs_threads = 20;
1091 num_es_threads = 20;
1092 num_hs_threads = 20;
1093 num_ls_threads = 20;
1094 num_ps_stack_entries = 42;
1095 num_vs_stack_entries = 42;
1096 num_gs_stack_entries = 42;
1097 num_es_stack_entries = 42;
1098 num_hs_stack_entries = 42;
1099 num_ls_stack_entries = 42;
1100 break;
1101 case CHIP_JUNIPER:
1102 num_ps_gprs = 93;
1103 num_vs_gprs = 46;
1104 num_temp_gprs = 4;
1105 num_gs_gprs = 31;
1106 num_es_gprs = 31;
1107 num_hs_gprs = 23;
1108 num_ls_gprs = 23;
1109 num_ps_threads = 128;
1110 num_vs_threads = 20;
1111 num_gs_threads = 20;
1112 num_es_threads = 20;
1113 num_hs_threads = 20;
1114 num_ls_threads = 20;
1115 num_ps_stack_entries = 85;
1116 num_vs_stack_entries = 85;
1117 num_gs_stack_entries = 85;
1118 num_es_stack_entries = 85;
1119 num_hs_stack_entries = 85;
1120 num_ls_stack_entries = 85;
1121 break;
1122 case CHIP_CYPRESS:
1123 case CHIP_HEMLOCK:
1124 num_ps_gprs = 93;
1125 num_vs_gprs = 46;
1126 num_temp_gprs = 4;
1127 num_gs_gprs = 31;
1128 num_es_gprs = 31;
1129 num_hs_gprs = 23;
1130 num_ls_gprs = 23;
1131 num_ps_threads = 128;
1132 num_vs_threads = 20;
1133 num_gs_threads = 20;
1134 num_es_threads = 20;
1135 num_hs_threads = 20;
1136 num_ls_threads = 20;
1137 num_ps_stack_entries = 85;
1138 num_vs_stack_entries = 85;
1139 num_gs_stack_entries = 85;
1140 num_es_stack_entries = 85;
1141 num_hs_stack_entries = 85;
1142 num_ls_stack_entries = 85;
1143 break;
1144 }
1145
1146 tmp = 0x00000000;
1147 switch (family) {
1148 case CHIP_CEDAR:
1149 break;
1150 default:
1151 tmp |= S_008C00_VC_ENABLE(1);
1152 break;
1153 }
1154 tmp |= S_008C00_EXPORT_SRC_C(1);
1155 tmp |= S_008C00_CS_PRIO(cs_prio);
1156 tmp |= S_008C00_LS_PRIO(ls_prio);
1157 tmp |= S_008C00_HS_PRIO(hs_prio);
1158 tmp |= S_008C00_PS_PRIO(ps_prio);
1159 tmp |= S_008C00_VS_PRIO(vs_prio);
1160 tmp |= S_008C00_GS_PRIO(gs_prio);
1161 tmp |= S_008C00_ES_PRIO(es_prio);
1162 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1163
1164 tmp = 0;
1165 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1166 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1167 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1168 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1169
1170 tmp = 0;
1171 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1172 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1173 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1174
1175 tmp = 0;
1176 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1177 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1178 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1179
1180 tmp = 0;
1181 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1182 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1183 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1184 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1185 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1186
1187 tmp = 0;
1188 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1189 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1190 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1191
1192 tmp = 0;
1193 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1194 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1195 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1196
1197 tmp = 0;
1198 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1199 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1200 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1201
1202 tmp = 0;
1203 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1204 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1205 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1206
1207 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1208 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1209
1210 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1211
1212 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1214 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1215
1216 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1217 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1219 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1220 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1221 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1222
1223 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1224 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1226 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1227
1228 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1229 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1230 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1232 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1233 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1234 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1235 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1236 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1237 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1238 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1239 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1240 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1241 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1242 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1243 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1244 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1246 r600_context_pipe_state_set(&rctx->ctx, rstate);
1247 }
1248
1249 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1250 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1251 {
1252 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1253 struct r600_pipe_state *rstate;
1254 struct r600_resource *rbuffer;
1255 unsigned i, j, offset, format, prim;
1256 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1257 struct pipe_vertex_buffer *vertex_buffer;
1258 struct r600_draw rdraw;
1259 struct r600_pipe_state vgt;
1260 struct r600_drawl draw;
1261
1262 assert(info->index_bias == 0);
1263
1264 draw.mode = info->mode;
1265 draw.start = info->start;
1266 draw.count = info->count;
1267 if (info->indexed && rctx->index_buffer.buffer) {
1268 draw.index_size = rctx->index_buffer.index_size;
1269 draw.index_buffer = rctx->index_buffer.buffer;
1270 assert(rctx->index_buffer.offset %
1271 rctx->index_buffer.index_size == 0);
1272 draw.start += rctx->index_buffer.offset /
1273 rctx->index_buffer.index_size;
1274 } else {
1275 draw.index_size = 0;
1276 draw.index_buffer = NULL;
1277 }
1278 switch (draw.index_size) {
1279 case 2:
1280 vgt_draw_initiator = 0;
1281 vgt_dma_index_type = 0;
1282 break;
1283 case 4:
1284 vgt_draw_initiator = 0;
1285 vgt_dma_index_type = 1;
1286 break;
1287 case 0:
1288 vgt_draw_initiator = 2;
1289 vgt_dma_index_type = 0;
1290 break;
1291 default:
1292 R600_ERR("unsupported index size %d\n", draw.index_size);
1293 return;
1294 }
1295 if (r600_conv_pipe_prim(draw.mode, &prim))
1296 return;
1297
1298 /* rebuild vertex shader if input format changed */
1299 if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
1300 return;
1301 if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
1302 return;
1303
1304 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1305 rstate = &rctx->vs_resource[i];
1306 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1307 vertex_buffer = &rctx->vertex_buffer[j];
1308 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1309 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
1310 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
1311 rstate->id = R600_PIPE_STATE_RESOURCE;
1312 rstate->nregs = 0;
1313
1314 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1315 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1316 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE,
1317 R_030008_RESOURCE0_WORD2,
1318 S_030008_STRIDE(vertex_buffer->stride) |
1319 S_030008_DATA_FORMAT(format),
1320 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE,
1322 R_03000C_RESOURCE0_WORD3,
1323 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1324 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1325 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1326 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1327 0xFFFFFFFF, NULL);
1328 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1329 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1330 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1331 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1332 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1333 }
1334
1335 mask = 0;
1336 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1337 mask |= (0xF << (i * 4));
1338 }
1339
1340 vgt.id = R600_PIPE_STATE_VGT;
1341 vgt.nregs = 0;
1342 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1343 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw.start, 0xFFFFFFFF, NULL);
1344 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1345 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1346
1347 rdraw.vgt_num_indices = draw.count;
1348 rdraw.vgt_num_instances = 1;
1349 rdraw.vgt_index_type = vgt_dma_index_type;
1350 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1351 rdraw.indices = NULL;
1352 if (draw.index_buffer) {
1353 rbuffer = (struct r600_resource*)draw.index_buffer;
1354 rdraw.indices = rbuffer->bo;
1355 rdraw.indices_bo_offset = 0;
1356 }
1357 evergreen_context_draw(&rctx->ctx, &rdraw);
1358 }
1359
1360 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1361 {
1362 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1363 struct r600_pipe_state *rstate = &shader->rstate;
1364 struct r600_shader *rshader = &shader->shader;
1365 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
1366 boolean have_pos = FALSE, have_face = FALSE;
1367
1368 /* clear previous register */
1369 rstate->nregs = 0;
1370
1371 for (i = 0; i < rshader->ninput; i++) {
1372 tmp = S_028644_SEMANTIC(i);
1373 tmp |= S_028644_SEL_CENTROID(1);
1374 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1375 have_pos = TRUE;
1376 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1377 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1378 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1379 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1380 }
1381 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1382 have_face = TRUE;
1383 if (rctx->sprite_coord_enable & (1 << i)) {
1384 tmp |= S_028644_PT_SPRITE_TEX(1);
1385 }
1386 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1387 }
1388
1389 exports_ps = 0;
1390 num_cout = 0;
1391 for (i = 0; i < rshader->noutput; i++) {
1392 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1393 exports_ps |= 1;
1394 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1395 num_cout++;
1396 }
1397 }
1398 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1399 if (!exports_ps) {
1400 /* always at least export 1 component per pixel */
1401 exports_ps = 2;
1402 }
1403
1404 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1405 S_0286CC_PERSP_GRADIENT_ENA(1);
1406 spi_input_z = 0;
1407 if (have_pos) {
1408 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1);
1409 spi_input_z |= 1;
1410 }
1411 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0,
1412 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1413 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1,
1414 S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
1415 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1416 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1417 R_028840_SQ_PGM_START_PS,
1418 0x00000000, 0xFFFFFFFF, shader->bo);
1419 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1420 R_028844_SQ_PGM_RESOURCES_PS,
1421 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1422 S_028844_PRIME_CACHE_ON_DRAW(1) |
1423 S_028844_STACK_SIZE(rshader->bc.nstack),
1424 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1426 R_02884C_SQ_PGM_EXPORTS_PS,
1427 exports_ps, 0xFFFFFFFF, NULL);
1428 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1429 R_0286E0_SPI_BARYC_CNTL,
1430 S_0286E0_PERSP_CENTROID_ENA(1) |
1431 S_0286E0_LINEAR_CENTROID_ENA(1),
1432 0xFFFFFFFF, NULL);
1433 }
1434
1435 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1436 {
1437 struct r600_pipe_state *rstate = &shader->rstate;
1438 struct r600_shader *rshader = &shader->shader;
1439 unsigned spi_vs_out_id[10];
1440 unsigned i, tmp;
1441
1442 /* clear previous register */
1443 rstate->nregs = 0;
1444
1445 /* so far never got proper semantic id from tgsi */
1446 for (i = 0; i < 10; i++) {
1447 spi_vs_out_id[i] = 0;
1448 }
1449 for (i = 0; i < 32; i++) {
1450 tmp = i << ((i & 3) * 8);
1451 spi_vs_out_id[i / 4] |= tmp;
1452 }
1453 for (i = 0; i < 10; i++) {
1454 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1455 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1456 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1457 }
1458
1459 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1460 R_0286C4_SPI_VS_OUT_CONFIG,
1461 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1462 0xFFFFFFFF, NULL);
1463 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1464 R_028860_SQ_PGM_RESOURCES_VS,
1465 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1466 S_028860_STACK_SIZE(rshader->bc.nstack),
1467 0xFFFFFFFF, NULL);
1468 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1469 R_0288A8_SQ_PGM_RESOURCES_FS,
1470 0x00000000, 0xFFFFFFFF, NULL);
1471 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1472 R_02885C_SQ_PGM_START_VS,
1473 0x00000000, 0xFFFFFFFF, shader->bo);
1474 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1475 R_0288A4_SQ_PGM_START_FS,
1476 0x00000000, 0xFFFFFFFF, shader->bo);
1477 }