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r600: fix cubemap arrays
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
172 static unsigned r600_tex_dim(struct r600_texture *rtex,
173 unsigned view_target, unsigned nr_samples)
174 {
175 unsigned res_target = rtex->resource.b.b.target;
176
177 if (view_target == PIPE_TEXTURE_CUBE ||
178 view_target == PIPE_TEXTURE_CUBE_ARRAY)
179 res_target = view_target;
180 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
181 else if (res_target == PIPE_TEXTURE_CUBE ||
182 res_target == PIPE_TEXTURE_CUBE_ARRAY)
183 res_target = PIPE_TEXTURE_2D_ARRAY;
184
185 switch (res_target) {
186 default:
187 case PIPE_TEXTURE_1D:
188 return V_030000_SQ_TEX_DIM_1D;
189 case PIPE_TEXTURE_1D_ARRAY:
190 return V_030000_SQ_TEX_DIM_1D_ARRAY;
191 case PIPE_TEXTURE_2D:
192 case PIPE_TEXTURE_RECT:
193 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
194 V_030000_SQ_TEX_DIM_2D;
195 case PIPE_TEXTURE_2D_ARRAY:
196 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
197 V_030000_SQ_TEX_DIM_2D_ARRAY;
198 case PIPE_TEXTURE_3D:
199 return V_030000_SQ_TEX_DIM_3D;
200 case PIPE_TEXTURE_CUBE:
201 case PIPE_TEXTURE_CUBE_ARRAY:
202 return V_030000_SQ_TEX_DIM_CUBEMAP;
203 }
204 }
205
206 static uint32_t r600_translate_dbformat(enum pipe_format format)
207 {
208 switch (format) {
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_028040_Z_16;
211 case PIPE_FORMAT_Z24X8_UNORM:
212 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
213 case PIPE_FORMAT_X8Z24_UNORM:
214 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
215 return V_028040_Z_24;
216 case PIPE_FORMAT_Z32_FLOAT:
217 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
218 return V_028040_Z_32_FLOAT;
219 default:
220 return ~0U;
221 }
222 }
223
224 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
225 {
226 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
227 FALSE) != ~0U;
228 }
229
230 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
231 {
232 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
233 r600_translate_colorswap(format, FALSE) != ~0U;
234 }
235
236 static bool r600_is_zs_format_supported(enum pipe_format format)
237 {
238 return r600_translate_dbformat(format) != ~0U;
239 }
240
241 boolean evergreen_is_format_supported(struct pipe_screen *screen,
242 enum pipe_format format,
243 enum pipe_texture_target target,
244 unsigned sample_count,
245 unsigned usage)
246 {
247 struct r600_screen *rscreen = (struct r600_screen*)screen;
248 unsigned retval = 0;
249
250 if (target >= PIPE_MAX_TEXTURE_TYPES) {
251 R600_ERR("r600: unsupported texture type %d\n", target);
252 return FALSE;
253 }
254
255 if (!util_format_is_supported(format, usage))
256 return FALSE;
257
258 if (sample_count > 1) {
259 if (!rscreen->has_msaa)
260 return FALSE;
261
262 switch (sample_count) {
263 case 2:
264 case 4:
265 case 8:
266 break;
267 default:
268 return FALSE;
269 }
270 }
271
272 if (usage & PIPE_BIND_SAMPLER_VIEW) {
273 if (target == PIPE_BUFFER) {
274 if (r600_is_vertex_format_supported(format))
275 retval |= PIPE_BIND_SAMPLER_VIEW;
276 } else {
277 if (r600_is_sampler_format_supported(screen, format))
278 retval |= PIPE_BIND_SAMPLER_VIEW;
279 }
280 }
281
282 if ((usage & (PIPE_BIND_RENDER_TARGET |
283 PIPE_BIND_DISPLAY_TARGET |
284 PIPE_BIND_SCANOUT |
285 PIPE_BIND_SHARED |
286 PIPE_BIND_BLENDABLE)) &&
287 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
288 retval |= usage &
289 (PIPE_BIND_RENDER_TARGET |
290 PIPE_BIND_DISPLAY_TARGET |
291 PIPE_BIND_SCANOUT |
292 PIPE_BIND_SHARED);
293 if (!util_format_is_pure_integer(format) &&
294 !util_format_is_depth_or_stencil(format))
295 retval |= usage & PIPE_BIND_BLENDABLE;
296 }
297
298 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
299 r600_is_zs_format_supported(format)) {
300 retval |= PIPE_BIND_DEPTH_STENCIL;
301 }
302
303 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
304 r600_is_vertex_format_supported(format)) {
305 retval |= PIPE_BIND_VERTEX_BUFFER;
306 }
307
308 if ((usage & PIPE_BIND_LINEAR) &&
309 !util_format_is_compressed(format) &&
310 !(usage & PIPE_BIND_DEPTH_STENCIL))
311 retval |= PIPE_BIND_LINEAR;
312
313 return retval == usage;
314 }
315
316 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
317 const struct pipe_blend_state *state, int mode)
318 {
319 uint32_t color_control = 0, target_mask = 0;
320 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
321
322 if (!blend) {
323 return NULL;
324 }
325
326 r600_init_command_buffer(&blend->buffer, 20);
327 r600_init_command_buffer(&blend->buffer_no_blend, 20);
328
329 if (state->logicop_enable) {
330 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
331 } else {
332 color_control |= (0xcc << 16);
333 }
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 if (state->independent_blend_enable) {
336 for (int i = 0; i < 8; i++) {
337 target_mask |= (state->rt[i].colormask << (4 * i));
338 }
339 } else {
340 for (int i = 0; i < 8; i++) {
341 target_mask |= (state->rt[0].colormask << (4 * i));
342 }
343 }
344
345 /* only have dual source on MRT0 */
346 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
347 blend->cb_target_mask = target_mask;
348 blend->alpha_to_one = state->alpha_to_one;
349
350 if (target_mask)
351 color_control |= S_028808_MODE(mode);
352 else
353 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
354
355
356 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
357 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
358 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
359 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
363 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
364
365 /* Copy over the dwords set so far into buffer_no_blend.
366 * Only the CB_BLENDi_CONTROL registers must be set after this. */
367 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
368 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
369
370 for (int i = 0; i < 8; i++) {
371 /* state->rt entries > 0 only written if independent blending */
372 const int j = state->independent_blend_enable ? i : 0;
373
374 unsigned eqRGB = state->rt[j].rgb_func;
375 unsigned srcRGB = state->rt[j].rgb_src_factor;
376 unsigned dstRGB = state->rt[j].rgb_dst_factor;
377 unsigned eqA = state->rt[j].alpha_func;
378 unsigned srcA = state->rt[j].alpha_src_factor;
379 unsigned dstA = state->rt[j].alpha_dst_factor;
380 uint32_t bc = 0;
381
382 r600_store_value(&blend->buffer_no_blend, 0);
383
384 if (!state->rt[j].blend_enable) {
385 r600_store_value(&blend->buffer, 0);
386 continue;
387 }
388
389 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
390 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
391 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
392 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
393
394 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
395 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
396 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
397 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
398 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
399 }
400 r600_store_value(&blend->buffer, bc);
401 }
402 return blend;
403 }
404
405 static void *evergreen_create_blend_state(struct pipe_context *ctx,
406 const struct pipe_blend_state *state)
407 {
408
409 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
410 }
411
412 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
413 const struct pipe_depth_stencil_alpha_state *state)
414 {
415 unsigned db_depth_control, alpha_test_control, alpha_ref;
416 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
417
418 if (!dsa) {
419 return NULL;
420 }
421
422 r600_init_command_buffer(&dsa->buffer, 3);
423
424 dsa->valuemask[0] = state->stencil[0].valuemask;
425 dsa->valuemask[1] = state->stencil[1].valuemask;
426 dsa->writemask[0] = state->stencil[0].writemask;
427 dsa->writemask[1] = state->stencil[1].writemask;
428 dsa->zwritemask = state->depth.writemask;
429
430 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
431 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
432 S_028800_ZFUNC(state->depth.func);
433
434 /* stencil */
435 if (state->stencil[0].enabled) {
436 db_depth_control |= S_028800_STENCIL_ENABLE(1);
437 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
438 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
439 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
440 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
441
442 if (state->stencil[1].enabled) {
443 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
444 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
445 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
446 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
447 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
448 }
449 }
450
451 /* alpha */
452 alpha_test_control = 0;
453 alpha_ref = 0;
454 if (state->alpha.enabled) {
455 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
456 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
457 alpha_ref = fui(state->alpha.ref_value);
458 }
459 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
460 dsa->alpha_ref = alpha_ref;
461
462 /* misc */
463 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
464 return dsa;
465 }
466
467 static void *evergreen_create_rs_state(struct pipe_context *ctx,
468 const struct pipe_rasterizer_state *state)
469 {
470 struct r600_context *rctx = (struct r600_context *)ctx;
471 unsigned tmp, spi_interp;
472 float psize_min, psize_max;
473 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
474
475 if (!rs) {
476 return NULL;
477 }
478
479 r600_init_command_buffer(&rs->buffer, 30);
480
481 rs->scissor_enable = state->scissor;
482 rs->clip_halfz = state->clip_halfz;
483 rs->flatshade = state->flatshade;
484 rs->sprite_coord_enable = state->sprite_coord_enable;
485 rs->rasterizer_discard = state->rasterizer_discard;
486 rs->two_side = state->light_twoside;
487 rs->clip_plane_enable = state->clip_plane_enable;
488 rs->pa_sc_line_stipple = state->line_stipple_enable ?
489 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
490 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
491 rs->pa_cl_clip_cntl =
492 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
493 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
494 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
495 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
496 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
497 rs->multisample_enable = state->multisample;
498
499 /* offset */
500 rs->offset_units = state->offset_units;
501 rs->offset_scale = state->offset_scale * 16.0f;
502 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
503 rs->offset_units_unscaled = state->offset_units_unscaled;
504
505 if (state->point_size_per_vertex) {
506 psize_min = util_get_min_point_size(state);
507 psize_max = 8192;
508 } else {
509 /* Force the point size to be as if the vertex output was disabled. */
510 psize_min = state->point_size;
511 psize_max = state->point_size;
512 }
513
514 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
515 if (state->sprite_coord_enable) {
516 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
517 S_0286D4_PNT_SPRITE_OVRD_X(2) |
518 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
519 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
520 S_0286D4_PNT_SPRITE_OVRD_W(1);
521 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
522 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
523 }
524 }
525
526 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
527 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
528 tmp = r600_pack_float_12p4(state->point_size/2);
529 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
530 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
531 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
532 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
533 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
534 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
535 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
536
537 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
538 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
539 S_028A48_MSAA_ENABLE(state->multisample) |
540 S_028A48_VPORT_SCISSOR_ENABLE(1) |
541 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
542
543 if (rctx->b.chip_class == CAYMAN) {
544 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
545 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
546 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
547 } else {
548 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
549 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
550 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
551 }
552
553 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
554 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
555 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
556 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
557 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
558 S_028814_FACE(!state->front_ccw) |
559 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
560 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
561 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
562 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
563 state->fill_back != PIPE_POLYGON_MODE_FILL) |
564 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
565 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
566 return rs;
567 }
568
569 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
570 const struct pipe_sampler_state *state)
571 {
572 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
573 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
574 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
575 : state->max_anisotropy;
576 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
577
578 if (!ss) {
579 return NULL;
580 }
581
582 ss->border_color_use = sampler_state_needs_border_color(state);
583
584 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
585 ss->tex_sampler_words[0] =
586 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
587 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
588 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
589 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
590 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
591 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
592 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
593 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
594 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
595 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
596 ss->tex_sampler_words[1] =
597 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
598 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
599 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
600 ss->tex_sampler_words[2] =
601 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
602 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
603 S_03C008_TYPE(1);
604
605 if (ss->border_color_use) {
606 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
607 }
608 return ss;
609 }
610
611 struct eg_buf_res_params {
612 enum pipe_format pipe_format;
613 unsigned offset;
614 unsigned size;
615 unsigned char swizzle[4];
616 bool uncached;
617 };
618
619 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
620 struct pipe_resource *buffer,
621 struct eg_buf_res_params *params,
622 bool *skip_mip_address_reloc,
623 unsigned tex_resource_words[8])
624 {
625 struct r600_texture *tmp = (struct r600_texture*)buffer;
626 uint64_t va;
627 int stride = util_format_get_blocksize(params->pipe_format);
628 unsigned format, num_format, format_comp, endian;
629 unsigned swizzle_res;
630 const struct util_format_description *desc;
631
632 r600_vertex_data_type(params->pipe_format,
633 &format, &num_format, &format_comp,
634 &endian);
635
636 desc = util_format_description(params->pipe_format);
637
638 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
639
640 va = tmp->resource.gpu_address + params->offset;
641 *skip_mip_address_reloc = true;
642 tex_resource_words[0] = va;
643 tex_resource_words[1] = params->size - 1;
644 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
645 S_030008_STRIDE(stride) |
646 S_030008_DATA_FORMAT(format) |
647 S_030008_NUM_FORMAT_ALL(num_format) |
648 S_030008_FORMAT_COMP_ALL(format_comp) |
649 S_030008_ENDIAN_SWAP(endian);
650 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
651 /*
652 * in theory dword 4 is for number of elements, for use with resinfo,
653 * but it seems to utterly fail to work, the amd gpu shader analyser
654 * uses a const buffer to store the element sizes for buffer txq
655 */
656 tex_resource_words[4] = 0;
657 tex_resource_words[5] = tex_resource_words[6] = 0;
658 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
659 }
660
661 static struct pipe_sampler_view *
662 texture_buffer_sampler_view(struct r600_context *rctx,
663 struct r600_pipe_sampler_view *view,
664 unsigned width0, unsigned height0)
665 {
666 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
667 struct eg_buf_res_params params;
668
669 memset(&params, 0, sizeof(params));
670
671 params.pipe_format = view->base.format;
672 params.offset = view->base.u.buf.offset;
673 params.size = view->base.u.buf.size;
674 params.swizzle[0] = view->base.swizzle_r;
675 params.swizzle[1] = view->base.swizzle_g;
676 params.swizzle[2] = view->base.swizzle_b;
677 params.swizzle[3] = view->base.swizzle_a;
678
679 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
680 &params, &view->skip_mip_address_reloc,
681 view->tex_resource_words);
682 view->tex_resource = &tmp->resource;
683
684 if (tmp->resource.gpu_address)
685 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
686 return &view->base;
687 }
688
689 struct eg_tex_res_params {
690 enum pipe_format pipe_format;
691 int force_level;
692 unsigned width0;
693 unsigned height0;
694 unsigned first_level;
695 unsigned last_level;
696 unsigned first_layer;
697 unsigned last_layer;
698 unsigned target;
699 unsigned char swizzle[4];
700 };
701
702 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
703 struct pipe_resource *texture,
704 struct eg_tex_res_params *params,
705 bool *skip_mip_address_reloc,
706 unsigned tex_resource_words[8])
707 {
708 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
709 struct r600_texture *tmp = (struct r600_texture*)texture;
710 unsigned format, endian;
711 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
712 unsigned char array_mode = 0, non_disp_tiling = 0;
713 unsigned height, depth, width;
714 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
715 struct legacy_surf_level *surflevel;
716 unsigned base_level, first_level, last_level;
717 unsigned dim, last_layer;
718 uint64_t va;
719 bool do_endian_swap = FALSE;
720
721 tile_split = tmp->surface.u.legacy.tile_split;
722 surflevel = tmp->surface.u.legacy.level;
723
724 /* Texturing with separate depth and stencil. */
725 if (tmp->db_compatible) {
726 switch (params->pipe_format) {
727 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
728 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
729 break;
730 case PIPE_FORMAT_X8Z24_UNORM:
731 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
732 /* Z24 is always stored like this for DB
733 * compatibility.
734 */
735 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
736 break;
737 case PIPE_FORMAT_X24S8_UINT:
738 case PIPE_FORMAT_S8X24_UINT:
739 case PIPE_FORMAT_X32_S8X24_UINT:
740 params->pipe_format = PIPE_FORMAT_S8_UINT;
741 tile_split = tmp->surface.u.legacy.stencil_tile_split;
742 surflevel = tmp->surface.u.legacy.stencil_level;
743 break;
744 default:;
745 }
746 }
747
748 if (R600_BIG_ENDIAN)
749 do_endian_swap = !tmp->db_compatible;
750
751 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
752 params->swizzle,
753 &word4, &yuv_format, do_endian_swap);
754 assert(format != ~0);
755 if (format == ~0) {
756 return -1;
757 }
758
759 endian = r600_colorformat_endian_swap(format, do_endian_swap);
760
761 base_level = 0;
762 first_level = params->first_level;
763 last_level = params->last_level;
764 width = params->width0;
765 height = params->height0;
766 depth = texture->depth0;
767
768 if (params->force_level) {
769 base_level = params->force_level;
770 first_level = 0;
771 last_level = 0;
772 width = u_minify(width, params->force_level);
773 height = u_minify(height, params->force_level);
774 depth = u_minify(depth, params->force_level);
775 }
776
777 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
778 non_disp_tiling = tmp->non_disp_tiling;
779
780 switch (surflevel[base_level].mode) {
781 default:
782 case RADEON_SURF_MODE_LINEAR_ALIGNED:
783 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
784 break;
785 case RADEON_SURF_MODE_2D:
786 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
787 break;
788 case RADEON_SURF_MODE_1D:
789 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
790 break;
791 }
792 macro_aspect = tmp->surface.u.legacy.mtilea;
793 bankw = tmp->surface.u.legacy.bankw;
794 bankh = tmp->surface.u.legacy.bankh;
795 tile_split = eg_tile_split(tile_split);
796 macro_aspect = eg_macro_tile_aspect(macro_aspect);
797 bankw = eg_bank_wh(bankw);
798 bankh = eg_bank_wh(bankh);
799 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
800
801 /* 128 bit formats require tile type = 1 */
802 if (rscreen->b.chip_class == CAYMAN) {
803 if (util_format_get_blocksize(params->pipe_format) >= 16)
804 non_disp_tiling = 1;
805 }
806 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
807
808 if (params->target == PIPE_TEXTURE_1D_ARRAY) {
809 height = 1;
810 depth = texture->array_size;
811 } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
812 depth = texture->array_size;
813 } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
814 depth = texture->array_size / 6;
815
816 va = tmp->resource.gpu_address;
817
818 /* array type views and views into array types need to use layer offset */
819 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
820 tex_resource_words[0] = (S_030000_DIM(dim) |
821 S_030000_PITCH((pitch / 8) - 1) |
822 S_030000_TEX_WIDTH(width - 1));
823 if (rscreen->b.chip_class == CAYMAN)
824 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
825 else
826 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
827 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
828 S_030004_TEX_DEPTH(depth - 1) |
829 S_030004_ARRAY_MODE(array_mode));
830 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
831
832 *skip_mip_address_reloc = false;
833 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
834 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
835 if (tmp->is_depth) {
836 /* disable FMASK (0 = disabled) */
837 tex_resource_words[3] = 0;
838 *skip_mip_address_reloc = true;
839 } else {
840 /* FMASK should be in MIP_ADDRESS for multisample textures */
841 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
842 }
843 } else if (last_level && texture->nr_samples <= 1) {
844 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
845 } else {
846 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
847 }
848
849 last_layer = params->last_layer;
850 if (params->target != texture->target && depth == 1) {
851 last_layer = params->first_layer;
852 }
853 tex_resource_words[4] = (word4 |
854 S_030010_ENDIAN_SWAP(endian));
855 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
856 S_030014_LAST_ARRAY(last_layer);
857 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
858
859 if (texture->nr_samples > 1) {
860 unsigned log_samples = util_logbase2(texture->nr_samples);
861 if (rscreen->b.chip_class == CAYMAN) {
862 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
863 }
864 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
865 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
866 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
867 } else {
868 bool no_mip = first_level == last_level;
869
870 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
871 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
872 /* aniso max 16 samples */
873 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
874 }
875
876 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
877 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
878 S_03001C_BANK_WIDTH(bankw) |
879 S_03001C_BANK_HEIGHT(bankh) |
880 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
881 S_03001C_NUM_BANKS(nbanks) |
882 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
883 return 0;
884 }
885
886 struct pipe_sampler_view *
887 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
888 struct pipe_resource *texture,
889 const struct pipe_sampler_view *state,
890 unsigned width0, unsigned height0,
891 unsigned force_level)
892 {
893 struct r600_context *rctx = (struct r600_context*)ctx;
894 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
895 struct r600_texture *tmp = (struct r600_texture*)texture;
896 struct eg_tex_res_params params;
897 int ret;
898
899 if (!view)
900 return NULL;
901
902 /* initialize base object */
903 view->base = *state;
904 view->base.texture = NULL;
905 pipe_reference(NULL, &texture->reference);
906 view->base.texture = texture;
907 view->base.reference.count = 1;
908 view->base.context = ctx;
909
910 if (state->target == PIPE_BUFFER)
911 return texture_buffer_sampler_view(rctx, view, width0, height0);
912
913 memset(&params, 0, sizeof(params));
914 params.pipe_format = state->format;
915 params.force_level = force_level;
916 params.width0 = width0;
917 params.height0 = height0;
918 params.first_level = state->u.tex.first_level;
919 params.last_level = state->u.tex.last_level;
920 params.first_layer = state->u.tex.first_layer;
921 params.last_layer = state->u.tex.last_layer;
922 params.target = state->target;
923 params.swizzle[0] = state->swizzle_r;
924 params.swizzle[1] = state->swizzle_g;
925 params.swizzle[2] = state->swizzle_b;
926 params.swizzle[3] = state->swizzle_a;
927
928 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
929 &view->skip_mip_address_reloc,
930 view->tex_resource_words);
931 if (ret != 0) {
932 FREE(view);
933 return NULL;
934 }
935
936 if (state->format == PIPE_FORMAT_X24S8_UINT ||
937 state->format == PIPE_FORMAT_S8X24_UINT ||
938 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
939 state->format == PIPE_FORMAT_S8_UINT)
940 view->is_stencil_sampler = true;
941
942 view->tex_resource = &tmp->resource;
943
944 return &view->base;
945 }
946
947 static struct pipe_sampler_view *
948 evergreen_create_sampler_view(struct pipe_context *ctx,
949 struct pipe_resource *tex,
950 const struct pipe_sampler_view *state)
951 {
952 return evergreen_create_sampler_view_custom(ctx, tex, state,
953 tex->width0, tex->height0, 0);
954 }
955
956 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
957 {
958 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
959 struct r600_config_state *a = (struct r600_config_state*)atom;
960
961 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
962 if (a->dyn_gpr_enabled) {
963 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
964 radeon_emit(cs, 0);
965 radeon_emit(cs, 0);
966 } else {
967 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
968 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
969 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
970 }
971 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
972 if (a->dyn_gpr_enabled) {
973 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
974 S_028838_PS_GPRS(0x1e) |
975 S_028838_VS_GPRS(0x1e) |
976 S_028838_GS_GPRS(0x1e) |
977 S_028838_ES_GPRS(0x1e) |
978 S_028838_HS_GPRS(0x1e) |
979 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
980 }
981 }
982
983 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
984 {
985 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
986 struct pipe_clip_state *state = &rctx->clip_state.state;
987
988 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
989 radeon_emit_array(cs, (unsigned*)state, 6*4);
990 }
991
992 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
993 const struct pipe_poly_stipple *state)
994 {
995 }
996
997 static void evergreen_get_scissor_rect(struct r600_context *rctx,
998 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
999 uint32_t *tl, uint32_t *br)
1000 {
1001 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1002
1003 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1004
1005 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1006 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1007 }
1008
1009 struct r600_tex_color_info {
1010 unsigned info;
1011 unsigned view;
1012 unsigned dim;
1013 unsigned pitch;
1014 unsigned slice;
1015 unsigned attrib;
1016 unsigned ntype;
1017 unsigned fmask;
1018 unsigned fmask_slice;
1019 uint64_t offset;
1020 boolean export_16bpc;
1021 };
1022
1023 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1024 struct r600_resource *res,
1025 enum pipe_format pformat,
1026 unsigned first_element,
1027 unsigned last_element,
1028 struct r600_tex_color_info *color)
1029 {
1030 unsigned format, swap, ntype, endian;
1031 const struct util_format_description *desc;
1032 unsigned block_size = align(util_format_get_blocksize(res->b.b.format), 4);
1033 unsigned pitch_alignment =
1034 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1035 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1036 int i;
1037 unsigned width_elements;
1038
1039 width_elements = last_element - first_element + 1;
1040
1041 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1042 swap = r600_translate_colorswap(pformat, FALSE);
1043
1044 endian = r600_colorformat_endian_swap(format, FALSE);
1045
1046 desc = util_format_description(pformat);
1047 for (i = 0; i < 4; i++) {
1048 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1049 break;
1050 }
1051 }
1052 ntype = V_028C70_NUMBER_UNORM;
1053 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1054 ntype = V_028C70_NUMBER_SRGB;
1055 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1056 if (desc->channel[i].normalized)
1057 ntype = V_028C70_NUMBER_SNORM;
1058 else if (desc->channel[i].pure_integer)
1059 ntype = V_028C70_NUMBER_SINT;
1060 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1061 if (desc->channel[i].normalized)
1062 ntype = V_028C70_NUMBER_UNORM;
1063 else if (desc->channel[i].pure_integer)
1064 ntype = V_028C70_NUMBER_UINT;
1065 }
1066 pitch = (pitch / 8) - 1;
1067 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1068
1069 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1070 color->info |= S_028C70_FORMAT(format) |
1071 S_028C70_COMP_SWAP(swap) |
1072 S_028C70_BLEND_CLAMP(0) |
1073 S_028C70_BLEND_BYPASS(1) |
1074 S_028C70_NUMBER_TYPE(ntype) |
1075 S_028C70_ENDIAN(endian);
1076 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1077 color->ntype = ntype;
1078 color->export_16bpc = false;
1079 color->dim = width_elements - 1;
1080 color->slice = 0; /* (width_elements / 64) - 1;*/
1081 color->view = 0;
1082 color->offset = res->gpu_address >> 8;
1083
1084 color->fmask = color->offset;
1085 color->fmask_slice = 0;
1086 }
1087
1088 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1089 struct r600_texture *rtex,
1090 unsigned level,
1091 unsigned first_layer,
1092 unsigned last_layer,
1093 enum pipe_format pformat,
1094 struct r600_tex_color_info *color)
1095 {
1096 struct r600_screen *rscreen = rctx->screen;
1097 unsigned pitch, slice;
1098 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1099 unsigned format, swap, ntype, endian;
1100 const struct util_format_description *desc;
1101 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1102 int i;
1103
1104 color->offset = rtex->surface.u.legacy.level[level].offset;
1105 color->view = S_028C6C_SLICE_START(first_layer) |
1106 S_028C6C_SLICE_MAX(last_layer);
1107
1108 color->offset += rtex->resource.gpu_address;
1109 color->offset >>= 8;
1110
1111 color->dim = 0;
1112 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1113 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1114 if (slice) {
1115 slice = slice - 1;
1116 }
1117
1118 color->info = 0;
1119 switch (rtex->surface.u.legacy.level[level].mode) {
1120 default:
1121 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1122 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1123 non_disp_tiling = 1;
1124 break;
1125 case RADEON_SURF_MODE_1D:
1126 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1127 non_disp_tiling = rtex->non_disp_tiling;
1128 break;
1129 case RADEON_SURF_MODE_2D:
1130 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1131 non_disp_tiling = rtex->non_disp_tiling;
1132 break;
1133 }
1134 tile_split = rtex->surface.u.legacy.tile_split;
1135 macro_aspect = rtex->surface.u.legacy.mtilea;
1136 bankw = rtex->surface.u.legacy.bankw;
1137 bankh = rtex->surface.u.legacy.bankh;
1138 if (rtex->fmask.size)
1139 fmask_bankh = rtex->fmask.bank_height;
1140 else
1141 fmask_bankh = rtex->surface.u.legacy.bankh;
1142 tile_split = eg_tile_split(tile_split);
1143 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1144 bankw = eg_bank_wh(bankw);
1145 bankh = eg_bank_wh(bankh);
1146 fmask_bankh = eg_bank_wh(fmask_bankh);
1147
1148 if (rscreen->b.chip_class == CAYMAN) {
1149 if (util_format_get_blocksize(pformat) >= 16)
1150 non_disp_tiling = 1;
1151 }
1152 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1153 desc = util_format_description(pformat);
1154 for (i = 0; i < 4; i++) {
1155 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1156 break;
1157 }
1158 }
1159 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1160 S_028C74_NUM_BANKS(nbanks) |
1161 S_028C74_BANK_WIDTH(bankw) |
1162 S_028C74_BANK_HEIGHT(bankh) |
1163 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1164 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1165 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1166
1167 if (rctx->b.chip_class == CAYMAN) {
1168 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1169 PIPE_SWIZZLE_1);
1170
1171 if (rtex->resource.b.b.nr_samples > 1) {
1172 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1173 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1174 S_028C74_NUM_FRAGMENTS(log_samples);
1175 }
1176 }
1177
1178 ntype = V_028C70_NUMBER_UNORM;
1179 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1180 ntype = V_028C70_NUMBER_SRGB;
1181 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1182 if (desc->channel[i].normalized)
1183 ntype = V_028C70_NUMBER_SNORM;
1184 else if (desc->channel[i].pure_integer)
1185 ntype = V_028C70_NUMBER_SINT;
1186 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1187 if (desc->channel[i].normalized)
1188 ntype = V_028C70_NUMBER_UNORM;
1189 else if (desc->channel[i].pure_integer)
1190 ntype = V_028C70_NUMBER_UINT;
1191 }
1192
1193 if (R600_BIG_ENDIAN)
1194 do_endian_swap = !rtex->db_compatible;
1195
1196 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1197 assert(format != ~0);
1198 swap = r600_translate_colorswap(pformat, do_endian_swap);
1199 assert(swap != ~0);
1200
1201 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1202
1203 /* blend clamp should be set for all NORM/SRGB types */
1204 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1205 ntype == V_028C70_NUMBER_SRGB)
1206 blend_clamp = 1;
1207
1208 /* set blend bypass according to docs if SINT/UINT or
1209 8/24 COLOR variants */
1210 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1211 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1212 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1213 blend_clamp = 0;
1214 blend_bypass = 1;
1215 }
1216
1217 color->ntype = ntype;
1218 color->info |= S_028C70_FORMAT(format) |
1219 S_028C70_COMP_SWAP(swap) |
1220 S_028C70_BLEND_CLAMP(blend_clamp) |
1221 S_028C70_BLEND_BYPASS(blend_bypass) |
1222 S_028C70_SIMPLE_FLOAT(1) |
1223 S_028C70_NUMBER_TYPE(ntype) |
1224 S_028C70_ENDIAN(endian);
1225
1226 if (rtex->fmask.size) {
1227 color->info |= S_028C70_COMPRESSION(1);
1228 }
1229
1230 /* EXPORT_NORM is an optimzation that can be enabled for better
1231 * performance in certain cases.
1232 * EXPORT_NORM can be enabled if:
1233 * - 11-bit or smaller UNORM/SNORM/SRGB
1234 * - 16-bit or smaller FLOAT
1235 */
1236 color->export_16bpc = false;
1237 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1238 ((desc->channel[i].size < 12 &&
1239 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1240 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1241 (desc->channel[i].size < 17 &&
1242 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1243 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1244 color->export_16bpc = true;
1245 }
1246
1247 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1248 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1249
1250 if (rtex->fmask.size) {
1251 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1252 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1253 } else {
1254 color->fmask = color->offset;
1255 color->fmask_slice = S_028C88_TILE_MAX(slice);
1256 }
1257 }
1258
1259 /**
1260 * This function intializes the CB* register values for RATs. It is meant
1261 * to be used for 1D aligned buffers that do not have an associated
1262 * radeon_surf.
1263 */
1264 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1265 struct r600_surface *surf)
1266 {
1267 struct pipe_resource *pipe_buffer = surf->base.texture;
1268 struct r600_tex_color_info color;
1269
1270 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1271 surf->base.format, 0, pipe_buffer->width0,
1272 &color);
1273
1274 surf->cb_color_base = color.offset;
1275 surf->cb_color_dim = color.dim;
1276 surf->cb_color_info = color.info | S_028C70_RAT(1);
1277 surf->cb_color_pitch = color.pitch;
1278 surf->cb_color_slice = color.slice;
1279 surf->cb_color_view = color.view;
1280 surf->cb_color_attrib = color.attrib;
1281 surf->cb_color_fmask = color.fmask;
1282 surf->cb_color_fmask_slice = color.fmask_slice;
1283
1284 surf->cb_color_view = 0;
1285
1286 /* Set the buffer range the GPU will have access to: */
1287 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1288 0, pipe_buffer->width0);
1289 }
1290
1291
1292 void evergreen_init_color_surface(struct r600_context *rctx,
1293 struct r600_surface *surf)
1294 {
1295 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1296 unsigned level = surf->base.u.tex.level;
1297 struct r600_tex_color_info color;
1298
1299 evergreen_set_color_surface_common(rctx, rtex, level,
1300 surf->base.u.tex.first_layer,
1301 surf->base.u.tex.last_layer,
1302 surf->base.format,
1303 &color);
1304
1305 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1306 color.ntype == V_028C70_NUMBER_SINT;
1307 surf->export_16bpc = color.export_16bpc;
1308
1309 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1310 surf->cb_color_base = color.offset;
1311 surf->cb_color_dim = color.dim;
1312 surf->cb_color_info = color.info;
1313 surf->cb_color_pitch = color.pitch;
1314 surf->cb_color_slice = color.slice;
1315 surf->cb_color_view = color.view;
1316 surf->cb_color_attrib = color.attrib;
1317 surf->cb_color_fmask = color.fmask;
1318 surf->cb_color_fmask_slice = color.fmask_slice;
1319
1320 surf->color_initialized = true;
1321 }
1322
1323 static void evergreen_init_depth_surface(struct r600_context *rctx,
1324 struct r600_surface *surf)
1325 {
1326 struct r600_screen *rscreen = rctx->screen;
1327 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1328 unsigned level = surf->base.u.tex.level;
1329 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1330 uint64_t offset;
1331 unsigned format, array_mode;
1332 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1333
1334
1335 format = r600_translate_dbformat(surf->base.format);
1336 assert(format != ~0);
1337
1338 offset = rtex->resource.gpu_address;
1339 offset += rtex->surface.u.legacy.level[level].offset;
1340
1341 switch (rtex->surface.u.legacy.level[level].mode) {
1342 case RADEON_SURF_MODE_2D:
1343 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1344 break;
1345 case RADEON_SURF_MODE_1D:
1346 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1347 default:
1348 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1349 break;
1350 }
1351 tile_split = rtex->surface.u.legacy.tile_split;
1352 macro_aspect = rtex->surface.u.legacy.mtilea;
1353 bankw = rtex->surface.u.legacy.bankw;
1354 bankh = rtex->surface.u.legacy.bankh;
1355 tile_split = eg_tile_split(tile_split);
1356 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1357 bankw = eg_bank_wh(bankw);
1358 bankh = eg_bank_wh(bankh);
1359 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1360 offset >>= 8;
1361
1362 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1363 S_028040_FORMAT(format) |
1364 S_028040_TILE_SPLIT(tile_split)|
1365 S_028040_NUM_BANKS(nbanks) |
1366 S_028040_BANK_WIDTH(bankw) |
1367 S_028040_BANK_HEIGHT(bankh) |
1368 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1369 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1370 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1371 }
1372
1373 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1374
1375 surf->db_depth_base = offset;
1376 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1377 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1378 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1379 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1380 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1381 levelinfo->nblk_y / 64 - 1);
1382
1383 if (rtex->surface.has_stencil) {
1384 uint64_t stencil_offset;
1385 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1386
1387 stile_split = eg_tile_split(stile_split);
1388
1389 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1390 stencil_offset += rtex->resource.gpu_address;
1391
1392 surf->db_stencil_base = stencil_offset >> 8;
1393 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1394 S_028044_TILE_SPLIT(stile_split);
1395 } else {
1396 surf->db_stencil_base = offset;
1397 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1398 * Older kernels are out of luck. */
1399 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1400 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1401 S_028044_FORMAT(V_028044_STENCIL_8);
1402 }
1403
1404 if (r600_htile_enabled(rtex, level)) {
1405 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1406 surf->db_htile_data_base = va >> 8;
1407 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1408 S_028ABC_HTILE_HEIGHT(1) |
1409 S_028ABC_FULL_CACHE(1);
1410 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1411 surf->db_preload_control = 0;
1412 }
1413
1414 surf->depth_initialized = true;
1415 }
1416
1417 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1418 const struct pipe_framebuffer_state *state)
1419 {
1420 struct r600_context *rctx = (struct r600_context *)ctx;
1421 struct r600_surface *surf;
1422 struct r600_texture *rtex;
1423 uint32_t i, log_samples;
1424
1425 /* Flush TC when changing the framebuffer state, because the only
1426 * client not using TC that can change textures is the framebuffer.
1427 * Other places don't typically have to flush TC.
1428 */
1429 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1430 R600_CONTEXT_FLUSH_AND_INV |
1431 R600_CONTEXT_FLUSH_AND_INV_CB |
1432 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1433 R600_CONTEXT_FLUSH_AND_INV_DB |
1434 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1435 R600_CONTEXT_INV_TEX_CACHE;
1436
1437 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1438
1439 /* Colorbuffers. */
1440 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1441 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1442 util_format_is_pure_integer(state->cbufs[0]->format);
1443 rctx->framebuffer.compressed_cb_mask = 0;
1444 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1445
1446 for (i = 0; i < state->nr_cbufs; i++) {
1447 surf = (struct r600_surface*)state->cbufs[i];
1448 if (!surf)
1449 continue;
1450
1451 rtex = (struct r600_texture*)surf->base.texture;
1452
1453 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1454
1455 if (!surf->color_initialized) {
1456 evergreen_init_color_surface(rctx, surf);
1457 }
1458
1459 if (!surf->export_16bpc) {
1460 rctx->framebuffer.export_16bpc = false;
1461 }
1462
1463 if (rtex->fmask.size) {
1464 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1465 }
1466 }
1467
1468 /* Update alpha-test state dependencies.
1469 * Alpha-test is done on the first colorbuffer only. */
1470 if (state->nr_cbufs) {
1471 bool alphatest_bypass = false;
1472 bool export_16bpc = true;
1473
1474 surf = (struct r600_surface*)state->cbufs[0];
1475 if (surf) {
1476 alphatest_bypass = surf->alphatest_bypass;
1477 export_16bpc = surf->export_16bpc;
1478 }
1479
1480 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1481 rctx->alphatest_state.bypass = alphatest_bypass;
1482 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1483 }
1484 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1485 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1486 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1487 }
1488 }
1489
1490 /* ZS buffer. */
1491 if (state->zsbuf) {
1492 surf = (struct r600_surface*)state->zsbuf;
1493
1494 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1495
1496 if (!surf->depth_initialized) {
1497 evergreen_init_depth_surface(rctx, surf);
1498 }
1499
1500 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1501 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1502 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1503 }
1504
1505 if (rctx->db_state.rsurf != surf) {
1506 rctx->db_state.rsurf = surf;
1507 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1508 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1509 }
1510 } else if (rctx->db_state.rsurf) {
1511 rctx->db_state.rsurf = NULL;
1512 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1513 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1514 }
1515
1516 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1517 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1518 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1519 }
1520
1521 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1522 rctx->alphatest_state.bypass = false;
1523 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1524 }
1525
1526 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1527 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1528 if ((rctx->b.chip_class == CAYMAN ||
1529 rctx->b.family == CHIP_RV770) &&
1530 rctx->db_misc_state.log_samples != log_samples) {
1531 rctx->db_misc_state.log_samples = log_samples;
1532 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1533 }
1534
1535
1536 /* Calculate the CS size. */
1537 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1538
1539 /* MSAA. */
1540 if (rctx->b.chip_class == EVERGREEN)
1541 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1542 else
1543 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1544
1545 /* Colorbuffers. */
1546 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1547 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1548 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1549
1550 /* ZS buffer. */
1551 if (state->zsbuf) {
1552 rctx->framebuffer.atom.num_dw += 24;
1553 rctx->framebuffer.atom.num_dw += 2;
1554 } else if (rctx->screen->b.info.drm_minor >= 18) {
1555 rctx->framebuffer.atom.num_dw += 4;
1556 }
1557
1558 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1559
1560 r600_set_sample_locations_constant_buffer(rctx);
1561 rctx->framebuffer.do_update_surf_dirtiness = true;
1562 }
1563
1564 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1565 {
1566 struct r600_context *rctx = (struct r600_context *)ctx;
1567
1568 if (rctx->ps_iter_samples == min_samples)
1569 return;
1570
1571 rctx->ps_iter_samples = min_samples;
1572 if (rctx->framebuffer.nr_samples > 1) {
1573 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1574 }
1575 }
1576
1577 /* 8xMSAA */
1578 static uint32_t sample_locs_8x[] = {
1579 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1580 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1581 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1582 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1583 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1584 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1585 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1586 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1587 };
1588 static unsigned max_dist_8x = 7;
1589
1590 static void evergreen_get_sample_position(struct pipe_context *ctx,
1591 unsigned sample_count,
1592 unsigned sample_index,
1593 float *out_value)
1594 {
1595 int offset, index;
1596 struct {
1597 int idx:4;
1598 } val;
1599 switch (sample_count) {
1600 case 1:
1601 default:
1602 out_value[0] = out_value[1] = 0.5;
1603 break;
1604 case 2:
1605 offset = 4 * (sample_index * 2);
1606 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1607 out_value[0] = (float)(val.idx + 8) / 16.0f;
1608 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1609 out_value[1] = (float)(val.idx + 8) / 16.0f;
1610 break;
1611 case 4:
1612 offset = 4 * (sample_index * 2);
1613 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1614 out_value[0] = (float)(val.idx + 8) / 16.0f;
1615 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1616 out_value[1] = (float)(val.idx + 8) / 16.0f;
1617 break;
1618 case 8:
1619 offset = 4 * (sample_index % 4 * 2);
1620 index = (sample_index / 4);
1621 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1622 out_value[0] = (float)(val.idx + 8) / 16.0f;
1623 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1624 out_value[1] = (float)(val.idx + 8) / 16.0f;
1625 break;
1626 }
1627 }
1628
1629 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1630 {
1631
1632 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1633 unsigned max_dist = 0;
1634
1635 switch (nr_samples) {
1636 default:
1637 nr_samples = 0;
1638 break;
1639 case 2:
1640 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1641 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1642 max_dist = eg_max_dist_2x;
1643 break;
1644 case 4:
1645 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1646 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1647 max_dist = eg_max_dist_4x;
1648 break;
1649 case 8:
1650 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1651 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1652 max_dist = max_dist_8x;
1653 break;
1654 }
1655
1656 if (nr_samples > 1) {
1657 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1658 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1659 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1660 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1661 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1662 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1663 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1664 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1665 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1666 } else {
1667 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1668 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1669 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1670 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1671 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1672 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1673 }
1674 }
1675
1676 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1677 {
1678 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1679 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1680 unsigned nr_cbufs = state->nr_cbufs;
1681 unsigned i, tl, br;
1682 struct r600_texture *tex = NULL;
1683 struct r600_surface *cb = NULL;
1684
1685 /* XXX support more colorbuffers once we need them */
1686 assert(nr_cbufs <= 8);
1687 if (nr_cbufs > 8)
1688 nr_cbufs = 8;
1689
1690 /* Colorbuffers. */
1691 for (i = 0; i < nr_cbufs; i++) {
1692 unsigned reloc, cmask_reloc;
1693
1694 cb = (struct r600_surface*)state->cbufs[i];
1695 if (!cb) {
1696 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1697 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1698 continue;
1699 }
1700
1701 tex = (struct r600_texture *)cb->base.texture;
1702 reloc = radeon_add_to_buffer_list(&rctx->b,
1703 &rctx->b.gfx,
1704 (struct r600_resource*)cb->base.texture,
1705 RADEON_USAGE_READWRITE,
1706 tex->resource.b.b.nr_samples > 1 ?
1707 RADEON_PRIO_COLOR_BUFFER_MSAA :
1708 RADEON_PRIO_COLOR_BUFFER);
1709
1710 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1711 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1712 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1713 RADEON_PRIO_CMASK);
1714 } else {
1715 cmask_reloc = reloc;
1716 }
1717
1718 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1719 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1720 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1721 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1722 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1723 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1724 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1725 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1726 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1727 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1728 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1729 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1730 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1731 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1732
1733 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1734 radeon_emit(cs, reloc);
1735
1736 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1737 radeon_emit(cs, reloc);
1738
1739 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1740 radeon_emit(cs, cmask_reloc);
1741
1742 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1743 radeon_emit(cs, reloc);
1744 }
1745 /* set CB_COLOR1_INFO for possible dual-src blending */
1746 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1747 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1748 cb->cb_color_info | tex->cb_color_info);
1749 i++;
1750 }
1751 for (; i < 8 ; i++)
1752 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1753 for (; i < 12; i++)
1754 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1755
1756 /* ZS buffer. */
1757 if (state->zsbuf) {
1758 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1759 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1760 &rctx->b.gfx,
1761 (struct r600_resource*)state->zsbuf->texture,
1762 RADEON_USAGE_READWRITE,
1763 zb->base.texture->nr_samples > 1 ?
1764 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1765 RADEON_PRIO_DEPTH_BUFFER);
1766
1767 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1768
1769 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1770 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1771 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1772 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1773 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1774 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1775 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1776 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1777 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1778
1779 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1780 radeon_emit(cs, reloc);
1781
1782 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1783 radeon_emit(cs, reloc);
1784
1785 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1786 radeon_emit(cs, reloc);
1787
1788 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1789 radeon_emit(cs, reloc);
1790 } else if (rctx->screen->b.info.drm_minor >= 18) {
1791 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1792 * Older kernels are out of luck. */
1793 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1794 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1795 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1796 }
1797
1798 /* Framebuffer dimensions. */
1799 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1800
1801 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1802 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1803 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1804
1805 if (rctx->b.chip_class == EVERGREEN) {
1806 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1807 } else {
1808 unsigned sc_mode_cntl_1 =
1809 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1810 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1811
1812 if (rctx->framebuffer.nr_samples > 1)
1813 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1814 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1815 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1816 }
1817 }
1818
1819 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1820 {
1821 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1822 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1823 float offset_units = state->offset_units;
1824 float offset_scale = state->offset_scale;
1825 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1826
1827 if (!state->offset_units_unscaled) {
1828 switch (state->zs_format) {
1829 case PIPE_FORMAT_Z24X8_UNORM:
1830 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1831 case PIPE_FORMAT_X8Z24_UNORM:
1832 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1833 offset_units *= 2.0f;
1834 pa_su_poly_offset_db_fmt_cntl =
1835 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1836 break;
1837 case PIPE_FORMAT_Z16_UNORM:
1838 offset_units *= 4.0f;
1839 pa_su_poly_offset_db_fmt_cntl =
1840 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1841 break;
1842 default:
1843 pa_su_poly_offset_db_fmt_cntl =
1844 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1845 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1846 }
1847 }
1848
1849 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1850 radeon_emit(cs, fui(offset_scale));
1851 radeon_emit(cs, fui(offset_units));
1852 radeon_emit(cs, fui(offset_scale));
1853 radeon_emit(cs, fui(offset_units));
1854
1855 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1856 pa_su_poly_offset_db_fmt_cntl);
1857 }
1858
1859 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1860 {
1861 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1862 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1863 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1864 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1865
1866 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1867 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1868 /* This must match the used export instructions exactly.
1869 * Other values may lead to undefined behavior and hangs.
1870 */
1871 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1872 }
1873
1874 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1875 {
1876 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1877 struct r600_db_state *a = (struct r600_db_state*)atom;
1878
1879 if (a->rsurf && a->rsurf->db_htile_surface) {
1880 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1881 unsigned reloc_idx;
1882
1883 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1884 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1885 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1886 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1887 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
1888 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1889 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1890 radeon_emit(cs, reloc_idx);
1891 } else {
1892 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1893 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1894 }
1895 }
1896
1897 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1898 {
1899 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1900 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1901 unsigned db_render_control = 0;
1902 unsigned db_count_control = 0;
1903 unsigned db_render_override =
1904 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1905 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1906
1907 if (rctx->b.num_occlusion_queries > 0 &&
1908 !a->occlusion_queries_disabled) {
1909 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1910 if (rctx->b.chip_class == CAYMAN) {
1911 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1912 }
1913 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1914 } else {
1915 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1916 }
1917
1918 /* This is to fix a lockup when hyperz and alpha test are enabled at
1919 * the same time somehow GPU get confuse on which order to pick for
1920 * z test
1921 */
1922 if (rctx->alphatest_state.sx_alpha_test_control)
1923 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1924
1925 if (a->flush_depthstencil_through_cb) {
1926 assert(a->copy_depth || a->copy_stencil);
1927
1928 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1929 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1930 S_028000_COPY_CENTROID(1) |
1931 S_028000_COPY_SAMPLE(a->copy_sample);
1932 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1933 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1934 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1935 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1936 }
1937 if (a->htile_clear) {
1938 /* FIXME we might want to disable cliprect here */
1939 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1940 }
1941
1942 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1943 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1944 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1945 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1946 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1947 }
1948
1949 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1950 struct r600_vertexbuf_state *state,
1951 unsigned resource_offset,
1952 unsigned pkt_flags)
1953 {
1954 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1955 uint32_t dirty_mask = state->dirty_mask;
1956
1957 while (dirty_mask) {
1958 struct pipe_vertex_buffer *vb;
1959 struct r600_resource *rbuffer;
1960 uint64_t va;
1961 unsigned buffer_index = u_bit_scan(&dirty_mask);
1962
1963 vb = &state->vb[buffer_index];
1964 rbuffer = (struct r600_resource*)vb->buffer.resource;
1965 assert(rbuffer);
1966
1967 va = rbuffer->gpu_address + vb->buffer_offset;
1968
1969 /* fetch resources start at index 992 */
1970 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1971 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1972 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1973 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1974 radeon_emit(cs, /* RESOURCEi_WORD2 */
1975 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1976 S_030008_STRIDE(vb->stride) |
1977 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1978 radeon_emit(cs, /* RESOURCEi_WORD3 */
1979 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1980 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1981 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1982 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1983 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1984 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1985 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1986 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1987
1988 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1989 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1990 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1991 }
1992 state->dirty_mask = 0;
1993 }
1994
1995 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1996 {
1997 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1998 }
1999
2000 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2001 {
2002 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2003 RADEON_CP_PACKET3_COMPUTE_MODE);
2004 }
2005
2006 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2007 struct r600_constbuf_state *state,
2008 unsigned buffer_id_base,
2009 unsigned reg_alu_constbuf_size,
2010 unsigned reg_alu_const_cache,
2011 unsigned pkt_flags)
2012 {
2013 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2014 uint32_t dirty_mask = state->dirty_mask;
2015
2016 while (dirty_mask) {
2017 struct pipe_constant_buffer *cb;
2018 struct r600_resource *rbuffer;
2019 uint64_t va;
2020 unsigned buffer_index = ffs(dirty_mask) - 1;
2021 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2022
2023 cb = &state->cb[buffer_index];
2024 rbuffer = (struct r600_resource*)cb->buffer;
2025 assert(rbuffer);
2026
2027 va = rbuffer->gpu_address + cb->buffer_offset;
2028
2029 if (!gs_ring_buffer) {
2030 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2031 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2032 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2033 pkt_flags);
2034 }
2035
2036 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2037 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2038 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2039
2040 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2041 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2042 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2043 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2044 radeon_emit(cs, /* RESOURCEi_WORD2 */
2045 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2046 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2047 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2048 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2049 radeon_emit(cs, /* RESOURCEi_WORD3 */
2050 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2051 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2052 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2053 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2054 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2055 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2056 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2057 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2058 radeon_emit(cs, /* RESOURCEi_WORD7 */
2059 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2060
2061 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2062 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2063 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2064
2065 dirty_mask &= ~(1 << buffer_index);
2066 }
2067 state->dirty_mask = 0;
2068 }
2069
2070 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2071 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2072 {
2073 if (rctx->vs_shader->current->shader.vs_as_ls) {
2074 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2075 EG_FETCH_CONSTANTS_OFFSET_LS,
2076 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2077 R_028F40_ALU_CONST_CACHE_LS_0,
2078 0 /* PKT3 flags */);
2079 } else {
2080 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2081 EG_FETCH_CONSTANTS_OFFSET_VS,
2082 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2083 R_028980_ALU_CONST_CACHE_VS_0,
2084 0 /* PKT3 flags */);
2085 }
2086 }
2087
2088 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2089 {
2090 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2091 EG_FETCH_CONSTANTS_OFFSET_GS,
2092 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2093 R_0289C0_ALU_CONST_CACHE_GS_0,
2094 0 /* PKT3 flags */);
2095 }
2096
2097 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2098 {
2099 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2100 EG_FETCH_CONSTANTS_OFFSET_PS,
2101 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2102 R_028940_ALU_CONST_CACHE_PS_0,
2103 0 /* PKT3 flags */);
2104 }
2105
2106 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2107 {
2108 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2109 EG_FETCH_CONSTANTS_OFFSET_CS,
2110 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2111 R_028F40_ALU_CONST_CACHE_LS_0,
2112 RADEON_CP_PACKET3_COMPUTE_MODE);
2113 }
2114
2115 /* tes constants can be emitted to VS or ES - which are common */
2116 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2117 {
2118 if (!rctx->tes_shader)
2119 return;
2120 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2121 EG_FETCH_CONSTANTS_OFFSET_VS,
2122 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2123 R_028980_ALU_CONST_CACHE_VS_0,
2124 0);
2125 }
2126
2127 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2128 {
2129 if (!rctx->tes_shader)
2130 return;
2131 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2132 EG_FETCH_CONSTANTS_OFFSET_HS,
2133 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2134 R_028F00_ALU_CONST_CACHE_HS_0,
2135 0);
2136 }
2137
2138 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2139 struct r600_samplerview_state *state,
2140 unsigned resource_id_base, unsigned pkt_flags)
2141 {
2142 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2143 uint32_t dirty_mask = state->dirty_mask;
2144
2145 while (dirty_mask) {
2146 struct r600_pipe_sampler_view *rview;
2147 unsigned resource_index = u_bit_scan(&dirty_mask);
2148 unsigned reloc;
2149
2150 rview = state->views[resource_index];
2151 assert(rview);
2152
2153 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2154 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2155 radeon_emit_array(cs, rview->tex_resource_words, 8);
2156
2157 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2158 RADEON_USAGE_READ,
2159 r600_get_sampler_view_priority(rview->tex_resource));
2160 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2161 radeon_emit(cs, reloc);
2162
2163 if (!rview->skip_mip_address_reloc) {
2164 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2165 radeon_emit(cs, reloc);
2166 }
2167 }
2168 state->dirty_mask = 0;
2169 }
2170
2171 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2172 {
2173 if (rctx->vs_shader->current->shader.vs_as_ls) {
2174 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2175 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2176 } else {
2177 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2178 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2179 }
2180 }
2181
2182 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2183 {
2184 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2185 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2186 }
2187
2188 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2189 {
2190 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2191 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2192 }
2193
2194 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2195 {
2196 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2197 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2198 }
2199
2200 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2201 {
2202 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2203 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2204 }
2205
2206 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2207 {
2208 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2209 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2210 }
2211
2212 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2213 struct r600_textures_info *texinfo,
2214 unsigned resource_id_base,
2215 unsigned border_index_reg,
2216 unsigned pkt_flags)
2217 {
2218 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2219 uint32_t dirty_mask = texinfo->states.dirty_mask;
2220
2221 while (dirty_mask) {
2222 struct r600_pipe_sampler_state *rstate;
2223 unsigned i = u_bit_scan(&dirty_mask);
2224
2225 rstate = texinfo->states.states[i];
2226 assert(rstate);
2227
2228 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2229 radeon_emit(cs, (resource_id_base + i) * 3);
2230 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2231
2232 if (rstate->border_color_use) {
2233 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2234 radeon_emit(cs, i);
2235 radeon_emit_array(cs, rstate->border_color.ui, 4);
2236 }
2237 }
2238 texinfo->states.dirty_mask = 0;
2239 }
2240
2241 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2242 {
2243 if (rctx->vs_shader->current->shader.vs_as_ls) {
2244 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2245 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2246 } else {
2247 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2248 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2249 }
2250 }
2251
2252 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2253 {
2254 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2255 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2256 }
2257
2258 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2259 {
2260 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2261 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2262 }
2263
2264 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2265 {
2266 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2267 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2268 }
2269
2270 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2271 {
2272 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2273 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2274 }
2275
2276 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2277 {
2278 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2279 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2280 RADEON_CP_PACKET3_COMPUTE_MODE);
2281 }
2282
2283 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2284 {
2285 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2286 uint8_t mask = s->sample_mask;
2287
2288 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2289 mask | (mask << 8) | (mask << 16) | (mask << 24));
2290 }
2291
2292 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2293 {
2294 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2295 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2296 uint16_t mask = s->sample_mask;
2297
2298 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2299 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2300 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2301 }
2302
2303 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2304 {
2305 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2306 struct r600_cso_state *state = (struct r600_cso_state*)a;
2307 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2308
2309 if (!shader)
2310 return;
2311
2312 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2313 (shader->buffer->gpu_address + shader->offset) >> 8);
2314 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2315 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2316 RADEON_USAGE_READ,
2317 RADEON_PRIO_SHADER_BINARY));
2318 }
2319
2320 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2321 {
2322 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2323 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2324
2325 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2326
2327 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2328 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2329 primid = 1;
2330 }
2331
2332 if (state->geom_enable) {
2333 uint32_t cut_val;
2334
2335 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2336 cut_val = V_028A40_GS_CUT_128;
2337 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2338 cut_val = V_028A40_GS_CUT_256;
2339 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2340 cut_val = V_028A40_GS_CUT_512;
2341 else
2342 cut_val = V_028A40_GS_CUT_1024;
2343
2344 v = S_028B54_GS_EN(1) |
2345 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2346 if (!rctx->tes_shader)
2347 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2348
2349 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2350 S_028A40_CUT_MODE(cut_val);
2351
2352 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2353 primid = 1;
2354 }
2355
2356 if (rctx->tes_shader) {
2357 uint32_t type, partitioning, topology;
2358 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2359 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2360 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2361 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2362 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2363 switch (tes_prim_mode) {
2364 case PIPE_PRIM_LINES:
2365 type = V_028B6C_TESS_ISOLINE;
2366 break;
2367 case PIPE_PRIM_TRIANGLES:
2368 type = V_028B6C_TESS_TRIANGLE;
2369 break;
2370 case PIPE_PRIM_QUADS:
2371 type = V_028B6C_TESS_QUAD;
2372 break;
2373 default:
2374 assert(0);
2375 return;
2376 }
2377
2378 switch (tes_spacing) {
2379 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2380 partitioning = V_028B6C_PART_FRAC_ODD;
2381 break;
2382 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2383 partitioning = V_028B6C_PART_FRAC_EVEN;
2384 break;
2385 case PIPE_TESS_SPACING_EQUAL:
2386 partitioning = V_028B6C_PART_INTEGER;
2387 break;
2388 default:
2389 assert(0);
2390 return;
2391 }
2392
2393 if (tes_point_mode)
2394 topology = V_028B6C_OUTPUT_POINT;
2395 else if (tes_prim_mode == PIPE_PRIM_LINES)
2396 topology = V_028B6C_OUTPUT_LINE;
2397 else if (tes_vertex_order_cw)
2398 /* XXX follow radeonsi and invert */
2399 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2400 else
2401 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2402
2403 tf_param = S_028B6C_TYPE(type) |
2404 S_028B6C_PARTITIONING(partitioning) |
2405 S_028B6C_TOPOLOGY(topology);
2406 }
2407
2408 if (rctx->tes_shader) {
2409 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2410 S_028B54_HS_EN(1);
2411 if (!state->geom_enable)
2412 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2413 else
2414 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2415 }
2416
2417 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2418 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2419 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2420 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2421 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2422 }
2423
2424 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2425 {
2426 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2427 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2428 struct r600_resource *rbuffer;
2429
2430 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2431 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2432 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2433
2434 if (state->enable) {
2435 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2436 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2437 rbuffer->gpu_address >> 8);
2438 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2439 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2440 RADEON_USAGE_READWRITE,
2441 RADEON_PRIO_SHADER_RINGS));
2442 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2443 state->esgs_ring.buffer_size >> 8);
2444
2445 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2446 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2447 rbuffer->gpu_address >> 8);
2448 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2449 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2450 RADEON_USAGE_READWRITE,
2451 RADEON_PRIO_SHADER_RINGS));
2452 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2453 state->gsvs_ring.buffer_size >> 8);
2454 } else {
2455 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2456 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2457 }
2458
2459 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2460 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2461 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2462 }
2463
2464 void cayman_init_common_regs(struct r600_command_buffer *cb,
2465 enum chip_class ctx_chip_class,
2466 enum radeon_family ctx_family,
2467 int ctx_drm_minor)
2468 {
2469 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2470 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2471 /* always set the temp clauses */
2472 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2473
2474 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2475 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2476 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2477
2478 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2479
2480 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2481 r600_store_value(cb, 0);
2482 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2483
2484 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2485 }
2486
2487 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2488 {
2489 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2490 int i;
2491
2492 r600_init_command_buffer(cb, 338);
2493
2494 /* This must be first. */
2495 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2496 r600_store_value(cb, 0x80000000);
2497 r600_store_value(cb, 0x80000000);
2498
2499 /* We're setting config registers here. */
2500 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2501 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2502
2503 /* This enables pipeline stat & streamout queries.
2504 * They are only disabled by blits.
2505 */
2506 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2507 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2508
2509 cayman_init_common_regs(cb, rctx->b.chip_class,
2510 rctx->b.family, rctx->screen->b.info.drm_minor);
2511
2512 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2513 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2514
2515 /* remove LS/HS from one SIMD for hw workaround */
2516 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2517 r600_store_value(cb, 0xffffffff);
2518 r600_store_value(cb, 0xffffffff);
2519 r600_store_value(cb, 0xfffffffe);
2520
2521 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2522 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2523 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2524 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2525 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2526 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2527 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2528
2529 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2530 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2531 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2532 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2533 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2534
2535 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2536 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2537 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2538 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2539 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2540 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2541 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2542 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2543 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2544 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2545 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2546 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2547 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2548 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2549
2550 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2551
2552 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2553
2554 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2555 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2556 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2557
2558 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2559 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2560 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2561
2562 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2563
2564 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2565 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2566 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2567
2568 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2569
2570 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2571
2572 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2573
2574 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2575 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2576 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2577 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2578
2579 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2580 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2581
2582 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2583 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2584
2585 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2586 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2587 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2588
2589 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2590 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2591 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2592
2593 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2594 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2595 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2596 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2597 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2598 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2599
2600 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2601
2602 /* to avoid GPU doing any preloading of constant from random address */
2603 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2604 for (i = 0; i < 16; i++)
2605 r600_store_value(cb, 0);
2606
2607 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2608 for (i = 0; i < 16; i++)
2609 r600_store_value(cb, 0);
2610
2611 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2612 for (i = 0; i < 16; i++)
2613 r600_store_value(cb, 0);
2614
2615 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2616 for (i = 0; i < 16; i++)
2617 r600_store_value(cb, 0);
2618
2619 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2620 for (i = 0; i < 16; i++)
2621 r600_store_value(cb, 0);
2622
2623 if (rctx->screen->b.has_streamout) {
2624 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2625 }
2626
2627 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2628 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2629 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2630 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2631 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2632 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2633
2634 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2635 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2636 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2637 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2638 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2639 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2640 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2641 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2642 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2643 }
2644
2645 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2646 enum chip_class ctx_chip_class,
2647 enum radeon_family ctx_family,
2648 int ctx_drm_minor)
2649 {
2650 int ps_prio;
2651 int vs_prio;
2652 int gs_prio;
2653 int es_prio;
2654
2655 int hs_prio;
2656 int cs_prio;
2657 int ls_prio;
2658
2659 unsigned tmp;
2660
2661 ps_prio = 0;
2662 vs_prio = 1;
2663 gs_prio = 2;
2664 es_prio = 3;
2665 hs_prio = 3;
2666 ls_prio = 3;
2667 cs_prio = 0;
2668
2669 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2670 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2671 rctx->r6xx_num_clause_temp_gprs = 4;
2672 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2673 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2674 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2675 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2676
2677 tmp = 0;
2678 switch (ctx_family) {
2679 case CHIP_CEDAR:
2680 case CHIP_PALM:
2681 case CHIP_SUMO:
2682 case CHIP_SUMO2:
2683 case CHIP_CAICOS:
2684 break;
2685 default:
2686 tmp |= S_008C00_VC_ENABLE(1);
2687 break;
2688 }
2689 tmp |= S_008C00_EXPORT_SRC_C(1);
2690 tmp |= S_008C00_CS_PRIO(cs_prio);
2691 tmp |= S_008C00_LS_PRIO(ls_prio);
2692 tmp |= S_008C00_HS_PRIO(hs_prio);
2693 tmp |= S_008C00_PS_PRIO(ps_prio);
2694 tmp |= S_008C00_VS_PRIO(vs_prio);
2695 tmp |= S_008C00_GS_PRIO(gs_prio);
2696 tmp |= S_008C00_ES_PRIO(es_prio);
2697
2698 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2699 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2700
2701 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2702 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2703 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2704
2705 /* The cs checker requires this register to be set. */
2706 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2707
2708 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2709 r600_store_value(cb, 0);
2710 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2711
2712 return;
2713 }
2714
2715 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2716 {
2717 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2718 int num_ps_threads;
2719 int num_vs_threads;
2720 int num_gs_threads;
2721 int num_es_threads;
2722 int num_hs_threads;
2723 int num_ls_threads;
2724
2725 int num_ps_stack_entries;
2726 int num_vs_stack_entries;
2727 int num_gs_stack_entries;
2728 int num_es_stack_entries;
2729 int num_hs_stack_entries;
2730 int num_ls_stack_entries;
2731 enum radeon_family family;
2732 unsigned tmp, i;
2733
2734 if (rctx->b.chip_class == CAYMAN) {
2735 cayman_init_atom_start_cs(rctx);
2736 return;
2737 }
2738
2739 r600_init_command_buffer(cb, 338);
2740
2741 /* This must be first. */
2742 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2743 r600_store_value(cb, 0x80000000);
2744 r600_store_value(cb, 0x80000000);
2745
2746 /* We're setting config registers here. */
2747 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2748 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2749
2750 /* This enables pipeline stat & streamout queries.
2751 * They are only disabled by blits.
2752 */
2753 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2754 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2755
2756 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2757 rctx->b.family, rctx->screen->b.info.drm_minor);
2758
2759 family = rctx->b.family;
2760 switch (family) {
2761 case CHIP_CEDAR:
2762 default:
2763 num_ps_threads = 96;
2764 num_vs_threads = 16;
2765 num_gs_threads = 16;
2766 num_es_threads = 16;
2767 num_hs_threads = 16;
2768 num_ls_threads = 16;
2769 num_ps_stack_entries = 42;
2770 num_vs_stack_entries = 42;
2771 num_gs_stack_entries = 42;
2772 num_es_stack_entries = 42;
2773 num_hs_stack_entries = 42;
2774 num_ls_stack_entries = 42;
2775 break;
2776 case CHIP_REDWOOD:
2777 num_ps_threads = 128;
2778 num_vs_threads = 20;
2779 num_gs_threads = 20;
2780 num_es_threads = 20;
2781 num_hs_threads = 20;
2782 num_ls_threads = 20;
2783 num_ps_stack_entries = 42;
2784 num_vs_stack_entries = 42;
2785 num_gs_stack_entries = 42;
2786 num_es_stack_entries = 42;
2787 num_hs_stack_entries = 42;
2788 num_ls_stack_entries = 42;
2789 break;
2790 case CHIP_JUNIPER:
2791 num_ps_threads = 128;
2792 num_vs_threads = 20;
2793 num_gs_threads = 20;
2794 num_es_threads = 20;
2795 num_hs_threads = 20;
2796 num_ls_threads = 20;
2797 num_ps_stack_entries = 85;
2798 num_vs_stack_entries = 85;
2799 num_gs_stack_entries = 85;
2800 num_es_stack_entries = 85;
2801 num_hs_stack_entries = 85;
2802 num_ls_stack_entries = 85;
2803 break;
2804 case CHIP_CYPRESS:
2805 case CHIP_HEMLOCK:
2806 num_ps_threads = 128;
2807 num_vs_threads = 20;
2808 num_gs_threads = 20;
2809 num_es_threads = 20;
2810 num_hs_threads = 20;
2811 num_ls_threads = 20;
2812 num_ps_stack_entries = 85;
2813 num_vs_stack_entries = 85;
2814 num_gs_stack_entries = 85;
2815 num_es_stack_entries = 85;
2816 num_hs_stack_entries = 85;
2817 num_ls_stack_entries = 85;
2818 break;
2819 case CHIP_PALM:
2820 num_ps_threads = 96;
2821 num_vs_threads = 16;
2822 num_gs_threads = 16;
2823 num_es_threads = 16;
2824 num_hs_threads = 16;
2825 num_ls_threads = 16;
2826 num_ps_stack_entries = 42;
2827 num_vs_stack_entries = 42;
2828 num_gs_stack_entries = 42;
2829 num_es_stack_entries = 42;
2830 num_hs_stack_entries = 42;
2831 num_ls_stack_entries = 42;
2832 break;
2833 case CHIP_SUMO:
2834 num_ps_threads = 96;
2835 num_vs_threads = 25;
2836 num_gs_threads = 25;
2837 num_es_threads = 25;
2838 num_hs_threads = 16;
2839 num_ls_threads = 16;
2840 num_ps_stack_entries = 42;
2841 num_vs_stack_entries = 42;
2842 num_gs_stack_entries = 42;
2843 num_es_stack_entries = 42;
2844 num_hs_stack_entries = 42;
2845 num_ls_stack_entries = 42;
2846 break;
2847 case CHIP_SUMO2:
2848 num_ps_threads = 96;
2849 num_vs_threads = 25;
2850 num_gs_threads = 25;
2851 num_es_threads = 25;
2852 num_hs_threads = 16;
2853 num_ls_threads = 16;
2854 num_ps_stack_entries = 85;
2855 num_vs_stack_entries = 85;
2856 num_gs_stack_entries = 85;
2857 num_es_stack_entries = 85;
2858 num_hs_stack_entries = 85;
2859 num_ls_stack_entries = 85;
2860 break;
2861 case CHIP_BARTS:
2862 num_ps_threads = 128;
2863 num_vs_threads = 20;
2864 num_gs_threads = 20;
2865 num_es_threads = 20;
2866 num_hs_threads = 20;
2867 num_ls_threads = 20;
2868 num_ps_stack_entries = 85;
2869 num_vs_stack_entries = 85;
2870 num_gs_stack_entries = 85;
2871 num_es_stack_entries = 85;
2872 num_hs_stack_entries = 85;
2873 num_ls_stack_entries = 85;
2874 break;
2875 case CHIP_TURKS:
2876 num_ps_threads = 128;
2877 num_vs_threads = 20;
2878 num_gs_threads = 20;
2879 num_es_threads = 20;
2880 num_hs_threads = 20;
2881 num_ls_threads = 20;
2882 num_ps_stack_entries = 42;
2883 num_vs_stack_entries = 42;
2884 num_gs_stack_entries = 42;
2885 num_es_stack_entries = 42;
2886 num_hs_stack_entries = 42;
2887 num_ls_stack_entries = 42;
2888 break;
2889 case CHIP_CAICOS:
2890 num_ps_threads = 96;
2891 num_vs_threads = 10;
2892 num_gs_threads = 10;
2893 num_es_threads = 10;
2894 num_hs_threads = 10;
2895 num_ls_threads = 10;
2896 num_ps_stack_entries = 42;
2897 num_vs_stack_entries = 42;
2898 num_gs_stack_entries = 42;
2899 num_es_stack_entries = 42;
2900 num_hs_stack_entries = 42;
2901 num_ls_stack_entries = 42;
2902 break;
2903 }
2904
2905 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2906 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2907 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2908 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2909
2910 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2911 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2912
2913 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2914 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2915 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2916
2917 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2918 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2919 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2920
2921 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2922 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2923 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2924
2925 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2926 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2927 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2928
2929 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2930 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2931
2932 /* remove LS/HS from one SIMD for hw workaround */
2933 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2934 r600_store_value(cb, 0xffffffff);
2935 r600_store_value(cb, 0xffffffff);
2936 r600_store_value(cb, 0xfffffffe);
2937
2938 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2939 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2940
2941 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2942 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2943 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2944 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2945 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2946 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2947 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2948
2949 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2950 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2951 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2952 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2953 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2954
2955 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2956 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2957 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2958 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2959 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2960 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2961 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2962 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2963 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2964 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2965 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2966 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2967 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2968 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2969
2970 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2971
2972 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2973
2974 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2975 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2976 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2977
2978 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2979
2980 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2981
2982 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2983 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2984 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2985
2986 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2987 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2988
2989 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2990 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2991 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2992 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2993
2994 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2995 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2996 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2997
2998 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2999 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3000 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3001
3002 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3003 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3004 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3005 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3006 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3007 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3008 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3009
3010 /* to avoid GPU doing any preloading of constant from random address */
3011 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3012 for (i = 0; i < 16; i++)
3013 r600_store_value(cb, 0);
3014
3015 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3016 for (i = 0; i < 16; i++)
3017 r600_store_value(cb, 0);
3018
3019 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3020 for (i = 0; i < 16; i++)
3021 r600_store_value(cb, 0);
3022
3023 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3024 for (i = 0; i < 16; i++)
3025 r600_store_value(cb, 0);
3026
3027 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3028 for (i = 0; i < 16; i++)
3029 r600_store_value(cb, 0);
3030
3031 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3032
3033 if (rctx->screen->b.has_streamout) {
3034 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3035 }
3036
3037 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3038 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3039 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3040 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3041 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3042 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3043
3044 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3045 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3046 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3047
3048 if (rctx->b.family == CHIP_CAICOS) {
3049 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3050 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3051 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3052 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3053 } else {
3054 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3055 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3056 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3057 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3058 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3059 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3060 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3061 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3062 }
3063
3064 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3065 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3066 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3067 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3068 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3069 }
3070
3071 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3072 {
3073 struct r600_context *rctx = (struct r600_context *)ctx;
3074 struct r600_command_buffer *cb = &shader->command_buffer;
3075 struct r600_shader *rshader = &shader->shader;
3076 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3077 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3078 int ninterp = 0;
3079 boolean have_perspective = FALSE, have_linear = FALSE;
3080 static const unsigned spi_baryc_enable_bit[6] = {
3081 S_0286E0_PERSP_SAMPLE_ENA(1),
3082 S_0286E0_PERSP_CENTER_ENA(1),
3083 S_0286E0_PERSP_CENTROID_ENA(1),
3084 S_0286E0_LINEAR_SAMPLE_ENA(1),
3085 S_0286E0_LINEAR_CENTER_ENA(1),
3086 S_0286E0_LINEAR_CENTROID_ENA(1)
3087 };
3088 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3089 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3090 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3091 uint32_t spi_ps_input_cntl[32];
3092
3093 if (!cb->buf) {
3094 r600_init_command_buffer(cb, 64);
3095 } else {
3096 cb->num_dw = 0;
3097 }
3098
3099 for (i = 0; i < rshader->ninput; i++) {
3100 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3101 POSITION goes via GPRs from the SC so isn't counted */
3102 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3103 pos_index = i;
3104 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3105 if (face_index == -1)
3106 face_index = i;
3107 }
3108 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3109 if (face_index == -1)
3110 face_index = i; /* lives in same register, same enable bit */
3111 }
3112 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3113 fixed_pt_position_index = i;
3114 }
3115 else {
3116 ninterp++;
3117 int k = eg_get_interpolator_index(
3118 rshader->input[i].interpolate,
3119 rshader->input[i].interpolate_location);
3120 if (k >= 0) {
3121 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3122 have_perspective |= k < 3;
3123 have_linear |= !(k < 3);
3124 }
3125 }
3126
3127 sid = rshader->input[i].spi_sid;
3128
3129 if (sid) {
3130 tmp = S_028644_SEMANTIC(sid);
3131
3132 /* D3D 9 behaviour. GL is undefined */
3133 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3134 tmp |= S_028644_DEFAULT_VAL(3);
3135
3136 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3137 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3138 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3139 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3140 tmp |= S_028644_FLAT_SHADE(1);
3141 }
3142
3143 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3144 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3145 tmp |= S_028644_PT_SPRITE_TEX(1);
3146 }
3147
3148 spi_ps_input_cntl[num++] = tmp;
3149 }
3150 }
3151
3152 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3153 r600_store_array(cb, num, spi_ps_input_cntl);
3154
3155 for (i = 0; i < rshader->noutput; i++) {
3156 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3157 z_export = 1;
3158 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3159 stencil_export = 1;
3160 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3161 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3162 mask_export = 1;
3163 }
3164 if (rshader->uses_kill)
3165 db_shader_control |= S_02880C_KILL_ENABLE(1);
3166
3167 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3168 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3169 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3170
3171 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
3172 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
3173
3174 switch (rshader->ps_conservative_z) {
3175 default: /* fall through */
3176 case TGSI_FS_DEPTH_LAYOUT_ANY:
3177 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3178 break;
3179 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3180 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3181 break;
3182 case TGSI_FS_DEPTH_LAYOUT_LESS:
3183 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3184 break;
3185 }
3186
3187 exports_ps = 0;
3188 for (i = 0; i < rshader->noutput; i++) {
3189 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3190 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3191 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3192 exports_ps |= 1;
3193 }
3194
3195 num_cout = rshader->nr_ps_color_exports;
3196
3197 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3198 if (!exports_ps) {
3199 /* always at least export 1 component per pixel */
3200 exports_ps = 2;
3201 }
3202 shader->nr_ps_color_outputs = num_cout;
3203 if (ninterp == 0) {
3204 ninterp = 1;
3205 have_perspective = TRUE;
3206 }
3207 if (!spi_baryc_cntl)
3208 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3209
3210 if (!have_perspective && !have_linear)
3211 have_perspective = TRUE;
3212
3213 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3214 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3215 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3216 spi_input_z = 0;
3217 if (pos_index != -1) {
3218 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3219 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3220 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3221 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3222 }
3223
3224 spi_ps_in_control_1 = 0;
3225 if (face_index != -1) {
3226 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3227 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3228 }
3229 if (fixed_pt_position_index != -1) {
3230 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3231 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3232 }
3233
3234 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3235 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3236 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3237
3238 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3239 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3240 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3241
3242 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3243 r600_store_value(cb, shader->bo->gpu_address >> 8);
3244 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3245 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3246 S_028844_PRIME_CACHE_ON_DRAW(1) |
3247 S_028844_STACK_SIZE(rshader->bc.nstack));
3248 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3249
3250 shader->db_shader_control = db_shader_control;
3251 shader->ps_depth_export = z_export | stencil_export | mask_export;
3252
3253 shader->sprite_coord_enable = sprite_coord_enable;
3254 if (rctx->rasterizer)
3255 shader->flatshade = rctx->rasterizer->flatshade;
3256 }
3257
3258 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3259 {
3260 struct r600_command_buffer *cb = &shader->command_buffer;
3261 struct r600_shader *rshader = &shader->shader;
3262
3263 r600_init_command_buffer(cb, 32);
3264
3265 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3266 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3267 S_028890_STACK_SIZE(rshader->bc.nstack));
3268 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3269 shader->bo->gpu_address >> 8);
3270 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3271 }
3272
3273 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3274 {
3275 struct r600_context *rctx = (struct r600_context *)ctx;
3276 struct r600_command_buffer *cb = &shader->command_buffer;
3277 struct r600_shader *rshader = &shader->shader;
3278 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3279 unsigned gsvs_itemsizes[4] = {
3280 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3281 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3282 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3283 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3284 };
3285
3286 r600_init_command_buffer(cb, 64);
3287
3288 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3289
3290
3291 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3292 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3293 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3294 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3295
3296 if (rctx->screen->b.info.drm_minor >= 35) {
3297 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3298 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3299 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3300 }
3301 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3302 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3303 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3304 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3305 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3306
3307 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3308 (rshader->ring_item_sizes[0]) >> 2);
3309
3310 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3311 gsvs_itemsizes[0] +
3312 gsvs_itemsizes[1] +
3313 gsvs_itemsizes[2] +
3314 gsvs_itemsizes[3]);
3315
3316 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3317 r600_store_value(cb, gsvs_itemsizes[0]);
3318 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3319 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3320
3321 /* FIXME calculate these values somehow ??? */
3322 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3323 r600_store_value(cb, 0x80); /* GS_PER_ES */
3324 r600_store_value(cb, 0x100); /* ES_PER_GS */
3325 r600_store_value(cb, 0x2); /* GS_PER_VS */
3326
3327 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3328 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3329 S_028878_STACK_SIZE(rshader->bc.nstack));
3330 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3331 shader->bo->gpu_address >> 8);
3332 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3333 }
3334
3335
3336 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3337 {
3338 struct r600_command_buffer *cb = &shader->command_buffer;
3339 struct r600_shader *rshader = &shader->shader;
3340 unsigned spi_vs_out_id[10] = {};
3341 unsigned i, tmp, nparams = 0;
3342
3343 for (i = 0; i < rshader->noutput; i++) {
3344 if (rshader->output[i].spi_sid) {
3345 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3346 spi_vs_out_id[nparams / 4] |= tmp;
3347 nparams++;
3348 }
3349 }
3350
3351 r600_init_command_buffer(cb, 32);
3352
3353 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3354 for (i = 0; i < 10; i++) {
3355 r600_store_value(cb, spi_vs_out_id[i]);
3356 }
3357
3358 /* Certain attributes (position, psize, etc.) don't count as params.
3359 * VS is required to export at least one param and r600_shader_from_tgsi()
3360 * takes care of adding a dummy export.
3361 */
3362 if (nparams < 1)
3363 nparams = 1;
3364
3365 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3366 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3367 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3368 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3369 S_028860_STACK_SIZE(rshader->bc.nstack));
3370 if (rshader->vs_position_window_space) {
3371 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3372 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3373 } else {
3374 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3375 S_028818_VTX_W0_FMT(1) |
3376 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3377 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3378 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3379
3380 }
3381 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3382 shader->bo->gpu_address >> 8);
3383 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3384
3385 shader->pa_cl_vs_out_cntl =
3386 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3387 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3388 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3389 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3390 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3391 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3392 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3393 }
3394
3395 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3396 {
3397 struct r600_command_buffer *cb = &shader->command_buffer;
3398 struct r600_shader *rshader = &shader->shader;
3399
3400 r600_init_command_buffer(cb, 32);
3401 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3402 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3403 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3404 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3405 shader->bo->gpu_address >> 8);
3406 }
3407
3408 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3409 {
3410 struct r600_command_buffer *cb = &shader->command_buffer;
3411 struct r600_shader *rshader = &shader->shader;
3412
3413 r600_init_command_buffer(cb, 32);
3414 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3415 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3416 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3417 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3418 shader->bo->gpu_address >> 8);
3419 }
3420 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3421 {
3422 struct pipe_blend_state blend;
3423
3424 memset(&blend, 0, sizeof(blend));
3425 blend.independent_blend_enable = true;
3426 blend.rt[0].colormask = 0xf;
3427 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3428 }
3429
3430 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3431 {
3432 struct pipe_blend_state blend;
3433 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3434 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3435
3436 memset(&blend, 0, sizeof(blend));
3437 blend.independent_blend_enable = true;
3438 blend.rt[0].colormask = 0xf;
3439 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3440 }
3441
3442 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3443 {
3444 struct pipe_blend_state blend;
3445 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3446
3447 memset(&blend, 0, sizeof(blend));
3448 blend.independent_blend_enable = true;
3449 blend.rt[0].colormask = 0xf;
3450 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3451 }
3452
3453 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3454 {
3455 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3456
3457 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3458 }
3459
3460 void evergreen_update_db_shader_control(struct r600_context * rctx)
3461 {
3462 bool dual_export;
3463 unsigned db_shader_control;
3464
3465 if (!rctx->ps_shader) {
3466 return;
3467 }
3468
3469 dual_export = rctx->framebuffer.export_16bpc &&
3470 !rctx->ps_shader->current->ps_depth_export;
3471
3472 db_shader_control = rctx->ps_shader->current->db_shader_control |
3473 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3474 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3475 V_02880C_EXPORT_DB_FULL) |
3476 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3477
3478 /* When alpha test is enabled we can't trust the hw to make the proper
3479 * decision on the order in which ztest should be run related to fragment
3480 * shader execution.
3481 *
3482 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3483 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3484 * execution and thus after alpha test so if discarded by the alpha test
3485 * the z value is not written.
3486 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3487 * get a hang unless you flush the DB in between. For now just use
3488 * LATE_Z.
3489 */
3490 if (rctx->alphatest_state.sx_alpha_test_control) {
3491 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3492 } else {
3493 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3494 }
3495
3496 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3497 rctx->db_misc_state.db_shader_control = db_shader_control;
3498 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3499 }
3500 }
3501
3502 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3503 struct pipe_resource *dst,
3504 unsigned dst_level,
3505 unsigned dst_x,
3506 unsigned dst_y,
3507 unsigned dst_z,
3508 struct pipe_resource *src,
3509 unsigned src_level,
3510 unsigned src_x,
3511 unsigned src_y,
3512 unsigned src_z,
3513 unsigned copy_height,
3514 unsigned pitch,
3515 unsigned bpp)
3516 {
3517 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3518 struct r600_texture *rsrc = (struct r600_texture*)src;
3519 struct r600_texture *rdst = (struct r600_texture*)dst;
3520 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3521 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3522 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3523 uint64_t base, addr;
3524
3525 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3526 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3527 assert(dst_mode != src_mode);
3528
3529 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3530 if (util_format_has_depth(util_format_description(src->format)))
3531 non_disp_tiling = 1;
3532
3533 y = 0;
3534 sub_cmd = EG_DMA_COPY_TILED;
3535 lbpp = util_logbase2(bpp);
3536 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3537 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3538
3539 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3540 /* T2L */
3541 array_mode = evergreen_array_mode(src_mode);
3542 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3543 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3544 /* linear height must be the same as the slice tile max height, it's ok even
3545 * if the linear destination/source have smaller heigh as the size of the
3546 * dma packet will be using the copy_height which is always smaller or equal
3547 * to the linear height
3548 */
3549 height = u_minify(rsrc->resource.b.b.height0, src_level);
3550 detile = 1;
3551 x = src_x;
3552 y = src_y;
3553 z = src_z;
3554 base = rsrc->surface.u.legacy.level[src_level].offset;
3555 addr = rdst->surface.u.legacy.level[dst_level].offset;
3556 addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
3557 addr += dst_y * pitch + dst_x * bpp;
3558 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3559 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3560 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3561 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3562 base += rsrc->resource.gpu_address;
3563 addr += rdst->resource.gpu_address;
3564 } else {
3565 /* L2T */
3566 array_mode = evergreen_array_mode(dst_mode);
3567 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3568 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3569 /* linear height must be the same as the slice tile max height, it's ok even
3570 * if the linear destination/source have smaller heigh as the size of the
3571 * dma packet will be using the copy_height which is always smaller or equal
3572 * to the linear height
3573 */
3574 height = u_minify(rdst->resource.b.b.height0, dst_level);
3575 detile = 0;
3576 x = dst_x;
3577 y = dst_y;
3578 z = dst_z;
3579 base = rdst->surface.u.legacy.level[dst_level].offset;
3580 addr = rsrc->surface.u.legacy.level[src_level].offset;
3581 addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
3582 addr += src_y * pitch + src_x * bpp;
3583 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3584 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3585 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3586 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3587 base += rdst->resource.gpu_address;
3588 addr += rsrc->resource.gpu_address;
3589 }
3590
3591 size = (copy_height * pitch) / 4;
3592 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3593 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3594
3595 for (i = 0; i < ncopy; i++) {
3596 cheight = copy_height;
3597 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3598 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3599 }
3600 size = (cheight * pitch) / 4;
3601 /* emit reloc before writing cs so that cs is always in consistent state */
3602 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3603 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3604 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3605 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3606 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3607 radeon_emit(cs, base >> 8);
3608 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3609 (lbpp << 24) | (bank_h << 21) |
3610 (bank_w << 18) | (mt_aspect << 16));
3611 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3612 radeon_emit(cs, (slice_tile_max << 0));
3613 radeon_emit(cs, (x << 0) | (z << 18));
3614 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3615 radeon_emit(cs, addr & 0xfffffffc);
3616 radeon_emit(cs, (addr >> 32UL) & 0xff);
3617 copy_height -= cheight;
3618 addr += cheight * pitch;
3619 y += cheight;
3620 }
3621 }
3622
3623 static void evergreen_dma_copy(struct pipe_context *ctx,
3624 struct pipe_resource *dst,
3625 unsigned dst_level,
3626 unsigned dstx, unsigned dsty, unsigned dstz,
3627 struct pipe_resource *src,
3628 unsigned src_level,
3629 const struct pipe_box *src_box)
3630 {
3631 struct r600_context *rctx = (struct r600_context *)ctx;
3632 struct r600_texture *rsrc = (struct r600_texture*)src;
3633 struct r600_texture *rdst = (struct r600_texture*)dst;
3634 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3635 unsigned src_w, dst_w;
3636 unsigned src_x, src_y;
3637 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3638
3639 if (rctx->b.dma.cs == NULL) {
3640 goto fallback;
3641 }
3642
3643 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3644 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3645 return;
3646 }
3647
3648 if (src_box->depth > 1 ||
3649 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3650 dstz, rsrc, src_level, src_box))
3651 goto fallback;
3652
3653 src_x = util_format_get_nblocksx(src->format, src_box->x);
3654 dst_x = util_format_get_nblocksx(src->format, dst_x);
3655 src_y = util_format_get_nblocksy(src->format, src_box->y);
3656 dst_y = util_format_get_nblocksy(src->format, dst_y);
3657
3658 bpp = rdst->surface.bpe;
3659 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3660 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3661 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3662 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3663 copy_height = src_box->height / rsrc->surface.blk_h;
3664
3665 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3666 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3667
3668 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3669 /* FIXME evergreen can do partial blit */
3670 goto fallback;
3671 }
3672 /* the x test here are currently useless (because we don't support partial blit)
3673 * but keep them around so we don't forget about those
3674 */
3675 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3676 goto fallback;
3677 }
3678
3679 /* 128 bpp surfaces require non_disp_tiling for both
3680 * tiled and linear buffers on cayman. However, async
3681 * DMA only supports it on the tiled side. As such
3682 * the tile order is backwards after a L2T/T2L packet.
3683 */
3684 if ((rctx->b.chip_class == CAYMAN) &&
3685 (src_mode != dst_mode) &&
3686 (util_format_get_blocksize(src->format) >= 16)) {
3687 goto fallback;
3688 }
3689
3690 if (src_mode == dst_mode) {
3691 uint64_t dst_offset, src_offset;
3692 /* simple dma blit would do NOTE code here assume :
3693 * src_box.x/y == 0
3694 * dst_x/y == 0
3695 * dst_pitch == src_pitch
3696 */
3697 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3698 src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
3699 src_offset += src_y * src_pitch + src_x * bpp;
3700 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3701 dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
3702 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3703 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3704 src_box->height * src_pitch);
3705 } else {
3706 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3707 src, src_level, src_x, src_y, src_box->z,
3708 copy_height, dst_pitch, bpp);
3709 }
3710 return;
3711
3712 fallback:
3713 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3714 src, src_level, src_box);
3715 }
3716
3717 static void evergreen_set_tess_state(struct pipe_context *ctx,
3718 const float default_outer_level[4],
3719 const float default_inner_level[2])
3720 {
3721 struct r600_context *rctx = (struct r600_context *)ctx;
3722
3723 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3724 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3725 rctx->tess_state_dirty = true;
3726 }
3727
3728 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3729 unsigned start_slot,
3730 unsigned count,
3731 const struct pipe_shader_buffer *buffers)
3732 {
3733 struct r600_context *rctx = (struct r600_context *)ctx;
3734 struct r600_atomic_buffer_state *astate;
3735 int i, idx;
3736
3737 astate = &rctx->atomic_buffer_state;
3738
3739 /* we'd probably like to expand this to 8 later so put the logic in */
3740 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3741 const struct pipe_shader_buffer *buf;
3742 struct pipe_shader_buffer *abuf;
3743
3744 abuf = &astate->buffer[i];
3745
3746 if (!buffers || !buffers[idx].buffer) {
3747 pipe_resource_reference(&abuf->buffer, NULL);
3748 astate->enabled_mask &= ~(1 << i);
3749 continue;
3750 }
3751 buf = &buffers[idx];
3752
3753 pipe_resource_reference(&abuf->buffer, buf->buffer);
3754 abuf->buffer_offset = buf->buffer_offset;
3755 abuf->buffer_size = buf->buffer_size;
3756 astate->enabled_mask |= (1 << i);
3757 }
3758 }
3759
3760 void evergreen_init_state_functions(struct r600_context *rctx)
3761 {
3762 unsigned id = 1;
3763 unsigned i;
3764 /* !!!
3765 * To avoid GPU lockup registers must be emitted in a specific order
3766 * (no kidding ...). The order below is important and have been
3767 * partially inferred from analyzing fglrx command stream.
3768 *
3769 * Don't reorder atom without carefully checking the effect (GPU lockup
3770 * or piglit regression).
3771 * !!!
3772 */
3773 if (rctx->b.chip_class == EVERGREEN) {
3774 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3775 rctx->config_state.dyn_gpr_enabled = true;
3776 }
3777 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3778 /* shader const */
3779 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3780 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3781 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3782 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3783 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3784 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3785 /* shader program */
3786 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3787 /* sampler */
3788 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3789 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3790 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3791 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3792 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3793 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3794 /* resources */
3795 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3796 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3797 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3798 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3799 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3800 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3801 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3802 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3803
3804 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3805
3806 if (rctx->b.chip_class == EVERGREEN) {
3807 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3808 } else {
3809 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3810 }
3811 rctx->sample_mask.sample_mask = ~0;
3812
3813 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3814 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3815 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3816 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3817 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3818 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3819 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3820 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3821 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3822 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
3823 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3824 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3825 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3826 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3827 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3828 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3829 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3830 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3831 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3832 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3833 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3834 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3835
3836 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3837 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3838 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3839 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3840 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3841 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3842 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3843 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3844 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3845 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
3846 if (rctx->b.chip_class == EVERGREEN)
3847 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3848 else
3849 rctx->b.b.get_sample_position = cayman_get_sample_position;
3850 rctx->b.dma_copy = evergreen_dma_copy;
3851
3852 evergreen_init_compute_state_functions(rctx);
3853 }
3854
3855 /**
3856 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3857 *
3858 * The information about LDS and other non-compile-time parameters is then
3859 * written to the const buffer.
3860
3861 * const buffer contains -
3862 * uint32_t input_patch_size
3863 * uint32_t input_vertex_size
3864 * uint32_t num_tcs_input_cp
3865 * uint32_t num_tcs_output_cp;
3866 * uint32_t output_patch_size
3867 * uint32_t output_vertex_size
3868 * uint32_t output_patch0_offset
3869 * uint32_t perpatch_output_offset
3870 * and the same constbuf is bound to LS/HS/VS(ES).
3871 */
3872 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3873 {
3874 struct pipe_constant_buffer constbuf = {0};
3875 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3876 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3877 unsigned num_tcs_input_cp = info->vertices_per_patch;
3878 unsigned num_tcs_outputs;
3879 unsigned num_tcs_output_cp;
3880 unsigned num_tcs_patch_outputs;
3881 unsigned num_tcs_inputs;
3882 unsigned input_vertex_size, output_vertex_size;
3883 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3884 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3885 uint32_t values[16];
3886 unsigned num_waves;
3887 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3888 unsigned wave_divisor = (16 * num_pipes);
3889
3890 *num_patches = 1;
3891
3892 if (!rctx->tes_shader) {
3893 rctx->lds_alloc = 0;
3894 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3895 R600_LDS_INFO_CONST_BUFFER, NULL);
3896 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3897 R600_LDS_INFO_CONST_BUFFER, NULL);
3898 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3899 R600_LDS_INFO_CONST_BUFFER, NULL);
3900 return;
3901 }
3902
3903 if (rctx->lds_alloc != 0 &&
3904 rctx->last_ls == ls &&
3905 !rctx->tess_state_dirty &&
3906 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3907 rctx->last_tcs == tcs)
3908 return;
3909
3910 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3911
3912 if (rctx->tcs_shader) {
3913 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3914 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3915 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3916 } else {
3917 num_tcs_outputs = num_tcs_inputs;
3918 num_tcs_output_cp = num_tcs_input_cp;
3919 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3920 }
3921
3922 /* size in bytes */
3923 input_vertex_size = num_tcs_inputs * 16;
3924 output_vertex_size = num_tcs_outputs * 16;
3925
3926 input_patch_size = num_tcs_input_cp * input_vertex_size;
3927
3928 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3929 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3930
3931 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3932 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3933
3934 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3935
3936 values[0] = input_patch_size;
3937 values[1] = input_vertex_size;
3938 values[2] = num_tcs_input_cp;
3939 values[3] = num_tcs_output_cp;
3940
3941 values[4] = output_patch_size;
3942 values[5] = output_vertex_size;
3943 values[6] = output_patch0_offset;
3944 values[7] = perpatch_output_offset;
3945
3946 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3947 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3948 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3949
3950 rctx->lds_alloc = (lds_size | (num_waves << 14));
3951
3952 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3953 values[14] = 0;
3954 values[15] = 0;
3955
3956 rctx->tess_state_dirty = false;
3957 rctx->last_ls = ls;
3958 rctx->last_tcs = tcs;
3959 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3960
3961 constbuf.user_buffer = values;
3962 constbuf.buffer_size = 16 * 4;
3963
3964 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3965 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3966 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3967 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3968 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3969 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3970 pipe_resource_reference(&constbuf.buffer, NULL);
3971 }
3972
3973 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3974 const struct pipe_draw_info *info,
3975 unsigned num_patches)
3976 {
3977 unsigned num_output_cp;
3978
3979 if (!rctx->tes_shader)
3980 return 0;
3981
3982 num_output_cp = rctx->tcs_shader ?
3983 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3984 info->vertices_per_patch;
3985
3986 return S_028B58_NUM_PATCHES(num_patches) |
3987 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3988 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3989 }
3990
3991 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3992 struct radeon_winsys_cs *cs,
3993 uint32_t ls_hs_config)
3994 {
3995 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3996 }
3997
3998 void evergreen_set_lds_alloc(struct r600_context *rctx,
3999 struct radeon_winsys_cs *cs,
4000 uint32_t lds_alloc)
4001 {
4002 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4003 }
4004
4005 /* on evergreen if you are running tessellation you need to disable dynamic
4006 GPRs to workaround a hardware bug.*/
4007 bool evergreen_adjust_gprs(struct r600_context *rctx)
4008 {
4009 unsigned num_gprs[EG_NUM_HW_STAGES];
4010 unsigned def_gprs[EG_NUM_HW_STAGES];
4011 unsigned cur_gprs[EG_NUM_HW_STAGES];
4012 unsigned new_gprs[EG_NUM_HW_STAGES];
4013 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4014 unsigned max_gprs;
4015 unsigned i;
4016 unsigned total_gprs;
4017 unsigned tmp[3];
4018 bool rework = false, set_default = false, set_dirty = false;
4019 max_gprs = 0;
4020 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4021 def_gprs[i] = rctx->default_gprs[i];
4022 max_gprs += def_gprs[i];
4023 }
4024 max_gprs += def_num_clause_temp_gprs * 2;
4025
4026 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4027 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4028 if (rctx->config_state.dyn_gpr_enabled)
4029 return true;
4030
4031 /* transition back to dyn gpr enabled state */
4032 rctx->config_state.dyn_gpr_enabled = true;
4033 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4034 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4035 return true;
4036 }
4037
4038
4039 /* gather required shader gprs */
4040 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4041 if (rctx->hw_shader_stages[i].shader)
4042 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4043 else
4044 num_gprs[i] = 0;
4045 }
4046
4047 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4048 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4049 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4050 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4051 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4052 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4053
4054 total_gprs = 0;
4055 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4056 new_gprs[i] = num_gprs[i];
4057 total_gprs += num_gprs[i];
4058 }
4059
4060 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4061 return false;
4062
4063 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4064 if (new_gprs[i] > cur_gprs[i]) {
4065 rework = true;
4066 break;
4067 }
4068 }
4069
4070 if (rctx->config_state.dyn_gpr_enabled) {
4071 set_dirty = true;
4072 rctx->config_state.dyn_gpr_enabled = false;
4073 }
4074
4075 if (rework) {
4076 set_default = true;
4077 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4078 if (new_gprs[i] > def_gprs[i])
4079 set_default = false;
4080 }
4081
4082 if (set_default) {
4083 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4084 new_gprs[i] = def_gprs[i];
4085 }
4086 } else {
4087 unsigned ps_value = max_gprs;
4088
4089 ps_value -= (def_num_clause_temp_gprs * 2);
4090 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4091 ps_value -= new_gprs[i];
4092
4093 new_gprs[R600_HW_STAGE_PS] = ps_value;
4094 }
4095
4096 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4097 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4098 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4099
4100 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4101 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4102
4103 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4104 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4105
4106 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4107 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4108 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4109 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4110 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4111 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4112 set_dirty = true;
4113 }
4114 }
4115
4116
4117 if (set_dirty) {
4118 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4119 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4120 }
4121 return true;
4122 }
4123
4124 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4125
4126 void eg_trace_emit(struct r600_context *rctx)
4127 {
4128 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4129 unsigned reloc;
4130
4131 if (rctx->b.chip_class < EVERGREEN)
4132 return;
4133
4134 /* This must be done after r600_need_cs_space. */
4135 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4136 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4137 RADEON_PRIO_CP_DMA);
4138
4139 rctx->trace_id++;
4140 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4141 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4142 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4143 radeon_emit(cs, rctx->trace_buf->gpu_address);
4144 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4145 radeon_emit(cs, rctx->trace_id);
4146 radeon_emit(cs, 0);
4147 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4148 radeon_emit(cs, reloc);
4149 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4150 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4151 }
4152
4153 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4154 struct r600_shader_atomic *combined_atomics,
4155 uint8_t *atomic_used_mask_p)
4156 {
4157 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4158 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4159 unsigned pkt_flags = 0;
4160 uint8_t atomic_used_mask = 0;
4161 int i, j, k;
4162
4163 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4164 uint8_t num_atomic_stage;
4165 struct r600_pipe_shader *pshader;
4166
4167 pshader = rctx->hw_shader_stages[i].shader;
4168 if (!pshader)
4169 continue;
4170
4171 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4172 if (!num_atomic_stage)
4173 continue;
4174
4175 for (j = 0; j < num_atomic_stage; j++) {
4176 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4177 int natomics = atomic->end - atomic->start + 1;
4178
4179 for (k = 0; k < natomics; k++) {
4180 /* seen this in a previous stage */
4181 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4182 continue;
4183
4184 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4185 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4186 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4187 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4188 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4189 }
4190 }
4191 }
4192
4193 uint32_t mask = atomic_used_mask;
4194 while (mask) {
4195 unsigned atomic_index = u_bit_scan(&mask);
4196 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4197 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4198 assert(resource);
4199 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4200 resource,
4201 RADEON_USAGE_READ,
4202 RADEON_PRIO_SHADER_RW_BUFFER);
4203 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4204 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4205
4206 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4207
4208 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4209 radeon_emit(cs, (reg_val << 16) | 0x3);
4210 radeon_emit(cs, dst_offset & 0xfffffffc);
4211 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4212 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4213 radeon_emit(cs, reloc);
4214 }
4215 *atomic_used_mask_p = atomic_used_mask;
4216 return true;
4217 }
4218
4219 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4220 struct r600_shader_atomic *combined_atomics,
4221 uint8_t *atomic_used_mask_p)
4222 {
4223 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4224 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4225 uint32_t pkt_flags = 0;
4226 uint32_t event = EVENT_TYPE_PS_DONE;
4227 uint32_t mask = astate->enabled_mask;
4228 uint64_t dst_offset;
4229 unsigned reloc;
4230
4231 mask = *atomic_used_mask_p;
4232 if (!mask)
4233 return;
4234
4235 while (mask) {
4236 unsigned atomic_index = u_bit_scan(&mask);
4237 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4238 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4239 assert(resource);
4240
4241 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4242 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4243 resource,
4244 RADEON_USAGE_WRITE,
4245 RADEON_PRIO_SHADER_RW_BUFFER);
4246 dst_offset = resource->gpu_address + (atomic->start * 4);
4247 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4248
4249 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4250 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4251 radeon_emit(cs, (dst_offset) & 0xffffffff);
4252 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4253 radeon_emit(cs, reg_val);
4254 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4255 radeon_emit(cs, reloc);
4256 }
4257 ++rctx->append_fence_id;
4258 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4259 r600_resource(rctx->append_fence),
4260 RADEON_USAGE_READWRITE,
4261 RADEON_PRIO_SHADER_RW_BUFFER);
4262 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4263 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4264 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4265 radeon_emit(cs, dst_offset & 0xffffffff);
4266 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4267 radeon_emit(cs, rctx->append_fence_id);
4268 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4269 radeon_emit(cs, reloc);
4270
4271 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4272 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4273 radeon_emit(cs, dst_offset & 0xffffffff);
4274 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4275 radeon_emit(cs, rctx->append_fence_id);
4276 radeon_emit(cs, 0xffffffff);
4277 radeon_emit(cs, 0xa);
4278 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4279 radeon_emit(cs, reloc);
4280 }