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r600/images: set offset for compute shaders with number of declared samplers
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600_query.h"
26 #include "evergreend.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_memory.h"
31 #include "util/u_framebuffer.h"
32 #include "util/u_dual_blend.h"
33 #include "evergreen_compute.h"
34 #include "util/u_math.h"
35
36 static inline unsigned evergreen_array_mode(unsigned mode)
37 {
38 switch (mode) {
39 default:
40 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
41 break;
42 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
43 break;
44 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(struct r600_texture *rtex,
174 unsigned view_target, unsigned nr_samples)
175 {
176 unsigned res_target = rtex->resource.b.b.target;
177
178 if (view_target == PIPE_TEXTURE_CUBE ||
179 view_target == PIPE_TEXTURE_CUBE_ARRAY)
180 res_target = view_target;
181 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
182 else if (res_target == PIPE_TEXTURE_CUBE ||
183 res_target == PIPE_TEXTURE_CUBE_ARRAY)
184 res_target = PIPE_TEXTURE_2D_ARRAY;
185
186 switch (res_target) {
187 default:
188 case PIPE_TEXTURE_1D:
189 return V_030000_SQ_TEX_DIM_1D;
190 case PIPE_TEXTURE_1D_ARRAY:
191 return V_030000_SQ_TEX_DIM_1D_ARRAY;
192 case PIPE_TEXTURE_2D:
193 case PIPE_TEXTURE_RECT:
194 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
195 V_030000_SQ_TEX_DIM_2D;
196 case PIPE_TEXTURE_2D_ARRAY:
197 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
198 V_030000_SQ_TEX_DIM_2D_ARRAY;
199 case PIPE_TEXTURE_3D:
200 return V_030000_SQ_TEX_DIM_3D;
201 case PIPE_TEXTURE_CUBE:
202 case PIPE_TEXTURE_CUBE_ARRAY:
203 return V_030000_SQ_TEX_DIM_CUBEMAP;
204 }
205 }
206
207 static uint32_t r600_translate_dbformat(enum pipe_format format)
208 {
209 switch (format) {
210 case PIPE_FORMAT_Z16_UNORM:
211 return V_028040_Z_16;
212 case PIPE_FORMAT_Z24X8_UNORM:
213 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
214 case PIPE_FORMAT_X8Z24_UNORM:
215 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
216 return V_028040_Z_24;
217 case PIPE_FORMAT_Z32_FLOAT:
218 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
219 return V_028040_Z_32_FLOAT;
220 default:
221 return ~0U;
222 }
223 }
224
225 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
226 {
227 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
228 FALSE) != ~0U;
229 }
230
231 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
232 {
233 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
234 r600_translate_colorswap(format, FALSE) != ~0U;
235 }
236
237 static bool r600_is_zs_format_supported(enum pipe_format format)
238 {
239 return r600_translate_dbformat(format) != ~0U;
240 }
241
242 boolean evergreen_is_format_supported(struct pipe_screen *screen,
243 enum pipe_format format,
244 enum pipe_texture_target target,
245 unsigned sample_count,
246 unsigned usage)
247 {
248 struct r600_screen *rscreen = (struct r600_screen*)screen;
249 unsigned retval = 0;
250
251 if (target >= PIPE_MAX_TEXTURE_TYPES) {
252 R600_ERR("r600: unsupported texture type %d\n", target);
253 return FALSE;
254 }
255
256 if (!util_format_is_supported(format, usage))
257 return FALSE;
258
259 if (sample_count > 1) {
260 if (!rscreen->has_msaa)
261 return FALSE;
262
263 switch (sample_count) {
264 case 2:
265 case 4:
266 case 8:
267 break;
268 default:
269 return FALSE;
270 }
271 }
272
273 if (usage & PIPE_BIND_SAMPLER_VIEW) {
274 if (target == PIPE_BUFFER) {
275 if (r600_is_vertex_format_supported(format))
276 retval |= PIPE_BIND_SAMPLER_VIEW;
277 } else {
278 if (r600_is_sampler_format_supported(screen, format))
279 retval |= PIPE_BIND_SAMPLER_VIEW;
280 }
281 }
282
283 if ((usage & (PIPE_BIND_RENDER_TARGET |
284 PIPE_BIND_DISPLAY_TARGET |
285 PIPE_BIND_SCANOUT |
286 PIPE_BIND_SHARED |
287 PIPE_BIND_BLENDABLE)) &&
288 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
289 retval |= usage &
290 (PIPE_BIND_RENDER_TARGET |
291 PIPE_BIND_DISPLAY_TARGET |
292 PIPE_BIND_SCANOUT |
293 PIPE_BIND_SHARED);
294 if (!util_format_is_pure_integer(format) &&
295 !util_format_is_depth_or_stencil(format))
296 retval |= usage & PIPE_BIND_BLENDABLE;
297 }
298
299 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
300 r600_is_zs_format_supported(format)) {
301 retval |= PIPE_BIND_DEPTH_STENCIL;
302 }
303
304 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
305 r600_is_vertex_format_supported(format)) {
306 retval |= PIPE_BIND_VERTEX_BUFFER;
307 }
308
309 if ((usage & PIPE_BIND_LINEAR) &&
310 !util_format_is_compressed(format) &&
311 !(usage & PIPE_BIND_DEPTH_STENCIL))
312 retval |= PIPE_BIND_LINEAR;
313
314 return retval == usage;
315 }
316
317 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
318 const struct pipe_blend_state *state, int mode)
319 {
320 uint32_t color_control = 0, target_mask = 0;
321 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
322
323 if (!blend) {
324 return NULL;
325 }
326
327 r600_init_command_buffer(&blend->buffer, 20);
328 r600_init_command_buffer(&blend->buffer_no_blend, 20);
329
330 if (state->logicop_enable) {
331 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
332 } else {
333 color_control |= (0xcc << 16);
334 }
335 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
336 if (state->independent_blend_enable) {
337 for (int i = 0; i < 8; i++) {
338 target_mask |= (state->rt[i].colormask << (4 * i));
339 }
340 } else {
341 for (int i = 0; i < 8; i++) {
342 target_mask |= (state->rt[0].colormask << (4 * i));
343 }
344 }
345
346 /* only have dual source on MRT0 */
347 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
348 blend->cb_target_mask = target_mask;
349 blend->alpha_to_one = state->alpha_to_one;
350
351 if (target_mask)
352 color_control |= S_028808_MODE(mode);
353 else
354 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
355
356
357 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
358 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
359 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
360 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
363 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
364 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
365
366 /* Copy over the dwords set so far into buffer_no_blend.
367 * Only the CB_BLENDi_CONTROL registers must be set after this. */
368 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
369 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
370
371 for (int i = 0; i < 8; i++) {
372 /* state->rt entries > 0 only written if independent blending */
373 const int j = state->independent_blend_enable ? i : 0;
374
375 unsigned eqRGB = state->rt[j].rgb_func;
376 unsigned srcRGB = state->rt[j].rgb_src_factor;
377 unsigned dstRGB = state->rt[j].rgb_dst_factor;
378 unsigned eqA = state->rt[j].alpha_func;
379 unsigned srcA = state->rt[j].alpha_src_factor;
380 unsigned dstA = state->rt[j].alpha_dst_factor;
381 uint32_t bc = 0;
382
383 r600_store_value(&blend->buffer_no_blend, 0);
384
385 if (!state->rt[j].blend_enable) {
386 r600_store_value(&blend->buffer, 0);
387 continue;
388 }
389
390 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
391 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
392 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
393 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
394
395 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
396 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
397 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
398 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
399 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
400 }
401 r600_store_value(&blend->buffer, bc);
402 }
403 return blend;
404 }
405
406 static void *evergreen_create_blend_state(struct pipe_context *ctx,
407 const struct pipe_blend_state *state)
408 {
409
410 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
411 }
412
413 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
414 const struct pipe_depth_stencil_alpha_state *state)
415 {
416 unsigned db_depth_control, alpha_test_control, alpha_ref;
417 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
418
419 if (!dsa) {
420 return NULL;
421 }
422
423 r600_init_command_buffer(&dsa->buffer, 3);
424
425 dsa->valuemask[0] = state->stencil[0].valuemask;
426 dsa->valuemask[1] = state->stencil[1].valuemask;
427 dsa->writemask[0] = state->stencil[0].writemask;
428 dsa->writemask[1] = state->stencil[1].writemask;
429 dsa->zwritemask = state->depth.writemask;
430
431 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
432 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
433 S_028800_ZFUNC(state->depth.func);
434
435 /* stencil */
436 if (state->stencil[0].enabled) {
437 db_depth_control |= S_028800_STENCIL_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
442
443 if (state->stencil[1].enabled) {
444 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
445 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
446 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
447 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
448 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
449 }
450 }
451
452 /* alpha */
453 alpha_test_control = 0;
454 alpha_ref = 0;
455 if (state->alpha.enabled) {
456 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
457 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
458 alpha_ref = fui(state->alpha.ref_value);
459 }
460 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
461 dsa->alpha_ref = alpha_ref;
462
463 /* misc */
464 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
465 return dsa;
466 }
467
468 static void *evergreen_create_rs_state(struct pipe_context *ctx,
469 const struct pipe_rasterizer_state *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472 unsigned tmp, spi_interp;
473 float psize_min, psize_max;
474 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
475
476 if (!rs) {
477 return NULL;
478 }
479
480 r600_init_command_buffer(&rs->buffer, 30);
481
482 rs->scissor_enable = state->scissor;
483 rs->clip_halfz = state->clip_halfz;
484 rs->flatshade = state->flatshade;
485 rs->sprite_coord_enable = state->sprite_coord_enable;
486 rs->rasterizer_discard = state->rasterizer_discard;
487 rs->two_side = state->light_twoside;
488 rs->clip_plane_enable = state->clip_plane_enable;
489 rs->pa_sc_line_stipple = state->line_stipple_enable ?
490 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
491 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
492 rs->pa_cl_clip_cntl =
493 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
494 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
495 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
496 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
497 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
498 rs->multisample_enable = state->multisample;
499
500 /* offset */
501 rs->offset_units = state->offset_units;
502 rs->offset_scale = state->offset_scale * 16.0f;
503 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
504 rs->offset_units_unscaled = state->offset_units_unscaled;
505
506 if (state->point_size_per_vertex) {
507 psize_min = util_get_min_point_size(state);
508 psize_max = 8192;
509 } else {
510 /* Force the point size to be as if the vertex output was disabled. */
511 psize_min = state->point_size;
512 psize_max = state->point_size;
513 }
514
515 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
516 if (state->sprite_coord_enable) {
517 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
518 S_0286D4_PNT_SPRITE_OVRD_X(2) |
519 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
520 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
521 S_0286D4_PNT_SPRITE_OVRD_W(1);
522 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
523 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
524 }
525 }
526
527 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
528 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
529 tmp = r600_pack_float_12p4(state->point_size/2);
530 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
531 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
532 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
533 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
534 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
535 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
536 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
537
538 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
539 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
540 S_028A48_MSAA_ENABLE(state->multisample) |
541 S_028A48_VPORT_SCISSOR_ENABLE(1) |
542 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
543
544 if (rctx->b.chip_class == CAYMAN) {
545 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
546 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
547 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
548 } else {
549 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
550 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
551 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
552 }
553
554 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
555 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
556 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
557 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
558 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
559 S_028814_FACE(!state->front_ccw) |
560 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
561 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
562 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
563 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
564 state->fill_back != PIPE_POLYGON_MODE_FILL) |
565 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
566 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
567 return rs;
568 }
569
570 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
571 const struct pipe_sampler_state *state)
572 {
573 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
574 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
575 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
576 : state->max_anisotropy;
577 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
578
579 if (!ss) {
580 return NULL;
581 }
582
583 ss->border_color_use = sampler_state_needs_border_color(state);
584
585 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
586 ss->tex_sampler_words[0] =
587 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
588 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
589 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
590 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
591 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
592 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
593 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
594 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
595 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
596 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
597 ss->tex_sampler_words[1] =
598 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
599 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
600 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
601 ss->tex_sampler_words[2] =
602 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
603 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
604 S_03C008_TYPE(1);
605
606 if (ss->border_color_use) {
607 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
608 }
609 return ss;
610 }
611
612 struct eg_buf_res_params {
613 enum pipe_format pipe_format;
614 unsigned offset;
615 unsigned size;
616 unsigned char swizzle[4];
617 bool uncached;
618 bool force_swizzle;
619 };
620
621 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
622 struct pipe_resource *buffer,
623 struct eg_buf_res_params *params,
624 bool *skip_mip_address_reloc,
625 unsigned tex_resource_words[8])
626 {
627 struct r600_texture *tmp = (struct r600_texture*)buffer;
628 uint64_t va;
629 int stride = util_format_get_blocksize(params->pipe_format);
630 unsigned format, num_format, format_comp, endian;
631 unsigned swizzle_res;
632 const struct util_format_description *desc;
633
634 r600_vertex_data_type(params->pipe_format,
635 &format, &num_format, &format_comp,
636 &endian);
637
638 desc = util_format_description(params->pipe_format);
639
640 if (params->force_swizzle)
641 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
642 else
643 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
644
645 va = tmp->resource.gpu_address + params->offset;
646 *skip_mip_address_reloc = true;
647 tex_resource_words[0] = va;
648 tex_resource_words[1] = params->size - 1;
649 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
650 S_030008_STRIDE(stride) |
651 S_030008_DATA_FORMAT(format) |
652 S_030008_NUM_FORMAT_ALL(num_format) |
653 S_030008_FORMAT_COMP_ALL(format_comp) |
654 S_030008_ENDIAN_SWAP(endian);
655 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
656 /*
657 * dword 4 is for number of elements, for use with resinfo,
658 * albeit the amd gpu shader analyser
659 * uses a const buffer to store the element sizes for buffer txq
660 */
661 tex_resource_words[4] = params->size / stride;
662
663 tex_resource_words[5] = tex_resource_words[6] = 0;
664 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
665 }
666
667 static struct pipe_sampler_view *
668 texture_buffer_sampler_view(struct r600_context *rctx,
669 struct r600_pipe_sampler_view *view,
670 unsigned width0, unsigned height0)
671 {
672 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
673 struct eg_buf_res_params params;
674
675 memset(&params, 0, sizeof(params));
676
677 params.pipe_format = view->base.format;
678 params.offset = view->base.u.buf.offset;
679 params.size = view->base.u.buf.size;
680 params.swizzle[0] = view->base.swizzle_r;
681 params.swizzle[1] = view->base.swizzle_g;
682 params.swizzle[2] = view->base.swizzle_b;
683 params.swizzle[3] = view->base.swizzle_a;
684
685 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
686 &params, &view->skip_mip_address_reloc,
687 view->tex_resource_words);
688 view->tex_resource = &tmp->resource;
689
690 if (tmp->resource.gpu_address)
691 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
692 return &view->base;
693 }
694
695 struct eg_tex_res_params {
696 enum pipe_format pipe_format;
697 int force_level;
698 unsigned width0;
699 unsigned height0;
700 unsigned first_level;
701 unsigned last_level;
702 unsigned first_layer;
703 unsigned last_layer;
704 unsigned target;
705 unsigned char swizzle[4];
706 };
707
708 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
709 struct pipe_resource *texture,
710 struct eg_tex_res_params *params,
711 bool *skip_mip_address_reloc,
712 unsigned tex_resource_words[8])
713 {
714 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
715 struct r600_texture *tmp = (struct r600_texture*)texture;
716 unsigned format, endian;
717 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
718 unsigned char array_mode = 0, non_disp_tiling = 0;
719 unsigned height, depth, width;
720 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
721 struct legacy_surf_level *surflevel;
722 unsigned base_level, first_level, last_level;
723 unsigned dim, last_layer;
724 uint64_t va;
725 bool do_endian_swap = FALSE;
726
727 tile_split = tmp->surface.u.legacy.tile_split;
728 surflevel = tmp->surface.u.legacy.level;
729
730 /* Texturing with separate depth and stencil. */
731 if (tmp->db_compatible) {
732 switch (params->pipe_format) {
733 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
734 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
735 break;
736 case PIPE_FORMAT_X8Z24_UNORM:
737 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
738 /* Z24 is always stored like this for DB
739 * compatibility.
740 */
741 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
742 break;
743 case PIPE_FORMAT_X24S8_UINT:
744 case PIPE_FORMAT_S8X24_UINT:
745 case PIPE_FORMAT_X32_S8X24_UINT:
746 params->pipe_format = PIPE_FORMAT_S8_UINT;
747 tile_split = tmp->surface.u.legacy.stencil_tile_split;
748 surflevel = tmp->surface.u.legacy.stencil_level;
749 break;
750 default:;
751 }
752 }
753
754 if (R600_BIG_ENDIAN)
755 do_endian_swap = !tmp->db_compatible;
756
757 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
758 params->swizzle,
759 &word4, &yuv_format, do_endian_swap);
760 assert(format != ~0);
761 if (format == ~0) {
762 return -1;
763 }
764
765 endian = r600_colorformat_endian_swap(format, do_endian_swap);
766
767 base_level = 0;
768 first_level = params->first_level;
769 last_level = params->last_level;
770 width = params->width0;
771 height = params->height0;
772 depth = texture->depth0;
773
774 if (params->force_level) {
775 base_level = params->force_level;
776 first_level = 0;
777 last_level = 0;
778 width = u_minify(width, params->force_level);
779 height = u_minify(height, params->force_level);
780 depth = u_minify(depth, params->force_level);
781 }
782
783 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
784 non_disp_tiling = tmp->non_disp_tiling;
785
786 switch (surflevel[base_level].mode) {
787 default:
788 case RADEON_SURF_MODE_LINEAR_ALIGNED:
789 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
790 break;
791 case RADEON_SURF_MODE_2D:
792 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
793 break;
794 case RADEON_SURF_MODE_1D:
795 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
796 break;
797 }
798 macro_aspect = tmp->surface.u.legacy.mtilea;
799 bankw = tmp->surface.u.legacy.bankw;
800 bankh = tmp->surface.u.legacy.bankh;
801 tile_split = eg_tile_split(tile_split);
802 macro_aspect = eg_macro_tile_aspect(macro_aspect);
803 bankw = eg_bank_wh(bankw);
804 bankh = eg_bank_wh(bankh);
805 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
806
807 /* 128 bit formats require tile type = 1 */
808 if (rscreen->b.chip_class == CAYMAN) {
809 if (util_format_get_blocksize(params->pipe_format) >= 16)
810 non_disp_tiling = 1;
811 }
812 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
813
814
815 va = tmp->resource.gpu_address;
816
817 /* array type views and views into array types need to use layer offset */
818 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
819
820 if (dim == V_030000_SQ_TEX_DIM_1D_ARRAY) {
821 height = 1;
822 depth = texture->array_size;
823 } else if (dim == V_030000_SQ_TEX_DIM_2D_ARRAY ||
824 dim == V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA) {
825 depth = texture->array_size;
826 } else if (dim == V_030000_SQ_TEX_DIM_CUBEMAP)
827 depth = texture->array_size / 6;
828
829 tex_resource_words[0] = (S_030000_DIM(dim) |
830 S_030000_PITCH((pitch / 8) - 1) |
831 S_030000_TEX_WIDTH(width - 1));
832 if (rscreen->b.chip_class == CAYMAN)
833 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
834 else
835 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
836 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
837 S_030004_TEX_DEPTH(depth - 1) |
838 S_030004_ARRAY_MODE(array_mode));
839 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
840
841 *skip_mip_address_reloc = false;
842 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
843 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
844 if (tmp->is_depth) {
845 /* disable FMASK (0 = disabled) */
846 tex_resource_words[3] = 0;
847 *skip_mip_address_reloc = true;
848 } else {
849 /* FMASK should be in MIP_ADDRESS for multisample textures */
850 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
851 }
852 } else if (last_level && texture->nr_samples <= 1) {
853 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
854 } else {
855 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
856 }
857
858 last_layer = params->last_layer;
859 if (params->target != texture->target && depth == 1) {
860 last_layer = params->first_layer;
861 }
862 tex_resource_words[4] = (word4 |
863 S_030010_ENDIAN_SWAP(endian));
864 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
865 S_030014_LAST_ARRAY(last_layer);
866 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
867
868 if (texture->nr_samples > 1) {
869 unsigned log_samples = util_logbase2(texture->nr_samples);
870 if (rscreen->b.chip_class == CAYMAN) {
871 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
872 }
873 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
874 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
875 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
876 } else {
877 bool no_mip = first_level == last_level;
878
879 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
880 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
881 /* aniso max 16 samples */
882 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
883 }
884
885 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
886 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
887 S_03001C_BANK_WIDTH(bankw) |
888 S_03001C_BANK_HEIGHT(bankh) |
889 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
890 S_03001C_NUM_BANKS(nbanks) |
891 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
892 return 0;
893 }
894
895 struct pipe_sampler_view *
896 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
897 struct pipe_resource *texture,
898 const struct pipe_sampler_view *state,
899 unsigned width0, unsigned height0,
900 unsigned force_level)
901 {
902 struct r600_context *rctx = (struct r600_context*)ctx;
903 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
904 struct r600_texture *tmp = (struct r600_texture*)texture;
905 struct eg_tex_res_params params;
906 int ret;
907
908 if (!view)
909 return NULL;
910
911 /* initialize base object */
912 view->base = *state;
913 view->base.texture = NULL;
914 pipe_reference(NULL, &texture->reference);
915 view->base.texture = texture;
916 view->base.reference.count = 1;
917 view->base.context = ctx;
918
919 if (state->target == PIPE_BUFFER)
920 return texture_buffer_sampler_view(rctx, view, width0, height0);
921
922 memset(&params, 0, sizeof(params));
923 params.pipe_format = state->format;
924 params.force_level = force_level;
925 params.width0 = width0;
926 params.height0 = height0;
927 params.first_level = state->u.tex.first_level;
928 params.last_level = state->u.tex.last_level;
929 params.first_layer = state->u.tex.first_layer;
930 params.last_layer = state->u.tex.last_layer;
931 params.target = state->target;
932 params.swizzle[0] = state->swizzle_r;
933 params.swizzle[1] = state->swizzle_g;
934 params.swizzle[2] = state->swizzle_b;
935 params.swizzle[3] = state->swizzle_a;
936
937 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
938 &view->skip_mip_address_reloc,
939 view->tex_resource_words);
940 if (ret != 0) {
941 FREE(view);
942 return NULL;
943 }
944
945 if (state->format == PIPE_FORMAT_X24S8_UINT ||
946 state->format == PIPE_FORMAT_S8X24_UINT ||
947 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
948 state->format == PIPE_FORMAT_S8_UINT)
949 view->is_stencil_sampler = true;
950
951 view->tex_resource = &tmp->resource;
952
953 return &view->base;
954 }
955
956 static struct pipe_sampler_view *
957 evergreen_create_sampler_view(struct pipe_context *ctx,
958 struct pipe_resource *tex,
959 const struct pipe_sampler_view *state)
960 {
961 return evergreen_create_sampler_view_custom(ctx, tex, state,
962 tex->width0, tex->height0, 0);
963 }
964
965 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
966 {
967 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
968 struct r600_config_state *a = (struct r600_config_state*)atom;
969
970 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
971 if (a->dyn_gpr_enabled) {
972 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
973 radeon_emit(cs, 0);
974 radeon_emit(cs, 0);
975 } else {
976 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
977 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
978 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
979 }
980 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
981 if (a->dyn_gpr_enabled) {
982 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
983 S_028838_PS_GPRS(0x1e) |
984 S_028838_VS_GPRS(0x1e) |
985 S_028838_GS_GPRS(0x1e) |
986 S_028838_ES_GPRS(0x1e) |
987 S_028838_HS_GPRS(0x1e) |
988 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
989 }
990 }
991
992 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
993 {
994 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
995 struct pipe_clip_state *state = &rctx->clip_state.state;
996
997 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
998 radeon_emit_array(cs, (unsigned*)state, 6*4);
999 }
1000
1001 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1002 const struct pipe_poly_stipple *state)
1003 {
1004 }
1005
1006 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1007 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1008 uint32_t *tl, uint32_t *br)
1009 {
1010 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1011
1012 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1013
1014 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1015 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1016 }
1017
1018 struct r600_tex_color_info {
1019 unsigned info;
1020 unsigned view;
1021 unsigned dim;
1022 unsigned pitch;
1023 unsigned slice;
1024 unsigned attrib;
1025 unsigned ntype;
1026 unsigned fmask;
1027 unsigned fmask_slice;
1028 uint64_t offset;
1029 boolean export_16bpc;
1030 };
1031
1032 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1033 struct r600_resource *res,
1034 enum pipe_format pformat,
1035 unsigned first_element,
1036 unsigned last_element,
1037 struct r600_tex_color_info *color)
1038 {
1039 unsigned format, swap, ntype, endian;
1040 const struct util_format_description *desc;
1041 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1042 unsigned pitch_alignment =
1043 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1044 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1045 int i;
1046 unsigned width_elements;
1047
1048 width_elements = last_element - first_element + 1;
1049
1050 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1051 swap = r600_translate_colorswap(pformat, FALSE);
1052
1053 endian = r600_colorformat_endian_swap(format, FALSE);
1054
1055 desc = util_format_description(pformat);
1056 for (i = 0; i < 4; i++) {
1057 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1058 break;
1059 }
1060 }
1061 ntype = V_028C70_NUMBER_UNORM;
1062 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1063 ntype = V_028C70_NUMBER_SRGB;
1064 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1065 if (desc->channel[i].normalized)
1066 ntype = V_028C70_NUMBER_SNORM;
1067 else if (desc->channel[i].pure_integer)
1068 ntype = V_028C70_NUMBER_SINT;
1069 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1070 if (desc->channel[i].normalized)
1071 ntype = V_028C70_NUMBER_UNORM;
1072 else if (desc->channel[i].pure_integer)
1073 ntype = V_028C70_NUMBER_UINT;
1074 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1075 ntype = V_028C70_NUMBER_FLOAT;
1076 }
1077
1078 pitch = (pitch / 8) - 1;
1079 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1080
1081 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1082 color->info |= S_028C70_FORMAT(format) |
1083 S_028C70_COMP_SWAP(swap) |
1084 S_028C70_BLEND_CLAMP(0) |
1085 S_028C70_BLEND_BYPASS(1) |
1086 S_028C70_NUMBER_TYPE(ntype) |
1087 S_028C70_ENDIAN(endian);
1088 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1089 color->ntype = ntype;
1090 color->export_16bpc = false;
1091 color->dim = width_elements - 1;
1092 color->slice = 0; /* (width_elements / 64) - 1;*/
1093 color->view = 0;
1094 color->offset = (res->gpu_address + first_element) >> 8;
1095
1096 color->fmask = color->offset;
1097 color->fmask_slice = 0;
1098 }
1099
1100 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1101 struct r600_texture *rtex,
1102 unsigned level,
1103 unsigned first_layer,
1104 unsigned last_layer,
1105 enum pipe_format pformat,
1106 struct r600_tex_color_info *color)
1107 {
1108 struct r600_screen *rscreen = rctx->screen;
1109 unsigned pitch, slice;
1110 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1111 unsigned format, swap, ntype, endian;
1112 const struct util_format_description *desc;
1113 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1114 int i;
1115
1116 color->offset = rtex->surface.u.legacy.level[level].offset;
1117 color->view = S_028C6C_SLICE_START(first_layer) |
1118 S_028C6C_SLICE_MAX(last_layer);
1119
1120 color->offset += rtex->resource.gpu_address;
1121 color->offset >>= 8;
1122
1123 color->dim = 0;
1124 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1125 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1126 if (slice) {
1127 slice = slice - 1;
1128 }
1129
1130 color->info = 0;
1131 switch (rtex->surface.u.legacy.level[level].mode) {
1132 default:
1133 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1134 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1135 non_disp_tiling = 1;
1136 break;
1137 case RADEON_SURF_MODE_1D:
1138 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1139 non_disp_tiling = rtex->non_disp_tiling;
1140 break;
1141 case RADEON_SURF_MODE_2D:
1142 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1143 non_disp_tiling = rtex->non_disp_tiling;
1144 break;
1145 }
1146 tile_split = rtex->surface.u.legacy.tile_split;
1147 macro_aspect = rtex->surface.u.legacy.mtilea;
1148 bankw = rtex->surface.u.legacy.bankw;
1149 bankh = rtex->surface.u.legacy.bankh;
1150 if (rtex->fmask.size)
1151 fmask_bankh = rtex->fmask.bank_height;
1152 else
1153 fmask_bankh = rtex->surface.u.legacy.bankh;
1154 tile_split = eg_tile_split(tile_split);
1155 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1156 bankw = eg_bank_wh(bankw);
1157 bankh = eg_bank_wh(bankh);
1158 fmask_bankh = eg_bank_wh(fmask_bankh);
1159
1160 if (rscreen->b.chip_class == CAYMAN) {
1161 if (util_format_get_blocksize(pformat) >= 16)
1162 non_disp_tiling = 1;
1163 }
1164 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1165 desc = util_format_description(pformat);
1166 for (i = 0; i < 4; i++) {
1167 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1168 break;
1169 }
1170 }
1171 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1172 S_028C74_NUM_BANKS(nbanks) |
1173 S_028C74_BANK_WIDTH(bankw) |
1174 S_028C74_BANK_HEIGHT(bankh) |
1175 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1176 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1177 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1178
1179 if (rctx->b.chip_class == CAYMAN) {
1180 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1181 PIPE_SWIZZLE_1);
1182
1183 if (rtex->resource.b.b.nr_samples > 1) {
1184 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1185 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1186 S_028C74_NUM_FRAGMENTS(log_samples);
1187 }
1188 }
1189
1190 ntype = V_028C70_NUMBER_UNORM;
1191 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1192 ntype = V_028C70_NUMBER_SRGB;
1193 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1194 if (desc->channel[i].normalized)
1195 ntype = V_028C70_NUMBER_SNORM;
1196 else if (desc->channel[i].pure_integer)
1197 ntype = V_028C70_NUMBER_SINT;
1198 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1199 if (desc->channel[i].normalized)
1200 ntype = V_028C70_NUMBER_UNORM;
1201 else if (desc->channel[i].pure_integer)
1202 ntype = V_028C70_NUMBER_UINT;
1203 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1204 ntype = V_028C70_NUMBER_FLOAT;
1205 }
1206
1207 if (R600_BIG_ENDIAN)
1208 do_endian_swap = !rtex->db_compatible;
1209
1210 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1211 assert(format != ~0);
1212 swap = r600_translate_colorswap(pformat, do_endian_swap);
1213 assert(swap != ~0);
1214
1215 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1216
1217 /* blend clamp should be set for all NORM/SRGB types */
1218 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1219 ntype == V_028C70_NUMBER_SRGB)
1220 blend_clamp = 1;
1221
1222 /* set blend bypass according to docs if SINT/UINT or
1223 8/24 COLOR variants */
1224 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1225 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1226 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1227 blend_clamp = 0;
1228 blend_bypass = 1;
1229 }
1230
1231 color->ntype = ntype;
1232 color->info |= S_028C70_FORMAT(format) |
1233 S_028C70_COMP_SWAP(swap) |
1234 S_028C70_BLEND_CLAMP(blend_clamp) |
1235 S_028C70_BLEND_BYPASS(blend_bypass) |
1236 S_028C70_SIMPLE_FLOAT(1) |
1237 S_028C70_NUMBER_TYPE(ntype) |
1238 S_028C70_ENDIAN(endian);
1239
1240 if (rtex->fmask.size) {
1241 color->info |= S_028C70_COMPRESSION(1);
1242 }
1243
1244 /* EXPORT_NORM is an optimzation that can be enabled for better
1245 * performance in certain cases.
1246 * EXPORT_NORM can be enabled if:
1247 * - 11-bit or smaller UNORM/SNORM/SRGB
1248 * - 16-bit or smaller FLOAT
1249 */
1250 color->export_16bpc = false;
1251 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1252 ((desc->channel[i].size < 12 &&
1253 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1254 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1255 (desc->channel[i].size < 17 &&
1256 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1257 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1258 color->export_16bpc = true;
1259 }
1260
1261 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1262 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1263
1264 if (rtex->fmask.size) {
1265 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1266 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1267 } else {
1268 color->fmask = color->offset;
1269 color->fmask_slice = S_028C88_TILE_MAX(slice);
1270 }
1271 }
1272
1273 /**
1274 * This function intializes the CB* register values for RATs. It is meant
1275 * to be used for 1D aligned buffers that do not have an associated
1276 * radeon_surf.
1277 */
1278 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1279 struct r600_surface *surf)
1280 {
1281 struct pipe_resource *pipe_buffer = surf->base.texture;
1282 struct r600_tex_color_info color;
1283
1284 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1285 surf->base.format, 0, pipe_buffer->width0,
1286 &color);
1287
1288 surf->cb_color_base = color.offset;
1289 surf->cb_color_dim = color.dim;
1290 surf->cb_color_info = color.info | S_028C70_RAT(1);
1291 surf->cb_color_pitch = color.pitch;
1292 surf->cb_color_slice = color.slice;
1293 surf->cb_color_view = color.view;
1294 surf->cb_color_attrib = color.attrib;
1295 surf->cb_color_fmask = color.fmask;
1296 surf->cb_color_fmask_slice = color.fmask_slice;
1297
1298 surf->cb_color_view = 0;
1299
1300 /* Set the buffer range the GPU will have access to: */
1301 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1302 0, pipe_buffer->width0);
1303 }
1304
1305
1306 void evergreen_init_color_surface(struct r600_context *rctx,
1307 struct r600_surface *surf)
1308 {
1309 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1310 unsigned level = surf->base.u.tex.level;
1311 struct r600_tex_color_info color;
1312
1313 evergreen_set_color_surface_common(rctx, rtex, level,
1314 surf->base.u.tex.first_layer,
1315 surf->base.u.tex.last_layer,
1316 surf->base.format,
1317 &color);
1318
1319 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1320 color.ntype == V_028C70_NUMBER_SINT;
1321 surf->export_16bpc = color.export_16bpc;
1322
1323 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1324 surf->cb_color_base = color.offset;
1325 surf->cb_color_dim = color.dim;
1326 surf->cb_color_info = color.info;
1327 surf->cb_color_pitch = color.pitch;
1328 surf->cb_color_slice = color.slice;
1329 surf->cb_color_view = color.view;
1330 surf->cb_color_attrib = color.attrib;
1331 surf->cb_color_fmask = color.fmask;
1332 surf->cb_color_fmask_slice = color.fmask_slice;
1333
1334 surf->color_initialized = true;
1335 }
1336
1337 static void evergreen_init_depth_surface(struct r600_context *rctx,
1338 struct r600_surface *surf)
1339 {
1340 struct r600_screen *rscreen = rctx->screen;
1341 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1342 unsigned level = surf->base.u.tex.level;
1343 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1344 uint64_t offset;
1345 unsigned format, array_mode;
1346 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1347
1348
1349 format = r600_translate_dbformat(surf->base.format);
1350 assert(format != ~0);
1351
1352 offset = rtex->resource.gpu_address;
1353 offset += rtex->surface.u.legacy.level[level].offset;
1354
1355 switch (rtex->surface.u.legacy.level[level].mode) {
1356 case RADEON_SURF_MODE_2D:
1357 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1358 break;
1359 case RADEON_SURF_MODE_1D:
1360 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1361 default:
1362 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1363 break;
1364 }
1365 tile_split = rtex->surface.u.legacy.tile_split;
1366 macro_aspect = rtex->surface.u.legacy.mtilea;
1367 bankw = rtex->surface.u.legacy.bankw;
1368 bankh = rtex->surface.u.legacy.bankh;
1369 tile_split = eg_tile_split(tile_split);
1370 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1371 bankw = eg_bank_wh(bankw);
1372 bankh = eg_bank_wh(bankh);
1373 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1374 offset >>= 8;
1375
1376 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1377 S_028040_FORMAT(format) |
1378 S_028040_TILE_SPLIT(tile_split)|
1379 S_028040_NUM_BANKS(nbanks) |
1380 S_028040_BANK_WIDTH(bankw) |
1381 S_028040_BANK_HEIGHT(bankh) |
1382 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1383 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1384 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1385 }
1386
1387 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1388
1389 surf->db_depth_base = offset;
1390 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1391 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1392 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1393 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1394 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1395 levelinfo->nblk_y / 64 - 1);
1396
1397 if (rtex->surface.has_stencil) {
1398 uint64_t stencil_offset;
1399 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1400
1401 stile_split = eg_tile_split(stile_split);
1402
1403 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1404 stencil_offset += rtex->resource.gpu_address;
1405
1406 surf->db_stencil_base = stencil_offset >> 8;
1407 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1408 S_028044_TILE_SPLIT(stile_split);
1409 } else {
1410 surf->db_stencil_base = offset;
1411 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1412 * Older kernels are out of luck. */
1413 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1414 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1415 S_028044_FORMAT(V_028044_STENCIL_8);
1416 }
1417
1418 if (r600_htile_enabled(rtex, level)) {
1419 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1420 surf->db_htile_data_base = va >> 8;
1421 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1422 S_028ABC_HTILE_HEIGHT(1) |
1423 S_028ABC_FULL_CACHE(1);
1424 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1425 surf->db_preload_control = 0;
1426 }
1427
1428 surf->depth_initialized = true;
1429 }
1430
1431 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1432 const struct pipe_framebuffer_state *state)
1433 {
1434 struct r600_context *rctx = (struct r600_context *)ctx;
1435 struct r600_surface *surf;
1436 struct r600_texture *rtex;
1437 uint32_t i, log_samples;
1438
1439 /* Flush TC when changing the framebuffer state, because the only
1440 * client not using TC that can change textures is the framebuffer.
1441 * Other places don't typically have to flush TC.
1442 */
1443 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1444 R600_CONTEXT_FLUSH_AND_INV |
1445 R600_CONTEXT_FLUSH_AND_INV_CB |
1446 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1447 R600_CONTEXT_FLUSH_AND_INV_DB |
1448 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1449 R600_CONTEXT_INV_TEX_CACHE;
1450
1451 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1452
1453 /* Colorbuffers. */
1454 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1455 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1456 util_format_is_pure_integer(state->cbufs[0]->format);
1457 rctx->framebuffer.compressed_cb_mask = 0;
1458 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1459
1460 for (i = 0; i < state->nr_cbufs; i++) {
1461 surf = (struct r600_surface*)state->cbufs[i];
1462 if (!surf)
1463 continue;
1464
1465 rtex = (struct r600_texture*)surf->base.texture;
1466
1467 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1468
1469 if (!surf->color_initialized) {
1470 evergreen_init_color_surface(rctx, surf);
1471 }
1472
1473 if (!surf->export_16bpc) {
1474 rctx->framebuffer.export_16bpc = false;
1475 }
1476
1477 if (rtex->fmask.size) {
1478 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1479 }
1480 }
1481
1482 /* Update alpha-test state dependencies.
1483 * Alpha-test is done on the first colorbuffer only. */
1484 if (state->nr_cbufs) {
1485 bool alphatest_bypass = false;
1486 bool export_16bpc = true;
1487
1488 surf = (struct r600_surface*)state->cbufs[0];
1489 if (surf) {
1490 alphatest_bypass = surf->alphatest_bypass;
1491 export_16bpc = surf->export_16bpc;
1492 }
1493
1494 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1495 rctx->alphatest_state.bypass = alphatest_bypass;
1496 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1497 }
1498 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1499 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1500 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1501 }
1502 }
1503
1504 /* ZS buffer. */
1505 if (state->zsbuf) {
1506 surf = (struct r600_surface*)state->zsbuf;
1507
1508 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1509
1510 if (!surf->depth_initialized) {
1511 evergreen_init_depth_surface(rctx, surf);
1512 }
1513
1514 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1515 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1516 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1517 }
1518
1519 if (rctx->db_state.rsurf != surf) {
1520 rctx->db_state.rsurf = surf;
1521 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1522 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1523 }
1524 } else if (rctx->db_state.rsurf) {
1525 rctx->db_state.rsurf = NULL;
1526 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1527 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1528 }
1529
1530 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1531 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1532 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1533 }
1534
1535 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1536 rctx->alphatest_state.bypass = false;
1537 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1538 }
1539
1540 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1541 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1542 if ((rctx->b.chip_class == CAYMAN ||
1543 rctx->b.family == CHIP_RV770) &&
1544 rctx->db_misc_state.log_samples != log_samples) {
1545 rctx->db_misc_state.log_samples = log_samples;
1546 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1547 }
1548
1549
1550 /* Calculate the CS size. */
1551 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1552
1553 /* MSAA. */
1554 if (rctx->b.chip_class == EVERGREEN)
1555 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1556 else
1557 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1558
1559 /* Colorbuffers. */
1560 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1561 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1562 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1563
1564 /* ZS buffer. */
1565 if (state->zsbuf) {
1566 rctx->framebuffer.atom.num_dw += 24;
1567 rctx->framebuffer.atom.num_dw += 2;
1568 } else if (rctx->screen->b.info.drm_minor >= 18) {
1569 rctx->framebuffer.atom.num_dw += 4;
1570 }
1571
1572 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1573
1574 r600_set_sample_locations_constant_buffer(rctx);
1575 rctx->framebuffer.do_update_surf_dirtiness = true;
1576 }
1577
1578 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1579 {
1580 struct r600_context *rctx = (struct r600_context *)ctx;
1581
1582 if (rctx->ps_iter_samples == min_samples)
1583 return;
1584
1585 rctx->ps_iter_samples = min_samples;
1586 if (rctx->framebuffer.nr_samples > 1) {
1587 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1588 }
1589 }
1590
1591 /* 8xMSAA */
1592 static uint32_t sample_locs_8x[] = {
1593 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1594 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1595 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1596 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1597 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1598 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1599 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1600 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1601 };
1602 static unsigned max_dist_8x = 7;
1603
1604 static void evergreen_get_sample_position(struct pipe_context *ctx,
1605 unsigned sample_count,
1606 unsigned sample_index,
1607 float *out_value)
1608 {
1609 int offset, index;
1610 struct {
1611 int idx:4;
1612 } val;
1613 switch (sample_count) {
1614 case 1:
1615 default:
1616 out_value[0] = out_value[1] = 0.5;
1617 break;
1618 case 2:
1619 offset = 4 * (sample_index * 2);
1620 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1621 out_value[0] = (float)(val.idx + 8) / 16.0f;
1622 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1623 out_value[1] = (float)(val.idx + 8) / 16.0f;
1624 break;
1625 case 4:
1626 offset = 4 * (sample_index * 2);
1627 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1628 out_value[0] = (float)(val.idx + 8) / 16.0f;
1629 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1630 out_value[1] = (float)(val.idx + 8) / 16.0f;
1631 break;
1632 case 8:
1633 offset = 4 * (sample_index % 4 * 2);
1634 index = (sample_index / 4);
1635 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1636 out_value[0] = (float)(val.idx + 8) / 16.0f;
1637 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1638 out_value[1] = (float)(val.idx + 8) / 16.0f;
1639 break;
1640 }
1641 }
1642
1643 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1644 {
1645
1646 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1647 unsigned max_dist = 0;
1648
1649 switch (nr_samples) {
1650 default:
1651 nr_samples = 0;
1652 break;
1653 case 2:
1654 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1655 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1656 max_dist = eg_max_dist_2x;
1657 break;
1658 case 4:
1659 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1660 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1661 max_dist = eg_max_dist_4x;
1662 break;
1663 case 8:
1664 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1665 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1666 max_dist = max_dist_8x;
1667 break;
1668 }
1669
1670 if (nr_samples > 1) {
1671 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1672 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1673 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1674 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1675 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1676 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1677 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1678 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1679 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1680 } else {
1681 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1682 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1683 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1684 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1685 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1686 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1687 }
1688 }
1689
1690 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1691 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags)
1692 {
1693 struct r600_image_state *state = (struct r600_image_state *)atom;
1694 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1695 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1696 struct r600_texture *rtex;
1697 struct r600_resource *resource;
1698 int i;
1699
1700 for (i = 0; i < R600_MAX_IMAGES; i++) {
1701 struct r600_image_view *image = &state->views[i];
1702 unsigned reloc, immed_reloc;
1703 int idx = i + offset;
1704
1705 if (!pkt_flags)
1706 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1707 if (!image->base.resource)
1708 continue;
1709
1710 resource = (struct r600_resource *)image->base.resource;
1711 if (resource->b.b.target != PIPE_BUFFER)
1712 rtex = (struct r600_texture *)image->base.resource;
1713 else
1714 rtex = NULL;
1715
1716 reloc = radeon_add_to_buffer_list(&rctx->b,
1717 &rctx->b.gfx,
1718 resource,
1719 RADEON_USAGE_READWRITE,
1720 RADEON_PRIO_SHADER_RW_BUFFER);
1721
1722 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1723 &rctx->b.gfx,
1724 resource->immed_buffer,
1725 RADEON_USAGE_READWRITE,
1726 RADEON_PRIO_SHADER_RW_BUFFER);
1727
1728 if (pkt_flags)
1729 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1730 else
1731 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1732
1733 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1734 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1735 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1736 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1737 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1738 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1739 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1740 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1741 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1742 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1743 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1744 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1745 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1746
1747 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1748 radeon_emit(cs, reloc);
1749
1750 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1751 radeon_emit(cs, reloc);
1752
1753 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1754 radeon_emit(cs, reloc);
1755
1756 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1757 radeon_emit(cs, reloc);
1758
1759 if (pkt_flags)
1760 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1761 else
1762 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1763
1764 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1765 radeon_emit(cs, immed_reloc);
1766
1767 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1768 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1769 radeon_emit_array(cs, image->immed_resource_words, 8);
1770
1771 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1772 radeon_emit(cs, immed_reloc);
1773
1774 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1775 radeon_emit(cs, (res_id_base + i + offset) * 8);
1776 radeon_emit_array(cs, image->resource_words, 8);
1777
1778 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1779 radeon_emit(cs, reloc);
1780
1781 if (!image->skip_mip_address_reloc) {
1782 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1783 radeon_emit(cs, reloc);
1784 }
1785 }
1786 }
1787
1788 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1789 {
1790 evergreen_emit_image_state(rctx, atom,
1791 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1792 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0);
1793 }
1794
1795 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1796 {
1797 evergreen_emit_image_state(rctx, atom,
1798 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1799 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1800 0, RADEON_CP_PACKET3_COMPUTE_MODE);
1801 }
1802
1803 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1804 {
1805 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1806 evergreen_emit_image_state(rctx, atom,
1807 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1808 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0);
1809 }
1810
1811 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1812 {
1813 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1814 evergreen_emit_image_state(rctx, atom,
1815 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1816 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1817 offset, RADEON_CP_PACKET3_COMPUTE_MODE);
1818 }
1819
1820 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1821 {
1822 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1823 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1824 unsigned nr_cbufs = state->nr_cbufs;
1825 unsigned i, tl, br;
1826 struct r600_texture *tex = NULL;
1827 struct r600_surface *cb = NULL;
1828
1829 /* XXX support more colorbuffers once we need them */
1830 assert(nr_cbufs <= 8);
1831 if (nr_cbufs > 8)
1832 nr_cbufs = 8;
1833
1834 /* Colorbuffers. */
1835 for (i = 0; i < nr_cbufs; i++) {
1836 unsigned reloc, cmask_reloc;
1837
1838 cb = (struct r600_surface*)state->cbufs[i];
1839 if (!cb) {
1840 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1841 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1842 continue;
1843 }
1844
1845 tex = (struct r600_texture *)cb->base.texture;
1846 reloc = radeon_add_to_buffer_list(&rctx->b,
1847 &rctx->b.gfx,
1848 (struct r600_resource*)cb->base.texture,
1849 RADEON_USAGE_READWRITE,
1850 tex->resource.b.b.nr_samples > 1 ?
1851 RADEON_PRIO_COLOR_BUFFER_MSAA :
1852 RADEON_PRIO_COLOR_BUFFER);
1853
1854 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1855 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1856 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1857 RADEON_PRIO_CMASK);
1858 } else {
1859 cmask_reloc = reloc;
1860 }
1861
1862 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1863 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1864 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1865 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1866 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1867 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1868 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1869 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1870 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1871 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1872 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1873 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1874 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1875 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1876
1877 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1878 radeon_emit(cs, reloc);
1879
1880 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1881 radeon_emit(cs, reloc);
1882
1883 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1884 radeon_emit(cs, cmask_reloc);
1885
1886 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1887 radeon_emit(cs, reloc);
1888 }
1889 /* set CB_COLOR1_INFO for possible dual-src blending */
1890 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1891 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1892 cb->cb_color_info | tex->cb_color_info);
1893 i++;
1894 }
1895 i += util_bitcount(rctx->fragment_images.enabled_mask);
1896 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1897 for (; i < 8 ; i++)
1898 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1899 for (; i < 12; i++)
1900 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1901
1902 /* ZS buffer. */
1903 if (state->zsbuf) {
1904 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1905 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1906 &rctx->b.gfx,
1907 (struct r600_resource*)state->zsbuf->texture,
1908 RADEON_USAGE_READWRITE,
1909 zb->base.texture->nr_samples > 1 ?
1910 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1911 RADEON_PRIO_DEPTH_BUFFER);
1912
1913 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1914
1915 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1916 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1917 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1918 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1919 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1920 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1921 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1922 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1923 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1924
1925 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1926 radeon_emit(cs, reloc);
1927
1928 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1929 radeon_emit(cs, reloc);
1930
1931 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1932 radeon_emit(cs, reloc);
1933
1934 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1935 radeon_emit(cs, reloc);
1936 } else if (rctx->screen->b.info.drm_minor >= 18) {
1937 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1938 * Older kernels are out of luck. */
1939 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1940 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1941 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1942 }
1943
1944 /* Framebuffer dimensions. */
1945 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1946
1947 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1948 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1949 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1950
1951 if (rctx->b.chip_class == EVERGREEN) {
1952 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1953 } else {
1954 unsigned sc_mode_cntl_1 =
1955 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1956 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1957
1958 if (rctx->framebuffer.nr_samples > 1)
1959 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1960 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1961 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1962 }
1963 }
1964
1965 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1966 {
1967 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1968 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1969 float offset_units = state->offset_units;
1970 float offset_scale = state->offset_scale;
1971 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1972
1973 if (!state->offset_units_unscaled) {
1974 switch (state->zs_format) {
1975 case PIPE_FORMAT_Z24X8_UNORM:
1976 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1977 case PIPE_FORMAT_X8Z24_UNORM:
1978 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1979 offset_units *= 2.0f;
1980 pa_su_poly_offset_db_fmt_cntl =
1981 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1982 break;
1983 case PIPE_FORMAT_Z16_UNORM:
1984 offset_units *= 4.0f;
1985 pa_su_poly_offset_db_fmt_cntl =
1986 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1987 break;
1988 default:
1989 pa_su_poly_offset_db_fmt_cntl =
1990 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1991 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1992 }
1993 }
1994
1995 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1996 radeon_emit(cs, fui(offset_scale));
1997 radeon_emit(cs, fui(offset_units));
1998 radeon_emit(cs, fui(offset_scale));
1999 radeon_emit(cs, fui(offset_units));
2000
2001 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2002 pa_su_poly_offset_db_fmt_cntl);
2003 }
2004
2005 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
2006 unsigned nr_cbufs)
2007 {
2008 unsigned base_mask = 0;
2009 unsigned dirty_mask = a->image_rat_enabled_mask;
2010 while (dirty_mask) {
2011 unsigned idx = u_bit_scan(&dirty_mask);
2012 base_mask |= (0xf << (idx * 4));
2013 }
2014 unsigned offset = util_last_bit(a->image_rat_enabled_mask);
2015 dirty_mask = a->buffer_rat_enabled_mask;
2016 while (dirty_mask) {
2017 unsigned idx = u_bit_scan(&dirty_mask);
2018 base_mask |= (0xf << (idx + offset) * 4);
2019 }
2020 return base_mask << (nr_cbufs * 4);
2021 }
2022
2023 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2024 {
2025 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2026 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2027 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2028 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2029 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
2030 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2031 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
2032 /* This must match the used export instructions exactly.
2033 * Other values may lead to undefined behavior and hangs.
2034 */
2035 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
2036 }
2037
2038 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2039 {
2040 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2041 struct r600_db_state *a = (struct r600_db_state*)atom;
2042
2043 if (a->rsurf && a->rsurf->db_htile_surface) {
2044 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2045 unsigned reloc_idx;
2046
2047 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2048 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2049 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2050 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2051 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2052 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
2053 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2054 radeon_emit(cs, reloc_idx);
2055 } else {
2056 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2057 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2058 }
2059 }
2060
2061 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2062 {
2063 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2064 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2065 unsigned db_render_control = 0;
2066 unsigned db_count_control = 0;
2067 unsigned db_render_override =
2068 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2069 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2070
2071 if (rctx->b.num_occlusion_queries > 0 &&
2072 !a->occlusion_queries_disabled) {
2073 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2074 if (rctx->b.chip_class == CAYMAN) {
2075 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2076 }
2077 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2078 } else {
2079 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2080 }
2081
2082 /* This is to fix a lockup when hyperz and alpha test are enabled at
2083 * the same time somehow GPU get confuse on which order to pick for
2084 * z test
2085 */
2086 if (rctx->alphatest_state.sx_alpha_test_control)
2087 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2088
2089 if (a->flush_depthstencil_through_cb) {
2090 assert(a->copy_depth || a->copy_stencil);
2091
2092 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2093 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2094 S_028000_COPY_CENTROID(1) |
2095 S_028000_COPY_SAMPLE(a->copy_sample);
2096 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2097 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2098 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2099 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2100 }
2101 if (a->htile_clear) {
2102 /* FIXME we might want to disable cliprect here */
2103 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2104 }
2105
2106 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2107 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2108 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2109 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2110 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2111 }
2112
2113 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2114 struct r600_vertexbuf_state *state,
2115 unsigned resource_offset,
2116 unsigned pkt_flags)
2117 {
2118 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2119 uint32_t dirty_mask = state->dirty_mask;
2120
2121 while (dirty_mask) {
2122 struct pipe_vertex_buffer *vb;
2123 struct r600_resource *rbuffer;
2124 uint64_t va;
2125 unsigned buffer_index = u_bit_scan(&dirty_mask);
2126
2127 vb = &state->vb[buffer_index];
2128 rbuffer = (struct r600_resource*)vb->buffer.resource;
2129 assert(rbuffer);
2130
2131 va = rbuffer->gpu_address + vb->buffer_offset;
2132
2133 /* fetch resources start at index 992 */
2134 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2135 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2136 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2137 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2138 radeon_emit(cs, /* RESOURCEi_WORD2 */
2139 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2140 S_030008_STRIDE(vb->stride) |
2141 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2142 radeon_emit(cs, /* RESOURCEi_WORD3 */
2143 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2144 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2145 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2146 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2147 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2148 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2149 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2150 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2151
2152 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2153 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2154 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
2155 }
2156 state->dirty_mask = 0;
2157 }
2158
2159 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2160 {
2161 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2162 }
2163
2164 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2165 {
2166 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2167 RADEON_CP_PACKET3_COMPUTE_MODE);
2168 }
2169
2170 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2171 struct r600_constbuf_state *state,
2172 unsigned buffer_id_base,
2173 unsigned reg_alu_constbuf_size,
2174 unsigned reg_alu_const_cache,
2175 unsigned pkt_flags)
2176 {
2177 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2178 uint32_t dirty_mask = state->dirty_mask;
2179
2180 while (dirty_mask) {
2181 struct pipe_constant_buffer *cb;
2182 struct r600_resource *rbuffer;
2183 uint64_t va;
2184 unsigned buffer_index = ffs(dirty_mask) - 1;
2185 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2186
2187 cb = &state->cb[buffer_index];
2188 rbuffer = (struct r600_resource*)cb->buffer;
2189 assert(rbuffer);
2190
2191 va = rbuffer->gpu_address + cb->buffer_offset;
2192
2193 if (buffer_index < R600_MAX_HW_CONST_BUFFERS) {
2194 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2195 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2196 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2197 pkt_flags);
2198 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2199 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2200 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2201 }
2202
2203 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2204 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2205 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2206 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2207 radeon_emit(cs, /* RESOURCEi_WORD2 */
2208 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2209 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2210 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2211 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2212 radeon_emit(cs, /* RESOURCEi_WORD3 */
2213 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2214 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2215 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2216 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2217 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2218 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2219 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2220 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2221 radeon_emit(cs, /* RESOURCEi_WORD7 */
2222 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2223
2224 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2225 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2226 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2227
2228 dirty_mask &= ~(1 << buffer_index);
2229 }
2230 state->dirty_mask = 0;
2231 }
2232
2233 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2234 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2235 {
2236 if (rctx->vs_shader->current->shader.vs_as_ls) {
2237 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2238 EG_FETCH_CONSTANTS_OFFSET_LS,
2239 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2240 R_028F40_ALU_CONST_CACHE_LS_0,
2241 0 /* PKT3 flags */);
2242 } else {
2243 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2244 EG_FETCH_CONSTANTS_OFFSET_VS,
2245 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2246 R_028980_ALU_CONST_CACHE_VS_0,
2247 0 /* PKT3 flags */);
2248 }
2249 }
2250
2251 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2252 {
2253 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2254 EG_FETCH_CONSTANTS_OFFSET_GS,
2255 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2256 R_0289C0_ALU_CONST_CACHE_GS_0,
2257 0 /* PKT3 flags */);
2258 }
2259
2260 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2261 {
2262 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2263 EG_FETCH_CONSTANTS_OFFSET_PS,
2264 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2265 R_028940_ALU_CONST_CACHE_PS_0,
2266 0 /* PKT3 flags */);
2267 }
2268
2269 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2270 {
2271 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2272 EG_FETCH_CONSTANTS_OFFSET_CS,
2273 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2274 R_028F40_ALU_CONST_CACHE_LS_0,
2275 RADEON_CP_PACKET3_COMPUTE_MODE);
2276 }
2277
2278 /* tes constants can be emitted to VS or ES - which are common */
2279 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2280 {
2281 if (!rctx->tes_shader)
2282 return;
2283 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2284 EG_FETCH_CONSTANTS_OFFSET_VS,
2285 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2286 R_028980_ALU_CONST_CACHE_VS_0,
2287 0);
2288 }
2289
2290 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2291 {
2292 if (!rctx->tes_shader)
2293 return;
2294 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2295 EG_FETCH_CONSTANTS_OFFSET_HS,
2296 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2297 R_028F00_ALU_CONST_CACHE_HS_0,
2298 0);
2299 }
2300
2301 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2302 struct r600_samplerview_state *state,
2303 unsigned resource_id_base, unsigned pkt_flags)
2304 {
2305 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2306 uint32_t dirty_mask = state->dirty_mask;
2307
2308 while (dirty_mask) {
2309 struct r600_pipe_sampler_view *rview;
2310 unsigned resource_index = u_bit_scan(&dirty_mask);
2311 unsigned reloc;
2312
2313 rview = state->views[resource_index];
2314 assert(rview);
2315
2316 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2317 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2318 radeon_emit_array(cs, rview->tex_resource_words, 8);
2319
2320 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2321 RADEON_USAGE_READ,
2322 r600_get_sampler_view_priority(rview->tex_resource));
2323 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2324 radeon_emit(cs, reloc);
2325
2326 if (!rview->skip_mip_address_reloc) {
2327 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2328 radeon_emit(cs, reloc);
2329 }
2330 }
2331 state->dirty_mask = 0;
2332 }
2333
2334 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2335 {
2336 if (rctx->vs_shader->current->shader.vs_as_ls) {
2337 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2338 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2339 } else {
2340 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2341 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2342 }
2343 }
2344
2345 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2346 {
2347 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2348 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2349 }
2350
2351 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2352 {
2353 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2354 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2355 }
2356
2357 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2358 {
2359 if (!rctx->tes_shader)
2360 return;
2361 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2362 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2363 }
2364
2365 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2366 {
2367 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2368 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2369 }
2370
2371 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2372 {
2373 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2374 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
2375 }
2376
2377 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2378 struct r600_textures_info *texinfo,
2379 unsigned resource_id_base,
2380 unsigned border_index_reg,
2381 unsigned pkt_flags)
2382 {
2383 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2384 uint32_t dirty_mask = texinfo->states.dirty_mask;
2385
2386 while (dirty_mask) {
2387 struct r600_pipe_sampler_state *rstate;
2388 unsigned i = u_bit_scan(&dirty_mask);
2389
2390 rstate = texinfo->states.states[i];
2391 assert(rstate);
2392
2393 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2394 radeon_emit(cs, (resource_id_base + i) * 3);
2395 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2396
2397 if (rstate->border_color_use) {
2398 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2399 radeon_emit(cs, i);
2400 radeon_emit_array(cs, rstate->border_color.ui, 4);
2401 }
2402 }
2403 texinfo->states.dirty_mask = 0;
2404 }
2405
2406 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2407 {
2408 if (rctx->vs_shader->current->shader.vs_as_ls) {
2409 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2410 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2411 } else {
2412 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2413 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2414 }
2415 }
2416
2417 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2418 {
2419 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2420 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2421 }
2422
2423 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2424 {
2425 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2426 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2427 }
2428
2429 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2430 {
2431 if (!rctx->tes_shader)
2432 return;
2433 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2434 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2435 }
2436
2437 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2438 {
2439 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2440 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2441 }
2442
2443 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2444 {
2445 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2446 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2447 RADEON_CP_PACKET3_COMPUTE_MODE);
2448 }
2449
2450 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2451 {
2452 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2453 uint8_t mask = s->sample_mask;
2454
2455 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2456 mask | (mask << 8) | (mask << 16) | (mask << 24));
2457 }
2458
2459 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2460 {
2461 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2462 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2463 uint16_t mask = s->sample_mask;
2464
2465 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2466 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2467 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2468 }
2469
2470 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2471 {
2472 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2473 struct r600_cso_state *state = (struct r600_cso_state*)a;
2474 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2475
2476 if (!shader)
2477 return;
2478
2479 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2480 (shader->buffer->gpu_address + shader->offset) >> 8);
2481 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2482 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2483 RADEON_USAGE_READ,
2484 RADEON_PRIO_SHADER_BINARY));
2485 }
2486
2487 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2488 {
2489 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2490 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2491
2492 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2493
2494 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2495 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2496 primid = 1;
2497 }
2498
2499 if (state->geom_enable) {
2500 uint32_t cut_val;
2501
2502 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2503 cut_val = V_028A40_GS_CUT_128;
2504 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2505 cut_val = V_028A40_GS_CUT_256;
2506 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2507 cut_val = V_028A40_GS_CUT_512;
2508 else
2509 cut_val = V_028A40_GS_CUT_1024;
2510
2511 v = S_028B54_GS_EN(1) |
2512 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2513 if (!rctx->tes_shader)
2514 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2515
2516 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2517 S_028A40_CUT_MODE(cut_val);
2518
2519 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2520 primid = 1;
2521 }
2522
2523 if (rctx->tes_shader) {
2524 uint32_t type, partitioning, topology;
2525 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2526 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2527 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2528 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2529 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2530 switch (tes_prim_mode) {
2531 case PIPE_PRIM_LINES:
2532 type = V_028B6C_TESS_ISOLINE;
2533 break;
2534 case PIPE_PRIM_TRIANGLES:
2535 type = V_028B6C_TESS_TRIANGLE;
2536 break;
2537 case PIPE_PRIM_QUADS:
2538 type = V_028B6C_TESS_QUAD;
2539 break;
2540 default:
2541 assert(0);
2542 return;
2543 }
2544
2545 switch (tes_spacing) {
2546 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2547 partitioning = V_028B6C_PART_FRAC_ODD;
2548 break;
2549 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2550 partitioning = V_028B6C_PART_FRAC_EVEN;
2551 break;
2552 case PIPE_TESS_SPACING_EQUAL:
2553 partitioning = V_028B6C_PART_INTEGER;
2554 break;
2555 default:
2556 assert(0);
2557 return;
2558 }
2559
2560 if (tes_point_mode)
2561 topology = V_028B6C_OUTPUT_POINT;
2562 else if (tes_prim_mode == PIPE_PRIM_LINES)
2563 topology = V_028B6C_OUTPUT_LINE;
2564 else if (tes_vertex_order_cw)
2565 /* XXX follow radeonsi and invert */
2566 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2567 else
2568 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2569
2570 tf_param = S_028B6C_TYPE(type) |
2571 S_028B6C_PARTITIONING(partitioning) |
2572 S_028B6C_TOPOLOGY(topology);
2573 }
2574
2575 if (rctx->tes_shader) {
2576 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2577 S_028B54_HS_EN(1);
2578 if (!state->geom_enable)
2579 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2580 else
2581 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2582 }
2583
2584 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2585 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2586 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2587 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2588 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2589 }
2590
2591 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2592 {
2593 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2594 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2595 struct r600_resource *rbuffer;
2596
2597 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2598 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2599 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2600
2601 if (state->enable) {
2602 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2603 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2604 rbuffer->gpu_address >> 8);
2605 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2606 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2607 RADEON_USAGE_READWRITE,
2608 RADEON_PRIO_SHADER_RINGS));
2609 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2610 state->esgs_ring.buffer_size >> 8);
2611
2612 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2613 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2614 rbuffer->gpu_address >> 8);
2615 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2616 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2617 RADEON_USAGE_READWRITE,
2618 RADEON_PRIO_SHADER_RINGS));
2619 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2620 state->gsvs_ring.buffer_size >> 8);
2621 } else {
2622 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2623 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2624 }
2625
2626 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2627 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2628 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2629 }
2630
2631 void cayman_init_common_regs(struct r600_command_buffer *cb,
2632 enum chip_class ctx_chip_class,
2633 enum radeon_family ctx_family,
2634 int ctx_drm_minor)
2635 {
2636 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2637 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2638 /* always set the temp clauses */
2639 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2640
2641 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2642 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2643 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2644
2645 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2646
2647 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2648 r600_store_value(cb, 0);
2649 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2650
2651 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2652 }
2653
2654 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2655 {
2656 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2657 int i;
2658
2659 r600_init_command_buffer(cb, 338);
2660
2661 /* This must be first. */
2662 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2663 r600_store_value(cb, 0x80000000);
2664 r600_store_value(cb, 0x80000000);
2665
2666 /* We're setting config registers here. */
2667 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2668 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2669
2670 /* This enables pipeline stat & streamout queries.
2671 * They are only disabled by blits.
2672 */
2673 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2674 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2675
2676 cayman_init_common_regs(cb, rctx->b.chip_class,
2677 rctx->b.family, rctx->screen->b.info.drm_minor);
2678
2679 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2680 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2681
2682 /* remove LS/HS from one SIMD for hw workaround */
2683 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2684 r600_store_value(cb, 0xffffffff);
2685 r600_store_value(cb, 0xffffffff);
2686 r600_store_value(cb, 0xfffffffe);
2687
2688 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2689 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2690 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2691 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2692 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2693 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2694 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2695
2696 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2697 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2698 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2699 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2700 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2701
2702 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2703 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2704 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2705 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2706 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2707 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2708 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2709 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2710 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2711 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2712 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2713 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2714 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2715 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2716
2717 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2718
2719 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2720
2721 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2722 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2723 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2724
2725 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2726 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2727 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2728 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2729
2730 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2731
2732 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2733 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2734 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2735
2736 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2737
2738 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2739
2740 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2741
2742 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2743 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2744 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2745 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2746
2747 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2748 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2749
2750 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2751 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2752
2753 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2754 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2755 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2756
2757 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2758 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2759 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2760
2761 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2762 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2763 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2764 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2765 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2766 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2767
2768 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2769
2770 /* to avoid GPU doing any preloading of constant from random address */
2771 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2772 for (i = 0; i < 16; i++)
2773 r600_store_value(cb, 0);
2774
2775 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2776 for (i = 0; i < 16; i++)
2777 r600_store_value(cb, 0);
2778
2779 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2780 for (i = 0; i < 16; i++)
2781 r600_store_value(cb, 0);
2782
2783 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2784 for (i = 0; i < 16; i++)
2785 r600_store_value(cb, 0);
2786
2787 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2788 for (i = 0; i < 16; i++)
2789 r600_store_value(cb, 0);
2790
2791 if (rctx->screen->b.has_streamout) {
2792 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2793 }
2794
2795 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2796 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2797 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2798 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2799 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2800 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2801
2802 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2803 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2804 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2805 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2806 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2807 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2808 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2809 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2810 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2811 }
2812
2813 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2814 enum chip_class ctx_chip_class,
2815 enum radeon_family ctx_family,
2816 int ctx_drm_minor)
2817 {
2818 int ps_prio;
2819 int vs_prio;
2820 int gs_prio;
2821 int es_prio;
2822
2823 int hs_prio;
2824 int cs_prio;
2825 int ls_prio;
2826
2827 unsigned tmp;
2828
2829 ps_prio = 0;
2830 vs_prio = 1;
2831 gs_prio = 2;
2832 es_prio = 3;
2833 hs_prio = 3;
2834 ls_prio = 3;
2835 cs_prio = 0;
2836
2837 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2838 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2839 rctx->r6xx_num_clause_temp_gprs = 4;
2840 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2841 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2842 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2843 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2844
2845 tmp = 0;
2846 switch (ctx_family) {
2847 case CHIP_CEDAR:
2848 case CHIP_PALM:
2849 case CHIP_SUMO:
2850 case CHIP_SUMO2:
2851 case CHIP_CAICOS:
2852 break;
2853 default:
2854 tmp |= S_008C00_VC_ENABLE(1);
2855 break;
2856 }
2857 tmp |= S_008C00_EXPORT_SRC_C(1);
2858 tmp |= S_008C00_CS_PRIO(cs_prio);
2859 tmp |= S_008C00_LS_PRIO(ls_prio);
2860 tmp |= S_008C00_HS_PRIO(hs_prio);
2861 tmp |= S_008C00_PS_PRIO(ps_prio);
2862 tmp |= S_008C00_VS_PRIO(vs_prio);
2863 tmp |= S_008C00_GS_PRIO(gs_prio);
2864 tmp |= S_008C00_ES_PRIO(es_prio);
2865
2866 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2867 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2868
2869 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2870 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2871 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2872
2873 /* The cs checker requires this register to be set. */
2874 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2875
2876 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2877 r600_store_value(cb, 0);
2878 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2879
2880 return;
2881 }
2882
2883 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2884 {
2885 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2886 int num_ps_threads;
2887 int num_vs_threads;
2888 int num_gs_threads;
2889 int num_es_threads;
2890 int num_hs_threads;
2891 int num_ls_threads;
2892
2893 int num_ps_stack_entries;
2894 int num_vs_stack_entries;
2895 int num_gs_stack_entries;
2896 int num_es_stack_entries;
2897 int num_hs_stack_entries;
2898 int num_ls_stack_entries;
2899 enum radeon_family family;
2900 unsigned tmp, i;
2901
2902 if (rctx->b.chip_class == CAYMAN) {
2903 cayman_init_atom_start_cs(rctx);
2904 return;
2905 }
2906
2907 r600_init_command_buffer(cb, 338);
2908
2909 /* This must be first. */
2910 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2911 r600_store_value(cb, 0x80000000);
2912 r600_store_value(cb, 0x80000000);
2913
2914 /* We're setting config registers here. */
2915 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2916 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2917
2918 /* This enables pipeline stat & streamout queries.
2919 * They are only disabled by blits.
2920 */
2921 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2922 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2923
2924 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2925 rctx->b.family, rctx->screen->b.info.drm_minor);
2926
2927 family = rctx->b.family;
2928 switch (family) {
2929 case CHIP_CEDAR:
2930 default:
2931 num_ps_threads = 96;
2932 num_vs_threads = 16;
2933 num_gs_threads = 16;
2934 num_es_threads = 16;
2935 num_hs_threads = 16;
2936 num_ls_threads = 16;
2937 num_ps_stack_entries = 42;
2938 num_vs_stack_entries = 42;
2939 num_gs_stack_entries = 42;
2940 num_es_stack_entries = 42;
2941 num_hs_stack_entries = 42;
2942 num_ls_stack_entries = 42;
2943 break;
2944 case CHIP_REDWOOD:
2945 num_ps_threads = 128;
2946 num_vs_threads = 20;
2947 num_gs_threads = 20;
2948 num_es_threads = 20;
2949 num_hs_threads = 20;
2950 num_ls_threads = 20;
2951 num_ps_stack_entries = 42;
2952 num_vs_stack_entries = 42;
2953 num_gs_stack_entries = 42;
2954 num_es_stack_entries = 42;
2955 num_hs_stack_entries = 42;
2956 num_ls_stack_entries = 42;
2957 break;
2958 case CHIP_JUNIPER:
2959 num_ps_threads = 128;
2960 num_vs_threads = 20;
2961 num_gs_threads = 20;
2962 num_es_threads = 20;
2963 num_hs_threads = 20;
2964 num_ls_threads = 20;
2965 num_ps_stack_entries = 85;
2966 num_vs_stack_entries = 85;
2967 num_gs_stack_entries = 85;
2968 num_es_stack_entries = 85;
2969 num_hs_stack_entries = 85;
2970 num_ls_stack_entries = 85;
2971 break;
2972 case CHIP_CYPRESS:
2973 case CHIP_HEMLOCK:
2974 num_ps_threads = 128;
2975 num_vs_threads = 20;
2976 num_gs_threads = 20;
2977 num_es_threads = 20;
2978 num_hs_threads = 20;
2979 num_ls_threads = 20;
2980 num_ps_stack_entries = 85;
2981 num_vs_stack_entries = 85;
2982 num_gs_stack_entries = 85;
2983 num_es_stack_entries = 85;
2984 num_hs_stack_entries = 85;
2985 num_ls_stack_entries = 85;
2986 break;
2987 case CHIP_PALM:
2988 num_ps_threads = 96;
2989 num_vs_threads = 16;
2990 num_gs_threads = 16;
2991 num_es_threads = 16;
2992 num_hs_threads = 16;
2993 num_ls_threads = 16;
2994 num_ps_stack_entries = 42;
2995 num_vs_stack_entries = 42;
2996 num_gs_stack_entries = 42;
2997 num_es_stack_entries = 42;
2998 num_hs_stack_entries = 42;
2999 num_ls_stack_entries = 42;
3000 break;
3001 case CHIP_SUMO:
3002 num_ps_threads = 96;
3003 num_vs_threads = 25;
3004 num_gs_threads = 25;
3005 num_es_threads = 25;
3006 num_hs_threads = 16;
3007 num_ls_threads = 16;
3008 num_ps_stack_entries = 42;
3009 num_vs_stack_entries = 42;
3010 num_gs_stack_entries = 42;
3011 num_es_stack_entries = 42;
3012 num_hs_stack_entries = 42;
3013 num_ls_stack_entries = 42;
3014 break;
3015 case CHIP_SUMO2:
3016 num_ps_threads = 96;
3017 num_vs_threads = 25;
3018 num_gs_threads = 25;
3019 num_es_threads = 25;
3020 num_hs_threads = 16;
3021 num_ls_threads = 16;
3022 num_ps_stack_entries = 85;
3023 num_vs_stack_entries = 85;
3024 num_gs_stack_entries = 85;
3025 num_es_stack_entries = 85;
3026 num_hs_stack_entries = 85;
3027 num_ls_stack_entries = 85;
3028 break;
3029 case CHIP_BARTS:
3030 num_ps_threads = 128;
3031 num_vs_threads = 20;
3032 num_gs_threads = 20;
3033 num_es_threads = 20;
3034 num_hs_threads = 20;
3035 num_ls_threads = 20;
3036 num_ps_stack_entries = 85;
3037 num_vs_stack_entries = 85;
3038 num_gs_stack_entries = 85;
3039 num_es_stack_entries = 85;
3040 num_hs_stack_entries = 85;
3041 num_ls_stack_entries = 85;
3042 break;
3043 case CHIP_TURKS:
3044 num_ps_threads = 128;
3045 num_vs_threads = 20;
3046 num_gs_threads = 20;
3047 num_es_threads = 20;
3048 num_hs_threads = 20;
3049 num_ls_threads = 20;
3050 num_ps_stack_entries = 42;
3051 num_vs_stack_entries = 42;
3052 num_gs_stack_entries = 42;
3053 num_es_stack_entries = 42;
3054 num_hs_stack_entries = 42;
3055 num_ls_stack_entries = 42;
3056 break;
3057 case CHIP_CAICOS:
3058 num_ps_threads = 96;
3059 num_vs_threads = 10;
3060 num_gs_threads = 10;
3061 num_es_threads = 10;
3062 num_hs_threads = 10;
3063 num_ls_threads = 10;
3064 num_ps_stack_entries = 42;
3065 num_vs_stack_entries = 42;
3066 num_gs_stack_entries = 42;
3067 num_es_stack_entries = 42;
3068 num_hs_stack_entries = 42;
3069 num_ls_stack_entries = 42;
3070 break;
3071 }
3072
3073 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3074 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3075 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3076 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3077
3078 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3079 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3080
3081 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3082 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3083 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3084
3085 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3086 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3087 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3088
3089 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3090 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3091 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3092
3093 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3094 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3095 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3096
3097 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3098 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3099
3100 /* remove LS/HS from one SIMD for hw workaround */
3101 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3102 r600_store_value(cb, 0xffffffff);
3103 r600_store_value(cb, 0xffffffff);
3104 r600_store_value(cb, 0xfffffffe);
3105
3106 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3107 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3108
3109 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3110 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3111 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3112 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3113 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3114 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3115 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3116
3117 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3118 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3119 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3120 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3121 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3122
3123 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3124 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3125 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3126 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3127 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3128 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3129 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3130 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3131 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3132 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3133 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3134 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3135 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3136 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3137
3138 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3139
3140 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3141
3142 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3143 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3144 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3145
3146 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3147
3148 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3149
3150 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3151 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3152 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3153
3154 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3155 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3156
3157 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3158 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3159 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3160 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3161
3162 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3163 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3164 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3165
3166 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3167 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3168 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3169
3170 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3171 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3172 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3173 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3174 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3175 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3176 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3177
3178 /* to avoid GPU doing any preloading of constant from random address */
3179 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3180 for (i = 0; i < 16; i++)
3181 r600_store_value(cb, 0);
3182
3183 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3184 for (i = 0; i < 16; i++)
3185 r600_store_value(cb, 0);
3186
3187 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3188 for (i = 0; i < 16; i++)
3189 r600_store_value(cb, 0);
3190
3191 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3192 for (i = 0; i < 16; i++)
3193 r600_store_value(cb, 0);
3194
3195 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3196 for (i = 0; i < 16; i++)
3197 r600_store_value(cb, 0);
3198
3199 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3200
3201 if (rctx->screen->b.has_streamout) {
3202 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3203 }
3204
3205 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3206 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3207 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3208 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3209 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3210 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3211
3212 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3213 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3214 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3215
3216 if (rctx->b.family == CHIP_CAICOS) {
3217 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3218 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3219 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3220 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3221 } else {
3222 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3223 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3224 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3225 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3226 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3227 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3228 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3229 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3230 }
3231
3232 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3233 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3234 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3235 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3236 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3237 }
3238
3239 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3240 {
3241 struct r600_context *rctx = (struct r600_context *)ctx;
3242 struct r600_command_buffer *cb = &shader->command_buffer;
3243 struct r600_shader *rshader = &shader->shader;
3244 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3245 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3246 int ninterp = 0;
3247 boolean have_perspective = FALSE, have_linear = FALSE;
3248 static const unsigned spi_baryc_enable_bit[6] = {
3249 S_0286E0_PERSP_SAMPLE_ENA(1),
3250 S_0286E0_PERSP_CENTER_ENA(1),
3251 S_0286E0_PERSP_CENTROID_ENA(1),
3252 S_0286E0_LINEAR_SAMPLE_ENA(1),
3253 S_0286E0_LINEAR_CENTER_ENA(1),
3254 S_0286E0_LINEAR_CENTROID_ENA(1)
3255 };
3256 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3257 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3258 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3259 uint32_t spi_ps_input_cntl[32];
3260
3261 if (!cb->buf) {
3262 r600_init_command_buffer(cb, 64);
3263 } else {
3264 cb->num_dw = 0;
3265 }
3266
3267 for (i = 0; i < rshader->ninput; i++) {
3268 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3269 POSITION goes via GPRs from the SC so isn't counted */
3270 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3271 pos_index = i;
3272 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3273 if (face_index == -1)
3274 face_index = i;
3275 }
3276 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3277 if (face_index == -1)
3278 face_index = i; /* lives in same register, same enable bit */
3279 }
3280 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3281 fixed_pt_position_index = i;
3282 }
3283 else {
3284 ninterp++;
3285 int k = eg_get_interpolator_index(
3286 rshader->input[i].interpolate,
3287 rshader->input[i].interpolate_location);
3288 if (k >= 0) {
3289 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3290 have_perspective |= k < 3;
3291 have_linear |= !(k < 3);
3292 }
3293 }
3294
3295 sid = rshader->input[i].spi_sid;
3296
3297 if (sid) {
3298 tmp = S_028644_SEMANTIC(sid);
3299
3300 /* D3D 9 behaviour. GL is undefined */
3301 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3302 tmp |= S_028644_DEFAULT_VAL(3);
3303
3304 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3305 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3306 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3307 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3308 tmp |= S_028644_FLAT_SHADE(1);
3309 }
3310
3311 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3312 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3313 tmp |= S_028644_PT_SPRITE_TEX(1);
3314 }
3315
3316 spi_ps_input_cntl[num++] = tmp;
3317 }
3318 }
3319
3320 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3321 r600_store_array(cb, num, spi_ps_input_cntl);
3322
3323 for (i = 0; i < rshader->noutput; i++) {
3324 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3325 z_export = 1;
3326 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3327 stencil_export = 1;
3328 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3329 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3330 mask_export = 1;
3331 }
3332 if (rshader->uses_kill)
3333 db_shader_control |= S_02880C_KILL_ENABLE(1);
3334
3335 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3336 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3337 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3338
3339 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3340 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3341 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3342 } else if (shader->selector->info.writes_memory) {
3343 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3344 }
3345
3346 switch (rshader->ps_conservative_z) {
3347 default: /* fall through */
3348 case TGSI_FS_DEPTH_LAYOUT_ANY:
3349 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3350 break;
3351 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3352 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3353 break;
3354 case TGSI_FS_DEPTH_LAYOUT_LESS:
3355 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3356 break;
3357 }
3358
3359 exports_ps = 0;
3360 for (i = 0; i < rshader->noutput; i++) {
3361 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3362 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3363 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3364 exports_ps |= 1;
3365 }
3366
3367 num_cout = rshader->nr_ps_color_exports;
3368
3369 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3370 if (!exports_ps) {
3371 /* always at least export 1 component per pixel */
3372 exports_ps = 2;
3373 }
3374 shader->nr_ps_color_outputs = num_cout;
3375 if (ninterp == 0) {
3376 ninterp = 1;
3377 have_perspective = TRUE;
3378 }
3379 if (!spi_baryc_cntl)
3380 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3381
3382 if (!have_perspective && !have_linear)
3383 have_perspective = TRUE;
3384
3385 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3386 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3387 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3388 spi_input_z = 0;
3389 if (pos_index != -1) {
3390 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3391 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3392 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3393 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3394 }
3395
3396 spi_ps_in_control_1 = 0;
3397 if (face_index != -1) {
3398 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3399 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3400 }
3401 if (fixed_pt_position_index != -1) {
3402 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3403 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3404 }
3405
3406 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3407 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3408 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3409
3410 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3411 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3412 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3413
3414 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3415 r600_store_value(cb, shader->bo->gpu_address >> 8);
3416 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3417 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3418 S_028844_PRIME_CACHE_ON_DRAW(1) |
3419 S_028844_DX10_CLAMP(1) |
3420 S_028844_STACK_SIZE(rshader->bc.nstack));
3421 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3422
3423 shader->db_shader_control = db_shader_control;
3424 shader->ps_depth_export = z_export | stencil_export | mask_export;
3425
3426 shader->sprite_coord_enable = sprite_coord_enable;
3427 if (rctx->rasterizer)
3428 shader->flatshade = rctx->rasterizer->flatshade;
3429 }
3430
3431 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3432 {
3433 struct r600_command_buffer *cb = &shader->command_buffer;
3434 struct r600_shader *rshader = &shader->shader;
3435
3436 r600_init_command_buffer(cb, 32);
3437
3438 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3439 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3440 S_028890_DX10_CLAMP(1) |
3441 S_028890_STACK_SIZE(rshader->bc.nstack));
3442 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3443 shader->bo->gpu_address >> 8);
3444 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3445 }
3446
3447 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3448 {
3449 struct r600_context *rctx = (struct r600_context *)ctx;
3450 struct r600_command_buffer *cb = &shader->command_buffer;
3451 struct r600_shader *rshader = &shader->shader;
3452 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3453 unsigned gsvs_itemsizes[4] = {
3454 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3455 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3456 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3457 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3458 };
3459
3460 r600_init_command_buffer(cb, 64);
3461
3462 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3463
3464
3465 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3466 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3467 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3468 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3469
3470 if (rctx->screen->b.info.drm_minor >= 35) {
3471 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3472 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3473 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3474 }
3475 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3476 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3477 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3478 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3479 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3480
3481 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3482 (rshader->ring_item_sizes[0]) >> 2);
3483
3484 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3485 gsvs_itemsizes[0] +
3486 gsvs_itemsizes[1] +
3487 gsvs_itemsizes[2] +
3488 gsvs_itemsizes[3]);
3489
3490 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3491 r600_store_value(cb, gsvs_itemsizes[0]);
3492 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3493 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3494
3495 /* FIXME calculate these values somehow ??? */
3496 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3497 r600_store_value(cb, 0x80); /* GS_PER_ES */
3498 r600_store_value(cb, 0x100); /* ES_PER_GS */
3499 r600_store_value(cb, 0x2); /* GS_PER_VS */
3500
3501 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3502 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3503 S_028878_DX10_CLAMP(1) |
3504 S_028878_STACK_SIZE(rshader->bc.nstack));
3505 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3506 shader->bo->gpu_address >> 8);
3507 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3508 }
3509
3510
3511 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3512 {
3513 struct r600_command_buffer *cb = &shader->command_buffer;
3514 struct r600_shader *rshader = &shader->shader;
3515 unsigned spi_vs_out_id[10] = {};
3516 unsigned i, tmp, nparams = 0;
3517
3518 for (i = 0; i < rshader->noutput; i++) {
3519 if (rshader->output[i].spi_sid) {
3520 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3521 spi_vs_out_id[nparams / 4] |= tmp;
3522 nparams++;
3523 }
3524 }
3525
3526 r600_init_command_buffer(cb, 32);
3527
3528 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3529 for (i = 0; i < 10; i++) {
3530 r600_store_value(cb, spi_vs_out_id[i]);
3531 }
3532
3533 /* Certain attributes (position, psize, etc.) don't count as params.
3534 * VS is required to export at least one param and r600_shader_from_tgsi()
3535 * takes care of adding a dummy export.
3536 */
3537 if (nparams < 1)
3538 nparams = 1;
3539
3540 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3541 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3542 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3543 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3544 S_028860_DX10_CLAMP(1) |
3545 S_028860_STACK_SIZE(rshader->bc.nstack));
3546 if (rshader->vs_position_window_space) {
3547 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3548 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3549 } else {
3550 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3551 S_028818_VTX_W0_FMT(1) |
3552 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3553 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3554 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3555
3556 }
3557 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3558 shader->bo->gpu_address >> 8);
3559 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3560
3561 shader->pa_cl_vs_out_cntl =
3562 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3563 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3564 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3565 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3566 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3567 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3568 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3569 }
3570
3571 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3572 {
3573 struct r600_command_buffer *cb = &shader->command_buffer;
3574 struct r600_shader *rshader = &shader->shader;
3575
3576 r600_init_command_buffer(cb, 32);
3577 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3578 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3579 S_0288BC_DX10_CLAMP(1) |
3580 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3581 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3582 shader->bo->gpu_address >> 8);
3583 }
3584
3585 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3586 {
3587 struct r600_command_buffer *cb = &shader->command_buffer;
3588 struct r600_shader *rshader = &shader->shader;
3589
3590 r600_init_command_buffer(cb, 32);
3591 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3592 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3593 S_0288D4_DX10_CLAMP(1) |
3594 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3595 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3596 shader->bo->gpu_address >> 8);
3597 }
3598 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3599 {
3600 struct pipe_blend_state blend;
3601
3602 memset(&blend, 0, sizeof(blend));
3603 blend.independent_blend_enable = true;
3604 blend.rt[0].colormask = 0xf;
3605 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3606 }
3607
3608 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3609 {
3610 struct pipe_blend_state blend;
3611 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3612 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3613
3614 memset(&blend, 0, sizeof(blend));
3615 blend.independent_blend_enable = true;
3616 blend.rt[0].colormask = 0xf;
3617 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3618 }
3619
3620 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3621 {
3622 struct pipe_blend_state blend;
3623 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3624
3625 memset(&blend, 0, sizeof(blend));
3626 blend.independent_blend_enable = true;
3627 blend.rt[0].colormask = 0xf;
3628 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3629 }
3630
3631 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3632 {
3633 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3634
3635 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3636 }
3637
3638 void evergreen_update_db_shader_control(struct r600_context * rctx)
3639 {
3640 bool dual_export;
3641 unsigned db_shader_control;
3642
3643 if (!rctx->ps_shader) {
3644 return;
3645 }
3646
3647 dual_export = rctx->framebuffer.export_16bpc &&
3648 !rctx->ps_shader->current->ps_depth_export;
3649
3650 db_shader_control = rctx->ps_shader->current->db_shader_control |
3651 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3652 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3653 V_02880C_EXPORT_DB_FULL) |
3654 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3655
3656 /* When alpha test is enabled we can't trust the hw to make the proper
3657 * decision on the order in which ztest should be run related to fragment
3658 * shader execution.
3659 *
3660 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3661 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3662 * execution and thus after alpha test so if discarded by the alpha test
3663 * the z value is not written.
3664 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3665 * get a hang unless you flush the DB in between. For now just use
3666 * LATE_Z.
3667 */
3668 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3669 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3670 } else {
3671 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3672 }
3673
3674 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3675 rctx->db_misc_state.db_shader_control = db_shader_control;
3676 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3677 }
3678 }
3679
3680 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3681 struct pipe_resource *dst,
3682 unsigned dst_level,
3683 unsigned dst_x,
3684 unsigned dst_y,
3685 unsigned dst_z,
3686 struct pipe_resource *src,
3687 unsigned src_level,
3688 unsigned src_x,
3689 unsigned src_y,
3690 unsigned src_z,
3691 unsigned copy_height,
3692 unsigned pitch,
3693 unsigned bpp)
3694 {
3695 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3696 struct r600_texture *rsrc = (struct r600_texture*)src;
3697 struct r600_texture *rdst = (struct r600_texture*)dst;
3698 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3699 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3700 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3701 uint64_t base, addr;
3702
3703 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3704 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3705 assert(dst_mode != src_mode);
3706
3707 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3708 if (util_format_has_depth(util_format_description(src->format)))
3709 non_disp_tiling = 1;
3710
3711 y = 0;
3712 sub_cmd = EG_DMA_COPY_TILED;
3713 lbpp = util_logbase2(bpp);
3714 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3715 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3716
3717 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3718 /* T2L */
3719 array_mode = evergreen_array_mode(src_mode);
3720 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3721 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3722 /* linear height must be the same as the slice tile max height, it's ok even
3723 * if the linear destination/source have smaller heigh as the size of the
3724 * dma packet will be using the copy_height which is always smaller or equal
3725 * to the linear height
3726 */
3727 height = u_minify(rsrc->resource.b.b.height0, src_level);
3728 detile = 1;
3729 x = src_x;
3730 y = src_y;
3731 z = src_z;
3732 base = rsrc->surface.u.legacy.level[src_level].offset;
3733 addr = rdst->surface.u.legacy.level[dst_level].offset;
3734 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3735 addr += dst_y * pitch + dst_x * bpp;
3736 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3737 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3738 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3739 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3740 base += rsrc->resource.gpu_address;
3741 addr += rdst->resource.gpu_address;
3742 } else {
3743 /* L2T */
3744 array_mode = evergreen_array_mode(dst_mode);
3745 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3746 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3747 /* linear height must be the same as the slice tile max height, it's ok even
3748 * if the linear destination/source have smaller heigh as the size of the
3749 * dma packet will be using the copy_height which is always smaller or equal
3750 * to the linear height
3751 */
3752 height = u_minify(rdst->resource.b.b.height0, dst_level);
3753 detile = 0;
3754 x = dst_x;
3755 y = dst_y;
3756 z = dst_z;
3757 base = rdst->surface.u.legacy.level[dst_level].offset;
3758 addr = rsrc->surface.u.legacy.level[src_level].offset;
3759 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3760 addr += src_y * pitch + src_x * bpp;
3761 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3762 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3763 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3764 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3765 base += rdst->resource.gpu_address;
3766 addr += rsrc->resource.gpu_address;
3767 }
3768
3769 size = (copy_height * pitch) / 4;
3770 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3771 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3772
3773 for (i = 0; i < ncopy; i++) {
3774 cheight = copy_height;
3775 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3776 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3777 }
3778 size = (cheight * pitch) / 4;
3779 /* emit reloc before writing cs so that cs is always in consistent state */
3780 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3781 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3782 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3783 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3784 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3785 radeon_emit(cs, base >> 8);
3786 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3787 (lbpp << 24) | (bank_h << 21) |
3788 (bank_w << 18) | (mt_aspect << 16));
3789 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3790 radeon_emit(cs, (slice_tile_max << 0));
3791 radeon_emit(cs, (x << 0) | (z << 18));
3792 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3793 radeon_emit(cs, addr & 0xfffffffc);
3794 radeon_emit(cs, (addr >> 32UL) & 0xff);
3795 copy_height -= cheight;
3796 addr += cheight * pitch;
3797 y += cheight;
3798 }
3799 }
3800
3801 static void evergreen_dma_copy(struct pipe_context *ctx,
3802 struct pipe_resource *dst,
3803 unsigned dst_level,
3804 unsigned dstx, unsigned dsty, unsigned dstz,
3805 struct pipe_resource *src,
3806 unsigned src_level,
3807 const struct pipe_box *src_box)
3808 {
3809 struct r600_context *rctx = (struct r600_context *)ctx;
3810 struct r600_texture *rsrc = (struct r600_texture*)src;
3811 struct r600_texture *rdst = (struct r600_texture*)dst;
3812 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3813 unsigned src_w, dst_w;
3814 unsigned src_x, src_y;
3815 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3816
3817 if (rctx->b.dma.cs == NULL) {
3818 goto fallback;
3819 }
3820
3821 if (rctx->cmd_buf_is_compute) {
3822 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3823 rctx->cmd_buf_is_compute = false;
3824 }
3825
3826 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3827 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3828 return;
3829 }
3830
3831 if (src_box->depth > 1 ||
3832 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3833 dstz, rsrc, src_level, src_box))
3834 goto fallback;
3835
3836 src_x = util_format_get_nblocksx(src->format, src_box->x);
3837 dst_x = util_format_get_nblocksx(src->format, dst_x);
3838 src_y = util_format_get_nblocksy(src->format, src_box->y);
3839 dst_y = util_format_get_nblocksy(src->format, dst_y);
3840
3841 bpp = rdst->surface.bpe;
3842 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3843 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3844 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3845 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3846 copy_height = src_box->height / rsrc->surface.blk_h;
3847
3848 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3849 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3850
3851 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3852 /* FIXME evergreen can do partial blit */
3853 goto fallback;
3854 }
3855 /* the x test here are currently useless (because we don't support partial blit)
3856 * but keep them around so we don't forget about those
3857 */
3858 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3859 goto fallback;
3860 }
3861
3862 /* 128 bpp surfaces require non_disp_tiling for both
3863 * tiled and linear buffers on cayman. However, async
3864 * DMA only supports it on the tiled side. As such
3865 * the tile order is backwards after a L2T/T2L packet.
3866 */
3867 if ((rctx->b.chip_class == CAYMAN) &&
3868 (src_mode != dst_mode) &&
3869 (util_format_get_blocksize(src->format) >= 16)) {
3870 goto fallback;
3871 }
3872
3873 if (src_mode == dst_mode) {
3874 uint64_t dst_offset, src_offset;
3875 /* simple dma blit would do NOTE code here assume :
3876 * src_box.x/y == 0
3877 * dst_x/y == 0
3878 * dst_pitch == src_pitch
3879 */
3880 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3881 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3882 src_offset += src_y * src_pitch + src_x * bpp;
3883 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3884 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3885 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3886 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3887 src_box->height * src_pitch);
3888 } else {
3889 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3890 src, src_level, src_x, src_y, src_box->z,
3891 copy_height, dst_pitch, bpp);
3892 }
3893 return;
3894
3895 fallback:
3896 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3897 src, src_level, src_box);
3898 }
3899
3900 static void evergreen_set_tess_state(struct pipe_context *ctx,
3901 const float default_outer_level[4],
3902 const float default_inner_level[2])
3903 {
3904 struct r600_context *rctx = (struct r600_context *)ctx;
3905
3906 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3907 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3908 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
3909 }
3910
3911 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
3912 struct r600_image_view *rview,
3913 enum pipe_format pformat)
3914 {
3915 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
3916 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
3917 struct eg_buf_res_params buf_params;
3918 bool skip_reloc = false;
3919 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
3920 if (!resource->immed_buffer) {
3921 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
3922 }
3923
3924 memset(&buf_params, 0, sizeof(buf_params));
3925 buf_params.pipe_format = pformat;
3926 buf_params.size = resource->immed_buffer->b.b.width0;
3927 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3928 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3929 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3930 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3931 buf_params.uncached = 1;
3932 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
3933 &buf_params, &skip_reloc,
3934 rview->immed_resource_words);
3935 }
3936
3937 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3938 unsigned start_slot,
3939 unsigned count,
3940 const struct pipe_shader_buffer *buffers)
3941 {
3942 struct r600_context *rctx = (struct r600_context *)ctx;
3943 struct r600_atomic_buffer_state *astate;
3944 int i, idx;
3945
3946 astate = &rctx->atomic_buffer_state;
3947
3948 /* we'd probably like to expand this to 8 later so put the logic in */
3949 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3950 const struct pipe_shader_buffer *buf;
3951 struct pipe_shader_buffer *abuf;
3952
3953 abuf = &astate->buffer[i];
3954
3955 if (!buffers || !buffers[idx].buffer) {
3956 pipe_resource_reference(&abuf->buffer, NULL);
3957 astate->enabled_mask &= ~(1 << i);
3958 continue;
3959 }
3960 buf = &buffers[idx];
3961
3962 pipe_resource_reference(&abuf->buffer, buf->buffer);
3963 abuf->buffer_offset = buf->buffer_offset;
3964 abuf->buffer_size = buf->buffer_size;
3965 astate->enabled_mask |= (1 << i);
3966 }
3967 }
3968
3969 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
3970 enum pipe_shader_type shader, unsigned start_slot,
3971 unsigned count,
3972 const struct pipe_shader_buffer *buffers)
3973 {
3974 struct r600_context *rctx = (struct r600_context *)ctx;
3975 struct r600_image_state *istate = NULL;
3976 struct r600_image_view *rview;
3977 struct r600_tex_color_info color;
3978 struct eg_buf_res_params buf_params;
3979 struct r600_resource *resource;
3980 int i, idx;
3981 unsigned old_mask;
3982
3983 if (shader != PIPE_SHADER_FRAGMENT &&
3984 shader != PIPE_SHADER_COMPUTE && count == 0)
3985 return;
3986
3987 if (shader == PIPE_SHADER_FRAGMENT)
3988 istate = &rctx->fragment_buffers;
3989 else if (shader == PIPE_SHADER_COMPUTE)
3990 istate = &rctx->compute_buffers;
3991
3992 old_mask = istate->enabled_mask;
3993 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3994 const struct pipe_shader_buffer *buf;
3995 unsigned res_type;
3996
3997 rview = &istate->views[i];
3998
3999 if (!buffers || !buffers[idx].buffer) {
4000 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4001 istate->enabled_mask &= ~(1 << i);
4002 continue;
4003 }
4004
4005 buf = &buffers[idx];
4006 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
4007
4008 resource = (struct r600_resource *)rview->base.resource;
4009
4010 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
4011
4012 color.offset = 0;
4013 color.view = 0;
4014 evergreen_set_color_surface_buffer(rctx, resource,
4015 PIPE_FORMAT_R32_UINT,
4016 buf->buffer_offset,
4017 buf->buffer_offset + buf->buffer_size,
4018 &color);
4019
4020 res_type = V_028C70_BUFFER;
4021
4022 rview->cb_color_base = color.offset;
4023 rview->cb_color_dim = color.dim;
4024 rview->cb_color_info = color.info |
4025 S_028C70_RAT(1) |
4026 S_028C70_RESOURCE_TYPE(res_type);
4027 rview->cb_color_pitch = color.pitch;
4028 rview->cb_color_slice = color.slice;
4029 rview->cb_color_view = color.view;
4030 rview->cb_color_attrib = color.attrib;
4031 rview->cb_color_fmask = color.fmask;
4032 rview->cb_color_fmask_slice = color.fmask_slice;
4033
4034 memset(&buf_params, 0, sizeof(buf_params));
4035 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
4036 buf_params.offset = buf->buffer_offset;
4037 buf_params.size = buf->buffer_size;
4038 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4039 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4040 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4041 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4042 buf_params.force_swizzle = true;
4043 buf_params.uncached = 1;
4044 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4045 &buf_params,
4046 &rview->skip_mip_address_reloc,
4047 rview->resource_words);
4048
4049 istate->enabled_mask |= (1 << i);
4050 }
4051
4052 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4053
4054 if (old_mask != istate->enabled_mask)
4055 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4056
4057 /* construct the target mask */
4058 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
4059 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
4060 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4061 }
4062
4063 if (shader == PIPE_SHADER_FRAGMENT)
4064 r600_mark_atom_dirty(rctx, &istate->atom);
4065 }
4066
4067 static void evergreen_set_shader_images(struct pipe_context *ctx,
4068 enum pipe_shader_type shader, unsigned start_slot,
4069 unsigned count,
4070 const struct pipe_image_view *images)
4071 {
4072 struct r600_context *rctx = (struct r600_context *)ctx;
4073 int i;
4074 struct r600_image_view *rview;
4075 struct pipe_resource *image;
4076 struct r600_resource *resource;
4077 struct r600_tex_color_info color;
4078 struct eg_buf_res_params buf_params;
4079 struct eg_tex_res_params tex_params;
4080 unsigned old_mask;
4081 struct r600_image_state *istate = NULL;
4082 int idx;
4083 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE && count == 0)
4084 return;
4085
4086 if (shader == PIPE_SHADER_FRAGMENT)
4087 istate = &rctx->fragment_images;
4088 else if (shader == PIPE_SHADER_COMPUTE)
4089 istate = &rctx->compute_images;
4090
4091 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4092
4093 old_mask = istate->enabled_mask;
4094 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4095 unsigned res_type;
4096 const struct pipe_image_view *iview;
4097 rview = &istate->views[i];
4098
4099 if (!images || !images[idx].resource) {
4100 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4101 istate->enabled_mask &= ~(1 << i);
4102 istate->compressed_colortex_mask &= ~(1 << i);
4103 istate->compressed_depthtex_mask &= ~(1 << i);
4104 continue;
4105 }
4106
4107 iview = &images[idx];
4108 image = iview->resource;
4109 resource = (struct r600_resource *)image;
4110
4111 r600_context_add_resource_size(ctx, image);
4112
4113 rview->base = *iview;
4114 rview->base.resource = NULL;
4115 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4116
4117 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4118
4119 bool is_buffer = image->target == PIPE_BUFFER;
4120 struct r600_texture *rtex = (struct r600_texture *)image;
4121 if (!is_buffer & rtex->db_compatible)
4122 istate->compressed_depthtex_mask |= 1 << i;
4123 else
4124 istate->compressed_depthtex_mask &= ~(1 << i);
4125
4126 if (!is_buffer && rtex->cmask.size)
4127 istate->compressed_colortex_mask |= 1 << i;
4128 else
4129 istate->compressed_colortex_mask &= ~(1 << i);
4130 if (!is_buffer) {
4131
4132 evergreen_set_color_surface_common(rctx, rtex,
4133 iview->u.tex.level,
4134 iview->u.tex.first_layer,
4135 iview->u.tex.last_layer,
4136 iview->format,
4137 &color);
4138 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4139 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4140 } else {
4141 color.offset = 0;
4142 color.view = 0;
4143 evergreen_set_color_surface_buffer(rctx, resource,
4144 iview->format,
4145 iview->u.buf.offset,
4146 iview->u.buf.size,
4147 &color);
4148 }
4149
4150 switch (image->target) {
4151 case PIPE_BUFFER:
4152 res_type = V_028C70_BUFFER;
4153 break;
4154 case PIPE_TEXTURE_1D:
4155 res_type = V_028C70_TEXTURE1D;
4156 break;
4157 case PIPE_TEXTURE_1D_ARRAY:
4158 res_type = V_028C70_TEXTURE1DARRAY;
4159 break;
4160 case PIPE_TEXTURE_2D:
4161 case PIPE_TEXTURE_RECT:
4162 res_type = V_028C70_TEXTURE2D;
4163 break;
4164 case PIPE_TEXTURE_3D:
4165 res_type = V_028C70_TEXTURE3D;
4166 break;
4167 case PIPE_TEXTURE_2D_ARRAY:
4168 case PIPE_TEXTURE_CUBE:
4169 case PIPE_TEXTURE_CUBE_ARRAY:
4170 res_type = V_028C70_TEXTURE2DARRAY;
4171 break;
4172 default:
4173 assert(0);
4174 res_type = 0;
4175 break;
4176 }
4177
4178 rview->cb_color_base = color.offset;
4179 rview->cb_color_dim = color.dim;
4180 rview->cb_color_info = color.info |
4181 S_028C70_RAT(1) |
4182 S_028C70_RESOURCE_TYPE(res_type);
4183 rview->cb_color_pitch = color.pitch;
4184 rview->cb_color_slice = color.slice;
4185 rview->cb_color_view = color.view;
4186 rview->cb_color_attrib = color.attrib;
4187 rview->cb_color_fmask = color.fmask;
4188 rview->cb_color_fmask_slice = color.fmask_slice;
4189
4190 if (image->target != PIPE_BUFFER) {
4191 memset(&tex_params, 0, sizeof(tex_params));
4192 tex_params.pipe_format = iview->format;
4193 tex_params.force_level = 0;
4194 tex_params.width0 = image->width0;
4195 tex_params.height0 = image->height0;
4196 tex_params.first_level = iview->u.tex.level;
4197 tex_params.last_level = iview->u.tex.level;
4198 tex_params.first_layer = iview->u.tex.first_layer;
4199 tex_params.last_layer = iview->u.tex.last_layer;
4200 tex_params.target = image->target;
4201 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4202 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4203 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4204 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4205 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4206 &rview->skip_mip_address_reloc,
4207 rview->resource_words);
4208
4209 } else {
4210 memset(&buf_params, 0, sizeof(buf_params));
4211 buf_params.pipe_format = iview->format;
4212 buf_params.size = iview->u.buf.size;
4213 buf_params.offset = iview->u.buf.offset;
4214 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4215 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4216 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4217 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4218 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4219 &buf_params,
4220 &rview->skip_mip_address_reloc,
4221 rview->resource_words);
4222 }
4223 istate->enabled_mask |= (1 << i);
4224 }
4225
4226 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4227 istate->dirty_buffer_constants = TRUE;
4228 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4229 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4230 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4231
4232 if (old_mask != istate->enabled_mask)
4233 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4234
4235 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
4236 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
4237 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4238 }
4239
4240 if (shader == PIPE_SHADER_FRAGMENT)
4241 r600_mark_atom_dirty(rctx, &istate->atom);
4242 }
4243
4244 static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx,
4245 enum pipe_shader_type shader, uint slot,
4246 struct pipe_constant_buffer *cbuf)
4247 {
4248 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4249 struct pipe_constant_buffer *cb;
4250 cbuf->user_buffer = NULL;
4251
4252 cb = &state->cb[slot];
4253
4254 cbuf->buffer_size = cb->buffer_size;
4255 pipe_resource_reference(&cbuf->buffer, cb->buffer);
4256 }
4257
4258 static void evergreen_get_shader_buffers(struct r600_context *rctx,
4259 enum pipe_shader_type shader,
4260 uint start_slot, uint count,
4261 struct pipe_shader_buffer *sbuf)
4262 {
4263 assert(shader == PIPE_SHADER_COMPUTE);
4264 int idx, i;
4265 struct r600_image_state *istate = &rctx->compute_buffers;
4266 struct r600_image_view *rview;
4267
4268 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4269
4270 rview = &istate->views[i];
4271
4272 pipe_resource_reference(&sbuf[idx].buffer, rview->base.resource);
4273 if (rview->base.resource) {
4274 uint64_t rview_va = ((struct r600_resource *)rview->base.resource)->gpu_address;
4275
4276 uint64_t prog_va = rview->resource_words[0];
4277
4278 prog_va += ((uint64_t)G_030008_BASE_ADDRESS_HI(rview->resource_words[2])) << 32;
4279 prog_va -= rview_va;
4280
4281 sbuf[idx].buffer_offset = prog_va & 0xffffffff;
4282 sbuf[idx].buffer_size = rview->resource_words[1] + 1;;
4283 } else {
4284 sbuf[idx].buffer_offset = 0;
4285 sbuf[idx].buffer_size = 0;
4286 }
4287 }
4288 }
4289
4290 static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
4291 {
4292 struct r600_context *rctx = (struct r600_context *)ctx;
4293 st->saved_compute = rctx->cs_shader_state.shader;
4294
4295 /* save constant buffer 0 */
4296 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
4297 /* save ssbo 0 */
4298 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
4299 }
4300
4301
4302 void evergreen_init_state_functions(struct r600_context *rctx)
4303 {
4304 unsigned id = 1;
4305 unsigned i;
4306 /* !!!
4307 * To avoid GPU lockup registers must be emitted in a specific order
4308 * (no kidding ...). The order below is important and have been
4309 * partially inferred from analyzing fglrx command stream.
4310 *
4311 * Don't reorder atom without carefully checking the effect (GPU lockup
4312 * or piglit regression).
4313 * !!!
4314 */
4315 if (rctx->b.chip_class == EVERGREEN) {
4316 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4317 rctx->config_state.dyn_gpr_enabled = true;
4318 }
4319 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4320 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4321 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4322 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4323 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4324 /* shader const */
4325 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4326 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4327 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4328 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4329 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4330 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4331 /* shader program */
4332 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4333 /* sampler */
4334 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4335 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4336 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4337 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4338 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4339 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4340 /* resources */
4341 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4342 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4343 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4344 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4345 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4346 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4347 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4348 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4349
4350 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4351
4352 if (rctx->b.chip_class == EVERGREEN) {
4353 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4354 } else {
4355 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4356 }
4357 rctx->sample_mask.sample_mask = ~0;
4358
4359 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4360 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4361 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4362 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4363 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4364 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4365 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4366 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4367 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4368 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4369 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4370 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4371 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4372 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4373 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4374 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4375 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4376 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4377 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4378 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4379 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4380 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4381
4382 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4383 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4384 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4385 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4386 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4387 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4388 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4389 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4390 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4391 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4392 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4393 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4394 if (rctx->b.chip_class == EVERGREEN)
4395 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4396 else
4397 rctx->b.b.get_sample_position = cayman_get_sample_position;
4398 rctx->b.dma_copy = evergreen_dma_copy;
4399 rctx->b.save_qbo_state = evergreen_save_qbo_state;
4400
4401 evergreen_init_compute_state_functions(rctx);
4402 }
4403
4404 /**
4405 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4406 *
4407 * The information about LDS and other non-compile-time parameters is then
4408 * written to the const buffer.
4409
4410 * const buffer contains -
4411 * uint32_t input_patch_size
4412 * uint32_t input_vertex_size
4413 * uint32_t num_tcs_input_cp
4414 * uint32_t num_tcs_output_cp;
4415 * uint32_t output_patch_size
4416 * uint32_t output_vertex_size
4417 * uint32_t output_patch0_offset
4418 * uint32_t perpatch_output_offset
4419 * and the same constbuf is bound to LS/HS/VS(ES).
4420 */
4421 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4422 {
4423 struct pipe_constant_buffer constbuf = {0};
4424 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4425 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4426 unsigned num_tcs_input_cp = info->vertices_per_patch;
4427 unsigned num_tcs_outputs;
4428 unsigned num_tcs_output_cp;
4429 unsigned num_tcs_patch_outputs;
4430 unsigned num_tcs_inputs;
4431 unsigned input_vertex_size, output_vertex_size;
4432 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4433 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4434 uint32_t values[8];
4435 unsigned num_waves;
4436 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4437 unsigned wave_divisor = (16 * num_pipes);
4438
4439 *num_patches = 1;
4440
4441 if (!rctx->tes_shader) {
4442 rctx->lds_alloc = 0;
4443 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4444 R600_LDS_INFO_CONST_BUFFER, NULL);
4445 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4446 R600_LDS_INFO_CONST_BUFFER, NULL);
4447 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4448 R600_LDS_INFO_CONST_BUFFER, NULL);
4449 return;
4450 }
4451
4452 if (rctx->lds_alloc != 0 &&
4453 rctx->last_ls == ls &&
4454 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4455 rctx->last_tcs == tcs)
4456 return;
4457
4458 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4459
4460 if (rctx->tcs_shader) {
4461 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4462 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4463 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4464 } else {
4465 num_tcs_outputs = num_tcs_inputs;
4466 num_tcs_output_cp = num_tcs_input_cp;
4467 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4468 }
4469
4470 /* size in bytes */
4471 input_vertex_size = num_tcs_inputs * 16;
4472 output_vertex_size = num_tcs_outputs * 16;
4473
4474 input_patch_size = num_tcs_input_cp * input_vertex_size;
4475
4476 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4477 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4478
4479 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4480 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4481
4482 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4483
4484 values[0] = input_patch_size;
4485 values[1] = input_vertex_size;
4486 values[2] = num_tcs_input_cp;
4487 values[3] = num_tcs_output_cp;
4488
4489 values[4] = output_patch_size;
4490 values[5] = output_vertex_size;
4491 values[6] = output_patch0_offset;
4492 values[7] = perpatch_output_offset;
4493
4494 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4495 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4496 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4497
4498 rctx->lds_alloc = (lds_size | (num_waves << 14));
4499
4500 rctx->last_ls = ls;
4501 rctx->last_tcs = tcs;
4502 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4503
4504 constbuf.user_buffer = values;
4505 constbuf.buffer_size = 8 * 4;
4506
4507 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4508 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4509 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4510 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4511 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4512 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4513 pipe_resource_reference(&constbuf.buffer, NULL);
4514 }
4515
4516 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4517 const struct pipe_draw_info *info,
4518 unsigned num_patches)
4519 {
4520 unsigned num_output_cp;
4521
4522 if (!rctx->tes_shader)
4523 return 0;
4524
4525 num_output_cp = rctx->tcs_shader ?
4526 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4527 info->vertices_per_patch;
4528
4529 return S_028B58_NUM_PATCHES(num_patches) |
4530 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
4531 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4532 }
4533
4534 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4535 struct radeon_winsys_cs *cs,
4536 uint32_t ls_hs_config)
4537 {
4538 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4539 }
4540
4541 void evergreen_set_lds_alloc(struct r600_context *rctx,
4542 struct radeon_winsys_cs *cs,
4543 uint32_t lds_alloc)
4544 {
4545 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4546 }
4547
4548 /* on evergreen if you are running tessellation you need to disable dynamic
4549 GPRs to workaround a hardware bug.*/
4550 bool evergreen_adjust_gprs(struct r600_context *rctx)
4551 {
4552 unsigned num_gprs[EG_NUM_HW_STAGES];
4553 unsigned def_gprs[EG_NUM_HW_STAGES];
4554 unsigned cur_gprs[EG_NUM_HW_STAGES];
4555 unsigned new_gprs[EG_NUM_HW_STAGES];
4556 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4557 unsigned max_gprs;
4558 unsigned i;
4559 unsigned total_gprs;
4560 unsigned tmp[3];
4561 bool rework = false, set_default = false, set_dirty = false;
4562 max_gprs = 0;
4563 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4564 def_gprs[i] = rctx->default_gprs[i];
4565 max_gprs += def_gprs[i];
4566 }
4567 max_gprs += def_num_clause_temp_gprs * 2;
4568
4569 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4570 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4571 if (rctx->config_state.dyn_gpr_enabled)
4572 return true;
4573
4574 /* transition back to dyn gpr enabled state */
4575 rctx->config_state.dyn_gpr_enabled = true;
4576 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4577 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4578 return true;
4579 }
4580
4581
4582 /* gather required shader gprs */
4583 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4584 if (rctx->hw_shader_stages[i].shader)
4585 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4586 else
4587 num_gprs[i] = 0;
4588 }
4589
4590 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4591 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4592 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4593 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4594 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4595 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4596
4597 total_gprs = 0;
4598 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4599 new_gprs[i] = num_gprs[i];
4600 total_gprs += num_gprs[i];
4601 }
4602
4603 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4604 return false;
4605
4606 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4607 if (new_gprs[i] > cur_gprs[i]) {
4608 rework = true;
4609 break;
4610 }
4611 }
4612
4613 if (rctx->config_state.dyn_gpr_enabled) {
4614 set_dirty = true;
4615 rctx->config_state.dyn_gpr_enabled = false;
4616 }
4617
4618 if (rework) {
4619 set_default = true;
4620 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4621 if (new_gprs[i] > def_gprs[i])
4622 set_default = false;
4623 }
4624
4625 if (set_default) {
4626 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4627 new_gprs[i] = def_gprs[i];
4628 }
4629 } else {
4630 unsigned ps_value = max_gprs;
4631
4632 ps_value -= (def_num_clause_temp_gprs * 2);
4633 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4634 ps_value -= new_gprs[i];
4635
4636 new_gprs[R600_HW_STAGE_PS] = ps_value;
4637 }
4638
4639 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4640 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4641 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4642
4643 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4644 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4645
4646 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4647 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4648
4649 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4650 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4651 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4652 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4653 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4654 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4655 set_dirty = true;
4656 }
4657 }
4658
4659
4660 if (set_dirty) {
4661 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4662 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4663 }
4664 return true;
4665 }
4666
4667 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4668
4669 void eg_trace_emit(struct r600_context *rctx)
4670 {
4671 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4672 unsigned reloc;
4673
4674 if (rctx->b.chip_class < EVERGREEN)
4675 return;
4676
4677 /* This must be done after r600_need_cs_space. */
4678 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4679 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4680 RADEON_PRIO_CP_DMA);
4681
4682 rctx->trace_id++;
4683 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4684 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4685 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4686 radeon_emit(cs, rctx->trace_buf->gpu_address);
4687 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4688 radeon_emit(cs, rctx->trace_id);
4689 radeon_emit(cs, 0);
4690 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4691 radeon_emit(cs, reloc);
4692 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4693 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4694 }
4695
4696 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4697 struct r600_shader_atomic *atomic,
4698 struct r600_resource *resource,
4699 uint32_t pkt_flags)
4700 {
4701 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4702 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4703 resource,
4704 RADEON_USAGE_READ,
4705 RADEON_PRIO_SHADER_RW_BUFFER);
4706 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4707 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4708
4709 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4710
4711 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4712 radeon_emit(cs, (reg_val << 16) | 0x3);
4713 radeon_emit(cs, dst_offset & 0xfffffffc);
4714 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4715 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4716 radeon_emit(cs, reloc);
4717 }
4718
4719 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4720 struct r600_shader_atomic *atomic,
4721 struct r600_resource *resource,
4722 uint32_t pkt_flags)
4723 {
4724 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4725 uint32_t event = EVENT_TYPE_PS_DONE;
4726 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4727 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4728 resource,
4729 RADEON_USAGE_WRITE,
4730 RADEON_PRIO_SHADER_RW_BUFFER);
4731 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4732 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4733
4734 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4735 event = EVENT_TYPE_CS_DONE;
4736
4737 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4738 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4739 radeon_emit(cs, (dst_offset) & 0xffffffff);
4740 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4741 radeon_emit(cs, reg_val);
4742 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4743 radeon_emit(cs, reloc);
4744 }
4745
4746 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4747 struct r600_shader_atomic *atomic,
4748 struct r600_resource *resource,
4749 uint32_t pkt_flags)
4750 {
4751 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4752 uint32_t event = EVENT_TYPE_PS_DONE;
4753 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4754 resource,
4755 RADEON_USAGE_WRITE,
4756 RADEON_PRIO_SHADER_RW_BUFFER);
4757 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4758
4759 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4760 event = EVENT_TYPE_CS_DONE;
4761
4762 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4763 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4764 radeon_emit(cs, (dst_offset) & 0xffffffff);
4765 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4766 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4767 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4768 radeon_emit(cs, reloc);
4769 }
4770
4771 /* writes count from a buffer into GDS */
4772 static void cayman_write_count_to_gds(struct r600_context *rctx,
4773 struct r600_shader_atomic *atomic,
4774 struct r600_resource *resource,
4775 uint32_t pkt_flags)
4776 {
4777 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4778 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4779 resource,
4780 RADEON_USAGE_READ,
4781 RADEON_PRIO_SHADER_RW_BUFFER);
4782 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4783
4784 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4785 radeon_emit(cs, dst_offset & 0xffffffff);
4786 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4787 radeon_emit(cs, atomic->hw_idx * 4);
4788 radeon_emit(cs, 0);
4789 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4790 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4791 radeon_emit(cs, reloc);
4792 }
4793
4794 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4795 struct r600_pipe_shader *cs_shader,
4796 struct r600_shader_atomic *combined_atomics,
4797 uint8_t *atomic_used_mask_p)
4798 {
4799 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4800 unsigned pkt_flags = 0;
4801 uint8_t atomic_used_mask = 0;
4802 int i, j, k;
4803 bool is_compute = cs_shader ? true : false;
4804
4805 if (is_compute)
4806 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4807
4808 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
4809 uint8_t num_atomic_stage;
4810 struct r600_pipe_shader *pshader;
4811
4812 if (is_compute)
4813 pshader = cs_shader;
4814 else
4815 pshader = rctx->hw_shader_stages[i].shader;
4816 if (!pshader)
4817 continue;
4818
4819 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4820 if (!num_atomic_stage)
4821 continue;
4822
4823 for (j = 0; j < num_atomic_stage; j++) {
4824 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4825 int natomics = atomic->end - atomic->start + 1;
4826
4827 for (k = 0; k < natomics; k++) {
4828 /* seen this in a previous stage */
4829 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4830 continue;
4831
4832 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4833 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4834 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4835 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4836 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4837 }
4838 }
4839 }
4840
4841 uint32_t mask = atomic_used_mask;
4842 while (mask) {
4843 unsigned atomic_index = u_bit_scan(&mask);
4844 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4845 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4846 assert(resource);
4847
4848 if (rctx->b.chip_class == CAYMAN)
4849 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4850 else
4851 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4852 }
4853 *atomic_used_mask_p = atomic_used_mask;
4854 return true;
4855 }
4856
4857 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4858 bool is_compute,
4859 struct r600_shader_atomic *combined_atomics,
4860 uint8_t *atomic_used_mask_p)
4861 {
4862 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4863 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4864 uint32_t pkt_flags = 0;
4865 uint32_t event = EVENT_TYPE_PS_DONE;
4866 uint32_t mask = astate->enabled_mask;
4867 uint64_t dst_offset;
4868 unsigned reloc;
4869
4870 if (is_compute)
4871 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4872
4873 mask = *atomic_used_mask_p;
4874 if (!mask)
4875 return;
4876
4877 while (mask) {
4878 unsigned atomic_index = u_bit_scan(&mask);
4879 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4880 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4881 assert(resource);
4882
4883 if (rctx->b.chip_class == CAYMAN)
4884 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4885 else
4886 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4887 }
4888
4889 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4890 event = EVENT_TYPE_CS_DONE;
4891
4892 ++rctx->append_fence_id;
4893 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4894 r600_resource(rctx->append_fence),
4895 RADEON_USAGE_READWRITE,
4896 RADEON_PRIO_SHADER_RW_BUFFER);
4897 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4898 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4899 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4900 radeon_emit(cs, dst_offset & 0xffffffff);
4901 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4902 radeon_emit(cs, rctx->append_fence_id);
4903 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4904 radeon_emit(cs, reloc);
4905
4906 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4907 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4908 radeon_emit(cs, dst_offset & 0xffffffff);
4909 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4910 radeon_emit(cs, rctx->append_fence_id);
4911 radeon_emit(cs, 0xffffffff);
4912 radeon_emit(cs, 0xa);
4913 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4914 radeon_emit(cs, reloc);
4915 }