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gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
172 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
173 {
174 switch (dim) {
175 default:
176 case PIPE_TEXTURE_1D:
177 return V_030000_SQ_TEX_DIM_1D;
178 case PIPE_TEXTURE_1D_ARRAY:
179 return V_030000_SQ_TEX_DIM_1D_ARRAY;
180 case PIPE_TEXTURE_2D:
181 case PIPE_TEXTURE_RECT:
182 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
183 V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
186 V_030000_SQ_TEX_DIM_2D_ARRAY;
187 case PIPE_TEXTURE_3D:
188 return V_030000_SQ_TEX_DIM_3D;
189 case PIPE_TEXTURE_CUBE:
190 case PIPE_TEXTURE_CUBE_ARRAY:
191 return V_030000_SQ_TEX_DIM_CUBEMAP;
192 }
193 }
194
195 static uint32_t r600_translate_dbformat(enum pipe_format format)
196 {
197 switch (format) {
198 case PIPE_FORMAT_Z16_UNORM:
199 return V_028040_Z_16;
200 case PIPE_FORMAT_Z24X8_UNORM:
201 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
202 case PIPE_FORMAT_X8Z24_UNORM:
203 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
204 return V_028040_Z_24;
205 case PIPE_FORMAT_Z32_FLOAT:
206 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
207 return V_028040_Z_32_FLOAT;
208 default:
209 return ~0U;
210 }
211 }
212
213 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
214 {
215 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
216 FALSE) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
222 r600_translate_colorswap(format, FALSE) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if ((usage & PIPE_BIND_LINEAR) &&
298 !util_format_is_compressed(format) &&
299 !(usage & PIPE_BIND_DEPTH_STENCIL))
300 retval |= PIPE_BIND_LINEAR;
301
302 return retval == usage;
303 }
304
305 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state, int mode)
307 {
308 uint32_t color_control = 0, target_mask = 0;
309 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
310
311 if (!blend) {
312 return NULL;
313 }
314
315 r600_init_command_buffer(&blend->buffer, 20);
316 r600_init_command_buffer(&blend->buffer_no_blend, 20);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 target_mask |= (state->rt[i].colormask << (4 * i));
327 }
328 } else {
329 for (int i = 0; i < 8; i++) {
330 target_mask |= (state->rt[0].colormask << (4 * i));
331 }
332 }
333
334 /* only have dual source on MRT0 */
335 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
336 blend->cb_target_mask = target_mask;
337 blend->alpha_to_one = state->alpha_to_one;
338
339 if (target_mask)
340 color_control |= S_028808_MODE(mode);
341 else
342 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
343
344
345 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
346 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
353
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 for (int i = 0; i < 8; i++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j = state->independent_blend_enable ? i : 0;
362
363 unsigned eqRGB = state->rt[j].rgb_func;
364 unsigned srcRGB = state->rt[j].rgb_src_factor;
365 unsigned dstRGB = state->rt[j].rgb_dst_factor;
366 unsigned eqA = state->rt[j].alpha_func;
367 unsigned srcA = state->rt[j].alpha_src_factor;
368 unsigned dstA = state->rt[j].alpha_dst_factor;
369 uint32_t bc = 0;
370
371 r600_store_value(&blend->buffer_no_blend, 0);
372
373 if (!state->rt[j].blend_enable) {
374 r600_store_value(&blend->buffer, 0);
375 continue;
376 }
377
378 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
380 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
381 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
382
383 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
384 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
386 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
387 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
388 }
389 r600_store_value(&blend->buffer, bc);
390 }
391 return blend;
392 }
393
394 static void *evergreen_create_blend_state(struct pipe_context *ctx,
395 const struct pipe_blend_state *state)
396 {
397
398 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
399 }
400
401 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (!dsa) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 /* misc */
452 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
453 return dsa;
454 }
455
456 static void *evergreen_create_rs_state(struct pipe_context *ctx,
457 const struct pipe_rasterizer_state *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 unsigned tmp, spi_interp;
461 float psize_min, psize_max;
462 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
463
464 if (!rs) {
465 return NULL;
466 }
467
468 r600_init_command_buffer(&rs->buffer, 30);
469
470 rs->scissor_enable = state->scissor;
471 rs->clip_halfz = state->clip_halfz;
472 rs->flatshade = state->flatshade;
473 rs->sprite_coord_enable = state->sprite_coord_enable;
474 rs->two_side = state->light_twoside;
475 rs->clip_plane_enable = state->clip_plane_enable;
476 rs->pa_sc_line_stipple = state->line_stipple_enable ?
477 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
478 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
479 rs->pa_cl_clip_cntl =
480 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
481 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
482 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
483 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
484 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
485 rs->multisample_enable = state->multisample;
486
487 /* offset */
488 rs->offset_units = state->offset_units;
489 rs->offset_scale = state->offset_scale * 16.0f;
490 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
491 rs->offset_units_unscaled = state->offset_units_unscaled;
492
493 if (state->point_size_per_vertex) {
494 psize_min = util_get_min_point_size(state);
495 psize_max = 8192;
496 } else {
497 /* Force the point size to be as if the vertex output was disabled. */
498 psize_min = state->point_size;
499 psize_max = state->point_size;
500 }
501
502 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
503 if (state->sprite_coord_enable) {
504 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
505 S_0286D4_PNT_SPRITE_OVRD_X(2) |
506 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
507 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
508 S_0286D4_PNT_SPRITE_OVRD_W(1);
509 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
510 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
511 }
512 }
513
514 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
515 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
516 tmp = r600_pack_float_12p4(state->point_size/2);
517 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
518 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
519 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
520 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
521 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
522 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
523 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
524
525 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
526 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
527 S_028A48_MSAA_ENABLE(state->multisample) |
528 S_028A48_VPORT_SCISSOR_ENABLE(1) |
529 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
530
531 if (rctx->b.chip_class == CAYMAN) {
532 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
533 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
534 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
535 } else {
536 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
537 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
538 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
539 }
540
541 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
542 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
543 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
544 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
545 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
546 S_028814_FACE(!state->front_ccw) |
547 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
548 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
549 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
550 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
551 state->fill_back != PIPE_POLYGON_MODE_FILL) |
552 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
553 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
554 return rs;
555 }
556
557 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
558 const struct pipe_sampler_state *state)
559 {
560 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
561 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
562 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
563 : state->max_anisotropy;
564 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
565
566 if (!ss) {
567 return NULL;
568 }
569
570 ss->border_color_use = sampler_state_needs_border_color(state);
571
572 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
573 ss->tex_sampler_words[0] =
574 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
575 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
576 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
577 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
578 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
579 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
580 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
581 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
582 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
583 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
584 ss->tex_sampler_words[1] =
585 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
586 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
587 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
588 ss->tex_sampler_words[2] =
589 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
590 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
591 S_03C008_TYPE(1);
592
593 if (ss->border_color_use) {
594 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
595 }
596 return ss;
597 }
598
599 struct eg_buf_res_params {
600 enum pipe_format pipe_format;
601 unsigned offset;
602 unsigned size;
603 unsigned char swizzle[4];
604 bool uncached;
605 };
606
607 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
608 struct pipe_resource *buffer,
609 struct eg_buf_res_params *params,
610 bool *skip_mip_address_reloc,
611 unsigned tex_resource_words[8])
612 {
613 struct r600_texture *tmp = (struct r600_texture*)buffer;
614 uint64_t va;
615 int stride = util_format_get_blocksize(params->pipe_format);
616 unsigned format, num_format, format_comp, endian;
617 unsigned swizzle_res;
618 const struct util_format_description *desc;
619
620 r600_vertex_data_type(params->pipe_format,
621 &format, &num_format, &format_comp,
622 &endian);
623
624 desc = util_format_description(params->pipe_format);
625
626 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
627
628 va = tmp->resource.gpu_address + params->offset;
629 *skip_mip_address_reloc = true;
630 tex_resource_words[0] = va;
631 tex_resource_words[1] = params->size - 1;
632 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
633 S_030008_STRIDE(stride) |
634 S_030008_DATA_FORMAT(format) |
635 S_030008_NUM_FORMAT_ALL(num_format) |
636 S_030008_FORMAT_COMP_ALL(format_comp) |
637 S_030008_ENDIAN_SWAP(endian);
638 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
639 /*
640 * in theory dword 4 is for number of elements, for use with resinfo,
641 * but it seems to utterly fail to work, the amd gpu shader analyser
642 * uses a const buffer to store the element sizes for buffer txq
643 */
644 tex_resource_words[4] = 0;
645 tex_resource_words[5] = tex_resource_words[6] = 0;
646 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
647 }
648
649 static struct pipe_sampler_view *
650 texture_buffer_sampler_view(struct r600_context *rctx,
651 struct r600_pipe_sampler_view *view,
652 unsigned width0, unsigned height0)
653 {
654 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
655 struct eg_buf_res_params params;
656
657 memset(&params, 0, sizeof(params));
658
659 params.pipe_format = view->base.format;
660 params.offset = view->base.u.buf.offset;
661 params.size = view->base.u.buf.size;
662 params.swizzle[0] = view->base.swizzle_r;
663 params.swizzle[1] = view->base.swizzle_g;
664 params.swizzle[2] = view->base.swizzle_b;
665 params.swizzle[3] = view->base.swizzle_a;
666
667 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
668 &params, &view->skip_mip_address_reloc,
669 view->tex_resource_words);
670 view->tex_resource = &tmp->resource;
671
672 if (tmp->resource.gpu_address)
673 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
674 return &view->base;
675 }
676
677 struct eg_tex_res_params {
678 enum pipe_format pipe_format;
679 int force_level;
680 unsigned width0;
681 unsigned height0;
682 unsigned first_level;
683 unsigned last_level;
684 unsigned first_layer;
685 unsigned last_layer;
686 unsigned target;
687 unsigned char swizzle[4];
688 };
689
690 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
691 struct pipe_resource *texture,
692 struct eg_tex_res_params *params,
693 bool *skip_mip_address_reloc,
694 unsigned tex_resource_words[8])
695 {
696 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
697 struct r600_texture *tmp = (struct r600_texture*)texture;
698 unsigned format, endian;
699 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
700 unsigned char array_mode = 0, non_disp_tiling = 0;
701 unsigned height, depth, width;
702 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
703 struct legacy_surf_level *surflevel;
704 unsigned base_level, first_level, last_level;
705 unsigned dim, last_layer;
706 uint64_t va;
707 bool do_endian_swap = FALSE;
708
709 tile_split = tmp->surface.u.legacy.tile_split;
710 surflevel = tmp->surface.u.legacy.level;
711
712 /* Texturing with separate depth and stencil. */
713 if (tmp->db_compatible) {
714 switch (params->pipe_format) {
715 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
716 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
717 break;
718 case PIPE_FORMAT_X8Z24_UNORM:
719 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
720 /* Z24 is always stored like this for DB
721 * compatibility.
722 */
723 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
724 break;
725 case PIPE_FORMAT_X24S8_UINT:
726 case PIPE_FORMAT_S8X24_UINT:
727 case PIPE_FORMAT_X32_S8X24_UINT:
728 params->pipe_format = PIPE_FORMAT_S8_UINT;
729 tile_split = tmp->surface.u.legacy.stencil_tile_split;
730 surflevel = tmp->surface.u.legacy.stencil_level;
731 break;
732 default:;
733 }
734 }
735
736 if (R600_BIG_ENDIAN)
737 do_endian_swap = !tmp->db_compatible;
738
739 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
740 params->swizzle,
741 &word4, &yuv_format, do_endian_swap);
742 assert(format != ~0);
743 if (format == ~0) {
744 return -1;
745 }
746
747 endian = r600_colorformat_endian_swap(format, do_endian_swap);
748
749 base_level = 0;
750 first_level = params->first_level;
751 last_level = params->last_level;
752 width = params->width0;
753 height = params->height0;
754 depth = texture->depth0;
755
756 if (params->force_level) {
757 base_level = params->force_level;
758 first_level = 0;
759 last_level = 0;
760 width = u_minify(width, params->force_level);
761 height = u_minify(height, params->force_level);
762 depth = u_minify(depth, params->force_level);
763 }
764
765 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
766 non_disp_tiling = tmp->non_disp_tiling;
767
768 switch (surflevel[base_level].mode) {
769 default:
770 case RADEON_SURF_MODE_LINEAR_ALIGNED:
771 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
772 break;
773 case RADEON_SURF_MODE_2D:
774 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
775 break;
776 case RADEON_SURF_MODE_1D:
777 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
778 break;
779 }
780 macro_aspect = tmp->surface.u.legacy.mtilea;
781 bankw = tmp->surface.u.legacy.bankw;
782 bankh = tmp->surface.u.legacy.bankh;
783 tile_split = eg_tile_split(tile_split);
784 macro_aspect = eg_macro_tile_aspect(macro_aspect);
785 bankw = eg_bank_wh(bankw);
786 bankh = eg_bank_wh(bankh);
787 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
788
789 /* 128 bit formats require tile type = 1 */
790 if (rscreen->b.chip_class == CAYMAN) {
791 if (util_format_get_blocksize(params->pipe_format) >= 16)
792 non_disp_tiling = 1;
793 }
794 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
795
796 if (params->target == PIPE_TEXTURE_1D_ARRAY) {
797 height = 1;
798 depth = texture->array_size;
799 } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
800 depth = texture->array_size;
801 } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
802 depth = texture->array_size / 6;
803
804 va = tmp->resource.gpu_address;
805
806 /* array type views and views into array types need to use layer offset */
807 dim = params->target;
808 if (params->target != PIPE_TEXTURE_CUBE)
809 dim = MAX2(params->target, texture->target);
810
811 tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
812 S_030000_PITCH((pitch / 8) - 1) |
813 S_030000_TEX_WIDTH(width - 1));
814 if (rscreen->b.chip_class == CAYMAN)
815 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
816 else
817 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
818 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
819 S_030004_TEX_DEPTH(depth - 1) |
820 S_030004_ARRAY_MODE(array_mode));
821 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
822
823 *skip_mip_address_reloc = false;
824 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
825 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
826 if (tmp->is_depth) {
827 /* disable FMASK (0 = disabled) */
828 tex_resource_words[3] = 0;
829 *skip_mip_address_reloc = true;
830 } else {
831 /* FMASK should be in MIP_ADDRESS for multisample textures */
832 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
833 }
834 } else if (last_level && texture->nr_samples <= 1) {
835 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
836 } else {
837 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
838 }
839
840 last_layer = params->last_layer;
841 if (params->target != texture->target && depth == 1) {
842 last_layer = params->first_layer;
843 }
844 tex_resource_words[4] = (word4 |
845 S_030010_ENDIAN_SWAP(endian));
846 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
847 S_030014_LAST_ARRAY(last_layer);
848 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
849
850 if (texture->nr_samples > 1) {
851 unsigned log_samples = util_logbase2(texture->nr_samples);
852 if (rscreen->b.chip_class == CAYMAN) {
853 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
854 }
855 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
856 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
857 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
858 } else {
859 bool no_mip = first_level == last_level;
860
861 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
862 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
863 /* aniso max 16 samples */
864 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
865 }
866
867 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
868 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
869 S_03001C_BANK_WIDTH(bankw) |
870 S_03001C_BANK_HEIGHT(bankh) |
871 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
872 S_03001C_NUM_BANKS(nbanks) |
873 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
874 return 0;
875 }
876
877 struct pipe_sampler_view *
878 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
879 struct pipe_resource *texture,
880 const struct pipe_sampler_view *state,
881 unsigned width0, unsigned height0,
882 unsigned force_level)
883 {
884 struct r600_context *rctx = (struct r600_context*)ctx;
885 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
886 struct r600_texture *tmp = (struct r600_texture*)texture;
887 struct eg_tex_res_params params;
888 int ret;
889
890 if (!view)
891 return NULL;
892
893 /* initialize base object */
894 view->base = *state;
895 view->base.texture = NULL;
896 pipe_reference(NULL, &texture->reference);
897 view->base.texture = texture;
898 view->base.reference.count = 1;
899 view->base.context = ctx;
900
901 if (state->target == PIPE_BUFFER)
902 return texture_buffer_sampler_view(rctx, view, width0, height0);
903
904 memset(&params, 0, sizeof(params));
905 params.pipe_format = state->format;
906 params.force_level = force_level;
907 params.width0 = width0;
908 params.height0 = height0;
909 params.first_level = state->u.tex.first_level;
910 params.last_level = state->u.tex.last_level;
911 params.first_layer = state->u.tex.first_layer;
912 params.last_layer = state->u.tex.last_layer;
913 params.target = state->target;
914 params.swizzle[0] = state->swizzle_r;
915 params.swizzle[1] = state->swizzle_g;
916 params.swizzle[2] = state->swizzle_b;
917 params.swizzle[3] = state->swizzle_a;
918
919 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
920 &view->skip_mip_address_reloc,
921 view->tex_resource_words);
922 if (ret != 0) {
923 FREE(view);
924 return NULL;
925 }
926
927 if (state->format == PIPE_FORMAT_X24S8_UINT ||
928 state->format == PIPE_FORMAT_S8X24_UINT ||
929 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
930 state->format == PIPE_FORMAT_S8_UINT)
931 view->is_stencil_sampler = true;
932
933 view->tex_resource = &tmp->resource;
934
935 return &view->base;
936 }
937
938 static struct pipe_sampler_view *
939 evergreen_create_sampler_view(struct pipe_context *ctx,
940 struct pipe_resource *tex,
941 const struct pipe_sampler_view *state)
942 {
943 return evergreen_create_sampler_view_custom(ctx, tex, state,
944 tex->width0, tex->height0, 0);
945 }
946
947 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
948 {
949 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
950 struct r600_config_state *a = (struct r600_config_state*)atom;
951
952 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
953 if (a->dyn_gpr_enabled) {
954 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
955 radeon_emit(cs, 0);
956 radeon_emit(cs, 0);
957 } else {
958 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
959 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
960 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
961 }
962 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
963 if (a->dyn_gpr_enabled) {
964 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
965 S_028838_PS_GPRS(0x1e) |
966 S_028838_VS_GPRS(0x1e) |
967 S_028838_GS_GPRS(0x1e) |
968 S_028838_ES_GPRS(0x1e) |
969 S_028838_HS_GPRS(0x1e) |
970 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
971 }
972 }
973
974 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
975 {
976 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
977 struct pipe_clip_state *state = &rctx->clip_state.state;
978
979 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
980 radeon_emit_array(cs, (unsigned*)state, 6*4);
981 }
982
983 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
984 const struct pipe_poly_stipple *state)
985 {
986 }
987
988 static void evergreen_get_scissor_rect(struct r600_context *rctx,
989 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
990 uint32_t *tl, uint32_t *br)
991 {
992 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
993
994 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
995
996 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
997 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
998 }
999
1000 struct r600_tex_color_info {
1001 unsigned info;
1002 unsigned view;
1003 unsigned dim;
1004 unsigned pitch;
1005 unsigned slice;
1006 unsigned attrib;
1007 unsigned ntype;
1008 unsigned fmask;
1009 unsigned fmask_slice;
1010 uint64_t offset;
1011 boolean export_16bpc;
1012 };
1013
1014 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1015 struct r600_resource *res,
1016 enum pipe_format pformat,
1017 unsigned first_element,
1018 unsigned last_element,
1019 struct r600_tex_color_info *color)
1020 {
1021 unsigned format, swap, ntype, endian;
1022 const struct util_format_description *desc;
1023 unsigned block_size = align(util_format_get_blocksize(res->b.b.format), 4);
1024 unsigned pitch_alignment =
1025 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1026 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1027 int i;
1028 unsigned width_elements;
1029
1030 width_elements = last_element - first_element + 1;
1031
1032 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1033 swap = r600_translate_colorswap(pformat, FALSE);
1034
1035 endian = r600_colorformat_endian_swap(format, FALSE);
1036
1037 desc = util_format_description(pformat);
1038 for (i = 0; i < 4; i++) {
1039 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1040 break;
1041 }
1042 }
1043 ntype = V_028C70_NUMBER_UNORM;
1044 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1045 ntype = V_028C70_NUMBER_SRGB;
1046 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1047 if (desc->channel[i].normalized)
1048 ntype = V_028C70_NUMBER_SNORM;
1049 else if (desc->channel[i].pure_integer)
1050 ntype = V_028C70_NUMBER_SINT;
1051 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1052 if (desc->channel[i].normalized)
1053 ntype = V_028C70_NUMBER_UNORM;
1054 else if (desc->channel[i].pure_integer)
1055 ntype = V_028C70_NUMBER_UINT;
1056 }
1057 pitch = (pitch / 8) - 1;
1058 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1059
1060 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1061 color->info |= S_028C70_FORMAT(format) |
1062 S_028C70_COMP_SWAP(swap) |
1063 S_028C70_BLEND_CLAMP(0) |
1064 S_028C70_BLEND_BYPASS(1) |
1065 S_028C70_NUMBER_TYPE(ntype) |
1066 S_028C70_ENDIAN(endian);
1067 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1068 color->ntype = ntype;
1069 color->export_16bpc = false;
1070 color->dim = width_elements - 1;
1071 color->slice = 0; /* (width_elements / 64) - 1;*/
1072 color->view = 0;
1073 color->offset = res->gpu_address >> 8;
1074
1075 color->fmask = color->offset;
1076 color->fmask_slice = 0;
1077 }
1078
1079 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1080 struct r600_texture *rtex,
1081 unsigned level,
1082 unsigned first_layer,
1083 unsigned last_layer,
1084 enum pipe_format pformat,
1085 struct r600_tex_color_info *color)
1086 {
1087 struct r600_screen *rscreen = rctx->screen;
1088 unsigned pitch, slice;
1089 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1090 unsigned format, swap, ntype, endian;
1091 const struct util_format_description *desc;
1092 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1093 int i;
1094
1095 color->offset = rtex->surface.u.legacy.level[level].offset;
1096 color->view = S_028C6C_SLICE_START(first_layer) |
1097 S_028C6C_SLICE_MAX(last_layer);
1098
1099 color->offset += rtex->resource.gpu_address;
1100 color->offset >>= 8;
1101
1102 color->dim = 0;
1103 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1104 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1105 if (slice) {
1106 slice = slice - 1;
1107 }
1108
1109 color->info = 0;
1110 switch (rtex->surface.u.legacy.level[level].mode) {
1111 default:
1112 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1113 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1114 non_disp_tiling = 1;
1115 break;
1116 case RADEON_SURF_MODE_1D:
1117 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1118 non_disp_tiling = rtex->non_disp_tiling;
1119 break;
1120 case RADEON_SURF_MODE_2D:
1121 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1122 non_disp_tiling = rtex->non_disp_tiling;
1123 break;
1124 }
1125 tile_split = rtex->surface.u.legacy.tile_split;
1126 macro_aspect = rtex->surface.u.legacy.mtilea;
1127 bankw = rtex->surface.u.legacy.bankw;
1128 bankh = rtex->surface.u.legacy.bankh;
1129 if (rtex->fmask.size)
1130 fmask_bankh = rtex->fmask.bank_height;
1131 else
1132 fmask_bankh = rtex->surface.u.legacy.bankh;
1133 tile_split = eg_tile_split(tile_split);
1134 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1135 bankw = eg_bank_wh(bankw);
1136 bankh = eg_bank_wh(bankh);
1137 fmask_bankh = eg_bank_wh(fmask_bankh);
1138
1139 if (rscreen->b.chip_class == CAYMAN) {
1140 if (util_format_get_blocksize(pformat) >= 16)
1141 non_disp_tiling = 1;
1142 }
1143 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1144 desc = util_format_description(pformat);
1145 for (i = 0; i < 4; i++) {
1146 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1147 break;
1148 }
1149 }
1150 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1151 S_028C74_NUM_BANKS(nbanks) |
1152 S_028C74_BANK_WIDTH(bankw) |
1153 S_028C74_BANK_HEIGHT(bankh) |
1154 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1155 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1156 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1157
1158 if (rctx->b.chip_class == CAYMAN) {
1159 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1160 PIPE_SWIZZLE_1);
1161
1162 if (rtex->resource.b.b.nr_samples > 1) {
1163 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1164 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1165 S_028C74_NUM_FRAGMENTS(log_samples);
1166 }
1167 }
1168
1169 ntype = V_028C70_NUMBER_UNORM;
1170 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1171 ntype = V_028C70_NUMBER_SRGB;
1172 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1173 if (desc->channel[i].normalized)
1174 ntype = V_028C70_NUMBER_SNORM;
1175 else if (desc->channel[i].pure_integer)
1176 ntype = V_028C70_NUMBER_SINT;
1177 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1178 if (desc->channel[i].normalized)
1179 ntype = V_028C70_NUMBER_UNORM;
1180 else if (desc->channel[i].pure_integer)
1181 ntype = V_028C70_NUMBER_UINT;
1182 }
1183
1184 if (R600_BIG_ENDIAN)
1185 do_endian_swap = !rtex->db_compatible;
1186
1187 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1188 assert(format != ~0);
1189 swap = r600_translate_colorswap(pformat, do_endian_swap);
1190 assert(swap != ~0);
1191
1192 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1193
1194 /* blend clamp should be set for all NORM/SRGB types */
1195 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1196 ntype == V_028C70_NUMBER_SRGB)
1197 blend_clamp = 1;
1198
1199 /* set blend bypass according to docs if SINT/UINT or
1200 8/24 COLOR variants */
1201 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1202 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1203 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1204 blend_clamp = 0;
1205 blend_bypass = 1;
1206 }
1207
1208 color->ntype = ntype;
1209 color->info |= S_028C70_FORMAT(format) |
1210 S_028C70_COMP_SWAP(swap) |
1211 S_028C70_BLEND_CLAMP(blend_clamp) |
1212 S_028C70_BLEND_BYPASS(blend_bypass) |
1213 S_028C70_NUMBER_TYPE(ntype) |
1214 S_028C70_ENDIAN(endian);
1215
1216 if (rtex->fmask.size) {
1217 color->info |= S_028C70_COMPRESSION(1);
1218 }
1219
1220 /* EXPORT_NORM is an optimzation that can be enabled for better
1221 * performance in certain cases.
1222 * EXPORT_NORM can be enabled if:
1223 * - 11-bit or smaller UNORM/SNORM/SRGB
1224 * - 16-bit or smaller FLOAT
1225 */
1226 color->export_16bpc = false;
1227 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1228 ((desc->channel[i].size < 12 &&
1229 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1230 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1231 (desc->channel[i].size < 17 &&
1232 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1233 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1234 color->export_16bpc = true;
1235 }
1236
1237 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1238 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1239
1240 if (rtex->fmask.size) {
1241 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1242 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1243 } else {
1244 color->fmask = color->offset;
1245 color->fmask_slice = S_028C88_TILE_MAX(slice);
1246 }
1247 }
1248
1249 /**
1250 * This function intializes the CB* register values for RATs. It is meant
1251 * to be used for 1D aligned buffers that do not have an associated
1252 * radeon_surf.
1253 */
1254 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1255 struct r600_surface *surf)
1256 {
1257 struct pipe_resource *pipe_buffer = surf->base.texture;
1258 struct r600_tex_color_info color;
1259
1260 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1261 surf->base.format, 0, pipe_buffer->width0,
1262 &color);
1263
1264 surf->cb_color_base = color.offset;
1265 surf->cb_color_dim = color.dim;
1266 surf->cb_color_info = color.info | S_028C70_RAT(1);
1267 surf->cb_color_pitch = color.pitch;
1268 surf->cb_color_slice = color.slice;
1269 surf->cb_color_view = color.view;
1270 surf->cb_color_attrib = color.attrib;
1271 surf->cb_color_fmask = color.fmask;
1272 surf->cb_color_fmask_slice = color.fmask_slice;
1273
1274 surf->cb_color_view = 0;
1275
1276 /* Set the buffer range the GPU will have access to: */
1277 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1278 0, pipe_buffer->width0);
1279 }
1280
1281
1282 void evergreen_init_color_surface(struct r600_context *rctx,
1283 struct r600_surface *surf)
1284 {
1285 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1286 unsigned level = surf->base.u.tex.level;
1287 struct r600_tex_color_info color;
1288
1289 evergreen_set_color_surface_common(rctx, rtex, level,
1290 surf->base.u.tex.first_layer,
1291 surf->base.u.tex.last_layer,
1292 surf->base.format,
1293 &color);
1294
1295 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1296 color.ntype == V_028C70_NUMBER_SINT;
1297 surf->export_16bpc = color.export_16bpc;
1298
1299 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1300 surf->cb_color_base = color.offset;
1301 surf->cb_color_dim = color.dim;
1302 surf->cb_color_info = color.info;
1303 surf->cb_color_pitch = color.pitch;
1304 surf->cb_color_slice = color.slice;
1305 surf->cb_color_view = color.view;
1306 surf->cb_color_attrib = color.attrib;
1307 surf->cb_color_fmask = color.fmask;
1308 surf->cb_color_fmask_slice = color.fmask_slice;
1309
1310 surf->color_initialized = true;
1311 }
1312
1313 static void evergreen_init_depth_surface(struct r600_context *rctx,
1314 struct r600_surface *surf)
1315 {
1316 struct r600_screen *rscreen = rctx->screen;
1317 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1318 unsigned level = surf->base.u.tex.level;
1319 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1320 uint64_t offset;
1321 unsigned format, array_mode;
1322 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1323
1324
1325 format = r600_translate_dbformat(surf->base.format);
1326 assert(format != ~0);
1327
1328 offset = rtex->resource.gpu_address;
1329 offset += rtex->surface.u.legacy.level[level].offset;
1330
1331 switch (rtex->surface.u.legacy.level[level].mode) {
1332 case RADEON_SURF_MODE_2D:
1333 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1334 break;
1335 case RADEON_SURF_MODE_1D:
1336 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1337 default:
1338 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1339 break;
1340 }
1341 tile_split = rtex->surface.u.legacy.tile_split;
1342 macro_aspect = rtex->surface.u.legacy.mtilea;
1343 bankw = rtex->surface.u.legacy.bankw;
1344 bankh = rtex->surface.u.legacy.bankh;
1345 tile_split = eg_tile_split(tile_split);
1346 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1347 bankw = eg_bank_wh(bankw);
1348 bankh = eg_bank_wh(bankh);
1349 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1350 offset >>= 8;
1351
1352 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1353 S_028040_FORMAT(format) |
1354 S_028040_TILE_SPLIT(tile_split)|
1355 S_028040_NUM_BANKS(nbanks) |
1356 S_028040_BANK_WIDTH(bankw) |
1357 S_028040_BANK_HEIGHT(bankh) |
1358 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1359 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1360 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1361 }
1362
1363 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1364
1365 surf->db_depth_base = offset;
1366 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1367 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1368 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1369 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1370 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1371 levelinfo->nblk_y / 64 - 1);
1372
1373 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1374 uint64_t stencil_offset;
1375 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1376
1377 stile_split = eg_tile_split(stile_split);
1378
1379 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1380 stencil_offset += rtex->resource.gpu_address;
1381
1382 surf->db_stencil_base = stencil_offset >> 8;
1383 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1384 S_028044_TILE_SPLIT(stile_split);
1385 } else {
1386 surf->db_stencil_base = offset;
1387 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1388 * Older kernels are out of luck. */
1389 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1390 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1391 S_028044_FORMAT(V_028044_STENCIL_8);
1392 }
1393
1394 /* use htile only for first level */
1395 if (rtex->htile_buffer && !level) {
1396 uint64_t va = rtex->htile_buffer->gpu_address;
1397 surf->db_htile_data_base = va >> 8;
1398 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1399 S_028ABC_HTILE_HEIGHT(1) |
1400 S_028ABC_FULL_CACHE(1);
1401 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1402 surf->db_preload_control = 0;
1403 }
1404
1405 surf->depth_initialized = true;
1406 }
1407
1408 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1409 const struct pipe_framebuffer_state *state)
1410 {
1411 struct r600_context *rctx = (struct r600_context *)ctx;
1412 struct r600_surface *surf;
1413 struct r600_texture *rtex;
1414 uint32_t i, log_samples;
1415
1416 /* Flush TC when changing the framebuffer state, because the only
1417 * client not using TC that can change textures is the framebuffer.
1418 * Other places don't typically have to flush TC.
1419 */
1420 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1421 R600_CONTEXT_FLUSH_AND_INV |
1422 R600_CONTEXT_FLUSH_AND_INV_CB |
1423 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1424 R600_CONTEXT_FLUSH_AND_INV_DB |
1425 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1426 R600_CONTEXT_INV_TEX_CACHE;
1427
1428 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1429
1430 /* Colorbuffers. */
1431 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1432 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1433 util_format_is_pure_integer(state->cbufs[0]->format);
1434 rctx->framebuffer.compressed_cb_mask = 0;
1435 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1436
1437 for (i = 0; i < state->nr_cbufs; i++) {
1438 surf = (struct r600_surface*)state->cbufs[i];
1439 if (!surf)
1440 continue;
1441
1442 rtex = (struct r600_texture*)surf->base.texture;
1443
1444 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1445
1446 if (!surf->color_initialized) {
1447 evergreen_init_color_surface(rctx, surf);
1448 }
1449
1450 if (!surf->export_16bpc) {
1451 rctx->framebuffer.export_16bpc = false;
1452 }
1453
1454 if (rtex->fmask.size) {
1455 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1456 }
1457 }
1458
1459 /* Update alpha-test state dependencies.
1460 * Alpha-test is done on the first colorbuffer only. */
1461 if (state->nr_cbufs) {
1462 bool alphatest_bypass = false;
1463 bool export_16bpc = true;
1464
1465 surf = (struct r600_surface*)state->cbufs[0];
1466 if (surf) {
1467 alphatest_bypass = surf->alphatest_bypass;
1468 export_16bpc = surf->export_16bpc;
1469 }
1470
1471 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1472 rctx->alphatest_state.bypass = alphatest_bypass;
1473 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1474 }
1475 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1476 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1477 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1478 }
1479 }
1480
1481 /* ZS buffer. */
1482 if (state->zsbuf) {
1483 surf = (struct r600_surface*)state->zsbuf;
1484
1485 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1486
1487 if (!surf->depth_initialized) {
1488 evergreen_init_depth_surface(rctx, surf);
1489 }
1490
1491 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1492 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1493 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1494 }
1495
1496 if (rctx->db_state.rsurf != surf) {
1497 rctx->db_state.rsurf = surf;
1498 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1499 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1500 }
1501 } else if (rctx->db_state.rsurf) {
1502 rctx->db_state.rsurf = NULL;
1503 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1504 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1505 }
1506
1507 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1508 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1509 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1510 }
1511
1512 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1513 rctx->alphatest_state.bypass = false;
1514 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1515 }
1516
1517 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1518 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1519 if ((rctx->b.chip_class == CAYMAN ||
1520 rctx->b.family == CHIP_RV770) &&
1521 rctx->db_misc_state.log_samples != log_samples) {
1522 rctx->db_misc_state.log_samples = log_samples;
1523 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1524 }
1525
1526
1527 /* Calculate the CS size. */
1528 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1529
1530 /* MSAA. */
1531 if (rctx->b.chip_class == EVERGREEN)
1532 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1533 else
1534 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1535
1536 /* Colorbuffers. */
1537 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1538 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1539 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1540
1541 /* ZS buffer. */
1542 if (state->zsbuf) {
1543 rctx->framebuffer.atom.num_dw += 24;
1544 rctx->framebuffer.atom.num_dw += 2;
1545 } else if (rctx->screen->b.info.drm_minor >= 18) {
1546 rctx->framebuffer.atom.num_dw += 4;
1547 }
1548
1549 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1550
1551 r600_set_sample_locations_constant_buffer(rctx);
1552 }
1553
1554 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1555 {
1556 struct r600_context *rctx = (struct r600_context *)ctx;
1557
1558 if (rctx->ps_iter_samples == min_samples)
1559 return;
1560
1561 rctx->ps_iter_samples = min_samples;
1562 if (rctx->framebuffer.nr_samples > 1) {
1563 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1564 }
1565 }
1566
1567 /* 8xMSAA */
1568 static uint32_t sample_locs_8x[] = {
1569 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1570 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1571 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1572 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1573 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1574 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1575 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1576 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1577 };
1578 static unsigned max_dist_8x = 7;
1579
1580 static void evergreen_get_sample_position(struct pipe_context *ctx,
1581 unsigned sample_count,
1582 unsigned sample_index,
1583 float *out_value)
1584 {
1585 int offset, index;
1586 struct {
1587 int idx:4;
1588 } val;
1589 switch (sample_count) {
1590 case 1:
1591 default:
1592 out_value[0] = out_value[1] = 0.5;
1593 break;
1594 case 2:
1595 offset = 4 * (sample_index * 2);
1596 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1597 out_value[0] = (float)(val.idx + 8) / 16.0f;
1598 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1599 out_value[1] = (float)(val.idx + 8) / 16.0f;
1600 break;
1601 case 4:
1602 offset = 4 * (sample_index * 2);
1603 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1604 out_value[0] = (float)(val.idx + 8) / 16.0f;
1605 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1606 out_value[1] = (float)(val.idx + 8) / 16.0f;
1607 break;
1608 case 8:
1609 offset = 4 * (sample_index % 4 * 2);
1610 index = (sample_index / 4);
1611 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1612 out_value[0] = (float)(val.idx + 8) / 16.0f;
1613 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1614 out_value[1] = (float)(val.idx + 8) / 16.0f;
1615 break;
1616 }
1617 }
1618
1619 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1620 {
1621
1622 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1623 unsigned max_dist = 0;
1624
1625 switch (nr_samples) {
1626 default:
1627 nr_samples = 0;
1628 break;
1629 case 2:
1630 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1631 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1632 max_dist = eg_max_dist_2x;
1633 break;
1634 case 4:
1635 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1636 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1637 max_dist = eg_max_dist_4x;
1638 break;
1639 case 8:
1640 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1641 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1642 max_dist = max_dist_8x;
1643 break;
1644 }
1645
1646 if (nr_samples > 1) {
1647 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1648 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1649 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1650 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1651 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1652 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1653 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1654 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1655 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1656 } else {
1657 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1658 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1659 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1660 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1661 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1662 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1663 }
1664 }
1665
1666 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1667 {
1668 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1669 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1670 unsigned nr_cbufs = state->nr_cbufs;
1671 unsigned i, tl, br;
1672 struct r600_texture *tex = NULL;
1673 struct r600_surface *cb = NULL;
1674
1675 /* XXX support more colorbuffers once we need them */
1676 assert(nr_cbufs <= 8);
1677 if (nr_cbufs > 8)
1678 nr_cbufs = 8;
1679
1680 /* Colorbuffers. */
1681 for (i = 0; i < nr_cbufs; i++) {
1682 unsigned reloc, cmask_reloc;
1683
1684 cb = (struct r600_surface*)state->cbufs[i];
1685 if (!cb) {
1686 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1687 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1688 continue;
1689 }
1690
1691 tex = (struct r600_texture *)cb->base.texture;
1692 reloc = radeon_add_to_buffer_list(&rctx->b,
1693 &rctx->b.gfx,
1694 (struct r600_resource*)cb->base.texture,
1695 RADEON_USAGE_READWRITE,
1696 tex->resource.b.b.nr_samples > 1 ?
1697 RADEON_PRIO_COLOR_BUFFER_MSAA :
1698 RADEON_PRIO_COLOR_BUFFER);
1699
1700 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1701 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1702 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1703 RADEON_PRIO_CMASK);
1704 } else {
1705 cmask_reloc = reloc;
1706 }
1707
1708 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1709 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1710 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1711 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1712 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1713 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1714 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1715 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1716 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1717 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1718 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1719 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1720 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1721 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1722
1723 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1724 radeon_emit(cs, reloc);
1725
1726 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1727 radeon_emit(cs, reloc);
1728
1729 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1730 radeon_emit(cs, cmask_reloc);
1731
1732 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1733 radeon_emit(cs, reloc);
1734 }
1735 /* set CB_COLOR1_INFO for possible dual-src blending */
1736 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1737 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1738 cb->cb_color_info | tex->cb_color_info);
1739 i++;
1740 }
1741 for (; i < 8 ; i++)
1742 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1743 for (; i < 12; i++)
1744 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1745
1746 /* ZS buffer. */
1747 if (state->zsbuf) {
1748 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1749 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1750 &rctx->b.gfx,
1751 (struct r600_resource*)state->zsbuf->texture,
1752 RADEON_USAGE_READWRITE,
1753 zb->base.texture->nr_samples > 1 ?
1754 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1755 RADEON_PRIO_DEPTH_BUFFER);
1756
1757 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1758
1759 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1760 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1761 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1762 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1763 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1764 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1765 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1766 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1767 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1768
1769 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1770 radeon_emit(cs, reloc);
1771
1772 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1773 radeon_emit(cs, reloc);
1774
1775 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1776 radeon_emit(cs, reloc);
1777
1778 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1779 radeon_emit(cs, reloc);
1780 } else if (rctx->screen->b.info.drm_minor >= 18) {
1781 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1782 * Older kernels are out of luck. */
1783 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1784 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1785 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1786 }
1787
1788 /* Framebuffer dimensions. */
1789 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1790
1791 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1792 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1793 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1794
1795 if (rctx->b.chip_class == EVERGREEN) {
1796 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1797 } else {
1798 unsigned sc_mode_cntl_1 =
1799 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1800 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1801
1802 if (rctx->framebuffer.nr_samples > 1)
1803 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1804 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1805 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1806 }
1807 }
1808
1809 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1810 {
1811 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1812 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1813 float offset_units = state->offset_units;
1814 float offset_scale = state->offset_scale;
1815 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1816
1817 if (!state->offset_units_unscaled) {
1818 switch (state->zs_format) {
1819 case PIPE_FORMAT_Z24X8_UNORM:
1820 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1821 case PIPE_FORMAT_X8Z24_UNORM:
1822 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1823 offset_units *= 2.0f;
1824 pa_su_poly_offset_db_fmt_cntl =
1825 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1826 break;
1827 case PIPE_FORMAT_Z16_UNORM:
1828 offset_units *= 4.0f;
1829 pa_su_poly_offset_db_fmt_cntl =
1830 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1831 break;
1832 default:
1833 pa_su_poly_offset_db_fmt_cntl =
1834 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1835 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1836 }
1837 }
1838
1839 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1840 radeon_emit(cs, fui(offset_scale));
1841 radeon_emit(cs, fui(offset_units));
1842 radeon_emit(cs, fui(offset_scale));
1843 radeon_emit(cs, fui(offset_units));
1844
1845 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1846 pa_su_poly_offset_db_fmt_cntl);
1847 }
1848
1849 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1850 {
1851 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1852 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1853 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1854 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1855
1856 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1857 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1858 /* This must match the used export instructions exactly.
1859 * Other values may lead to undefined behavior and hangs.
1860 */
1861 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1862 }
1863
1864 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1865 {
1866 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1867 struct r600_db_state *a = (struct r600_db_state*)atom;
1868
1869 if (a->rsurf && a->rsurf->db_htile_surface) {
1870 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1871 unsigned reloc_idx;
1872
1873 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1874 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1875 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1876 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1877 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1878 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1879 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1880 radeon_emit(cs, reloc_idx);
1881 } else {
1882 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1883 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1884 }
1885 }
1886
1887 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1888 {
1889 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1890 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1891 unsigned db_render_control = 0;
1892 unsigned db_count_control = 0;
1893 unsigned db_render_override =
1894 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1895 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1896
1897 if (rctx->b.num_occlusion_queries > 0 &&
1898 !a->occlusion_queries_disabled) {
1899 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1900 if (rctx->b.chip_class == CAYMAN) {
1901 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1902 }
1903 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1904 } else {
1905 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1906 }
1907
1908 /* This is to fix a lockup when hyperz and alpha test are enabled at
1909 * the same time somehow GPU get confuse on which order to pick for
1910 * z test
1911 */
1912 if (rctx->alphatest_state.sx_alpha_test_control)
1913 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1914
1915 if (a->flush_depthstencil_through_cb) {
1916 assert(a->copy_depth || a->copy_stencil);
1917
1918 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1919 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1920 S_028000_COPY_CENTROID(1) |
1921 S_028000_COPY_SAMPLE(a->copy_sample);
1922 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1923 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1924 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1925 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1926 }
1927 if (a->htile_clear) {
1928 /* FIXME we might want to disable cliprect here */
1929 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1930 }
1931
1932 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1933 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1934 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1935 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1936 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1937 }
1938
1939 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1940 struct r600_vertexbuf_state *state,
1941 unsigned resource_offset,
1942 unsigned pkt_flags)
1943 {
1944 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1945 uint32_t dirty_mask = state->dirty_mask;
1946
1947 while (dirty_mask) {
1948 struct pipe_vertex_buffer *vb;
1949 struct r600_resource *rbuffer;
1950 uint64_t va;
1951 unsigned buffer_index = u_bit_scan(&dirty_mask);
1952
1953 vb = &state->vb[buffer_index];
1954 rbuffer = (struct r600_resource*)vb->buffer;
1955 assert(rbuffer);
1956
1957 va = rbuffer->gpu_address + vb->buffer_offset;
1958
1959 /* fetch resources start at index 992 */
1960 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1961 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1962 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1963 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1964 radeon_emit(cs, /* RESOURCEi_WORD2 */
1965 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1966 S_030008_STRIDE(vb->stride) |
1967 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1968 radeon_emit(cs, /* RESOURCEi_WORD3 */
1969 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1970 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1971 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1972 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1973 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1974 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1975 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1976 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1977
1978 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1979 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1980 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1981 }
1982 state->dirty_mask = 0;
1983 }
1984
1985 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1986 {
1987 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1988 }
1989
1990 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1991 {
1992 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1993 RADEON_CP_PACKET3_COMPUTE_MODE);
1994 }
1995
1996 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1997 struct r600_constbuf_state *state,
1998 unsigned buffer_id_base,
1999 unsigned reg_alu_constbuf_size,
2000 unsigned reg_alu_const_cache,
2001 unsigned pkt_flags)
2002 {
2003 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2004 uint32_t dirty_mask = state->dirty_mask;
2005
2006 while (dirty_mask) {
2007 struct pipe_constant_buffer *cb;
2008 struct r600_resource *rbuffer;
2009 uint64_t va;
2010 unsigned buffer_index = ffs(dirty_mask) - 1;
2011 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2012
2013 cb = &state->cb[buffer_index];
2014 rbuffer = (struct r600_resource*)cb->buffer;
2015 assert(rbuffer);
2016
2017 va = rbuffer->gpu_address + cb->buffer_offset;
2018
2019 if (!gs_ring_buffer) {
2020 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2021 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2022 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2023 pkt_flags);
2024 }
2025
2026 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2027 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2028 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2029
2030 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2031 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2032 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2033 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2034 radeon_emit(cs, /* RESOURCEi_WORD2 */
2035 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2036 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2037 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2038 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2039 radeon_emit(cs, /* RESOURCEi_WORD3 */
2040 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2041 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2042 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2043 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2044 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2045 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2046 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2047 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2048 radeon_emit(cs, /* RESOURCEi_WORD7 */
2049 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2050
2051 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2052 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2053 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2054
2055 dirty_mask &= ~(1 << buffer_index);
2056 }
2057 state->dirty_mask = 0;
2058 }
2059
2060 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2061 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2062 {
2063 if (rctx->vs_shader->current->shader.vs_as_ls) {
2064 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2065 EG_FETCH_CONSTANTS_OFFSET_LS,
2066 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2067 R_028F40_ALU_CONST_CACHE_LS_0,
2068 0 /* PKT3 flags */);
2069 } else {
2070 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2071 EG_FETCH_CONSTANTS_OFFSET_VS,
2072 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2073 R_028980_ALU_CONST_CACHE_VS_0,
2074 0 /* PKT3 flags */);
2075 }
2076 }
2077
2078 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2079 {
2080 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2081 EG_FETCH_CONSTANTS_OFFSET_GS,
2082 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2083 R_0289C0_ALU_CONST_CACHE_GS_0,
2084 0 /* PKT3 flags */);
2085 }
2086
2087 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2088 {
2089 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2090 EG_FETCH_CONSTANTS_OFFSET_PS,
2091 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2092 R_028940_ALU_CONST_CACHE_PS_0,
2093 0 /* PKT3 flags */);
2094 }
2095
2096 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2097 {
2098 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2099 EG_FETCH_CONSTANTS_OFFSET_CS,
2100 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2101 R_028F40_ALU_CONST_CACHE_LS_0,
2102 RADEON_CP_PACKET3_COMPUTE_MODE);
2103 }
2104
2105 /* tes constants can be emitted to VS or ES - which are common */
2106 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2107 {
2108 if (!rctx->tes_shader)
2109 return;
2110 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2111 EG_FETCH_CONSTANTS_OFFSET_VS,
2112 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2113 R_028980_ALU_CONST_CACHE_VS_0,
2114 0);
2115 }
2116
2117 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2118 {
2119 if (!rctx->tes_shader)
2120 return;
2121 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2122 EG_FETCH_CONSTANTS_OFFSET_HS,
2123 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2124 R_028F00_ALU_CONST_CACHE_HS_0,
2125 0);
2126 }
2127
2128 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2129 struct r600_samplerview_state *state,
2130 unsigned resource_id_base, unsigned pkt_flags)
2131 {
2132 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2133 uint32_t dirty_mask = state->dirty_mask;
2134
2135 while (dirty_mask) {
2136 struct r600_pipe_sampler_view *rview;
2137 unsigned resource_index = u_bit_scan(&dirty_mask);
2138 unsigned reloc;
2139
2140 rview = state->views[resource_index];
2141 assert(rview);
2142
2143 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2144 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2145 radeon_emit_array(cs, rview->tex_resource_words, 8);
2146
2147 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2148 RADEON_USAGE_READ,
2149 r600_get_sampler_view_priority(rview->tex_resource));
2150 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2151 radeon_emit(cs, reloc);
2152
2153 if (!rview->skip_mip_address_reloc) {
2154 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2155 radeon_emit(cs, reloc);
2156 }
2157 }
2158 state->dirty_mask = 0;
2159 }
2160
2161 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2162 {
2163 if (rctx->vs_shader->current->shader.vs_as_ls) {
2164 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2165 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2166 } else {
2167 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2168 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2169 }
2170 }
2171
2172 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2173 {
2174 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2175 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2176 }
2177
2178 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2179 {
2180 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2181 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2182 }
2183
2184 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2185 {
2186 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2187 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2188 }
2189
2190 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2191 {
2192 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2193 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2194 }
2195
2196 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2197 {
2198 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2199 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2200 }
2201
2202 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2203 struct r600_textures_info *texinfo,
2204 unsigned resource_id_base,
2205 unsigned border_index_reg,
2206 unsigned pkt_flags)
2207 {
2208 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2209 uint32_t dirty_mask = texinfo->states.dirty_mask;
2210
2211 while (dirty_mask) {
2212 struct r600_pipe_sampler_state *rstate;
2213 unsigned i = u_bit_scan(&dirty_mask);
2214
2215 rstate = texinfo->states.states[i];
2216 assert(rstate);
2217
2218 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2219 radeon_emit(cs, (resource_id_base + i) * 3);
2220 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2221
2222 if (rstate->border_color_use) {
2223 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2224 radeon_emit(cs, i);
2225 radeon_emit_array(cs, rstate->border_color.ui, 4);
2226 }
2227 }
2228 texinfo->states.dirty_mask = 0;
2229 }
2230
2231 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2232 {
2233 if (rctx->vs_shader->current->shader.vs_as_ls) {
2234 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2235 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2236 } else {
2237 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2238 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2239 }
2240 }
2241
2242 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2243 {
2244 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2245 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2246 }
2247
2248 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2249 {
2250 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2251 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2252 }
2253
2254 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2255 {
2256 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2257 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2258 }
2259
2260 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2261 {
2262 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2263 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2264 }
2265
2266 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2267 {
2268 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2269 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2270 RADEON_CP_PACKET3_COMPUTE_MODE);
2271 }
2272
2273 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2274 {
2275 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2276 uint8_t mask = s->sample_mask;
2277
2278 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2279 mask | (mask << 8) | (mask << 16) | (mask << 24));
2280 }
2281
2282 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2283 {
2284 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2285 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2286 uint16_t mask = s->sample_mask;
2287
2288 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2289 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2290 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2291 }
2292
2293 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2294 {
2295 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2296 struct r600_cso_state *state = (struct r600_cso_state*)a;
2297 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2298
2299 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2300 (shader->buffer->gpu_address + shader->offset) >> 8);
2301 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2302 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2303 RADEON_USAGE_READ,
2304 RADEON_PRIO_SHADER_BINARY));
2305 }
2306
2307 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2308 {
2309 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2310 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2311
2312 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2313
2314 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2315 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2316 primid = 1;
2317 }
2318
2319 if (state->geom_enable) {
2320 uint32_t cut_val;
2321
2322 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2323 cut_val = V_028A40_GS_CUT_128;
2324 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2325 cut_val = V_028A40_GS_CUT_256;
2326 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2327 cut_val = V_028A40_GS_CUT_512;
2328 else
2329 cut_val = V_028A40_GS_CUT_1024;
2330
2331 v = S_028B54_GS_EN(1) |
2332 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2333 if (!rctx->tes_shader)
2334 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2335
2336 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2337 S_028A40_CUT_MODE(cut_val);
2338
2339 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2340 primid = 1;
2341 }
2342
2343 if (rctx->tes_shader) {
2344 uint32_t type, partitioning, topology;
2345 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2346 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2347 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2348 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2349 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2350 switch (tes_prim_mode) {
2351 case PIPE_PRIM_LINES:
2352 type = V_028B6C_TESS_ISOLINE;
2353 break;
2354 case PIPE_PRIM_TRIANGLES:
2355 type = V_028B6C_TESS_TRIANGLE;
2356 break;
2357 case PIPE_PRIM_QUADS:
2358 type = V_028B6C_TESS_QUAD;
2359 break;
2360 default:
2361 assert(0);
2362 return;
2363 }
2364
2365 switch (tes_spacing) {
2366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2367 partitioning = V_028B6C_PART_FRAC_ODD;
2368 break;
2369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2370 partitioning = V_028B6C_PART_FRAC_EVEN;
2371 break;
2372 case PIPE_TESS_SPACING_EQUAL:
2373 partitioning = V_028B6C_PART_INTEGER;
2374 break;
2375 default:
2376 assert(0);
2377 return;
2378 }
2379
2380 if (tes_point_mode)
2381 topology = V_028B6C_OUTPUT_POINT;
2382 else if (tes_prim_mode == PIPE_PRIM_LINES)
2383 topology = V_028B6C_OUTPUT_LINE;
2384 else if (tes_vertex_order_cw)
2385 /* XXX follow radeonsi and invert */
2386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2387 else
2388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2389
2390 tf_param = S_028B6C_TYPE(type) |
2391 S_028B6C_PARTITIONING(partitioning) |
2392 S_028B6C_TOPOLOGY(topology);
2393 }
2394
2395 if (rctx->tes_shader) {
2396 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2397 S_028B54_HS_EN(1);
2398 if (!state->geom_enable)
2399 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2400 else
2401 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2402 }
2403
2404 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2405 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2406 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2407 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2408 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2409 }
2410
2411 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2412 {
2413 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2414 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2415 struct r600_resource *rbuffer;
2416
2417 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2418 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2419 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2420
2421 if (state->enable) {
2422 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2423 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2424 rbuffer->gpu_address >> 8);
2425 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2426 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2427 RADEON_USAGE_READWRITE,
2428 RADEON_PRIO_SHADER_RINGS));
2429 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2430 state->esgs_ring.buffer_size >> 8);
2431
2432 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2433 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2434 rbuffer->gpu_address >> 8);
2435 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2436 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2437 RADEON_USAGE_READWRITE,
2438 RADEON_PRIO_SHADER_RINGS));
2439 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2440 state->gsvs_ring.buffer_size >> 8);
2441 } else {
2442 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2443 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2444 }
2445
2446 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2447 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2448 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2449 }
2450
2451 void cayman_init_common_regs(struct r600_command_buffer *cb,
2452 enum chip_class ctx_chip_class,
2453 enum radeon_family ctx_family,
2454 int ctx_drm_minor)
2455 {
2456 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2457 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2458 /* always set the temp clauses */
2459 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2460
2461 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2462 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2463 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2464
2465 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2466
2467 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2468 r600_store_value(cb, 0);
2469 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2470
2471 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2472 }
2473
2474 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2475 {
2476 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2477 int i;
2478
2479 r600_init_command_buffer(cb, 338);
2480
2481 /* This must be first. */
2482 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2483 r600_store_value(cb, 0x80000000);
2484 r600_store_value(cb, 0x80000000);
2485
2486 /* We're setting config registers here. */
2487 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2488 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2489
2490 /* This enables pipeline stat & streamout queries.
2491 * They are only disabled by blits.
2492 */
2493 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2494 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2495
2496 cayman_init_common_regs(cb, rctx->b.chip_class,
2497 rctx->b.family, rctx->screen->b.info.drm_minor);
2498
2499 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2500 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2501
2502 /* remove LS/HS from one SIMD for hw workaround */
2503 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2504 r600_store_value(cb, 0xffffffff);
2505 r600_store_value(cb, 0xffffffff);
2506 r600_store_value(cb, 0xfffffffe);
2507
2508 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2509 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2510 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2511 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2512 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2513 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2514 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2515
2516 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2517 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2518 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2519 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2520 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2521
2522 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2523 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2524 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2525 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2526 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2527 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2528 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2529 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2530 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2531 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2532 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2533 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2534 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2535 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2536
2537 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2538
2539 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2540
2541 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2542 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2543 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2544
2545 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2546 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2547 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2548
2549 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2550
2551 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2552 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2553 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2554
2555 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2556
2557 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2558
2559 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2560
2561 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2562 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2563 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2564 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2565
2566 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2567 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2568
2569 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2570 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2571
2572 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2573 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2574 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2575
2576 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2577 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2578 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2579
2580 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2581 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2582 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2583 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2584 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2585 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2586
2587 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2588
2589 /* to avoid GPU doing any preloading of constant from random address */
2590 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2591 for (i = 0; i < 16; i++)
2592 r600_store_value(cb, 0);
2593
2594 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2595 for (i = 0; i < 16; i++)
2596 r600_store_value(cb, 0);
2597
2598 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2599 for (i = 0; i < 16; i++)
2600 r600_store_value(cb, 0);
2601
2602 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2603 for (i = 0; i < 16; i++)
2604 r600_store_value(cb, 0);
2605
2606 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2607 for (i = 0; i < 16; i++)
2608 r600_store_value(cb, 0);
2609
2610 if (rctx->screen->b.has_streamout) {
2611 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2612 }
2613
2614 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2615 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2616 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2617 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2618 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2619 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2620
2621 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2622 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2623 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2624 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2625 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2626 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2627 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2628 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2629 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2630 }
2631
2632 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2633 enum chip_class ctx_chip_class,
2634 enum radeon_family ctx_family,
2635 int ctx_drm_minor)
2636 {
2637 int ps_prio;
2638 int vs_prio;
2639 int gs_prio;
2640 int es_prio;
2641
2642 int hs_prio;
2643 int cs_prio;
2644 int ls_prio;
2645
2646 unsigned tmp;
2647
2648 ps_prio = 0;
2649 vs_prio = 1;
2650 gs_prio = 2;
2651 es_prio = 3;
2652 hs_prio = 3;
2653 ls_prio = 3;
2654 cs_prio = 0;
2655
2656 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2657 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2658 rctx->r6xx_num_clause_temp_gprs = 4;
2659 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2660 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2661 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2662 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2663
2664 tmp = 0;
2665 switch (ctx_family) {
2666 case CHIP_CEDAR:
2667 case CHIP_PALM:
2668 case CHIP_SUMO:
2669 case CHIP_SUMO2:
2670 case CHIP_CAICOS:
2671 break;
2672 default:
2673 tmp |= S_008C00_VC_ENABLE(1);
2674 break;
2675 }
2676 tmp |= S_008C00_EXPORT_SRC_C(1);
2677 tmp |= S_008C00_CS_PRIO(cs_prio);
2678 tmp |= S_008C00_LS_PRIO(ls_prio);
2679 tmp |= S_008C00_HS_PRIO(hs_prio);
2680 tmp |= S_008C00_PS_PRIO(ps_prio);
2681 tmp |= S_008C00_VS_PRIO(vs_prio);
2682 tmp |= S_008C00_GS_PRIO(gs_prio);
2683 tmp |= S_008C00_ES_PRIO(es_prio);
2684
2685 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2686 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2687
2688 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2689 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2690 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2691
2692 /* The cs checker requires this register to be set. */
2693 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2694
2695 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2696 r600_store_value(cb, 0);
2697 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2698
2699 return;
2700 }
2701
2702 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2703 {
2704 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2705 int num_ps_threads;
2706 int num_vs_threads;
2707 int num_gs_threads;
2708 int num_es_threads;
2709 int num_hs_threads;
2710 int num_ls_threads;
2711
2712 int num_ps_stack_entries;
2713 int num_vs_stack_entries;
2714 int num_gs_stack_entries;
2715 int num_es_stack_entries;
2716 int num_hs_stack_entries;
2717 int num_ls_stack_entries;
2718 enum radeon_family family;
2719 unsigned tmp, i;
2720
2721 if (rctx->b.chip_class == CAYMAN) {
2722 cayman_init_atom_start_cs(rctx);
2723 return;
2724 }
2725
2726 r600_init_command_buffer(cb, 338);
2727
2728 /* This must be first. */
2729 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2730 r600_store_value(cb, 0x80000000);
2731 r600_store_value(cb, 0x80000000);
2732
2733 /* We're setting config registers here. */
2734 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2735 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2736
2737 /* This enables pipeline stat & streamout queries.
2738 * They are only disabled by blits.
2739 */
2740 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2741 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2742
2743 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2744 rctx->b.family, rctx->screen->b.info.drm_minor);
2745
2746 family = rctx->b.family;
2747 switch (family) {
2748 case CHIP_CEDAR:
2749 default:
2750 num_ps_threads = 96;
2751 num_vs_threads = 16;
2752 num_gs_threads = 16;
2753 num_es_threads = 16;
2754 num_hs_threads = 16;
2755 num_ls_threads = 16;
2756 num_ps_stack_entries = 42;
2757 num_vs_stack_entries = 42;
2758 num_gs_stack_entries = 42;
2759 num_es_stack_entries = 42;
2760 num_hs_stack_entries = 42;
2761 num_ls_stack_entries = 42;
2762 break;
2763 case CHIP_REDWOOD:
2764 num_ps_threads = 128;
2765 num_vs_threads = 20;
2766 num_gs_threads = 20;
2767 num_es_threads = 20;
2768 num_hs_threads = 20;
2769 num_ls_threads = 20;
2770 num_ps_stack_entries = 42;
2771 num_vs_stack_entries = 42;
2772 num_gs_stack_entries = 42;
2773 num_es_stack_entries = 42;
2774 num_hs_stack_entries = 42;
2775 num_ls_stack_entries = 42;
2776 break;
2777 case CHIP_JUNIPER:
2778 num_ps_threads = 128;
2779 num_vs_threads = 20;
2780 num_gs_threads = 20;
2781 num_es_threads = 20;
2782 num_hs_threads = 20;
2783 num_ls_threads = 20;
2784 num_ps_stack_entries = 85;
2785 num_vs_stack_entries = 85;
2786 num_gs_stack_entries = 85;
2787 num_es_stack_entries = 85;
2788 num_hs_stack_entries = 85;
2789 num_ls_stack_entries = 85;
2790 break;
2791 case CHIP_CYPRESS:
2792 case CHIP_HEMLOCK:
2793 num_ps_threads = 128;
2794 num_vs_threads = 20;
2795 num_gs_threads = 20;
2796 num_es_threads = 20;
2797 num_hs_threads = 20;
2798 num_ls_threads = 20;
2799 num_ps_stack_entries = 85;
2800 num_vs_stack_entries = 85;
2801 num_gs_stack_entries = 85;
2802 num_es_stack_entries = 85;
2803 num_hs_stack_entries = 85;
2804 num_ls_stack_entries = 85;
2805 break;
2806 case CHIP_PALM:
2807 num_ps_threads = 96;
2808 num_vs_threads = 16;
2809 num_gs_threads = 16;
2810 num_es_threads = 16;
2811 num_hs_threads = 16;
2812 num_ls_threads = 16;
2813 num_ps_stack_entries = 42;
2814 num_vs_stack_entries = 42;
2815 num_gs_stack_entries = 42;
2816 num_es_stack_entries = 42;
2817 num_hs_stack_entries = 42;
2818 num_ls_stack_entries = 42;
2819 break;
2820 case CHIP_SUMO:
2821 num_ps_threads = 96;
2822 num_vs_threads = 25;
2823 num_gs_threads = 25;
2824 num_es_threads = 25;
2825 num_hs_threads = 16;
2826 num_ls_threads = 16;
2827 num_ps_stack_entries = 42;
2828 num_vs_stack_entries = 42;
2829 num_gs_stack_entries = 42;
2830 num_es_stack_entries = 42;
2831 num_hs_stack_entries = 42;
2832 num_ls_stack_entries = 42;
2833 break;
2834 case CHIP_SUMO2:
2835 num_ps_threads = 96;
2836 num_vs_threads = 25;
2837 num_gs_threads = 25;
2838 num_es_threads = 25;
2839 num_hs_threads = 16;
2840 num_ls_threads = 16;
2841 num_ps_stack_entries = 85;
2842 num_vs_stack_entries = 85;
2843 num_gs_stack_entries = 85;
2844 num_es_stack_entries = 85;
2845 num_hs_stack_entries = 85;
2846 num_ls_stack_entries = 85;
2847 break;
2848 case CHIP_BARTS:
2849 num_ps_threads = 128;
2850 num_vs_threads = 20;
2851 num_gs_threads = 20;
2852 num_es_threads = 20;
2853 num_hs_threads = 20;
2854 num_ls_threads = 20;
2855 num_ps_stack_entries = 85;
2856 num_vs_stack_entries = 85;
2857 num_gs_stack_entries = 85;
2858 num_es_stack_entries = 85;
2859 num_hs_stack_entries = 85;
2860 num_ls_stack_entries = 85;
2861 break;
2862 case CHIP_TURKS:
2863 num_ps_threads = 128;
2864 num_vs_threads = 20;
2865 num_gs_threads = 20;
2866 num_es_threads = 20;
2867 num_hs_threads = 20;
2868 num_ls_threads = 20;
2869 num_ps_stack_entries = 42;
2870 num_vs_stack_entries = 42;
2871 num_gs_stack_entries = 42;
2872 num_es_stack_entries = 42;
2873 num_hs_stack_entries = 42;
2874 num_ls_stack_entries = 42;
2875 break;
2876 case CHIP_CAICOS:
2877 num_ps_threads = 96;
2878 num_vs_threads = 10;
2879 num_gs_threads = 10;
2880 num_es_threads = 10;
2881 num_hs_threads = 10;
2882 num_ls_threads = 10;
2883 num_ps_stack_entries = 42;
2884 num_vs_stack_entries = 42;
2885 num_gs_stack_entries = 42;
2886 num_es_stack_entries = 42;
2887 num_hs_stack_entries = 42;
2888 num_ls_stack_entries = 42;
2889 break;
2890 }
2891
2892 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2893 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2894 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2895 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2896
2897 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2898 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2899
2900 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2901 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2902 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2903
2904 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2905 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2906 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2907
2908 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2909 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2910 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2911
2912 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2913 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2914 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2915
2916 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2917 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2918
2919 /* remove LS/HS from one SIMD for hw workaround */
2920 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2921 r600_store_value(cb, 0xffffffff);
2922 r600_store_value(cb, 0xffffffff);
2923 r600_store_value(cb, 0xfffffffe);
2924
2925 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2926 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2927
2928 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2929 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2930 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2931 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2932 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2933 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2934 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2935
2936 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2937 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2938 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2939 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2940 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2941
2942 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2943 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2944 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2945 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2946 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2947 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2948 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2949 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2950 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2951 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2952 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2953 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2954 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2955 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2956
2957 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2958
2959 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2960
2961 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2962 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2963 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2964
2965 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2966
2967 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2968
2969 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2970 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2971 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2972
2973 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2974 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2975
2976 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2977 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2978 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2979 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2980
2981 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2982 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2983 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2984
2985 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2986 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2987 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2988
2989 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2990 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2991 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2992 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2993 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2994 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2995 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2996
2997 /* to avoid GPU doing any preloading of constant from random address */
2998 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2999 for (i = 0; i < 16; i++)
3000 r600_store_value(cb, 0);
3001
3002 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3003 for (i = 0; i < 16; i++)
3004 r600_store_value(cb, 0);
3005
3006 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3007 for (i = 0; i < 16; i++)
3008 r600_store_value(cb, 0);
3009
3010 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3011 for (i = 0; i < 16; i++)
3012 r600_store_value(cb, 0);
3013
3014 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3015 for (i = 0; i < 16; i++)
3016 r600_store_value(cb, 0);
3017
3018 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3019
3020 if (rctx->screen->b.has_streamout) {
3021 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3022 }
3023
3024 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3025 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3026 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3027 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3028 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3029 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3030
3031 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3032 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3033 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3034
3035 if (rctx->b.family == CHIP_CAICOS) {
3036 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3037 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3038 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3039 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3040 } else {
3041 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3042 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3043 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3044 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3045 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3046 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3047 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3048 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3049 }
3050
3051 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3052 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3053 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3054 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3055 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3056 }
3057
3058 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3059 {
3060 struct r600_context *rctx = (struct r600_context *)ctx;
3061 struct r600_command_buffer *cb = &shader->command_buffer;
3062 struct r600_shader *rshader = &shader->shader;
3063 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3064 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3065 int ninterp = 0;
3066 boolean have_perspective = FALSE, have_linear = FALSE;
3067 static const unsigned spi_baryc_enable_bit[6] = {
3068 S_0286E0_PERSP_SAMPLE_ENA(1),
3069 S_0286E0_PERSP_CENTER_ENA(1),
3070 S_0286E0_PERSP_CENTROID_ENA(1),
3071 S_0286E0_LINEAR_SAMPLE_ENA(1),
3072 S_0286E0_LINEAR_CENTER_ENA(1),
3073 S_0286E0_LINEAR_CENTROID_ENA(1)
3074 };
3075 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3076 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3077 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3078 uint32_t spi_ps_input_cntl[32];
3079
3080 if (!cb->buf) {
3081 r600_init_command_buffer(cb, 64);
3082 } else {
3083 cb->num_dw = 0;
3084 }
3085
3086 for (i = 0; i < rshader->ninput; i++) {
3087 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3088 POSITION goes via GPRs from the SC so isn't counted */
3089 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3090 pos_index = i;
3091 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3092 if (face_index == -1)
3093 face_index = i;
3094 }
3095 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3096 if (face_index == -1)
3097 face_index = i; /* lives in same register, same enable bit */
3098 }
3099 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3100 fixed_pt_position_index = i;
3101 }
3102 else {
3103 ninterp++;
3104 int k = eg_get_interpolator_index(
3105 rshader->input[i].interpolate,
3106 rshader->input[i].interpolate_location);
3107 if (k >= 0) {
3108 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3109 have_perspective |= k < 3;
3110 have_linear |= !(k < 3);
3111 }
3112 }
3113
3114 sid = rshader->input[i].spi_sid;
3115
3116 if (sid) {
3117 tmp = S_028644_SEMANTIC(sid);
3118
3119 /* D3D 9 behaviour. GL is undefined */
3120 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3121 tmp |= S_028644_DEFAULT_VAL(3);
3122
3123 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3124 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3125 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3126 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3127 tmp |= S_028644_FLAT_SHADE(1);
3128 }
3129
3130 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3131 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3132 tmp |= S_028644_PT_SPRITE_TEX(1);
3133 }
3134
3135 spi_ps_input_cntl[num++] = tmp;
3136 }
3137 }
3138
3139 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3140 r600_store_array(cb, num, spi_ps_input_cntl);
3141
3142 for (i = 0; i < rshader->noutput; i++) {
3143 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3144 z_export = 1;
3145 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3146 stencil_export = 1;
3147 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3148 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3149 mask_export = 1;
3150 }
3151 if (rshader->uses_kill)
3152 db_shader_control |= S_02880C_KILL_ENABLE(1);
3153
3154 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3155 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3156 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3157
3158 switch (rshader->ps_conservative_z) {
3159 default: /* fall through */
3160 case TGSI_FS_DEPTH_LAYOUT_ANY:
3161 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3162 break;
3163 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3164 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3165 break;
3166 case TGSI_FS_DEPTH_LAYOUT_LESS:
3167 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3168 break;
3169 }
3170
3171 exports_ps = 0;
3172 for (i = 0; i < rshader->noutput; i++) {
3173 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3174 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3175 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3176 exports_ps |= 1;
3177 }
3178
3179 num_cout = rshader->nr_ps_color_exports;
3180
3181 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3182 if (!exports_ps) {
3183 /* always at least export 1 component per pixel */
3184 exports_ps = 2;
3185 }
3186 shader->nr_ps_color_outputs = num_cout;
3187 if (ninterp == 0) {
3188 ninterp = 1;
3189 have_perspective = TRUE;
3190 }
3191 if (!spi_baryc_cntl)
3192 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3193
3194 if (!have_perspective && !have_linear)
3195 have_perspective = TRUE;
3196
3197 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3198 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3199 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3200 spi_input_z = 0;
3201 if (pos_index != -1) {
3202 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3203 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3204 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3205 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3206 }
3207
3208 spi_ps_in_control_1 = 0;
3209 if (face_index != -1) {
3210 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3211 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3212 }
3213 if (fixed_pt_position_index != -1) {
3214 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3215 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3216 }
3217
3218 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3219 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3220 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3221
3222 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3223 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3224 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3225
3226 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3227 r600_store_value(cb, shader->bo->gpu_address >> 8);
3228 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3229 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3230 S_028844_PRIME_CACHE_ON_DRAW(1) |
3231 S_028844_STACK_SIZE(rshader->bc.nstack));
3232 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3233
3234 shader->db_shader_control = db_shader_control;
3235 shader->ps_depth_export = z_export | stencil_export | mask_export;
3236
3237 shader->sprite_coord_enable = sprite_coord_enable;
3238 if (rctx->rasterizer)
3239 shader->flatshade = rctx->rasterizer->flatshade;
3240 }
3241
3242 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3243 {
3244 struct r600_command_buffer *cb = &shader->command_buffer;
3245 struct r600_shader *rshader = &shader->shader;
3246
3247 r600_init_command_buffer(cb, 32);
3248
3249 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3250 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3251 S_028890_STACK_SIZE(rshader->bc.nstack));
3252 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3253 shader->bo->gpu_address >> 8);
3254 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3255 }
3256
3257 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3258 {
3259 struct r600_context *rctx = (struct r600_context *)ctx;
3260 struct r600_command_buffer *cb = &shader->command_buffer;
3261 struct r600_shader *rshader = &shader->shader;
3262 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3263 unsigned gsvs_itemsizes[4] = {
3264 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3265 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3266 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3267 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3268 };
3269
3270 r600_init_command_buffer(cb, 64);
3271
3272 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3273
3274
3275 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3276 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3277 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3278 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3279
3280 if (rctx->screen->b.info.drm_minor >= 35) {
3281 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3282 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3283 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3284 }
3285 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3286 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3287 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3288 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3289 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3290
3291 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3292 (rshader->ring_item_sizes[0]) >> 2);
3293
3294 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3295 gsvs_itemsizes[0] +
3296 gsvs_itemsizes[1] +
3297 gsvs_itemsizes[2] +
3298 gsvs_itemsizes[3]);
3299
3300 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3301 r600_store_value(cb, gsvs_itemsizes[0]);
3302 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3303 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3304
3305 /* FIXME calculate these values somehow ??? */
3306 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3307 r600_store_value(cb, 0x80); /* GS_PER_ES */
3308 r600_store_value(cb, 0x100); /* ES_PER_GS */
3309 r600_store_value(cb, 0x2); /* GS_PER_VS */
3310
3311 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3312 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3313 S_028878_STACK_SIZE(rshader->bc.nstack));
3314 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3315 shader->bo->gpu_address >> 8);
3316 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3317 }
3318
3319
3320 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3321 {
3322 struct r600_command_buffer *cb = &shader->command_buffer;
3323 struct r600_shader *rshader = &shader->shader;
3324 unsigned spi_vs_out_id[10] = {};
3325 unsigned i, tmp, nparams = 0;
3326
3327 for (i = 0; i < rshader->noutput; i++) {
3328 if (rshader->output[i].spi_sid) {
3329 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3330 spi_vs_out_id[nparams / 4] |= tmp;
3331 nparams++;
3332 }
3333 }
3334
3335 r600_init_command_buffer(cb, 32);
3336
3337 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3338 for (i = 0; i < 10; i++) {
3339 r600_store_value(cb, spi_vs_out_id[i]);
3340 }
3341
3342 /* Certain attributes (position, psize, etc.) don't count as params.
3343 * VS is required to export at least one param and r600_shader_from_tgsi()
3344 * takes care of adding a dummy export.
3345 */
3346 if (nparams < 1)
3347 nparams = 1;
3348
3349 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3350 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3351 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3352 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3353 S_028860_STACK_SIZE(rshader->bc.nstack));
3354 if (rshader->vs_position_window_space) {
3355 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3356 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3357 } else {
3358 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3359 S_028818_VTX_W0_FMT(1) |
3360 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3361 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3362 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3363
3364 }
3365 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3366 shader->bo->gpu_address >> 8);
3367 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3368
3369 shader->pa_cl_vs_out_cntl =
3370 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3371 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3372 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3373 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3374 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3375 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3376 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3377 }
3378
3379 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3380 {
3381 struct r600_command_buffer *cb = &shader->command_buffer;
3382 struct r600_shader *rshader = &shader->shader;
3383
3384 r600_init_command_buffer(cb, 32);
3385 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3386 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3387 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3388 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3389 shader->bo->gpu_address >> 8);
3390 }
3391
3392 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3393 {
3394 struct r600_command_buffer *cb = &shader->command_buffer;
3395 struct r600_shader *rshader = &shader->shader;
3396
3397 r600_init_command_buffer(cb, 32);
3398 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3399 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3400 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3401 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3402 shader->bo->gpu_address >> 8);
3403 }
3404 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3405 {
3406 struct pipe_blend_state blend;
3407
3408 memset(&blend, 0, sizeof(blend));
3409 blend.independent_blend_enable = true;
3410 blend.rt[0].colormask = 0xf;
3411 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3412 }
3413
3414 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3415 {
3416 struct pipe_blend_state blend;
3417 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3418 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3419
3420 memset(&blend, 0, sizeof(blend));
3421 blend.independent_blend_enable = true;
3422 blend.rt[0].colormask = 0xf;
3423 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3424 }
3425
3426 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3427 {
3428 struct pipe_blend_state blend;
3429 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3430
3431 memset(&blend, 0, sizeof(blend));
3432 blend.independent_blend_enable = true;
3433 blend.rt[0].colormask = 0xf;
3434 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3435 }
3436
3437 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3438 {
3439 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3440
3441 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3442 }
3443
3444 void evergreen_update_db_shader_control(struct r600_context * rctx)
3445 {
3446 bool dual_export;
3447 unsigned db_shader_control;
3448
3449 if (!rctx->ps_shader) {
3450 return;
3451 }
3452
3453 dual_export = rctx->framebuffer.export_16bpc &&
3454 !rctx->ps_shader->current->ps_depth_export;
3455
3456 db_shader_control = rctx->ps_shader->current->db_shader_control |
3457 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3458 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3459 V_02880C_EXPORT_DB_FULL) |
3460 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3461
3462 /* When alpha test is enabled we can't trust the hw to make the proper
3463 * decision on the order in which ztest should be run related to fragment
3464 * shader execution.
3465 *
3466 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3467 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3468 * execution and thus after alpha test so if discarded by the alpha test
3469 * the z value is not written.
3470 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3471 * get a hang unless you flush the DB in between. For now just use
3472 * LATE_Z.
3473 */
3474 if (rctx->alphatest_state.sx_alpha_test_control) {
3475 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3476 } else {
3477 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3478 }
3479
3480 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3481 rctx->db_misc_state.db_shader_control = db_shader_control;
3482 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3483 }
3484 }
3485
3486 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3487 struct pipe_resource *dst,
3488 unsigned dst_level,
3489 unsigned dst_x,
3490 unsigned dst_y,
3491 unsigned dst_z,
3492 struct pipe_resource *src,
3493 unsigned src_level,
3494 unsigned src_x,
3495 unsigned src_y,
3496 unsigned src_z,
3497 unsigned copy_height,
3498 unsigned pitch,
3499 unsigned bpp)
3500 {
3501 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3502 struct r600_texture *rsrc = (struct r600_texture*)src;
3503 struct r600_texture *rdst = (struct r600_texture*)dst;
3504 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3505 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3506 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3507 uint64_t base, addr;
3508
3509 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3510 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3511 assert(dst_mode != src_mode);
3512
3513 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3514 if (util_format_has_depth(util_format_description(src->format)))
3515 non_disp_tiling = 1;
3516
3517 y = 0;
3518 sub_cmd = EG_DMA_COPY_TILED;
3519 lbpp = util_logbase2(bpp);
3520 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3521 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3522
3523 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3524 /* T2L */
3525 array_mode = evergreen_array_mode(src_mode);
3526 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3527 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3528 /* linear height must be the same as the slice tile max height, it's ok even
3529 * if the linear destination/source have smaller heigh as the size of the
3530 * dma packet will be using the copy_height which is always smaller or equal
3531 * to the linear height
3532 */
3533 height = u_minify(rsrc->resource.b.b.height0, src_level);
3534 detile = 1;
3535 x = src_x;
3536 y = src_y;
3537 z = src_z;
3538 base = rsrc->surface.u.legacy.level[src_level].offset;
3539 addr = rdst->surface.u.legacy.level[dst_level].offset;
3540 addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
3541 addr += dst_y * pitch + dst_x * bpp;
3542 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3543 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3544 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3545 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3546 base += rsrc->resource.gpu_address;
3547 addr += rdst->resource.gpu_address;
3548 } else {
3549 /* L2T */
3550 array_mode = evergreen_array_mode(dst_mode);
3551 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3552 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3553 /* linear height must be the same as the slice tile max height, it's ok even
3554 * if the linear destination/source have smaller heigh as the size of the
3555 * dma packet will be using the copy_height which is always smaller or equal
3556 * to the linear height
3557 */
3558 height = u_minify(rdst->resource.b.b.height0, dst_level);
3559 detile = 0;
3560 x = dst_x;
3561 y = dst_y;
3562 z = dst_z;
3563 base = rdst->surface.u.legacy.level[dst_level].offset;
3564 addr = rsrc->surface.u.legacy.level[src_level].offset;
3565 addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
3566 addr += src_y * pitch + src_x * bpp;
3567 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3568 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3569 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3570 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3571 base += rdst->resource.gpu_address;
3572 addr += rsrc->resource.gpu_address;
3573 }
3574
3575 size = (copy_height * pitch) / 4;
3576 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3577 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3578
3579 for (i = 0; i < ncopy; i++) {
3580 cheight = copy_height;
3581 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3582 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3583 }
3584 size = (cheight * pitch) / 4;
3585 /* emit reloc before writing cs so that cs is always in consistent state */
3586 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3587 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3588 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3589 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3590 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3591 radeon_emit(cs, base >> 8);
3592 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3593 (lbpp << 24) | (bank_h << 21) |
3594 (bank_w << 18) | (mt_aspect << 16));
3595 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3596 radeon_emit(cs, (slice_tile_max << 0));
3597 radeon_emit(cs, (x << 0) | (z << 18));
3598 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3599 radeon_emit(cs, addr & 0xfffffffc);
3600 radeon_emit(cs, (addr >> 32UL) & 0xff);
3601 copy_height -= cheight;
3602 addr += cheight * pitch;
3603 y += cheight;
3604 }
3605 }
3606
3607 static void evergreen_dma_copy(struct pipe_context *ctx,
3608 struct pipe_resource *dst,
3609 unsigned dst_level,
3610 unsigned dstx, unsigned dsty, unsigned dstz,
3611 struct pipe_resource *src,
3612 unsigned src_level,
3613 const struct pipe_box *src_box)
3614 {
3615 struct r600_context *rctx = (struct r600_context *)ctx;
3616 struct r600_texture *rsrc = (struct r600_texture*)src;
3617 struct r600_texture *rdst = (struct r600_texture*)dst;
3618 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3619 unsigned src_w, dst_w;
3620 unsigned src_x, src_y;
3621 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3622
3623 if (rctx->b.dma.cs == NULL) {
3624 goto fallback;
3625 }
3626
3627 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3628 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3629 return;
3630 }
3631
3632 if (src_box->depth > 1 ||
3633 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3634 dstz, rsrc, src_level, src_box))
3635 goto fallback;
3636
3637 src_x = util_format_get_nblocksx(src->format, src_box->x);
3638 dst_x = util_format_get_nblocksx(src->format, dst_x);
3639 src_y = util_format_get_nblocksy(src->format, src_box->y);
3640 dst_y = util_format_get_nblocksy(src->format, dst_y);
3641
3642 bpp = rdst->surface.bpe;
3643 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3644 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3645 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3646 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3647 copy_height = src_box->height / rsrc->surface.blk_h;
3648
3649 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3650 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3651
3652 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3653 /* FIXME evergreen can do partial blit */
3654 goto fallback;
3655 }
3656 /* the x test here are currently useless (because we don't support partial blit)
3657 * but keep them around so we don't forget about those
3658 */
3659 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3660 goto fallback;
3661 }
3662
3663 /* 128 bpp surfaces require non_disp_tiling for both
3664 * tiled and linear buffers on cayman. However, async
3665 * DMA only supports it on the tiled side. As such
3666 * the tile order is backwards after a L2T/T2L packet.
3667 */
3668 if ((rctx->b.chip_class == CAYMAN) &&
3669 (src_mode != dst_mode) &&
3670 (util_format_get_blocksize(src->format) >= 16)) {
3671 goto fallback;
3672 }
3673
3674 if (src_mode == dst_mode) {
3675 uint64_t dst_offset, src_offset;
3676 /* simple dma blit would do NOTE code here assume :
3677 * src_box.x/y == 0
3678 * dst_x/y == 0
3679 * dst_pitch == src_pitch
3680 */
3681 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3682 src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
3683 src_offset += src_y * src_pitch + src_x * bpp;
3684 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3685 dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
3686 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3687 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3688 src_box->height * src_pitch);
3689 } else {
3690 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3691 src, src_level, src_x, src_y, src_box->z,
3692 copy_height, dst_pitch, bpp);
3693 }
3694 return;
3695
3696 fallback:
3697 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3698 src, src_level, src_box);
3699 }
3700
3701 static void evergreen_set_tess_state(struct pipe_context *ctx,
3702 const float default_outer_level[4],
3703 const float default_inner_level[2])
3704 {
3705 struct r600_context *rctx = (struct r600_context *)ctx;
3706
3707 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3708 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3709 rctx->tess_state_dirty = true;
3710 }
3711
3712 void evergreen_init_state_functions(struct r600_context *rctx)
3713 {
3714 unsigned id = 1;
3715 unsigned i;
3716 /* !!!
3717 * To avoid GPU lockup registers must be emitted in a specific order
3718 * (no kidding ...). The order below is important and have been
3719 * partially inferred from analyzing fglrx command stream.
3720 *
3721 * Don't reorder atom without carefully checking the effect (GPU lockup
3722 * or piglit regression).
3723 * !!!
3724 */
3725 if (rctx->b.chip_class == EVERGREEN) {
3726 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3727 rctx->config_state.dyn_gpr_enabled = true;
3728 }
3729 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3730 /* shader const */
3731 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3732 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3733 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3734 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3735 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3736 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3737 /* shader program */
3738 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3739 /* sampler */
3740 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3741 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3742 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3743 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3744 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3745 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3746 /* resources */
3747 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3748 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3749 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3750 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3751 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3752 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3753 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3754 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3755
3756 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3757
3758 if (rctx->b.chip_class == EVERGREEN) {
3759 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3760 } else {
3761 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3762 }
3763 rctx->sample_mask.sample_mask = ~0;
3764
3765 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3766 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3767 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3768 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3769 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3770 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3771 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3772 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3773 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3774 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
3775 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3776 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3777 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3778 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3779 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3780 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3781 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3782 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3783 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3784 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3785 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3786 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3787
3788 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3789 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3790 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3791 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3792 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3793 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3794 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3795 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3796 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3797 if (rctx->b.chip_class == EVERGREEN)
3798 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3799 else
3800 rctx->b.b.get_sample_position = cayman_get_sample_position;
3801 rctx->b.dma_copy = evergreen_dma_copy;
3802
3803 evergreen_init_compute_state_functions(rctx);
3804 }
3805
3806 /**
3807 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3808 *
3809 * The information about LDS and other non-compile-time parameters is then
3810 * written to the const buffer.
3811
3812 * const buffer contains -
3813 * uint32_t input_patch_size
3814 * uint32_t input_vertex_size
3815 * uint32_t num_tcs_input_cp
3816 * uint32_t num_tcs_output_cp;
3817 * uint32_t output_patch_size
3818 * uint32_t output_vertex_size
3819 * uint32_t output_patch0_offset
3820 * uint32_t perpatch_output_offset
3821 * and the same constbuf is bound to LS/HS/VS(ES).
3822 */
3823 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3824 {
3825 struct pipe_constant_buffer constbuf = {0};
3826 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3827 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3828 unsigned num_tcs_input_cp = info->vertices_per_patch;
3829 unsigned num_tcs_outputs;
3830 unsigned num_tcs_output_cp;
3831 unsigned num_tcs_patch_outputs;
3832 unsigned num_tcs_inputs;
3833 unsigned input_vertex_size, output_vertex_size;
3834 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3835 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3836 uint32_t values[16];
3837 unsigned num_waves;
3838 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3839 unsigned wave_divisor = (16 * num_pipes);
3840
3841 *num_patches = 1;
3842
3843 if (!rctx->tes_shader) {
3844 rctx->lds_alloc = 0;
3845 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3846 R600_LDS_INFO_CONST_BUFFER, NULL);
3847 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3848 R600_LDS_INFO_CONST_BUFFER, NULL);
3849 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3850 R600_LDS_INFO_CONST_BUFFER, NULL);
3851 return;
3852 }
3853
3854 if (rctx->lds_alloc != 0 &&
3855 rctx->last_ls == ls &&
3856 !rctx->tess_state_dirty &&
3857 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3858 rctx->last_tcs == tcs)
3859 return;
3860
3861 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3862
3863 if (rctx->tcs_shader) {
3864 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3865 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3866 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3867 } else {
3868 num_tcs_outputs = num_tcs_inputs;
3869 num_tcs_output_cp = num_tcs_input_cp;
3870 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3871 }
3872
3873 /* size in bytes */
3874 input_vertex_size = num_tcs_inputs * 16;
3875 output_vertex_size = num_tcs_outputs * 16;
3876
3877 input_patch_size = num_tcs_input_cp * input_vertex_size;
3878
3879 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3880 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3881
3882 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3883 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3884
3885 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3886
3887 values[0] = input_patch_size;
3888 values[1] = input_vertex_size;
3889 values[2] = num_tcs_input_cp;
3890 values[3] = num_tcs_output_cp;
3891
3892 values[4] = output_patch_size;
3893 values[5] = output_vertex_size;
3894 values[6] = output_patch0_offset;
3895 values[7] = perpatch_output_offset;
3896
3897 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3898 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3899 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3900
3901 rctx->lds_alloc = (lds_size | (num_waves << 14));
3902
3903 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3904 values[14] = 0;
3905 values[15] = 0;
3906
3907 rctx->tess_state_dirty = false;
3908 rctx->last_ls = ls;
3909 rctx->last_tcs = tcs;
3910 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3911
3912 constbuf.user_buffer = values;
3913 constbuf.buffer_size = 16 * 4;
3914
3915 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3916 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3917 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3918 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3919 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3920 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3921 pipe_resource_reference(&constbuf.buffer, NULL);
3922 }
3923
3924 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3925 const struct pipe_draw_info *info,
3926 unsigned num_patches)
3927 {
3928 unsigned num_output_cp;
3929
3930 if (!rctx->tes_shader)
3931 return 0;
3932
3933 num_output_cp = rctx->tcs_shader ?
3934 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3935 info->vertices_per_patch;
3936
3937 return S_028B58_NUM_PATCHES(num_patches) |
3938 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3939 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3940 }
3941
3942 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3943 struct radeon_winsys_cs *cs,
3944 uint32_t ls_hs_config)
3945 {
3946 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3947 }
3948
3949 void evergreen_set_lds_alloc(struct r600_context *rctx,
3950 struct radeon_winsys_cs *cs,
3951 uint32_t lds_alloc)
3952 {
3953 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3954 }
3955
3956 /* on evergreen if you are running tessellation you need to disable dynamic
3957 GPRs to workaround a hardware bug.*/
3958 bool evergreen_adjust_gprs(struct r600_context *rctx)
3959 {
3960 unsigned num_gprs[EG_NUM_HW_STAGES];
3961 unsigned def_gprs[EG_NUM_HW_STAGES];
3962 unsigned cur_gprs[EG_NUM_HW_STAGES];
3963 unsigned new_gprs[EG_NUM_HW_STAGES];
3964 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3965 unsigned max_gprs;
3966 unsigned i;
3967 unsigned total_gprs;
3968 unsigned tmp[3];
3969 bool rework = false, set_default = false, set_dirty = false;
3970 max_gprs = 0;
3971 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3972 def_gprs[i] = rctx->default_gprs[i];
3973 max_gprs += def_gprs[i];
3974 }
3975 max_gprs += def_num_clause_temp_gprs * 2;
3976
3977 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3978 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3979 if (rctx->config_state.dyn_gpr_enabled)
3980 return true;
3981
3982 /* transition back to dyn gpr enabled state */
3983 rctx->config_state.dyn_gpr_enabled = true;
3984 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3985 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3986 return true;
3987 }
3988
3989
3990 /* gather required shader gprs */
3991 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3992 if (rctx->hw_shader_stages[i].shader)
3993 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3994 else
3995 num_gprs[i] = 0;
3996 }
3997
3998 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3999 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4000 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4001 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4002 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4003 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4004
4005 total_gprs = 0;
4006 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4007 new_gprs[i] = num_gprs[i];
4008 total_gprs += num_gprs[i];
4009 }
4010
4011 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4012 return false;
4013
4014 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4015 if (new_gprs[i] > cur_gprs[i]) {
4016 rework = true;
4017 break;
4018 }
4019 }
4020
4021 if (rctx->config_state.dyn_gpr_enabled) {
4022 set_dirty = true;
4023 rctx->config_state.dyn_gpr_enabled = false;
4024 }
4025
4026 if (rework) {
4027 set_default = true;
4028 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4029 if (new_gprs[i] > def_gprs[i])
4030 set_default = false;
4031 }
4032
4033 if (set_default) {
4034 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4035 new_gprs[i] = def_gprs[i];
4036 }
4037 } else {
4038 unsigned ps_value = max_gprs;
4039
4040 ps_value -= (def_num_clause_temp_gprs * 2);
4041 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4042 ps_value -= new_gprs[i];
4043
4044 new_gprs[R600_HW_STAGE_PS] = ps_value;
4045 }
4046
4047 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4048 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4049 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4050
4051 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4052 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4053
4054 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4055 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4056
4057 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4058 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4059 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4060 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4061 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4062 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4063 set_dirty = true;
4064 }
4065 }
4066
4067
4068 if (set_dirty) {
4069 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4070 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4071 }
4072 return true;
4073 }