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gallium: merge PIPE_SWIZZLE_* and UTIL_FORMAT_SWIZZLE_*
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
215 {
216 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format) != ~0U &&
222 r600_translate_colorswap(format) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 if ((usage & PIPE_BIND_LINEAR) &&
303 !util_format_is_compressed(format) &&
304 !(usage & PIPE_BIND_DEPTH_STENCIL))
305 retval |= PIPE_BIND_LINEAR;
306
307 return retval == usage;
308 }
309
310 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
311 const struct pipe_blend_state *state, int mode)
312 {
313 uint32_t color_control = 0, target_mask = 0;
314 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
315
316 if (!blend) {
317 return NULL;
318 }
319
320 r600_init_command_buffer(&blend->buffer, 20);
321 r600_init_command_buffer(&blend->buffer_no_blend, 20);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 target_mask |= (state->rt[i].colormask << (4 * i));
332 }
333 } else {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[0].colormask << (4 * i));
336 }
337 }
338
339 /* only have dual source on MRT0 */
340 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
341 blend->cb_target_mask = target_mask;
342 blend->alpha_to_one = state->alpha_to_one;
343
344 if (target_mask)
345 color_control |= S_028808_MODE(mode);
346 else
347 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
348
349
350 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
351 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
358
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
362 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
363
364 for (int i = 0; i < 8; i++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j = state->independent_blend_enable ? i : 0;
367
368 unsigned eqRGB = state->rt[j].rgb_func;
369 unsigned srcRGB = state->rt[j].rgb_src_factor;
370 unsigned dstRGB = state->rt[j].rgb_dst_factor;
371 unsigned eqA = state->rt[j].alpha_func;
372 unsigned srcA = state->rt[j].alpha_src_factor;
373 unsigned dstA = state->rt[j].alpha_dst_factor;
374 uint32_t bc = 0;
375
376 r600_store_value(&blend->buffer_no_blend, 0);
377
378 if (!state->rt[j].blend_enable) {
379 r600_store_value(&blend->buffer, 0);
380 continue;
381 }
382
383 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
385 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
386 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
387
388 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
389 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
391 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
392 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
393 }
394 r600_store_value(&blend->buffer, bc);
395 }
396 return blend;
397 }
398
399 static void *evergreen_create_blend_state(struct pipe_context *ctx,
400 const struct pipe_blend_state *state)
401 {
402
403 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
404 }
405
406 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
407 const struct pipe_depth_stencil_alpha_state *state)
408 {
409 unsigned db_depth_control, alpha_test_control, alpha_ref;
410 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
411
412 if (!dsa) {
413 return NULL;
414 }
415
416 r600_init_command_buffer(&dsa->buffer, 3);
417
418 dsa->valuemask[0] = state->stencil[0].valuemask;
419 dsa->valuemask[1] = state->stencil[1].valuemask;
420 dsa->writemask[0] = state->stencil[0].writemask;
421 dsa->writemask[1] = state->stencil[1].writemask;
422 dsa->zwritemask = state->depth.writemask;
423
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436 if (state->stencil[1].enabled) {
437 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
442 }
443 }
444
445 /* alpha */
446 alpha_test_control = 0;
447 alpha_ref = 0;
448 if (state->alpha.enabled) {
449 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
450 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref = fui(state->alpha.ref_value);
452 }
453 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
454 dsa->alpha_ref = alpha_ref;
455
456 /* misc */
457 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
458 return dsa;
459 }
460
461 static void *evergreen_create_rs_state(struct pipe_context *ctx,
462 const struct pipe_rasterizer_state *state)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465 unsigned tmp, spi_interp;
466 float psize_min, psize_max;
467 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
468
469 if (!rs) {
470 return NULL;
471 }
472
473 r600_init_command_buffer(&rs->buffer, 30);
474
475 rs->scissor_enable = state->scissor;
476 rs->flatshade = state->flatshade;
477 rs->sprite_coord_enable = state->sprite_coord_enable;
478 rs->two_side = state->light_twoside;
479 rs->clip_plane_enable = state->clip_plane_enable;
480 rs->pa_sc_line_stipple = state->line_stipple_enable ?
481 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
482 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
483 rs->pa_cl_clip_cntl =
484 S_028810_PS_UCP_MODE(3) |
485 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
486 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
487 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
488 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
489 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
490 rs->multisample_enable = state->multisample;
491
492 /* offset */
493 rs->offset_units = state->offset_units;
494 rs->offset_scale = state->offset_scale * 16.0f;
495 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
496
497 if (state->point_size_per_vertex) {
498 psize_min = util_get_min_point_size(state);
499 psize_max = 8192;
500 } else {
501 /* Force the point size to be as if the vertex output was disabled. */
502 psize_min = state->point_size;
503 psize_max = state->point_size;
504 }
505
506 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
507 if (state->sprite_coord_enable) {
508 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
509 S_0286D4_PNT_SPRITE_OVRD_X(2) |
510 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
511 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
512 S_0286D4_PNT_SPRITE_OVRD_W(1);
513 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
514 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
515 }
516 }
517
518 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
519 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
520 tmp = r600_pack_float_12p4(state->point_size/2);
521 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
522 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
523 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
524 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
525 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
526 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
527 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
528
529 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
530 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
531 S_028A48_MSAA_ENABLE(state->multisample) |
532 S_028A48_VPORT_SCISSOR_ENABLE(1) |
533 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
534
535 if (rctx->b.chip_class == CAYMAN) {
536 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
537 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
538 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
539 } else {
540 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
541 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
542 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
543 }
544
545 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
546 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
547 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
548 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
549 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
550 S_028814_FACE(!state->front_ccw) |
551 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
552 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
553 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
554 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
555 state->fill_back != PIPE_POLYGON_MODE_FILL) |
556 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
557 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
558 return rs;
559 }
560
561 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
562 const struct pipe_sampler_state *state)
563 {
564 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
565 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
566 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
567 : state->max_anisotropy;
568 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
569
570 if (!ss) {
571 return NULL;
572 }
573
574 ss->border_color_use = sampler_state_needs_border_color(state);
575
576 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
577 ss->tex_sampler_words[0] =
578 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
579 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
580 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
581 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
582 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
583 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
584 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
585 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
586 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
587 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
588 ss->tex_sampler_words[1] =
589 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
590 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
591 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
592 ss->tex_sampler_words[2] =
593 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
594 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
595 S_03C008_TYPE(1);
596
597 if (ss->border_color_use) {
598 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
599 }
600 return ss;
601 }
602
603 static struct pipe_sampler_view *
604 texture_buffer_sampler_view(struct r600_context *rctx,
605 struct r600_pipe_sampler_view *view,
606 unsigned width0, unsigned height0)
607
608 {
609 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
610 uint64_t va;
611 int stride = util_format_get_blocksize(view->base.format);
612 unsigned format, num_format, format_comp, endian;
613 unsigned swizzle_res;
614 unsigned char swizzle[4];
615 const struct util_format_description *desc;
616 unsigned offset = view->base.u.buf.first_element * stride;
617 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
618
619 swizzle[0] = view->base.swizzle_r;
620 swizzle[1] = view->base.swizzle_g;
621 swizzle[2] = view->base.swizzle_b;
622 swizzle[3] = view->base.swizzle_a;
623
624 r600_vertex_data_type(view->base.format,
625 &format, &num_format, &format_comp,
626 &endian);
627
628 desc = util_format_description(view->base.format);
629
630 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
631
632 va = tmp->resource.gpu_address + offset;
633 view->tex_resource = &tmp->resource;
634
635 view->skip_mip_address_reloc = true;
636 view->tex_resource_words[0] = va;
637 view->tex_resource_words[1] = size - 1;
638 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
639 S_030008_STRIDE(stride) |
640 S_030008_DATA_FORMAT(format) |
641 S_030008_NUM_FORMAT_ALL(num_format) |
642 S_030008_FORMAT_COMP_ALL(format_comp) |
643 S_030008_ENDIAN_SWAP(endian);
644 view->tex_resource_words[3] = swizzle_res;
645 /*
646 * in theory dword 4 is for number of elements, for use with resinfo,
647 * but it seems to utterly fail to work, the amd gpu shader analyser
648 * uses a const buffer to store the element sizes for buffer txq
649 */
650 view->tex_resource_words[4] = 0;
651 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
652 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
653
654 if (tmp->resource.gpu_address)
655 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
656 return &view->base;
657 }
658
659 struct pipe_sampler_view *
660 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
661 struct pipe_resource *texture,
662 const struct pipe_sampler_view *state,
663 unsigned width0, unsigned height0,
664 unsigned force_level)
665 {
666 struct r600_context *rctx = (struct r600_context*)ctx;
667 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
668 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
669 struct r600_texture *tmp = (struct r600_texture*)texture;
670 unsigned format, endian;
671 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
672 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
673 unsigned height, depth, width;
674 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
675 enum pipe_format pipe_format = state->format;
676 struct radeon_surf_level *surflevel;
677 unsigned base_level, first_level, last_level;
678 unsigned dim, last_layer;
679 uint64_t va;
680
681 if (!view)
682 return NULL;
683
684 /* initialize base object */
685 view->base = *state;
686 view->base.texture = NULL;
687 pipe_reference(NULL, &texture->reference);
688 view->base.texture = texture;
689 view->base.reference.count = 1;
690 view->base.context = ctx;
691
692 if (state->target == PIPE_BUFFER)
693 return texture_buffer_sampler_view(rctx, view, width0, height0);
694
695 swizzle[0] = state->swizzle_r;
696 swizzle[1] = state->swizzle_g;
697 swizzle[2] = state->swizzle_b;
698 swizzle[3] = state->swizzle_a;
699
700 tile_split = tmp->surface.tile_split;
701 surflevel = tmp->surface.level;
702
703 /* Texturing with separate depth and stencil. */
704 if (tmp->is_depth && !tmp->is_flushing_texture) {
705 switch (pipe_format) {
706 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
707 pipe_format = PIPE_FORMAT_Z32_FLOAT;
708 break;
709 case PIPE_FORMAT_X8Z24_UNORM:
710 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
711 /* Z24 is always stored like this. */
712 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
713 break;
714 case PIPE_FORMAT_X24S8_UINT:
715 case PIPE_FORMAT_S8X24_UINT:
716 case PIPE_FORMAT_X32_S8X24_UINT:
717 pipe_format = PIPE_FORMAT_S8_UINT;
718 tile_split = tmp->surface.stencil_tile_split;
719 surflevel = tmp->surface.stencil_level;
720 break;
721 default:;
722 }
723 }
724
725 format = r600_translate_texformat(ctx->screen, pipe_format,
726 swizzle,
727 &word4, &yuv_format);
728 assert(format != ~0);
729 if (format == ~0) {
730 FREE(view);
731 return NULL;
732 }
733
734 endian = r600_colorformat_endian_swap(format);
735
736 base_level = 0;
737 first_level = state->u.tex.first_level;
738 last_level = state->u.tex.last_level;
739 width = width0;
740 height = height0;
741 depth = texture->depth0;
742
743 if (force_level) {
744 base_level = force_level;
745 first_level = 0;
746 last_level = 0;
747 width = u_minify(width, force_level);
748 height = u_minify(height, force_level);
749 depth = u_minify(depth, force_level);
750 }
751
752 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
753 non_disp_tiling = tmp->non_disp_tiling;
754
755 switch (surflevel[base_level].mode) {
756 case RADEON_SURF_MODE_LINEAR_ALIGNED:
757 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
758 break;
759 case RADEON_SURF_MODE_2D:
760 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
761 break;
762 case RADEON_SURF_MODE_1D:
763 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
764 break;
765 case RADEON_SURF_MODE_LINEAR:
766 default:
767 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
768 break;
769 }
770 macro_aspect = tmp->surface.mtilea;
771 bankw = tmp->surface.bankw;
772 bankh = tmp->surface.bankh;
773 tile_split = eg_tile_split(tile_split);
774 macro_aspect = eg_macro_tile_aspect(macro_aspect);
775 bankw = eg_bank_wh(bankw);
776 bankh = eg_bank_wh(bankh);
777 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
778
779 /* 128 bit formats require tile type = 1 */
780 if (rscreen->b.chip_class == CAYMAN) {
781 if (util_format_get_blocksize(pipe_format) >= 16)
782 non_disp_tiling = 1;
783 }
784 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
785
786 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
787 height = 1;
788 depth = texture->array_size;
789 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
790 depth = texture->array_size;
791 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
792 depth = texture->array_size / 6;
793
794 va = tmp->resource.gpu_address;
795
796 if (state->format == PIPE_FORMAT_X24S8_UINT ||
797 state->format == PIPE_FORMAT_S8X24_UINT ||
798 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
799 state->format == PIPE_FORMAT_S8_UINT)
800 view->is_stencil_sampler = true;
801
802 view->tex_resource = &tmp->resource;
803
804 /* array type views and views into array types need to use layer offset */
805 dim = state->target;
806 if (state->target != PIPE_TEXTURE_CUBE)
807 dim = MAX2(state->target, texture->target);
808
809 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
810 S_030000_PITCH((pitch / 8) - 1) |
811 S_030000_TEX_WIDTH(width - 1));
812 if (rscreen->b.chip_class == CAYMAN)
813 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
814 else
815 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
816 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
817 S_030004_TEX_DEPTH(depth - 1) |
818 S_030004_ARRAY_MODE(array_mode));
819 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
820
821 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
822 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
823 if (tmp->is_depth) {
824 /* disable FMASK (0 = disabled) */
825 view->tex_resource_words[3] = 0;
826 view->skip_mip_address_reloc = true;
827 } else {
828 /* FMASK should be in MIP_ADDRESS for multisample textures */
829 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
830 }
831 } else if (last_level && texture->nr_samples <= 1) {
832 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
833 } else {
834 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
835 }
836
837 last_layer = state->u.tex.last_layer;
838 if (state->target != texture->target && depth == 1) {
839 last_layer = state->u.tex.first_layer;
840 }
841 view->tex_resource_words[4] = (word4 |
842 S_030010_ENDIAN_SWAP(endian));
843 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
844 S_030014_LAST_ARRAY(last_layer);
845 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
846
847 if (texture->nr_samples > 1) {
848 unsigned log_samples = util_logbase2(texture->nr_samples);
849 if (rscreen->b.chip_class == CAYMAN) {
850 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
851 }
852 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
853 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
854 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
855 } else {
856 bool no_mip = first_level == last_level;
857
858 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
859 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
860 /* aniso max 16 samples */
861 view->tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
862 }
863
864 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
865 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
866 S_03001C_BANK_WIDTH(bankw) |
867 S_03001C_BANK_HEIGHT(bankh) |
868 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
869 S_03001C_NUM_BANKS(nbanks) |
870 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
871 return &view->base;
872 }
873
874 static struct pipe_sampler_view *
875 evergreen_create_sampler_view(struct pipe_context *ctx,
876 struct pipe_resource *tex,
877 const struct pipe_sampler_view *state)
878 {
879 return evergreen_create_sampler_view_custom(ctx, tex, state,
880 tex->width0, tex->height0, 0);
881 }
882
883 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
884 {
885 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
886 struct r600_config_state *a = (struct r600_config_state*)atom;
887
888 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
889 if (a->dyn_gpr_enabled) {
890 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
891 radeon_emit(cs, 0);
892 radeon_emit(cs, 0);
893 } else {
894 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
895 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
896 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
897 }
898 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
899 if (a->dyn_gpr_enabled) {
900 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
901 S_028838_PS_GPRS(0x1e) |
902 S_028838_VS_GPRS(0x1e) |
903 S_028838_GS_GPRS(0x1e) |
904 S_028838_ES_GPRS(0x1e) |
905 S_028838_HS_GPRS(0x1e) |
906 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
907 }
908 }
909
910 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
911 {
912 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
913 struct pipe_clip_state *state = &rctx->clip_state.state;
914
915 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
916 radeon_emit_array(cs, (unsigned*)state, 6*4);
917 }
918
919 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
920 const struct pipe_poly_stipple *state)
921 {
922 }
923
924 static void evergreen_get_scissor_rect(struct r600_context *rctx,
925 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
926 uint32_t *tl, uint32_t *br)
927 {
928 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
929
930 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
931
932 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
933 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
934 }
935
936 /**
937 * This function intializes the CB* register values for RATs. It is meant
938 * to be used for 1D aligned buffers that do not have an associated
939 * radeon_surf.
940 */
941 void evergreen_init_color_surface_rat(struct r600_context *rctx,
942 struct r600_surface *surf)
943 {
944 struct pipe_resource *pipe_buffer = surf->base.texture;
945 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
946 surf->base.format);
947 unsigned endian = r600_colorformat_endian_swap(format);
948 unsigned swap = r600_translate_colorswap(surf->base.format);
949 unsigned block_size =
950 align(util_format_get_blocksize(pipe_buffer->format), 4);
951 unsigned pitch_alignment =
952 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
953 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
954
955 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
956
957 surf->cb_color_pitch = (pitch / 8) - 1;
958
959 surf->cb_color_slice = 0;
960
961 surf->cb_color_view = 0;
962
963 surf->cb_color_info =
964 S_028C70_ENDIAN(endian)
965 | S_028C70_FORMAT(format)
966 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
967 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
968 | S_028C70_COMP_SWAP(swap)
969 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
970 * are using NUMBER_UINT */
971 | S_028C70_RAT(1)
972 ;
973
974 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
975
976 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
977 * elements. */
978 surf->cb_color_dim = pipe_buffer->width0;
979
980 /* Set the buffer range the GPU will have access to: */
981 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
982 0, pipe_buffer->width0);
983
984 surf->cb_color_fmask = surf->cb_color_base;
985 surf->cb_color_fmask_slice = 0;
986 }
987
988 void evergreen_init_color_surface(struct r600_context *rctx,
989 struct r600_surface *surf)
990 {
991 struct r600_screen *rscreen = rctx->screen;
992 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
993 unsigned level = surf->base.u.tex.level;
994 unsigned pitch, slice;
995 unsigned color_info, color_attrib, color_dim = 0, color_view;
996 unsigned format, swap, ntype, endian;
997 uint64_t offset, base_offset;
998 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
999 const struct util_format_description *desc;
1000 int i;
1001 bool blend_clamp = 0, blend_bypass = 0;
1002
1003 offset = rtex->surface.level[level].offset;
1004 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1005 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1006 offset += rtex->surface.level[level].slice_size *
1007 surf->base.u.tex.first_layer;
1008 color_view = 0;
1009 } else
1010 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1011 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1012
1013 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1014 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1015 if (slice) {
1016 slice = slice - 1;
1017 }
1018 color_info = 0;
1019 switch (rtex->surface.level[level].mode) {
1020 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1021 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1022 non_disp_tiling = 1;
1023 break;
1024 case RADEON_SURF_MODE_1D:
1025 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1026 non_disp_tiling = rtex->non_disp_tiling;
1027 break;
1028 case RADEON_SURF_MODE_2D:
1029 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1030 non_disp_tiling = rtex->non_disp_tiling;
1031 break;
1032 case RADEON_SURF_MODE_LINEAR:
1033 default:
1034 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1035 non_disp_tiling = 1;
1036 break;
1037 }
1038 tile_split = rtex->surface.tile_split;
1039 macro_aspect = rtex->surface.mtilea;
1040 bankw = rtex->surface.bankw;
1041 bankh = rtex->surface.bankh;
1042 if (rtex->fmask.size)
1043 fmask_bankh = rtex->fmask.bank_height;
1044 else
1045 fmask_bankh = rtex->surface.bankh;
1046 tile_split = eg_tile_split(tile_split);
1047 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1048 bankw = eg_bank_wh(bankw);
1049 bankh = eg_bank_wh(bankh);
1050 fmask_bankh = eg_bank_wh(fmask_bankh);
1051
1052 /* 128 bit formats require tile type = 1 */
1053 if (rscreen->b.chip_class == CAYMAN) {
1054 if (util_format_get_blocksize(surf->base.format) >= 16)
1055 non_disp_tiling = 1;
1056 }
1057 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1058 desc = util_format_description(surf->base.format);
1059 for (i = 0; i < 4; i++) {
1060 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1061 break;
1062 }
1063 }
1064
1065 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1066 S_028C74_NUM_BANKS(nbanks) |
1067 S_028C74_BANK_WIDTH(bankw) |
1068 S_028C74_BANK_HEIGHT(bankh) |
1069 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1070 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1071 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1072
1073 if (rctx->b.chip_class == CAYMAN) {
1074 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1075 PIPE_SWIZZLE_1);
1076
1077 if (rtex->resource.b.b.nr_samples > 1) {
1078 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1079 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1080 S_028C74_NUM_FRAGMENTS(log_samples);
1081 }
1082 }
1083
1084 ntype = V_028C70_NUMBER_UNORM;
1085 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1086 ntype = V_028C70_NUMBER_SRGB;
1087 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1088 if (desc->channel[i].normalized)
1089 ntype = V_028C70_NUMBER_SNORM;
1090 else if (desc->channel[i].pure_integer)
1091 ntype = V_028C70_NUMBER_SINT;
1092 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1093 if (desc->channel[i].normalized)
1094 ntype = V_028C70_NUMBER_UNORM;
1095 else if (desc->channel[i].pure_integer)
1096 ntype = V_028C70_NUMBER_UINT;
1097 }
1098
1099 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1100 assert(format != ~0);
1101
1102 swap = r600_translate_colorswap(surf->base.format);
1103 assert(swap != ~0);
1104
1105 endian = r600_colorformat_endian_swap(format);
1106
1107 /* blend clamp should be set for all NORM/SRGB types */
1108 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1109 ntype == V_028C70_NUMBER_SRGB)
1110 blend_clamp = 1;
1111
1112 /* set blend bypass according to docs if SINT/UINT or
1113 8/24 COLOR variants */
1114 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1115 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1116 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1117 blend_clamp = 0;
1118 blend_bypass = 1;
1119 }
1120
1121 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1122
1123 color_info |= S_028C70_FORMAT(format) |
1124 S_028C70_COMP_SWAP(swap) |
1125 S_028C70_BLEND_CLAMP(blend_clamp) |
1126 S_028C70_BLEND_BYPASS(blend_bypass) |
1127 S_028C70_NUMBER_TYPE(ntype) |
1128 S_028C70_ENDIAN(endian);
1129
1130 /* EXPORT_NORM is an optimzation that can be enabled for better
1131 * performance in certain cases.
1132 * EXPORT_NORM can be enabled if:
1133 * - 11-bit or smaller UNORM/SNORM/SRGB
1134 * - 16-bit or smaller FLOAT
1135 */
1136 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1137 ((desc->channel[i].size < 12 &&
1138 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1139 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1140 (desc->channel[i].size < 17 &&
1141 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1142 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1143 surf->export_16bpc = true;
1144 }
1145
1146 if (rtex->fmask.size) {
1147 color_info |= S_028C70_COMPRESSION(1);
1148 }
1149
1150 base_offset = rtex->resource.gpu_address;
1151
1152 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1153 surf->cb_color_base = (base_offset + offset) >> 8;
1154 surf->cb_color_dim = color_dim;
1155 surf->cb_color_info = color_info;
1156 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1157 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1158 surf->cb_color_view = color_view;
1159 surf->cb_color_attrib = color_attrib;
1160 if (rtex->fmask.size) {
1161 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1162 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1163 } else {
1164 surf->cb_color_fmask = surf->cb_color_base;
1165 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1166 }
1167
1168 surf->color_initialized = true;
1169 }
1170
1171 static void evergreen_init_depth_surface(struct r600_context *rctx,
1172 struct r600_surface *surf)
1173 {
1174 struct r600_screen *rscreen = rctx->screen;
1175 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1176 unsigned level = surf->base.u.tex.level;
1177 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1178 uint64_t offset;
1179 unsigned format, array_mode;
1180 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1181
1182
1183 format = r600_translate_dbformat(surf->base.format);
1184 assert(format != ~0);
1185
1186 offset = rtex->resource.gpu_address;
1187 offset += rtex->surface.level[level].offset;
1188
1189 switch (rtex->surface.level[level].mode) {
1190 case RADEON_SURF_MODE_2D:
1191 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1192 break;
1193 case RADEON_SURF_MODE_1D:
1194 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1195 case RADEON_SURF_MODE_LINEAR:
1196 default:
1197 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1198 break;
1199 }
1200 tile_split = rtex->surface.tile_split;
1201 macro_aspect = rtex->surface.mtilea;
1202 bankw = rtex->surface.bankw;
1203 bankh = rtex->surface.bankh;
1204 tile_split = eg_tile_split(tile_split);
1205 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1206 bankw = eg_bank_wh(bankw);
1207 bankh = eg_bank_wh(bankh);
1208 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1209 offset >>= 8;
1210
1211 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1212 S_028040_FORMAT(format) |
1213 S_028040_TILE_SPLIT(tile_split)|
1214 S_028040_NUM_BANKS(nbanks) |
1215 S_028040_BANK_WIDTH(bankw) |
1216 S_028040_BANK_HEIGHT(bankh) |
1217 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1218 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1219 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1220 }
1221
1222 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1223
1224 surf->db_depth_base = offset;
1225 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1226 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1227 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1228 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1229 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1230 levelinfo->nblk_y / 64 - 1);
1231
1232 switch (surf->base.format) {
1233 case PIPE_FORMAT_Z24X8_UNORM:
1234 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1235 case PIPE_FORMAT_X8Z24_UNORM:
1236 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1237 surf->pa_su_poly_offset_db_fmt_cntl =
1238 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1239 break;
1240 case PIPE_FORMAT_Z32_FLOAT:
1241 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1242 surf->pa_su_poly_offset_db_fmt_cntl =
1243 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1244 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1245 break;
1246 case PIPE_FORMAT_Z16_UNORM:
1247 surf->pa_su_poly_offset_db_fmt_cntl =
1248 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1249 break;
1250 default:;
1251 }
1252
1253 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1254 uint64_t stencil_offset;
1255 unsigned stile_split = rtex->surface.stencil_tile_split;
1256
1257 stile_split = eg_tile_split(stile_split);
1258
1259 stencil_offset = rtex->surface.stencil_level[level].offset;
1260 stencil_offset += rtex->resource.gpu_address;
1261
1262 surf->db_stencil_base = stencil_offset >> 8;
1263 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1264 S_028044_TILE_SPLIT(stile_split);
1265 } else {
1266 surf->db_stencil_base = offset;
1267 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1268 * Older kernels are out of luck. */
1269 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1270 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1271 S_028044_FORMAT(V_028044_STENCIL_8);
1272 }
1273
1274 /* use htile only for first level */
1275 if (rtex->htile_buffer && !level) {
1276 uint64_t va = rtex->htile_buffer->gpu_address;
1277 surf->db_htile_data_base = va >> 8;
1278 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1279 S_028ABC_HTILE_HEIGHT(1) |
1280 S_028ABC_FULL_CACHE(1);
1281 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1282 surf->db_preload_control = 0;
1283 }
1284
1285 surf->depth_initialized = true;
1286 }
1287
1288 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1289 const struct pipe_framebuffer_state *state)
1290 {
1291 struct r600_context *rctx = (struct r600_context *)ctx;
1292 struct r600_surface *surf;
1293 struct r600_texture *rtex;
1294 uint32_t i, log_samples;
1295
1296 if (rctx->framebuffer.state.nr_cbufs) {
1297 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1298 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1299 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1300 }
1301 if (rctx->framebuffer.state.zsbuf) {
1302 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1303 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1304
1305 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1306 if (rtex->htile_buffer) {
1307 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1308 }
1309 }
1310
1311 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1312
1313 /* Colorbuffers. */
1314 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1315 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1316 util_format_is_pure_integer(state->cbufs[0]->format);
1317 rctx->framebuffer.compressed_cb_mask = 0;
1318 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1319
1320 for (i = 0; i < state->nr_cbufs; i++) {
1321 surf = (struct r600_surface*)state->cbufs[i];
1322 if (!surf)
1323 continue;
1324
1325 rtex = (struct r600_texture*)surf->base.texture;
1326
1327 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1328
1329 if (!surf->color_initialized) {
1330 evergreen_init_color_surface(rctx, surf);
1331 }
1332
1333 if (!surf->export_16bpc) {
1334 rctx->framebuffer.export_16bpc = false;
1335 }
1336
1337 if (rtex->fmask.size && rtex->cmask.size) {
1338 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1339 }
1340 }
1341
1342 /* Update alpha-test state dependencies.
1343 * Alpha-test is done on the first colorbuffer only. */
1344 if (state->nr_cbufs) {
1345 bool alphatest_bypass = false;
1346 bool export_16bpc = true;
1347
1348 surf = (struct r600_surface*)state->cbufs[0];
1349 if (surf) {
1350 alphatest_bypass = surf->alphatest_bypass;
1351 export_16bpc = surf->export_16bpc;
1352 }
1353
1354 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1355 rctx->alphatest_state.bypass = alphatest_bypass;
1356 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1357 }
1358 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1359 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1360 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1361 }
1362 }
1363
1364 /* ZS buffer. */
1365 if (state->zsbuf) {
1366 surf = (struct r600_surface*)state->zsbuf;
1367
1368 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1369
1370 if (!surf->depth_initialized) {
1371 evergreen_init_depth_surface(rctx, surf);
1372 }
1373
1374 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1375 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1376 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1377 }
1378
1379 if (rctx->db_state.rsurf != surf) {
1380 rctx->db_state.rsurf = surf;
1381 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1382 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1383 }
1384 } else if (rctx->db_state.rsurf) {
1385 rctx->db_state.rsurf = NULL;
1386 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1387 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1388 }
1389
1390 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1391 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1392 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1393 }
1394
1395 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1396 rctx->alphatest_state.bypass = false;
1397 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1398 }
1399
1400 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1401 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1402 if ((rctx->b.chip_class == CAYMAN ||
1403 rctx->b.family == CHIP_RV770) &&
1404 rctx->db_misc_state.log_samples != log_samples) {
1405 rctx->db_misc_state.log_samples = log_samples;
1406 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1407 }
1408
1409
1410 /* Calculate the CS size. */
1411 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1412
1413 /* MSAA. */
1414 if (rctx->b.chip_class == EVERGREEN)
1415 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1416 else
1417 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1418
1419 /* Colorbuffers. */
1420 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1421 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1422 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1423
1424 /* ZS buffer. */
1425 if (state->zsbuf) {
1426 rctx->framebuffer.atom.num_dw += 24;
1427 rctx->framebuffer.atom.num_dw += 2;
1428 } else if (rctx->screen->b.info.drm_minor >= 18) {
1429 rctx->framebuffer.atom.num_dw += 4;
1430 }
1431
1432 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1433
1434 r600_set_sample_locations_constant_buffer(rctx);
1435 }
1436
1437 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1438 {
1439 struct r600_context *rctx = (struct r600_context *)ctx;
1440
1441 if (rctx->ps_iter_samples == min_samples)
1442 return;
1443
1444 rctx->ps_iter_samples = min_samples;
1445 if (rctx->framebuffer.nr_samples > 1) {
1446 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1447 }
1448 }
1449
1450 /* 8xMSAA */
1451 static uint32_t sample_locs_8x[] = {
1452 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1453 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1454 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1455 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1456 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1457 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1458 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1459 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1460 };
1461 static unsigned max_dist_8x = 7;
1462
1463 static void evergreen_get_sample_position(struct pipe_context *ctx,
1464 unsigned sample_count,
1465 unsigned sample_index,
1466 float *out_value)
1467 {
1468 int offset, index;
1469 struct {
1470 int idx:4;
1471 } val;
1472 switch (sample_count) {
1473 case 1:
1474 default:
1475 out_value[0] = out_value[1] = 0.5;
1476 break;
1477 case 2:
1478 offset = 4 * (sample_index * 2);
1479 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1480 out_value[0] = (float)(val.idx + 8) / 16.0f;
1481 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1482 out_value[1] = (float)(val.idx + 8) / 16.0f;
1483 break;
1484 case 4:
1485 offset = 4 * (sample_index * 2);
1486 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1487 out_value[0] = (float)(val.idx + 8) / 16.0f;
1488 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1489 out_value[1] = (float)(val.idx + 8) / 16.0f;
1490 break;
1491 case 8:
1492 offset = 4 * (sample_index % 4 * 2);
1493 index = (sample_index / 4);
1494 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1495 out_value[0] = (float)(val.idx + 8) / 16.0f;
1496 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1497 out_value[1] = (float)(val.idx + 8) / 16.0f;
1498 break;
1499 }
1500 }
1501
1502 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1503 {
1504
1505 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1506 unsigned max_dist = 0;
1507
1508 switch (nr_samples) {
1509 default:
1510 nr_samples = 0;
1511 break;
1512 case 2:
1513 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1514 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1515 max_dist = eg_max_dist_2x;
1516 break;
1517 case 4:
1518 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1519 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1520 max_dist = eg_max_dist_4x;
1521 break;
1522 case 8:
1523 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1524 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1525 max_dist = max_dist_8x;
1526 break;
1527 }
1528
1529 if (nr_samples > 1) {
1530 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1531 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1532 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1533 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1534 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1535 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1536 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1537 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1538 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1539 } else {
1540 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1541 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1542 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1543 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1544 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1545 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1546 }
1547 }
1548
1549 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1550 {
1551 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1552 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1553 unsigned nr_cbufs = state->nr_cbufs;
1554 unsigned i, tl, br;
1555 struct r600_texture *tex = NULL;
1556 struct r600_surface *cb = NULL;
1557
1558 /* XXX support more colorbuffers once we need them */
1559 assert(nr_cbufs <= 8);
1560 if (nr_cbufs > 8)
1561 nr_cbufs = 8;
1562
1563 /* Colorbuffers. */
1564 for (i = 0; i < nr_cbufs; i++) {
1565 unsigned reloc, cmask_reloc;
1566
1567 cb = (struct r600_surface*)state->cbufs[i];
1568 if (!cb) {
1569 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1570 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1571 continue;
1572 }
1573
1574 tex = (struct r600_texture *)cb->base.texture;
1575 reloc = radeon_add_to_buffer_list(&rctx->b,
1576 &rctx->b.gfx,
1577 (struct r600_resource*)cb->base.texture,
1578 RADEON_USAGE_READWRITE,
1579 tex->surface.nsamples > 1 ?
1580 RADEON_PRIO_COLOR_BUFFER_MSAA :
1581 RADEON_PRIO_COLOR_BUFFER);
1582
1583 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1584 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1585 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1586 RADEON_PRIO_CMASK);
1587 } else {
1588 cmask_reloc = reloc;
1589 }
1590
1591 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1592 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1593 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1594 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1595 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1596 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1597 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1598 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1599 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1600 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1601 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1602 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1603 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1604 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1605
1606 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1607 radeon_emit(cs, reloc);
1608
1609 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1610 radeon_emit(cs, reloc);
1611
1612 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1613 radeon_emit(cs, cmask_reloc);
1614
1615 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1616 radeon_emit(cs, reloc);
1617 }
1618 /* set CB_COLOR1_INFO for possible dual-src blending */
1619 if (i == 1 && state->cbufs[0]) {
1620 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1621 cb->cb_color_info | tex->cb_color_info);
1622 i++;
1623 }
1624 for (; i < 8 ; i++)
1625 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1626 for (; i < 12; i++)
1627 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1628
1629 /* ZS buffer. */
1630 if (state->zsbuf) {
1631 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1632 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1633 &rctx->b.gfx,
1634 (struct r600_resource*)state->zsbuf->texture,
1635 RADEON_USAGE_READWRITE,
1636 zb->base.texture->nr_samples > 1 ?
1637 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1638 RADEON_PRIO_DEPTH_BUFFER);
1639
1640 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1641 zb->pa_su_poly_offset_db_fmt_cntl);
1642 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1643
1644 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1645 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1646 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1647 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1648 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1649 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1650 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1651 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1652 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1653
1654 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1655 radeon_emit(cs, reloc);
1656
1657 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1658 radeon_emit(cs, reloc);
1659
1660 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1661 radeon_emit(cs, reloc);
1662
1663 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1664 radeon_emit(cs, reloc);
1665 } else if (rctx->screen->b.info.drm_minor >= 18) {
1666 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1667 * Older kernels are out of luck. */
1668 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1669 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1670 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1671 }
1672
1673 /* Framebuffer dimensions. */
1674 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1675
1676 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1677 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1678 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1679
1680 if (rctx->b.chip_class == EVERGREEN) {
1681 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1682 } else {
1683 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1684 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
1685 }
1686 }
1687
1688 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1689 {
1690 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1691 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1692 float offset_units = state->offset_units;
1693 float offset_scale = state->offset_scale;
1694
1695 switch (state->zs_format) {
1696 case PIPE_FORMAT_Z24X8_UNORM:
1697 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1698 case PIPE_FORMAT_X8Z24_UNORM:
1699 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1700 offset_units *= 2.0f;
1701 break;
1702 case PIPE_FORMAT_Z16_UNORM:
1703 offset_units *= 4.0f;
1704 break;
1705 default:;
1706 }
1707
1708 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1709 radeon_emit(cs, fui(offset_scale));
1710 radeon_emit(cs, fui(offset_units));
1711 radeon_emit(cs, fui(offset_scale));
1712 radeon_emit(cs, fui(offset_units));
1713 }
1714
1715 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1716 {
1717 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1718 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1719 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1720 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1721
1722 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1723 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1724 /* This must match the used export instructions exactly.
1725 * Other values may lead to undefined behavior and hangs.
1726 */
1727 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1728 }
1729
1730 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1731 {
1732 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1733 struct r600_db_state *a = (struct r600_db_state*)atom;
1734
1735 if (a->rsurf && a->rsurf->db_htile_surface) {
1736 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1737 unsigned reloc_idx;
1738
1739 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1740 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1741 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1742 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1743 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1744 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1745 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1746 cs->buf[cs->cdw++] = reloc_idx;
1747 } else {
1748 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1749 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1750 }
1751 }
1752
1753 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1754 {
1755 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1756 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1757 unsigned db_render_control = 0;
1758 unsigned db_count_control = 0;
1759 unsigned db_render_override =
1760 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1761 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1762
1763 if (rctx->b.num_occlusion_queries > 0 &&
1764 !a->occlusion_queries_disabled) {
1765 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1766 if (rctx->b.chip_class == CAYMAN) {
1767 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1768 }
1769 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1770 } else {
1771 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1772 }
1773
1774 /* This is to fix a lockup when hyperz and alpha test are enabled at
1775 * the same time somehow GPU get confuse on which order to pick for
1776 * z test
1777 */
1778 if (rctx->alphatest_state.sx_alpha_test_control)
1779 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1780
1781 if (a->flush_depthstencil_through_cb) {
1782 assert(a->copy_depth || a->copy_stencil);
1783
1784 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1785 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1786 S_028000_COPY_CENTROID(1) |
1787 S_028000_COPY_SAMPLE(a->copy_sample);
1788 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1789 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1790 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1791 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1792 }
1793 if (a->htile_clear) {
1794 /* FIXME we might want to disable cliprect here */
1795 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1796 }
1797
1798 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1799 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1800 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1801 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1802 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1803 }
1804
1805 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1806 struct r600_vertexbuf_state *state,
1807 unsigned resource_offset,
1808 unsigned pkt_flags)
1809 {
1810 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1811 uint32_t dirty_mask = state->dirty_mask;
1812
1813 while (dirty_mask) {
1814 struct pipe_vertex_buffer *vb;
1815 struct r600_resource *rbuffer;
1816 uint64_t va;
1817 unsigned buffer_index = u_bit_scan(&dirty_mask);
1818
1819 vb = &state->vb[buffer_index];
1820 rbuffer = (struct r600_resource*)vb->buffer;
1821 assert(rbuffer);
1822
1823 va = rbuffer->gpu_address + vb->buffer_offset;
1824
1825 /* fetch resources start at index 992 */
1826 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1827 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1828 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1829 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1830 radeon_emit(cs, /* RESOURCEi_WORD2 */
1831 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1832 S_030008_STRIDE(vb->stride) |
1833 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1834 radeon_emit(cs, /* RESOURCEi_WORD3 */
1835 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1836 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1837 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1838 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1839 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1840 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1841 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1842 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1843
1844 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1845 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1846 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1847 }
1848 state->dirty_mask = 0;
1849 }
1850
1851 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1852 {
1853 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1854 }
1855
1856 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1857 {
1858 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1859 RADEON_CP_PACKET3_COMPUTE_MODE);
1860 }
1861
1862 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1863 struct r600_constbuf_state *state,
1864 unsigned buffer_id_base,
1865 unsigned reg_alu_constbuf_size,
1866 unsigned reg_alu_const_cache,
1867 unsigned pkt_flags)
1868 {
1869 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1870 uint32_t dirty_mask = state->dirty_mask;
1871
1872 while (dirty_mask) {
1873 struct pipe_constant_buffer *cb;
1874 struct r600_resource *rbuffer;
1875 uint64_t va;
1876 unsigned buffer_index = ffs(dirty_mask) - 1;
1877 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1878
1879 cb = &state->cb[buffer_index];
1880 rbuffer = (struct r600_resource*)cb->buffer;
1881 assert(rbuffer);
1882
1883 va = rbuffer->gpu_address + cb->buffer_offset;
1884
1885 if (!gs_ring_buffer) {
1886 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1887 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1888 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1889 pkt_flags);
1890 }
1891
1892 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1893 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1894 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1895
1896 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1897 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1898 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1899 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1900 radeon_emit(cs, /* RESOURCEi_WORD2 */
1901 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1902 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1903 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1904 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1905 radeon_emit(cs, /* RESOURCEi_WORD3 */
1906 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1907 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1908 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1909 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1910 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1911 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1912 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1913 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1914 radeon_emit(cs, /* RESOURCEi_WORD7 */
1915 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1916
1917 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1918 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1919 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1920
1921 dirty_mask &= ~(1 << buffer_index);
1922 }
1923 state->dirty_mask = 0;
1924 }
1925
1926 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1927 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1928 {
1929 if (rctx->vs_shader->current->shader.vs_as_ls) {
1930 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1931 EG_FETCH_CONSTANTS_OFFSET_LS,
1932 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1933 R_028F40_ALU_CONST_CACHE_LS_0,
1934 0 /* PKT3 flags */);
1935 } else {
1936 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1937 EG_FETCH_CONSTANTS_OFFSET_VS,
1938 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1939 R_028980_ALU_CONST_CACHE_VS_0,
1940 0 /* PKT3 flags */);
1941 }
1942 }
1943
1944 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1945 {
1946 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1947 EG_FETCH_CONSTANTS_OFFSET_GS,
1948 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1949 R_0289C0_ALU_CONST_CACHE_GS_0,
1950 0 /* PKT3 flags */);
1951 }
1952
1953 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1954 {
1955 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1956 EG_FETCH_CONSTANTS_OFFSET_PS,
1957 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1958 R_028940_ALU_CONST_CACHE_PS_0,
1959 0 /* PKT3 flags */);
1960 }
1961
1962 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1963 {
1964 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
1965 EG_FETCH_CONSTANTS_OFFSET_CS,
1966 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1967 R_028F40_ALU_CONST_CACHE_LS_0,
1968 RADEON_CP_PACKET3_COMPUTE_MODE);
1969 }
1970
1971 /* tes constants can be emitted to VS or ES - which are common */
1972 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1973 {
1974 if (!rctx->tes_shader)
1975 return;
1976 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
1977 EG_FETCH_CONSTANTS_OFFSET_VS,
1978 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1979 R_028980_ALU_CONST_CACHE_VS_0,
1980 0);
1981 }
1982
1983 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1984 {
1985 if (!rctx->tes_shader)
1986 return;
1987 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
1988 EG_FETCH_CONSTANTS_OFFSET_HS,
1989 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
1990 R_028F00_ALU_CONST_CACHE_HS_0,
1991 0);
1992 }
1993
1994 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1995 struct r600_samplerview_state *state,
1996 unsigned resource_id_base, unsigned pkt_flags)
1997 {
1998 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1999 uint32_t dirty_mask = state->dirty_mask;
2000
2001 while (dirty_mask) {
2002 struct r600_pipe_sampler_view *rview;
2003 unsigned resource_index = u_bit_scan(&dirty_mask);
2004 unsigned reloc;
2005
2006 rview = state->views[resource_index];
2007 assert(rview);
2008
2009 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2010 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2011 radeon_emit_array(cs, rview->tex_resource_words, 8);
2012
2013 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2014 RADEON_USAGE_READ,
2015 r600_get_sampler_view_priority(rview->tex_resource));
2016 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2017 radeon_emit(cs, reloc);
2018
2019 if (!rview->skip_mip_address_reloc) {
2020 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2021 radeon_emit(cs, reloc);
2022 }
2023 }
2024 state->dirty_mask = 0;
2025 }
2026
2027 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2028 {
2029 if (rctx->vs_shader->current->shader.vs_as_ls) {
2030 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2031 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2032 } else {
2033 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2034 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2035 }
2036 }
2037
2038 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2039 {
2040 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2041 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2042 }
2043
2044 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2045 {
2046 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2047 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2048 }
2049
2050 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2051 {
2052 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2053 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2054 }
2055
2056 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2057 {
2058 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2059 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2060 }
2061
2062 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2063 {
2064 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2065 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2066 }
2067
2068 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2069 struct r600_textures_info *texinfo,
2070 unsigned resource_id_base,
2071 unsigned border_index_reg,
2072 unsigned pkt_flags)
2073 {
2074 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2075 uint32_t dirty_mask = texinfo->states.dirty_mask;
2076
2077 while (dirty_mask) {
2078 struct r600_pipe_sampler_state *rstate;
2079 unsigned i = u_bit_scan(&dirty_mask);
2080
2081 rstate = texinfo->states.states[i];
2082 assert(rstate);
2083
2084 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2085 radeon_emit(cs, (resource_id_base + i) * 3);
2086 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2087
2088 if (rstate->border_color_use) {
2089 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2090 radeon_emit(cs, i);
2091 radeon_emit_array(cs, rstate->border_color.ui, 4);
2092 }
2093 }
2094 texinfo->states.dirty_mask = 0;
2095 }
2096
2097 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2098 {
2099 if (rctx->vs_shader->current->shader.vs_as_ls) {
2100 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2101 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2102 } else {
2103 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2104 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2105 }
2106 }
2107
2108 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2109 {
2110 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2111 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2112 }
2113
2114 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2115 {
2116 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2117 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2118 }
2119
2120 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2121 {
2122 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2123 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2124 }
2125
2126 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2127 {
2128 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2129 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2130 }
2131
2132 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2133 {
2134 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2135 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2136 RADEON_CP_PACKET3_COMPUTE_MODE);
2137 }
2138
2139 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2140 {
2141 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2142 uint8_t mask = s->sample_mask;
2143
2144 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2145 mask | (mask << 8) | (mask << 16) | (mask << 24));
2146 }
2147
2148 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2149 {
2150 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2151 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2152 uint16_t mask = s->sample_mask;
2153
2154 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2155 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2156 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2157 }
2158
2159 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2160 {
2161 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2162 struct r600_cso_state *state = (struct r600_cso_state*)a;
2163 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2164
2165 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2166 (shader->buffer->gpu_address + shader->offset) >> 8);
2167 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2168 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2169 RADEON_USAGE_READ,
2170 RADEON_PRIO_INTERNAL_SHADER));
2171 }
2172
2173 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2174 {
2175 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2176 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2177
2178 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2179
2180 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2181 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2182 primid = 1;
2183 }
2184
2185 if (state->geom_enable) {
2186 uint32_t cut_val;
2187
2188 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2189 cut_val = V_028A40_GS_CUT_128;
2190 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2191 cut_val = V_028A40_GS_CUT_256;
2192 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2193 cut_val = V_028A40_GS_CUT_512;
2194 else
2195 cut_val = V_028A40_GS_CUT_1024;
2196
2197 v = S_028B54_GS_EN(1) |
2198 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2199 if (!rctx->tes_shader)
2200 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2201
2202 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2203 S_028A40_CUT_MODE(cut_val);
2204
2205 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2206 primid = 1;
2207 }
2208
2209 if (rctx->tes_shader) {
2210 uint32_t type, partitioning, topology;
2211 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2212 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2213 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2214 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2215 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2216 switch (tes_prim_mode) {
2217 case PIPE_PRIM_LINES:
2218 type = V_028B6C_TESS_ISOLINE;
2219 break;
2220 case PIPE_PRIM_TRIANGLES:
2221 type = V_028B6C_TESS_TRIANGLE;
2222 break;
2223 case PIPE_PRIM_QUADS:
2224 type = V_028B6C_TESS_QUAD;
2225 break;
2226 default:
2227 assert(0);
2228 return;
2229 }
2230
2231 switch (tes_spacing) {
2232 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2233 partitioning = V_028B6C_PART_FRAC_ODD;
2234 break;
2235 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2236 partitioning = V_028B6C_PART_FRAC_EVEN;
2237 break;
2238 case PIPE_TESS_SPACING_EQUAL:
2239 partitioning = V_028B6C_PART_INTEGER;
2240 break;
2241 default:
2242 assert(0);
2243 return;
2244 }
2245
2246 if (tes_point_mode)
2247 topology = V_028B6C_OUTPUT_POINT;
2248 else if (tes_prim_mode == PIPE_PRIM_LINES)
2249 topology = V_028B6C_OUTPUT_LINE;
2250 else if (tes_vertex_order_cw)
2251 /* XXX follow radeonsi and invert */
2252 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2253 else
2254 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2255
2256 tf_param = S_028B6C_TYPE(type) |
2257 S_028B6C_PARTITIONING(partitioning) |
2258 S_028B6C_TOPOLOGY(topology);
2259 }
2260
2261 if (rctx->tes_shader) {
2262 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2263 S_028B54_HS_EN(1);
2264 if (!state->geom_enable)
2265 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2266 else
2267 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2268 }
2269
2270 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2271 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2272 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2273 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2274 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2275 }
2276
2277 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2278 {
2279 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2280 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2281 struct r600_resource *rbuffer;
2282
2283 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2284 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2285 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2286
2287 if (state->enable) {
2288 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2289 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2290 rbuffer->gpu_address >> 8);
2291 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2292 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2293 RADEON_USAGE_READWRITE,
2294 RADEON_PRIO_RINGS_STREAMOUT));
2295 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2296 state->esgs_ring.buffer_size >> 8);
2297
2298 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2299 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2300 rbuffer->gpu_address >> 8);
2301 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2302 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2303 RADEON_USAGE_READWRITE,
2304 RADEON_PRIO_RINGS_STREAMOUT));
2305 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2306 state->gsvs_ring.buffer_size >> 8);
2307 } else {
2308 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2309 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2310 }
2311
2312 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2313 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2314 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2315 }
2316
2317 void cayman_init_common_regs(struct r600_command_buffer *cb,
2318 enum chip_class ctx_chip_class,
2319 enum radeon_family ctx_family,
2320 int ctx_drm_minor)
2321 {
2322 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2323 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2324 /* always set the temp clauses */
2325 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2326
2327 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2328 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2329 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2330
2331 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2332
2333 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2334 r600_store_value(cb, 0);
2335 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2336
2337 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2338 }
2339
2340 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2341 {
2342 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2343 int tmp, i;
2344
2345 r600_init_command_buffer(cb, 338);
2346
2347 /* This must be first. */
2348 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2349 r600_store_value(cb, 0x80000000);
2350 r600_store_value(cb, 0x80000000);
2351
2352 /* We're setting config registers here. */
2353 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2354 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2355
2356 /* This enables pipeline stat & streamout queries.
2357 * They are only disabled by blits.
2358 */
2359 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2360 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2361
2362 cayman_init_common_regs(cb, rctx->b.chip_class,
2363 rctx->b.family, rctx->screen->b.info.drm_minor);
2364
2365 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2366 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2367
2368 /* remove LS/HS from one SIMD for hw workaround */
2369 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2370 r600_store_value(cb, 0xffffffff);
2371 r600_store_value(cb, 0xffffffff);
2372 r600_store_value(cb, 0xfffffffe);
2373
2374 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2375 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2376 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2377 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2378 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2379 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2380 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2381
2382 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2383 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2384 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2385 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2386 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2387
2388 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2389 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2390 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2391 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2392 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2393 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2394 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2395 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2396 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2397 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2398 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2399 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2400 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2401 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2402
2403 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2404
2405 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2406
2407 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2408 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2409 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2410
2411 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2412 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2413 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2414
2415 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2416
2417 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2418 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2419 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2420
2421 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2422
2423 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2424
2425 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2426
2427 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2428 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2429 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2430 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2431
2432 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2433 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2434
2435 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2436 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2437 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2438 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2439 }
2440
2441 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2442 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2443
2444 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2445 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2446 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2447
2448 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2449 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2450 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2451
2452 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2453 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2454 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2455 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2456 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2457 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2458
2459 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2460
2461 /* to avoid GPU doing any preloading of constant from random address */
2462 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2463 for (i = 0; i < 16; i++)
2464 r600_store_value(cb, 0);
2465
2466 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2467 for (i = 0; i < 16; i++)
2468 r600_store_value(cb, 0);
2469
2470 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2471 for (i = 0; i < 16; i++)
2472 r600_store_value(cb, 0);
2473
2474 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2475 for (i = 0; i < 16; i++)
2476 r600_store_value(cb, 0);
2477
2478 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2479 for (i = 0; i < 16; i++)
2480 r600_store_value(cb, 0);
2481
2482 if (rctx->screen->b.has_streamout) {
2483 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2484 }
2485
2486 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2487 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2488 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2489 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2490 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2491 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2492
2493 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2494 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2495 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2496 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2497 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2498 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2499 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2500 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2501 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2502 }
2503
2504 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2505 enum chip_class ctx_chip_class,
2506 enum radeon_family ctx_family,
2507 int ctx_drm_minor)
2508 {
2509 int ps_prio;
2510 int vs_prio;
2511 int gs_prio;
2512 int es_prio;
2513
2514 int hs_prio;
2515 int cs_prio;
2516 int ls_prio;
2517
2518 unsigned tmp;
2519
2520 ps_prio = 0;
2521 vs_prio = 1;
2522 gs_prio = 2;
2523 es_prio = 3;
2524 hs_prio = 3;
2525 ls_prio = 3;
2526 cs_prio = 0;
2527
2528 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2529 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2530 rctx->r6xx_num_clause_temp_gprs = 4;
2531 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2532 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2533 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2534 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2535
2536 tmp = 0;
2537 switch (ctx_family) {
2538 case CHIP_CEDAR:
2539 case CHIP_PALM:
2540 case CHIP_SUMO:
2541 case CHIP_SUMO2:
2542 case CHIP_CAICOS:
2543 break;
2544 default:
2545 tmp |= S_008C00_VC_ENABLE(1);
2546 break;
2547 }
2548 tmp |= S_008C00_EXPORT_SRC_C(1);
2549 tmp |= S_008C00_CS_PRIO(cs_prio);
2550 tmp |= S_008C00_LS_PRIO(ls_prio);
2551 tmp |= S_008C00_HS_PRIO(hs_prio);
2552 tmp |= S_008C00_PS_PRIO(ps_prio);
2553 tmp |= S_008C00_VS_PRIO(vs_prio);
2554 tmp |= S_008C00_GS_PRIO(gs_prio);
2555 tmp |= S_008C00_ES_PRIO(es_prio);
2556
2557 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2558 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2559
2560 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2561 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2562 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2563
2564 /* The cs checker requires this register to be set. */
2565 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2566
2567 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2568 r600_store_value(cb, 0);
2569 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2570
2571 return;
2572 }
2573
2574 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2575 {
2576 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2577 int num_ps_threads;
2578 int num_vs_threads;
2579 int num_gs_threads;
2580 int num_es_threads;
2581 int num_hs_threads;
2582 int num_ls_threads;
2583
2584 int num_ps_stack_entries;
2585 int num_vs_stack_entries;
2586 int num_gs_stack_entries;
2587 int num_es_stack_entries;
2588 int num_hs_stack_entries;
2589 int num_ls_stack_entries;
2590 enum radeon_family family;
2591 unsigned tmp, i;
2592
2593 if (rctx->b.chip_class == CAYMAN) {
2594 cayman_init_atom_start_cs(rctx);
2595 return;
2596 }
2597
2598 r600_init_command_buffer(cb, 338);
2599
2600 /* This must be first. */
2601 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2602 r600_store_value(cb, 0x80000000);
2603 r600_store_value(cb, 0x80000000);
2604
2605 /* We're setting config registers here. */
2606 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2607 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2608
2609 /* This enables pipeline stat & streamout queries.
2610 * They are only disabled by blits.
2611 */
2612 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2613 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2614
2615 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2616 rctx->b.family, rctx->screen->b.info.drm_minor);
2617
2618 family = rctx->b.family;
2619 switch (family) {
2620 case CHIP_CEDAR:
2621 default:
2622 num_ps_threads = 96;
2623 num_vs_threads = 16;
2624 num_gs_threads = 16;
2625 num_es_threads = 16;
2626 num_hs_threads = 16;
2627 num_ls_threads = 16;
2628 num_ps_stack_entries = 42;
2629 num_vs_stack_entries = 42;
2630 num_gs_stack_entries = 42;
2631 num_es_stack_entries = 42;
2632 num_hs_stack_entries = 42;
2633 num_ls_stack_entries = 42;
2634 break;
2635 case CHIP_REDWOOD:
2636 num_ps_threads = 128;
2637 num_vs_threads = 20;
2638 num_gs_threads = 20;
2639 num_es_threads = 20;
2640 num_hs_threads = 20;
2641 num_ls_threads = 20;
2642 num_ps_stack_entries = 42;
2643 num_vs_stack_entries = 42;
2644 num_gs_stack_entries = 42;
2645 num_es_stack_entries = 42;
2646 num_hs_stack_entries = 42;
2647 num_ls_stack_entries = 42;
2648 break;
2649 case CHIP_JUNIPER:
2650 num_ps_threads = 128;
2651 num_vs_threads = 20;
2652 num_gs_threads = 20;
2653 num_es_threads = 20;
2654 num_hs_threads = 20;
2655 num_ls_threads = 20;
2656 num_ps_stack_entries = 85;
2657 num_vs_stack_entries = 85;
2658 num_gs_stack_entries = 85;
2659 num_es_stack_entries = 85;
2660 num_hs_stack_entries = 85;
2661 num_ls_stack_entries = 85;
2662 break;
2663 case CHIP_CYPRESS:
2664 case CHIP_HEMLOCK:
2665 num_ps_threads = 128;
2666 num_vs_threads = 20;
2667 num_gs_threads = 20;
2668 num_es_threads = 20;
2669 num_hs_threads = 20;
2670 num_ls_threads = 20;
2671 num_ps_stack_entries = 85;
2672 num_vs_stack_entries = 85;
2673 num_gs_stack_entries = 85;
2674 num_es_stack_entries = 85;
2675 num_hs_stack_entries = 85;
2676 num_ls_stack_entries = 85;
2677 break;
2678 case CHIP_PALM:
2679 num_ps_threads = 96;
2680 num_vs_threads = 16;
2681 num_gs_threads = 16;
2682 num_es_threads = 16;
2683 num_hs_threads = 16;
2684 num_ls_threads = 16;
2685 num_ps_stack_entries = 42;
2686 num_vs_stack_entries = 42;
2687 num_gs_stack_entries = 42;
2688 num_es_stack_entries = 42;
2689 num_hs_stack_entries = 42;
2690 num_ls_stack_entries = 42;
2691 break;
2692 case CHIP_SUMO:
2693 num_ps_threads = 96;
2694 num_vs_threads = 25;
2695 num_gs_threads = 25;
2696 num_es_threads = 25;
2697 num_hs_threads = 16;
2698 num_ls_threads = 16;
2699 num_ps_stack_entries = 42;
2700 num_vs_stack_entries = 42;
2701 num_gs_stack_entries = 42;
2702 num_es_stack_entries = 42;
2703 num_hs_stack_entries = 42;
2704 num_ls_stack_entries = 42;
2705 break;
2706 case CHIP_SUMO2:
2707 num_ps_threads = 96;
2708 num_vs_threads = 25;
2709 num_gs_threads = 25;
2710 num_es_threads = 25;
2711 num_hs_threads = 16;
2712 num_ls_threads = 16;
2713 num_ps_stack_entries = 85;
2714 num_vs_stack_entries = 85;
2715 num_gs_stack_entries = 85;
2716 num_es_stack_entries = 85;
2717 num_hs_stack_entries = 85;
2718 num_ls_stack_entries = 85;
2719 break;
2720 case CHIP_BARTS:
2721 num_ps_threads = 128;
2722 num_vs_threads = 20;
2723 num_gs_threads = 20;
2724 num_es_threads = 20;
2725 num_hs_threads = 20;
2726 num_ls_threads = 20;
2727 num_ps_stack_entries = 85;
2728 num_vs_stack_entries = 85;
2729 num_gs_stack_entries = 85;
2730 num_es_stack_entries = 85;
2731 num_hs_stack_entries = 85;
2732 num_ls_stack_entries = 85;
2733 break;
2734 case CHIP_TURKS:
2735 num_ps_threads = 128;
2736 num_vs_threads = 20;
2737 num_gs_threads = 20;
2738 num_es_threads = 20;
2739 num_hs_threads = 20;
2740 num_ls_threads = 20;
2741 num_ps_stack_entries = 42;
2742 num_vs_stack_entries = 42;
2743 num_gs_stack_entries = 42;
2744 num_es_stack_entries = 42;
2745 num_hs_stack_entries = 42;
2746 num_ls_stack_entries = 42;
2747 break;
2748 case CHIP_CAICOS:
2749 num_ps_threads = 96;
2750 num_vs_threads = 10;
2751 num_gs_threads = 10;
2752 num_es_threads = 10;
2753 num_hs_threads = 10;
2754 num_ls_threads = 10;
2755 num_ps_stack_entries = 42;
2756 num_vs_stack_entries = 42;
2757 num_gs_stack_entries = 42;
2758 num_es_stack_entries = 42;
2759 num_hs_stack_entries = 42;
2760 num_ls_stack_entries = 42;
2761 break;
2762 }
2763
2764 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2765 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2766 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2767 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2768
2769 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2770 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2771
2772 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2773 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2774 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2775
2776 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2777 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2778 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2779
2780 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2781 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2782 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2783
2784 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2785 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2786 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2787
2788 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2789 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2790
2791 /* remove LS/HS from one SIMD for hw workaround */
2792 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2793 r600_store_value(cb, 0xffffffff);
2794 r600_store_value(cb, 0xffffffff);
2795 r600_store_value(cb, 0xfffffffe);
2796
2797 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2798 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2799
2800 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2801 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2802 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2803 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2804 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2805 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2806 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2807
2808 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2809 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2810 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2811 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2812 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2813
2814 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2815 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2816 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2817 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2818 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2819 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2820 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2821 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2822 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2823 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2824 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2825 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2826 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2827 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2828
2829 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2830
2831 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2832
2833 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2834 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2835 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2836
2837 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2838
2839 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2840
2841 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2842 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2843 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2844
2845 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2846 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2847 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2848 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2849 }
2850
2851 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2852 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2853
2854 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2855 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2856 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2857 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2858
2859 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2860 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2861 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2862
2863 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2864 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2865 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2866
2867 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2868 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2869 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2870 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2871 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2872 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2873 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2874
2875 /* to avoid GPU doing any preloading of constant from random address */
2876 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2877 for (i = 0; i < 16; i++)
2878 r600_store_value(cb, 0);
2879
2880 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2881 for (i = 0; i < 16; i++)
2882 r600_store_value(cb, 0);
2883
2884 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2885 for (i = 0; i < 16; i++)
2886 r600_store_value(cb, 0);
2887
2888 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2889 for (i = 0; i < 16; i++)
2890 r600_store_value(cb, 0);
2891
2892 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2893 for (i = 0; i < 16; i++)
2894 r600_store_value(cb, 0);
2895
2896 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2897
2898 if (rctx->screen->b.has_streamout) {
2899 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2900 }
2901
2902 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2903 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2904 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2905 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2906 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2907 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2908
2909 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2910 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2911 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2912
2913 if (rctx->b.family == CHIP_CAICOS) {
2914 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2915 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2916 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2917 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2918 } else {
2919 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2920 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2921 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2922 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2923 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2924 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2925 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2926 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2927 }
2928
2929 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2930 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2931 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2932 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2933 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2934 }
2935
2936 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2937 {
2938 struct r600_context *rctx = (struct r600_context *)ctx;
2939 struct r600_command_buffer *cb = &shader->command_buffer;
2940 struct r600_shader *rshader = &shader->shader;
2941 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2942 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2943 int ninterp = 0;
2944 boolean have_perspective = FALSE, have_linear = FALSE;
2945 static const unsigned spi_baryc_enable_bit[6] = {
2946 S_0286E0_PERSP_SAMPLE_ENA(1),
2947 S_0286E0_PERSP_CENTER_ENA(1),
2948 S_0286E0_PERSP_CENTROID_ENA(1),
2949 S_0286E0_LINEAR_SAMPLE_ENA(1),
2950 S_0286E0_LINEAR_CENTER_ENA(1),
2951 S_0286E0_LINEAR_CENTROID_ENA(1)
2952 };
2953 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
2954 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2955 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2956 uint32_t spi_ps_input_cntl[32];
2957
2958 if (!cb->buf) {
2959 r600_init_command_buffer(cb, 64);
2960 } else {
2961 cb->num_dw = 0;
2962 }
2963
2964 for (i = 0; i < rshader->ninput; i++) {
2965 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2966 POSITION goes via GPRs from the SC so isn't counted */
2967 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2968 pos_index = i;
2969 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
2970 if (face_index == -1)
2971 face_index = i;
2972 }
2973 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2974 if (face_index == -1)
2975 face_index = i; /* lives in same register, same enable bit */
2976 }
2977 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
2978 fixed_pt_position_index = i;
2979 }
2980 else {
2981 ninterp++;
2982 int k = eg_get_interpolator_index(
2983 rshader->input[i].interpolate,
2984 rshader->input[i].interpolate_location);
2985 if (k >= 0) {
2986 spi_baryc_cntl |= spi_baryc_enable_bit[k];
2987 have_perspective |= k < 3;
2988 have_linear |= !(k < 3);
2989 }
2990 }
2991
2992 sid = rshader->input[i].spi_sid;
2993
2994 if (sid) {
2995 tmp = S_028644_SEMANTIC(sid);
2996
2997 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2998 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2999 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3000 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3001 tmp |= S_028644_FLAT_SHADE(1);
3002 }
3003
3004 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3005 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3006 tmp |= S_028644_PT_SPRITE_TEX(1);
3007 }
3008
3009 spi_ps_input_cntl[num++] = tmp;
3010 }
3011 }
3012
3013 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3014 r600_store_array(cb, num, spi_ps_input_cntl);
3015
3016 for (i = 0; i < rshader->noutput; i++) {
3017 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3018 z_export = 1;
3019 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3020 stencil_export = 1;
3021 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3022 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3023 mask_export = 1;
3024 }
3025 if (rshader->uses_kill)
3026 db_shader_control |= S_02880C_KILL_ENABLE(1);
3027
3028 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3029 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3030 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3031
3032 switch (rshader->ps_conservative_z) {
3033 default: /* fall through */
3034 case TGSI_FS_DEPTH_LAYOUT_ANY:
3035 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3036 break;
3037 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3038 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3039 break;
3040 case TGSI_FS_DEPTH_LAYOUT_LESS:
3041 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3042 break;
3043 }
3044
3045 exports_ps = 0;
3046 for (i = 0; i < rshader->noutput; i++) {
3047 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3048 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3049 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3050 exports_ps |= 1;
3051 }
3052
3053 num_cout = rshader->nr_ps_color_exports;
3054
3055 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3056 if (!exports_ps) {
3057 /* always at least export 1 component per pixel */
3058 exports_ps = 2;
3059 }
3060 shader->nr_ps_color_outputs = num_cout;
3061 if (ninterp == 0) {
3062 ninterp = 1;
3063 have_perspective = TRUE;
3064 }
3065 if (!spi_baryc_cntl)
3066 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3067
3068 if (!have_perspective && !have_linear)
3069 have_perspective = TRUE;
3070
3071 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3072 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3073 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3074 spi_input_z = 0;
3075 if (pos_index != -1) {
3076 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3077 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3078 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3079 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3080 }
3081
3082 spi_ps_in_control_1 = 0;
3083 if (face_index != -1) {
3084 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3085 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3086 }
3087 if (fixed_pt_position_index != -1) {
3088 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3089 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3090 }
3091
3092 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3093 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3094 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3095
3096 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3097 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3098 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3099
3100 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3101 r600_store_value(cb, shader->bo->gpu_address >> 8);
3102 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3103 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3104 S_028844_PRIME_CACHE_ON_DRAW(1) |
3105 S_028844_STACK_SIZE(rshader->bc.nstack));
3106 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3107
3108 shader->db_shader_control = db_shader_control;
3109 shader->ps_depth_export = z_export | stencil_export | mask_export;
3110
3111 shader->sprite_coord_enable = sprite_coord_enable;
3112 if (rctx->rasterizer)
3113 shader->flatshade = rctx->rasterizer->flatshade;
3114 }
3115
3116 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3117 {
3118 struct r600_command_buffer *cb = &shader->command_buffer;
3119 struct r600_shader *rshader = &shader->shader;
3120
3121 r600_init_command_buffer(cb, 32);
3122
3123 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3124 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3125 S_028890_STACK_SIZE(rshader->bc.nstack));
3126 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3127 shader->bo->gpu_address >> 8);
3128 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3129 }
3130
3131 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3132 {
3133 struct r600_context *rctx = (struct r600_context *)ctx;
3134 struct r600_command_buffer *cb = &shader->command_buffer;
3135 struct r600_shader *rshader = &shader->shader;
3136 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3137 unsigned gsvs_itemsizes[4] = {
3138 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3139 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3140 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3141 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3142 };
3143
3144 r600_init_command_buffer(cb, 64);
3145
3146 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3147
3148
3149 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3150 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3151 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3152 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3153
3154 if (rctx->screen->b.info.drm_minor >= 35) {
3155 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3156 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3157 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3158 }
3159 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3160 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3161 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3162 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3163 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3164
3165 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3166 (rshader->ring_item_sizes[0]) >> 2);
3167
3168 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3169 gsvs_itemsizes[0] +
3170 gsvs_itemsizes[1] +
3171 gsvs_itemsizes[2] +
3172 gsvs_itemsizes[3]);
3173
3174 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3175 r600_store_value(cb, gsvs_itemsizes[0]);
3176 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3177 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3178
3179 /* FIXME calculate these values somehow ??? */
3180 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3181 r600_store_value(cb, 0x80); /* GS_PER_ES */
3182 r600_store_value(cb, 0x100); /* ES_PER_GS */
3183 r600_store_value(cb, 0x2); /* GS_PER_VS */
3184
3185 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3186 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3187 S_028878_STACK_SIZE(rshader->bc.nstack));
3188 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3189 shader->bo->gpu_address >> 8);
3190 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3191 }
3192
3193
3194 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3195 {
3196 struct r600_command_buffer *cb = &shader->command_buffer;
3197 struct r600_shader *rshader = &shader->shader;
3198 unsigned spi_vs_out_id[10] = {};
3199 unsigned i, tmp, nparams = 0;
3200
3201 for (i = 0; i < rshader->noutput; i++) {
3202 if (rshader->output[i].spi_sid) {
3203 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3204 spi_vs_out_id[nparams / 4] |= tmp;
3205 nparams++;
3206 }
3207 }
3208
3209 r600_init_command_buffer(cb, 32);
3210
3211 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3212 for (i = 0; i < 10; i++) {
3213 r600_store_value(cb, spi_vs_out_id[i]);
3214 }
3215
3216 /* Certain attributes (position, psize, etc.) don't count as params.
3217 * VS is required to export at least one param and r600_shader_from_tgsi()
3218 * takes care of adding a dummy export.
3219 */
3220 if (nparams < 1)
3221 nparams = 1;
3222
3223 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3224 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3225 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3226 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3227 S_028860_STACK_SIZE(rshader->bc.nstack));
3228 if (rshader->vs_position_window_space) {
3229 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3230 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3231 } else {
3232 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3233 S_028818_VTX_W0_FMT(1) |
3234 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3235 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3236 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3237
3238 }
3239 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3240 shader->bo->gpu_address >> 8);
3241 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3242
3243 shader->pa_cl_vs_out_cntl =
3244 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3245 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3246 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3247 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3248 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3249 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3250 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3251 }
3252
3253 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3254 {
3255 struct r600_command_buffer *cb = &shader->command_buffer;
3256 struct r600_shader *rshader = &shader->shader;
3257
3258 r600_init_command_buffer(cb, 32);
3259 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3260 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3261 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3262 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3263 shader->bo->gpu_address >> 8);
3264 }
3265
3266 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3267 {
3268 struct r600_command_buffer *cb = &shader->command_buffer;
3269 struct r600_shader *rshader = &shader->shader;
3270
3271 r600_init_command_buffer(cb, 32);
3272 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3273 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3274 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3275 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3276 shader->bo->gpu_address >> 8);
3277 }
3278 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3279 {
3280 struct pipe_blend_state blend;
3281
3282 memset(&blend, 0, sizeof(blend));
3283 blend.independent_blend_enable = true;
3284 blend.rt[0].colormask = 0xf;
3285 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3286 }
3287
3288 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3289 {
3290 struct pipe_blend_state blend;
3291 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3292 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3293
3294 memset(&blend, 0, sizeof(blend));
3295 blend.independent_blend_enable = true;
3296 blend.rt[0].colormask = 0xf;
3297 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3298 }
3299
3300 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3301 {
3302 struct pipe_blend_state blend;
3303 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3304
3305 memset(&blend, 0, sizeof(blend));
3306 blend.independent_blend_enable = true;
3307 blend.rt[0].colormask = 0xf;
3308 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3309 }
3310
3311 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3312 {
3313 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3314
3315 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3316 }
3317
3318 void evergreen_update_db_shader_control(struct r600_context * rctx)
3319 {
3320 bool dual_export;
3321 unsigned db_shader_control;
3322
3323 if (!rctx->ps_shader) {
3324 return;
3325 }
3326
3327 dual_export = rctx->framebuffer.export_16bpc &&
3328 !rctx->ps_shader->current->ps_depth_export;
3329
3330 db_shader_control = rctx->ps_shader->current->db_shader_control |
3331 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3332 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3333 V_02880C_EXPORT_DB_FULL) |
3334 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3335
3336 /* When alpha test is enabled we can't trust the hw to make the proper
3337 * decision on the order in which ztest should be run related to fragment
3338 * shader execution.
3339 *
3340 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3341 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3342 * execution and thus after alpha test so if discarded by the alpha test
3343 * the z value is not written.
3344 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3345 * get a hang unless you flush the DB in between. For now just use
3346 * LATE_Z.
3347 */
3348 if (rctx->alphatest_state.sx_alpha_test_control) {
3349 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3350 } else {
3351 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3352 }
3353
3354 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3355 rctx->db_misc_state.db_shader_control = db_shader_control;
3356 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3357 }
3358 }
3359
3360 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3361 struct pipe_resource *dst,
3362 unsigned dst_level,
3363 unsigned dst_x,
3364 unsigned dst_y,
3365 unsigned dst_z,
3366 struct pipe_resource *src,
3367 unsigned src_level,
3368 unsigned src_x,
3369 unsigned src_y,
3370 unsigned src_z,
3371 unsigned copy_height,
3372 unsigned pitch,
3373 unsigned bpp)
3374 {
3375 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3376 struct r600_texture *rsrc = (struct r600_texture*)src;
3377 struct r600_texture *rdst = (struct r600_texture*)dst;
3378 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3379 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3380 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3381 uint64_t base, addr;
3382
3383 dst_mode = rdst->surface.level[dst_level].mode;
3384 src_mode = rsrc->surface.level[src_level].mode;
3385 /* downcast linear aligned to linear to simplify test */
3386 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3387 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3388 assert(dst_mode != src_mode);
3389
3390 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3391 if (util_format_has_depth(util_format_description(src->format)))
3392 non_disp_tiling = 1;
3393
3394 y = 0;
3395 sub_cmd = EG_DMA_COPY_TILED;
3396 lbpp = util_logbase2(bpp);
3397 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3398 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3399
3400 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3401 /* T2L */
3402 array_mode = evergreen_array_mode(src_mode);
3403 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3404 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3405 /* linear height must be the same as the slice tile max height, it's ok even
3406 * if the linear destination/source have smaller heigh as the size of the
3407 * dma packet will be using the copy_height which is always smaller or equal
3408 * to the linear height
3409 */
3410 height = rsrc->surface.level[src_level].npix_y;
3411 detile = 1;
3412 x = src_x;
3413 y = src_y;
3414 z = src_z;
3415 base = rsrc->surface.level[src_level].offset;
3416 addr = rdst->surface.level[dst_level].offset;
3417 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3418 addr += dst_y * pitch + dst_x * bpp;
3419 bank_h = eg_bank_wh(rsrc->surface.bankh);
3420 bank_w = eg_bank_wh(rsrc->surface.bankw);
3421 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3422 tile_split = eg_tile_split(rsrc->surface.tile_split);
3423 base += rsrc->resource.gpu_address;
3424 addr += rdst->resource.gpu_address;
3425 } else {
3426 /* L2T */
3427 array_mode = evergreen_array_mode(dst_mode);
3428 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3429 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3430 /* linear height must be the same as the slice tile max height, it's ok even
3431 * if the linear destination/source have smaller heigh as the size of the
3432 * dma packet will be using the copy_height which is always smaller or equal
3433 * to the linear height
3434 */
3435 height = rdst->surface.level[dst_level].npix_y;
3436 detile = 0;
3437 x = dst_x;
3438 y = dst_y;
3439 z = dst_z;
3440 base = rdst->surface.level[dst_level].offset;
3441 addr = rsrc->surface.level[src_level].offset;
3442 addr += rsrc->surface.level[src_level].slice_size * src_z;
3443 addr += src_y * pitch + src_x * bpp;
3444 bank_h = eg_bank_wh(rdst->surface.bankh);
3445 bank_w = eg_bank_wh(rdst->surface.bankw);
3446 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3447 tile_split = eg_tile_split(rdst->surface.tile_split);
3448 base += rdst->resource.gpu_address;
3449 addr += rsrc->resource.gpu_address;
3450 }
3451
3452 size = (copy_height * pitch) / 4;
3453 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3454 r600_need_dma_space(&rctx->b, ncopy * 9);
3455
3456 for (i = 0; i < ncopy; i++) {
3457 cheight = copy_height;
3458 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3459 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3460 }
3461 size = (cheight * pitch) / 4;
3462 /* emit reloc before writing cs so that cs is always in consistent state */
3463 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3464 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3465 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3466 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3467 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3468 cs->buf[cs->cdw++] = base >> 8;
3469 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3470 (lbpp << 24) | (bank_h << 21) |
3471 (bank_w << 18) | (mt_aspect << 16);
3472 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3473 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3474 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3475 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3476 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3477 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3478 copy_height -= cheight;
3479 addr += cheight * pitch;
3480 y += cheight;
3481 }
3482 }
3483
3484 static void evergreen_dma_copy(struct pipe_context *ctx,
3485 struct pipe_resource *dst,
3486 unsigned dst_level,
3487 unsigned dstx, unsigned dsty, unsigned dstz,
3488 struct pipe_resource *src,
3489 unsigned src_level,
3490 const struct pipe_box *src_box)
3491 {
3492 struct r600_context *rctx = (struct r600_context *)ctx;
3493 struct r600_texture *rsrc = (struct r600_texture*)src;
3494 struct r600_texture *rdst = (struct r600_texture*)dst;
3495 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3496 unsigned src_w, dst_w;
3497 unsigned src_x, src_y;
3498 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3499
3500 if (rctx->b.dma.cs == NULL) {
3501 goto fallback;
3502 }
3503
3504 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3505 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3506 return;
3507 }
3508
3509 if (src->format != dst->format || src_box->depth > 1 ||
3510 (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
3511 goto fallback;
3512 }
3513
3514 if (rsrc->dirty_level_mask & (1 << src_level)) {
3515 ctx->flush_resource(ctx, src);
3516 }
3517
3518 src_x = util_format_get_nblocksx(src->format, src_box->x);
3519 dst_x = util_format_get_nblocksx(src->format, dst_x);
3520 src_y = util_format_get_nblocksy(src->format, src_box->y);
3521 dst_y = util_format_get_nblocksy(src->format, dst_y);
3522
3523 bpp = rdst->surface.bpe;
3524 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3525 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3526 src_w = rsrc->surface.level[src_level].npix_x;
3527 dst_w = rdst->surface.level[dst_level].npix_x;
3528 copy_height = src_box->height / rsrc->surface.blk_h;
3529
3530 dst_mode = rdst->surface.level[dst_level].mode;
3531 src_mode = rsrc->surface.level[src_level].mode;
3532 /* downcast linear aligned to linear to simplify test */
3533 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3534 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3535
3536 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3537 /* FIXME evergreen can do partial blit */
3538 goto fallback;
3539 }
3540 /* the x test here are currently useless (because we don't support partial blit)
3541 * but keep them around so we don't forget about those
3542 */
3543 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3544 goto fallback;
3545 }
3546
3547 /* 128 bpp surfaces require non_disp_tiling for both
3548 * tiled and linear buffers on cayman. However, async
3549 * DMA only supports it on the tiled side. As such
3550 * the tile order is backwards after a L2T/T2L packet.
3551 */
3552 if ((rctx->b.chip_class == CAYMAN) &&
3553 (src_mode != dst_mode) &&
3554 (util_format_get_blocksize(src->format) >= 16)) {
3555 goto fallback;
3556 }
3557
3558 if (src_mode == dst_mode) {
3559 uint64_t dst_offset, src_offset;
3560 /* simple dma blit would do NOTE code here assume :
3561 * src_box.x/y == 0
3562 * dst_x/y == 0
3563 * dst_pitch == src_pitch
3564 */
3565 src_offset= rsrc->surface.level[src_level].offset;
3566 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3567 src_offset += src_y * src_pitch + src_x * bpp;
3568 dst_offset = rdst->surface.level[dst_level].offset;
3569 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3570 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3571 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3572 src_box->height * src_pitch);
3573 } else {
3574 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3575 src, src_level, src_x, src_y, src_box->z,
3576 copy_height, dst_pitch, bpp);
3577 }
3578 return;
3579
3580 fallback:
3581 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3582 src, src_level, src_box);
3583 }
3584
3585 static void evergreen_set_tess_state(struct pipe_context *ctx,
3586 const float default_outer_level[4],
3587 const float default_inner_level[2])
3588 {
3589 struct r600_context *rctx = (struct r600_context *)ctx;
3590
3591 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3592 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3593 rctx->tess_state_dirty = true;
3594 }
3595
3596 void evergreen_init_state_functions(struct r600_context *rctx)
3597 {
3598 unsigned id = 1;
3599 unsigned i;
3600 /* !!!
3601 * To avoid GPU lockup registers must be emitted in a specific order
3602 * (no kidding ...). The order below is important and have been
3603 * partially inferred from analyzing fglrx command stream.
3604 *
3605 * Don't reorder atom without carefully checking the effect (GPU lockup
3606 * or piglit regression).
3607 * !!!
3608 */
3609 if (rctx->b.chip_class == EVERGREEN) {
3610 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3611 rctx->config_state.dyn_gpr_enabled = true;
3612 }
3613 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3614 /* shader const */
3615 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3616 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3617 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3618 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3619 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3620 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3621 /* shader program */
3622 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3623 /* sampler */
3624 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3625 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3626 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3627 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3628 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3629 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3630 /* resources */
3631 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3632 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3633 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3634 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3635 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3636 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3637 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3638 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3639
3640 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3641
3642 if (rctx->b.chip_class == EVERGREEN) {
3643 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3644 } else {
3645 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3646 }
3647 rctx->sample_mask.sample_mask = ~0;
3648
3649 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3650 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3651 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3652 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3653 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3654 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3655 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3656 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3657 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3658 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3659 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3660 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3661 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3662 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3663 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3664 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3665 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3666 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3667 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3668 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3669 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3670 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3671
3672 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3673 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3674 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3675 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3676 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3677 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3678 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3679 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3680 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3681 if (rctx->b.chip_class == EVERGREEN)
3682 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3683 else
3684 rctx->b.b.get_sample_position = cayman_get_sample_position;
3685 rctx->b.dma_copy = evergreen_dma_copy;
3686
3687 evergreen_init_compute_state_functions(rctx);
3688 }
3689
3690 /**
3691 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3692 *
3693 * The information about LDS and other non-compile-time parameters is then
3694 * written to the const buffer.
3695
3696 * const buffer contains -
3697 * uint32_t input_patch_size
3698 * uint32_t input_vertex_size
3699 * uint32_t num_tcs_input_cp
3700 * uint32_t num_tcs_output_cp;
3701 * uint32_t output_patch_size
3702 * uint32_t output_vertex_size
3703 * uint32_t output_patch0_offset
3704 * uint32_t perpatch_output_offset
3705 * and the same constbuf is bound to LS/HS/VS(ES).
3706 */
3707 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3708 {
3709 struct pipe_constant_buffer constbuf = {0};
3710 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3711 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3712 unsigned num_tcs_input_cp = info->vertices_per_patch;
3713 unsigned num_tcs_outputs;
3714 unsigned num_tcs_output_cp;
3715 unsigned num_tcs_patch_outputs;
3716 unsigned num_tcs_inputs;
3717 unsigned input_vertex_size, output_vertex_size;
3718 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3719 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3720 uint32_t values[16];
3721 unsigned num_waves;
3722 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3723 unsigned wave_divisor = (16 * num_pipes);
3724
3725 *num_patches = 1;
3726
3727 if (!rctx->tes_shader) {
3728 rctx->lds_alloc = 0;
3729 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3730 R600_LDS_INFO_CONST_BUFFER, NULL);
3731 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3732 R600_LDS_INFO_CONST_BUFFER, NULL);
3733 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3734 R600_LDS_INFO_CONST_BUFFER, NULL);
3735 return;
3736 }
3737
3738 if (rctx->lds_alloc != 0 &&
3739 rctx->last_ls == ls &&
3740 !rctx->tess_state_dirty &&
3741 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3742 rctx->last_tcs == tcs)
3743 return;
3744
3745 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3746
3747 if (rctx->tcs_shader) {
3748 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3749 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3750 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3751 } else {
3752 num_tcs_outputs = num_tcs_inputs;
3753 num_tcs_output_cp = num_tcs_input_cp;
3754 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3755 }
3756
3757 /* size in bytes */
3758 input_vertex_size = num_tcs_inputs * 16;
3759 output_vertex_size = num_tcs_outputs * 16;
3760
3761 input_patch_size = num_tcs_input_cp * input_vertex_size;
3762
3763 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3764 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3765
3766 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3767 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3768
3769 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3770
3771 values[0] = input_patch_size;
3772 values[1] = input_vertex_size;
3773 values[2] = num_tcs_input_cp;
3774 values[3] = num_tcs_output_cp;
3775
3776 values[4] = output_patch_size;
3777 values[5] = output_vertex_size;
3778 values[6] = output_patch0_offset;
3779 values[7] = perpatch_output_offset;
3780
3781 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3782 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3783 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3784
3785 rctx->lds_alloc = (lds_size | (num_waves << 14));
3786
3787 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3788 values[14] = 0;
3789 values[15] = 0;
3790
3791 rctx->tess_state_dirty = false;
3792 rctx->last_ls = ls;
3793 rctx->last_tcs = tcs;
3794 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3795
3796 constbuf.user_buffer = values;
3797 constbuf.buffer_size = 16 * 4;
3798
3799 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3800 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3801 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3802 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3803 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3804 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3805 pipe_resource_reference(&constbuf.buffer, NULL);
3806 }
3807
3808 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3809 const struct pipe_draw_info *info,
3810 unsigned num_patches)
3811 {
3812 unsigned num_output_cp;
3813
3814 if (!rctx->tes_shader)
3815 return 0;
3816
3817 num_output_cp = rctx->tcs_shader ?
3818 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3819 info->vertices_per_patch;
3820
3821 return S_028B58_NUM_PATCHES(num_patches) |
3822 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3823 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3824 }
3825
3826 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3827 struct radeon_winsys_cs *cs,
3828 uint32_t ls_hs_config)
3829 {
3830 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3831 }
3832
3833 void evergreen_set_lds_alloc(struct r600_context *rctx,
3834 struct radeon_winsys_cs *cs,
3835 uint32_t lds_alloc)
3836 {
3837 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3838 }
3839
3840 /* on evergreen if you are running tessellation you need to disable dynamic
3841 GPRs to workaround a hardware bug.*/
3842 bool evergreen_adjust_gprs(struct r600_context *rctx)
3843 {
3844 unsigned num_gprs[EG_NUM_HW_STAGES];
3845 unsigned def_gprs[EG_NUM_HW_STAGES];
3846 unsigned cur_gprs[EG_NUM_HW_STAGES];
3847 unsigned new_gprs[EG_NUM_HW_STAGES];
3848 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3849 unsigned max_gprs;
3850 unsigned i;
3851 unsigned total_gprs;
3852 unsigned tmp[3];
3853 bool rework = false, set_default = false, set_dirty = false;
3854 max_gprs = 0;
3855 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3856 def_gprs[i] = rctx->default_gprs[i];
3857 max_gprs += def_gprs[i];
3858 }
3859 max_gprs += def_num_clause_temp_gprs * 2;
3860
3861 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3862 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3863 if (rctx->config_state.dyn_gpr_enabled)
3864 return true;
3865
3866 /* transition back to dyn gpr enabled state */
3867 rctx->config_state.dyn_gpr_enabled = true;
3868 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3869 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3870 return true;
3871 }
3872
3873
3874 /* gather required shader gprs */
3875 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3876 if (rctx->hw_shader_stages[i].shader)
3877 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3878 else
3879 num_gprs[i] = 0;
3880 }
3881
3882 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3883 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3884 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3885 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3886 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3887 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3888
3889 total_gprs = 0;
3890 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3891 new_gprs[i] = num_gprs[i];
3892 total_gprs += num_gprs[i];
3893 }
3894
3895 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3896 return false;
3897
3898 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3899 if (new_gprs[i] > cur_gprs[i]) {
3900 rework = true;
3901 break;
3902 }
3903 }
3904
3905 if (rctx->config_state.dyn_gpr_enabled) {
3906 set_dirty = true;
3907 rctx->config_state.dyn_gpr_enabled = false;
3908 }
3909
3910 if (rework) {
3911 set_default = true;
3912 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3913 if (new_gprs[i] > def_gprs[i])
3914 set_default = false;
3915 }
3916
3917 if (set_default) {
3918 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3919 new_gprs[i] = def_gprs[i];
3920 }
3921 } else {
3922 unsigned ps_value = max_gprs;
3923
3924 ps_value -= (def_num_clause_temp_gprs * 2);
3925 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3926 ps_value -= new_gprs[i];
3927
3928 new_gprs[R600_HW_STAGE_PS] = ps_value;
3929 }
3930
3931 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3932 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3933 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3934
3935 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3936 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3937
3938 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3939 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3940
3941 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3942 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3943 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
3944 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
3945 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
3946 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
3947 set_dirty = true;
3948 }
3949 }
3950
3951
3952 if (set_dirty) {
3953 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3954 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3955 }
3956 return true;
3957 }