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mesa: minor tweaks in _mesa_set_fetch_functions()
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
39 {
40 if(alu->is_op3)
41 return 3;
42
43 switch (bc->chiprev) {
44 case CHIPREV_R600:
45 case CHIPREV_R700:
46 switch (alu->inst) {
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
48 return 0;
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
68 return 2;
69
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
87 return 1;
88 default: R600_ERR(
89 "Need instruction operand number for 0x%x.\n", alu->inst);
90 }
91 break;
92 case CHIPREV_EVERGREEN:
93 switch (alu->inst) {
94 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
95 return 0;
96 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
97 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
98 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
99 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
100 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
101 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
103 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
117 return 2;
118
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
135 return 1;
136 default: R600_ERR(
137 "Need instruction operand number for 0x%x.\n", alu->inst);
138 }
139 break;
140 }
141
142 return 3;
143 }
144
145 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
146
147 static struct r600_bc_cf *r600_bc_cf(void)
148 {
149 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
150
151 if (cf == NULL)
152 return NULL;
153 LIST_INITHEAD(&cf->list);
154 LIST_INITHEAD(&cf->alu);
155 LIST_INITHEAD(&cf->vtx);
156 LIST_INITHEAD(&cf->tex);
157 return cf;
158 }
159
160 static struct r600_bc_alu *r600_bc_alu(void)
161 {
162 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
163
164 if (alu == NULL)
165 return NULL;
166 LIST_INITHEAD(&alu->list);
167 return alu;
168 }
169
170 static struct r600_bc_vtx *r600_bc_vtx(void)
171 {
172 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
173
174 if (vtx == NULL)
175 return NULL;
176 LIST_INITHEAD(&vtx->list);
177 return vtx;
178 }
179
180 static struct r600_bc_tex *r600_bc_tex(void)
181 {
182 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
183
184 if (tex == NULL)
185 return NULL;
186 LIST_INITHEAD(&tex->list);
187 return tex;
188 }
189
190 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
191 {
192 LIST_INITHEAD(&bc->cf);
193 bc->family = family;
194 switch (bc->family) {
195 case CHIP_R600:
196 case CHIP_RV610:
197 case CHIP_RV630:
198 case CHIP_RV670:
199 case CHIP_RV620:
200 case CHIP_RV635:
201 case CHIP_RS780:
202 case CHIP_RS880:
203 bc->chiprev = CHIPREV_R600;
204 break;
205 case CHIP_RV770:
206 case CHIP_RV730:
207 case CHIP_RV710:
208 case CHIP_RV740:
209 bc->chiprev = CHIPREV_R700;
210 break;
211 case CHIP_CEDAR:
212 case CHIP_REDWOOD:
213 case CHIP_JUNIPER:
214 case CHIP_CYPRESS:
215 case CHIP_HEMLOCK:
216 case CHIP_PALM:
217 case CHIP_BARTS:
218 case CHIP_TURKS:
219 case CHIP_CAICOS:
220 bc->chiprev = CHIPREV_EVERGREEN;
221 break;
222 default:
223 R600_ERR("unknown family %d\n", bc->family);
224 return -EINVAL;
225 }
226 return 0;
227 }
228
229 static int r600_bc_add_cf(struct r600_bc *bc)
230 {
231 struct r600_bc_cf *cf = r600_bc_cf();
232
233 if (cf == NULL)
234 return -ENOMEM;
235 LIST_ADDTAIL(&cf->list, &bc->cf);
236 if (bc->cf_last)
237 cf->id = bc->cf_last->id + 2;
238 bc->cf_last = cf;
239 bc->ncf++;
240 bc->ndw += 2;
241 bc->force_add_cf = 0;
242 return 0;
243 }
244
245 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
246 {
247 int r;
248
249 r = r600_bc_add_cf(bc);
250 if (r)
251 return r;
252 bc->cf_last->inst = output->inst;
253 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
254 return 0;
255 }
256
257 /* alu instructions that can ony exits once per group */
258 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
259 {
260 switch (bc->chiprev) {
261 case CHIPREV_R600:
262 case CHIPREV_R700:
263 return !alu->is_op3 && (
264 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
265 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
266 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
267 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
268 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
269 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
270 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
271 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
272 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
273 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
274 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
275 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
276 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
277 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
278 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
279 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
280 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
281 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
282 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
283 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
284 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
285 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
286 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
287 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
288 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
289 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
290 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
291 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
292 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
293 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
294 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
295 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
296 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
297 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
298 case CHIPREV_EVERGREEN:
299 default:
300 return !alu->is_op3 && (
301 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
302 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
303 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
304 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
305 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
306 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
307 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
308 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
309 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
310 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
311 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
312 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
313 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
314 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
315 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
316 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
317 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
318 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
319 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
320 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
321 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
322 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
323 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
324 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
325 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
326 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
327 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
328 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
329 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
330 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
331 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
332 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
333 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
334 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
335 }
336 }
337
338 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
339 {
340 switch (bc->chiprev) {
341 case CHIPREV_R600:
342 case CHIPREV_R700:
343 return !alu->is_op3 && (
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
348 case CHIPREV_EVERGREEN:
349 default:
350 return !alu->is_op3 && (
351 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
352 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
353 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
354 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
355 }
356 }
357
358 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
359 {
360 switch (bc->chiprev) {
361 case CHIPREV_R600:
362 case CHIPREV_R700:
363 return !alu->is_op3 && (
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
367 case CHIPREV_EVERGREEN:
368 default:
369 return !alu->is_op3 && (
370 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
371 }
372 }
373
374 /* alu instructions that can only execute on the vector unit */
375 static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
376 {
377 return is_alu_reduction_inst(bc, alu) ||
378 is_alu_mova_inst(bc, alu);
379 }
380
381 /* alu instructions that can only execute on the trans unit */
382 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
383 {
384 switch (bc->chiprev) {
385 case CHIPREV_R600:
386 case CHIPREV_R700:
387 if (!alu->is_op3)
388 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
389 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
390 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
391 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
392 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
393 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
394 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
395 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
396 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
397 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
398 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
399 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
400 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
401 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
402 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
403 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
404 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
405 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
406 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
407 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
408 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
409 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
410 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
411 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
412 else
413 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
414 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
415 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
416 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
417 case CHIPREV_EVERGREEN:
418 default:
419 if (!alu->is_op3)
420 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
421 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
422 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
423 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
424 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
425 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
426 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
427 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
428 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
429 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
430 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
431 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
433 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
434 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
435 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
436 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
437 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
438 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
439 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
440 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
441 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
442 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
443 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
444 else
445 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
446 }
447 }
448
449 /* alu instructions that can execute on any unit */
450 static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
451 {
452 return !is_alu_vec_unit_inst(bc, alu) &&
453 !is_alu_trans_unit_inst(bc, alu);
454 }
455
456 static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
457 struct r600_bc_alu *assignment[5])
458 {
459 struct r600_bc_alu *alu;
460 unsigned i, chan, trans;
461
462 for (i = 0; i < 5; i++)
463 assignment[i] = NULL;
464
465 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
466 chan = alu->dst.chan;
467 if (is_alu_trans_unit_inst(bc, alu))
468 trans = 1;
469 else if (is_alu_vec_unit_inst(bc, alu))
470 trans = 0;
471 else if (assignment[chan])
472 trans = 1; // assume ALU_INST_PREFER_VECTOR
473 else
474 trans = 0;
475
476 if (trans) {
477 if (assignment[4]) {
478 assert(0); //ALU.Trans has already been allocated
479 return -1;
480 }
481 assignment[4] = alu;
482 } else {
483 if (assignment[chan]) {
484 assert(0); //ALU.chan has already been allocated
485 return -1;
486 }
487 assignment[chan] = alu;
488 }
489
490 if (alu->last)
491 break;
492 }
493 return 0;
494 }
495
496 struct alu_bank_swizzle {
497 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
498 int hw_cfile_addr[4];
499 int hw_cfile_elem[4];
500 };
501
502 const unsigned cycle_for_bank_swizzle_vec[][3] = {
503 [SQ_ALU_VEC_012] = { 0, 1, 2 },
504 [SQ_ALU_VEC_021] = { 0, 2, 1 },
505 [SQ_ALU_VEC_120] = { 1, 2, 0 },
506 [SQ_ALU_VEC_102] = { 1, 0, 2 },
507 [SQ_ALU_VEC_201] = { 2, 0, 1 },
508 [SQ_ALU_VEC_210] = { 2, 1, 0 }
509 };
510
511 const unsigned cycle_for_bank_swizzle_scl[][3] = {
512 [SQ_ALU_SCL_210] = { 2, 1, 0 },
513 [SQ_ALU_SCL_122] = { 1, 2, 2 },
514 [SQ_ALU_SCL_212] = { 2, 1, 2 },
515 [SQ_ALU_SCL_221] = { 2, 2, 1 }
516 };
517
518 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
519 {
520 int i, cycle, component;
521 /* set up gpr use */
522 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
523 for (component = 0; component < NUM_OF_COMPONENTS; component++)
524 bs->hw_gpr[cycle][component] = -1;
525 for (i = 0; i < 4; i++)
526 bs->hw_cfile_addr[i] = -1;
527 for (i = 0; i < 4; i++)
528 bs->hw_cfile_elem[i] = -1;
529 }
530
531 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
532 {
533 if (bs->hw_gpr[cycle][chan] == -1)
534 bs->hw_gpr[cycle][chan] = sel;
535 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
536 // Another scalar operation has already used GPR read port for channel
537 return -1;
538 }
539 return 0;
540 }
541
542 static int reserve_cfile(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
543 {
544 int res, resmatch = -1, resempty = -1;
545 for (res = 3; res >= 0; --res) {
546 if (bs->hw_cfile_addr[res] == -1)
547 resempty = res;
548 else if (bs->hw_cfile_addr[res] == sel &&
549 bs->hw_cfile_elem[res] == chan)
550 resmatch = res;
551 }
552 if (resmatch != -1)
553 return 0; // Read for this scalar element already reserved, nothing to do here.
554 else if (resempty != -1) {
555 bs->hw_cfile_addr[resempty] = sel;
556 bs->hw_cfile_elem[resempty] = chan;
557 } else {
558 // All cfile read ports are used, cannot reference vector element
559 return -1;
560 }
561 return 0;
562 }
563
564 static int is_gpr(unsigned sel)
565 {
566 return (sel >= 0 && sel <= 127);
567 }
568
569 /* CB constants start at 512, and get translated to a kcache index when ALU
570 * clauses are constructed. Note that we handle kcache constants the same way
571 * as (the now gone) cfile constants, is that really required? */
572 static int is_cfile(unsigned sel)
573 {
574 return (sel > 255 && sel < 512) ||
575 (sel > 511 && sel < 4607) || // Kcache before translate
576 (sel > 127 && sel < 192); // Kcache after translate
577 }
578
579 static int is_const(int sel)
580 {
581 return is_cfile(sel) ||
582 (sel >= V_SQ_ALU_SRC_0 &&
583 sel <= V_SQ_ALU_SRC_LITERAL);
584 }
585
586 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
587 struct alu_bank_swizzle *bs, int bank_swizzle)
588 {
589 int r, src, num_src, sel, elem, cycle;
590
591 num_src = r600_bc_get_num_operands(bc, alu);
592 for (src = 0; src < num_src; src++) {
593 sel = alu->src[src].sel;
594 elem = alu->src[src].chan;
595 if (is_gpr(sel)) {
596 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
597 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
598 // Nothing to do; special-case optimization,
599 // second source uses first source’s reservation
600 continue;
601 else {
602 r = reserve_gpr(bs, sel, elem, cycle);
603 if (r)
604 return r;
605 }
606 } else if (is_cfile(sel)) {
607 r = reserve_cfile(bs, sel, elem);
608 if (r)
609 return r;
610 }
611 // No restrictions on PV, PS, literal or special constants
612 }
613 return 0;
614 }
615
616 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
617 struct alu_bank_swizzle *bs, int bank_swizzle)
618 {
619 int r, src, num_src, const_count, sel, elem, cycle;
620
621 num_src = r600_bc_get_num_operands(bc, alu);
622 for (const_count = 0, src = 0; src < num_src; ++src) {
623 sel = alu->src[src].sel;
624 elem = alu->src[src].chan;
625 if (is_const(sel)) { // Any constant, including literal and inline constants
626 if (const_count >= 2)
627 // More than two references to a constant in
628 // transcendental operation.
629 return -1;
630 else
631 const_count++;
632 }
633 if (is_cfile(sel)) {
634 r = reserve_cfile(bs, sel, elem);
635 if (r)
636 return r;
637 }
638 }
639 for (src = 0; src < num_src; ++src) {
640 sel = alu->src[src].sel;
641 elem = alu->src[src].chan;
642 if (is_gpr(sel)) {
643 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
644 if (cycle < const_count)
645 // Cycle for GPR load conflicts with
646 // constant load in transcendental operation.
647 return -1;
648 r = reserve_gpr(bs, sel, elem, cycle);
649 if (r)
650 return r;
651 }
652 // Constants already processed
653 // No restrictions on PV, PS
654 }
655 return 0;
656 }
657
658 static int check_and_set_bank_swizzle(struct r600_bc *bc,
659 struct r600_bc_alu *slots[5])
660 {
661 struct alu_bank_swizzle bs;
662 int bank_swizzle[5];
663 int i, r = 0, forced = 0;
664
665 for (i = 0; i < 5; i++)
666 if (slots[i] && slots[i]->bank_swizzle_force) {
667 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
668 forced = 1;
669 }
670
671 if (forced)
672 return 0;
673
674 // just check every possible combination of bank swizzle
675 // not very efficent, but works on the first try in most of the cases
676 for (i = 0; i < 4; i++)
677 bank_swizzle[i] = SQ_ALU_VEC_012;
678 bank_swizzle[4] = SQ_ALU_SCL_210;
679 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
680 init_bank_swizzle(&bs);
681 for (i = 0; i < 4; i++) {
682 if (slots[i]) {
683 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
684 if (r)
685 break;
686 }
687 }
688 if (!r && slots[4]) {
689 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
690 }
691 if (!r) {
692 for (i = 0; i < 5; i++) {
693 if (slots[i])
694 slots[i]->bank_swizzle = bank_swizzle[i];
695 }
696 return 0;
697 }
698
699 for (i = 0; i < 5; i++) {
700 bank_swizzle[i]++;
701 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
702 break;
703 else
704 bank_swizzle[i] = SQ_ALU_VEC_012;
705 }
706 }
707
708 // couldn't find a working swizzle
709 return -1;
710 }
711
712 static int replace_gpr_with_pv_ps(struct r600_bc *bc,
713 struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
714 {
715 struct r600_bc_alu *prev[5];
716 int gpr[5], chan[5];
717 int i, j, r, src, num_src;
718
719 r = assign_alu_units(bc, alu_prev, prev);
720 if (r)
721 return r;
722
723 for (i = 0; i < 5; ++i) {
724 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
725 gpr[i] = prev[i]->dst.sel;
726 if (is_alu_reduction_inst(bc, prev[i]))
727 chan[i] = 0;
728 else
729 chan[i] = prev[i]->dst.chan;
730 } else
731 gpr[i] = -1;
732 }
733
734 for (i = 0; i < 5; ++i) {
735 struct r600_bc_alu *alu = slots[i];
736 if(!alu)
737 continue;
738
739 num_src = r600_bc_get_num_operands(bc, alu);
740 for (src = 0; src < num_src; ++src) {
741 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
742 continue;
743
744 if (alu->src[src].sel == gpr[4] &&
745 alu->src[src].chan == chan[4]) {
746 alu->src[src].sel = V_SQ_ALU_SRC_PS;
747 alu->src[src].chan = 0;
748 continue;
749 }
750
751 for (j = 0; j < 4; ++j) {
752 if (alu->src[src].sel == gpr[j] &&
753 alu->src[src].chan == j) {
754 alu->src[src].sel = V_SQ_ALU_SRC_PV;
755 alu->src[src].chan = chan[j];
756 break;
757 }
758 }
759 }
760 }
761
762 return 0;
763 }
764
765 void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
766 {
767 switch(value) {
768 case 0:
769 *sel = V_SQ_ALU_SRC_0;
770 break;
771 case 1:
772 *sel = V_SQ_ALU_SRC_1_INT;
773 break;
774 case -1:
775 *sel = V_SQ_ALU_SRC_M_1_INT;
776 break;
777 case 0x3F800000: // 1.0f
778 *sel = V_SQ_ALU_SRC_1;
779 break;
780 case 0x3F000000: // 0.5f
781 *sel = V_SQ_ALU_SRC_0_5;
782 break;
783 case 0xBF800000: // -1.0f
784 *sel = V_SQ_ALU_SRC_1;
785 *neg ^= 1;
786 break;
787 case 0xBF000000: // -0.5f
788 *sel = V_SQ_ALU_SRC_0_5;
789 *neg ^= 1;
790 break;
791 default:
792 *sel = V_SQ_ALU_SRC_LITERAL;
793 break;
794 }
795 }
796
797 /* compute how many literal are needed */
798 static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
799 uint32_t literal[4], unsigned *nliteral)
800 {
801 unsigned num_src = r600_bc_get_num_operands(bc, alu);
802 unsigned i, j;
803
804 for (i = 0; i < num_src; ++i) {
805 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
806 uint32_t value = alu->src[i].value[alu->src[i].chan];
807 unsigned found = 0;
808 for (j = 0; j < *nliteral; ++j) {
809 if (literal[j] == value) {
810 found = 1;
811 break;
812 }
813 }
814 if (!found) {
815 if (*nliteral >= 4)
816 return -EINVAL;
817 literal[(*nliteral)++] = value;
818 }
819 }
820 }
821 return 0;
822 }
823
824 static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
825 struct r600_bc_alu *alu,
826 uint32_t literal[4], unsigned nliteral)
827 {
828 unsigned num_src = r600_bc_get_num_operands(bc, alu);
829 unsigned i, j;
830
831 for (i = 0; i < num_src; ++i) {
832 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
833 uint32_t value = alu->src[i].value[alu->src[i].chan];
834 for (j = 0; j < nliteral; ++j) {
835 if (literal[j] == value) {
836 alu->src[i].chan = j;
837 break;
838 }
839 }
840 }
841 }
842 }
843
844 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
845 struct r600_bc_alu *alu_prev)
846 {
847 struct r600_bc_alu *prev[5];
848 struct r600_bc_alu *result[5] = { NULL };
849
850 uint32_t literal[4], prev_literal[4];
851 unsigned nliteral = 0, prev_nliteral = 0;
852
853 int i, j, r, src, num_src;
854 int num_once_inst = 0;
855
856 r = assign_alu_units(bc, alu_prev, prev);
857 if (r)
858 return r;
859
860 for (i = 0; i < 5; ++i) {
861 struct r600_bc_alu *alu;
862
863 /* check number of literals */
864 if (prev[i]) {
865 if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
866 return 0;
867 if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
868 return 0;
869 }
870 if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
871 return 0;
872
873 // let's check used slots
874 if (prev[i] && !slots[i]) {
875 result[i] = prev[i];
876 num_once_inst += is_alu_once_inst(bc, prev[i]);
877 continue;
878 } else if (prev[i] && slots[i]) {
879 if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
880 // trans unit is still free try to use it
881 if (is_alu_any_unit_inst(bc, slots[i])) {
882 result[i] = prev[i];
883 result[4] = slots[i];
884 } else if (is_alu_any_unit_inst(bc, prev[i])) {
885 result[i] = slots[i];
886 result[4] = prev[i];
887 } else
888 return 0;
889 } else
890 return 0;
891 } else if(!slots[i]) {
892 continue;
893 } else
894 result[i] = slots[i];
895
896 // let's check source gprs
897 alu = slots[i];
898 num_once_inst += is_alu_once_inst(bc, alu);
899
900 num_src = r600_bc_get_num_operands(bc, alu);
901 for (src = 0; src < num_src; ++src) {
902 // constants doesn't matter
903 if (!is_gpr(alu->src[src].sel))
904 continue;
905
906 for (j = 0; j < 5; ++j) {
907 if (!prev[j] || !prev[j]->dst.write)
908 continue;
909
910 // if it's relative then we can't determin which gpr is really used
911 if (prev[j]->dst.chan == alu->src[src].chan &&
912 (prev[j]->dst.sel == alu->src[src].sel ||
913 prev[j]->dst.rel || alu->src[src].rel))
914 return 0;
915 }
916 }
917 }
918
919 /* more than one PRED_ or KILL_ ? */
920 if (num_once_inst > 1)
921 return 0;
922
923 /* check if the result can still be swizzlet */
924 r = check_and_set_bank_swizzle(bc, result);
925 if (r)
926 return 0;
927
928 /* looks like everything worked out right, apply the changes */
929
930 /* undo adding previus literals */
931 bc->cf_last->ndw -= align(prev_nliteral, 2);
932
933 /* sort instructions */
934 for (i = 0; i < 5; ++i) {
935 slots[i] = result[i];
936 if (result[i]) {
937 LIST_DEL(&result[i]->list);
938 result[i]->last = 0;
939 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
940 }
941 }
942
943 /* determine new last instruction */
944 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
945
946 /* determine new first instruction */
947 for (i = 0; i < 5; ++i) {
948 if (result[i]) {
949 bc->cf_last->curr_bs_head = result[i];
950 break;
951 }
952 }
953
954 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
955 bc->cf_last->prev2_bs_head = NULL;
956
957 return 0;
958 }
959
960 /* This code handles kcache lines as single blocks of 32 constants. We could
961 * probably do slightly better by recognizing that we actually have two
962 * consecutive lines of 16 constants, but the resulting code would also be
963 * somewhat more complicated. */
964 static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
965 {
966 struct r600_bc_kcache *kcache = bc->cf_last->kcache;
967 unsigned int required_lines;
968 unsigned int free_lines = 0;
969 unsigned int cache_line[3];
970 unsigned int count = 0;
971 unsigned int i, j;
972 int r;
973
974 /* Collect required cache lines. */
975 for (i = 0; i < 3; ++i) {
976 bool found = false;
977 unsigned int line;
978
979 if (alu->src[i].sel < 512)
980 continue;
981
982 line = ((alu->src[i].sel - 512) / 32) * 2;
983
984 for (j = 0; j < count; ++j) {
985 if (cache_line[j] == line) {
986 found = true;
987 break;
988 }
989 }
990
991 if (!found)
992 cache_line[count++] = line;
993 }
994
995 /* This should never actually happen. */
996 if (count >= 3) return -ENOMEM;
997
998 for (i = 0; i < 2; ++i) {
999 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1000 ++free_lines;
1001 }
1002 }
1003
1004 /* Filter lines pulled in by previous intructions. Note that this is
1005 * only for the required_lines count, we can't remove these from the
1006 * cache_line array since we may have to start a new ALU clause. */
1007 for (i = 0, required_lines = count; i < count; ++i) {
1008 for (j = 0; j < 2; ++j) {
1009 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1010 kcache[j].addr == cache_line[i]) {
1011 --required_lines;
1012 break;
1013 }
1014 }
1015 }
1016
1017 /* Start a new ALU clause if needed. */
1018 if (required_lines > free_lines) {
1019 if ((r = r600_bc_add_cf(bc))) {
1020 return r;
1021 }
1022 bc->cf_last->inst = (type << 3);
1023 kcache = bc->cf_last->kcache;
1024 }
1025
1026 /* Setup the kcache lines. */
1027 for (i = 0; i < count; ++i) {
1028 bool found = false;
1029
1030 for (j = 0; j < 2; ++j) {
1031 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1032 kcache[j].addr == cache_line[i]) {
1033 found = true;
1034 break;
1035 }
1036 }
1037
1038 if (found) continue;
1039
1040 for (j = 0; j < 2; ++j) {
1041 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1042 kcache[j].bank = 0;
1043 kcache[j].addr = cache_line[i];
1044 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1045 break;
1046 }
1047 }
1048 }
1049
1050 /* Alter the src operands to refer to the kcache. */
1051 for (i = 0; i < 3; ++i) {
1052 static const unsigned int base[] = {128, 160, 256, 288};
1053 unsigned int line;
1054
1055 if (alu->src[i].sel < 512)
1056 continue;
1057
1058 alu->src[i].sel -= 512;
1059 line = (alu->src[i].sel / 32) * 2;
1060
1061 for (j = 0; j < 2; ++j) {
1062 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1063 kcache[j].addr == line) {
1064 alu->src[i].sel &= 0x1f;
1065 alu->src[i].sel += base[j];
1066 break;
1067 }
1068 }
1069 }
1070
1071 return 0;
1072 }
1073
1074 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
1075 {
1076 struct r600_bc_alu *nalu = r600_bc_alu();
1077 struct r600_bc_alu *lalu;
1078 int i, r;
1079
1080 if (nalu == NULL)
1081 return -ENOMEM;
1082 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
1083
1084 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1085 /* check if we could add it anyway */
1086 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1087 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1088 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1089 if (lalu->predicate) {
1090 bc->force_add_cf = 1;
1091 break;
1092 }
1093 }
1094 } else
1095 bc->force_add_cf = 1;
1096 }
1097
1098 /* cf can contains only alu or only vtx or only tex */
1099 if (bc->cf_last == NULL || bc->force_add_cf) {
1100 r = r600_bc_add_cf(bc);
1101 if (r) {
1102 free(nalu);
1103 return r;
1104 }
1105 }
1106 bc->cf_last->inst = (type << 3);
1107
1108 /* Setup the kcache for this ALU instruction. This will start a new
1109 * ALU clause if needed. */
1110 if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
1111 free(nalu);
1112 return r;
1113 }
1114
1115 if (!bc->cf_last->curr_bs_head) {
1116 bc->cf_last->curr_bs_head = nalu;
1117 }
1118 /* number of gpr == the last gpr used in any alu */
1119 for (i = 0; i < 3; i++) {
1120 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1121 bc->ngpr = nalu->src[i].sel + 1;
1122 }
1123 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1124 r600_bc_special_constants(
1125 nalu->src[i].value[nalu->src[i].chan],
1126 &nalu->src[i].sel, &nalu->src[i].neg);
1127 }
1128 if (nalu->dst.sel >= bc->ngpr) {
1129 bc->ngpr = nalu->dst.sel + 1;
1130 }
1131 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1132 /* each alu use 2 dwords */
1133 bc->cf_last->ndw += 2;
1134 bc->ndw += 2;
1135
1136 /* process cur ALU instructions for bank swizzle */
1137 if (nalu->last) {
1138 uint32_t literal[4];
1139 unsigned nliteral;
1140 struct r600_bc_alu *slots[5];
1141 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1142 if (r)
1143 return r;
1144
1145 if (bc->cf_last->prev_bs_head) {
1146 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1147 if (r)
1148 return r;
1149 }
1150
1151 if (bc->cf_last->prev_bs_head) {
1152 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1153 if (r)
1154 return r;
1155 }
1156
1157 r = check_and_set_bank_swizzle(bc, slots);
1158 if (r)
1159 return r;
1160
1161 for (i = 0, nliteral = 0; i < 5; i++) {
1162 if (slots[i]) {
1163 r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
1164 if (r)
1165 return r;
1166 }
1167 }
1168 bc->cf_last->ndw += align(nliteral, 2);
1169
1170 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1171 * worst case */
1172 if ((bc->cf_last->ndw >> 1) >= 120) {
1173 bc->force_add_cf = 1;
1174 }
1175
1176 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1177 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1178 bc->cf_last->curr_bs_head = NULL;
1179 }
1180 return 0;
1181 }
1182
1183 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
1184 {
1185 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1186 }
1187
1188 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
1189 {
1190 struct r600_bc_vtx *nvtx = r600_bc_vtx();
1191 int r;
1192
1193 if (nvtx == NULL)
1194 return -ENOMEM;
1195 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
1196
1197 /* cf can contains only alu or only vtx or only tex */
1198 if (bc->cf_last == NULL ||
1199 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1200 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
1201 bc->force_add_cf) {
1202 r = r600_bc_add_cf(bc);
1203 if (r) {
1204 free(nvtx);
1205 return r;
1206 }
1207 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1208 }
1209 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1210 /* each fetch use 4 dwords */
1211 bc->cf_last->ndw += 4;
1212 bc->ndw += 4;
1213 if ((bc->cf_last->ndw / 4) > 7)
1214 bc->force_add_cf = 1;
1215 return 0;
1216 }
1217
1218 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
1219 {
1220 struct r600_bc_tex *ntex = r600_bc_tex();
1221 int r;
1222
1223 if (ntex == NULL)
1224 return -ENOMEM;
1225 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
1226
1227 /* cf can contains only alu or only vtx or only tex */
1228 if (bc->cf_last == NULL ||
1229 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1230 bc->force_add_cf) {
1231 r = r600_bc_add_cf(bc);
1232 if (r) {
1233 free(ntex);
1234 return r;
1235 }
1236 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1237 }
1238 if (ntex->src_gpr >= bc->ngpr) {
1239 bc->ngpr = ntex->src_gpr + 1;
1240 }
1241 if (ntex->dst_gpr >= bc->ngpr) {
1242 bc->ngpr = ntex->dst_gpr + 1;
1243 }
1244 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1245 /* each texture fetch use 4 dwords */
1246 bc->cf_last->ndw += 4;
1247 bc->ndw += 4;
1248 if ((bc->cf_last->ndw / 4) > 7)
1249 bc->force_add_cf = 1;
1250 return 0;
1251 }
1252
1253 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
1254 {
1255 int r;
1256 r = r600_bc_add_cf(bc);
1257 if (r)
1258 return r;
1259
1260 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1261 bc->cf_last->inst = inst;
1262 return 0;
1263 }
1264
1265 /* common to all 3 families */
1266 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
1267 {
1268 unsigned fetch_resource_start = 0;
1269
1270 /* check if we are fetch shader */
1271 /* fetch shader can also access vertex resource,
1272 * first fetch shader resource is at 160
1273 */
1274 if (bc->type == -1) {
1275 switch (bc->chiprev) {
1276 /* r600 */
1277 case CHIPREV_R600:
1278 /* r700 */
1279 case CHIPREV_R700:
1280 fetch_resource_start = 160;
1281 break;
1282 /* evergreen */
1283 case CHIPREV_EVERGREEN:
1284 fetch_resource_start = 0;
1285 break;
1286 default:
1287 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
1288 __FILE__, __func__, __LINE__, bc->chiprev);
1289 break;
1290 }
1291 }
1292 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
1293 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1294 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
1295 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1296 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1297 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1298 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1299 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1300 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1301 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1302 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1303 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1304 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1305 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1306 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
1307 bc->bytecode[id++] = 0;
1308 return 0;
1309 }
1310
1311 /* common to all 3 families */
1312 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
1313 {
1314 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1315 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1316 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1317 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1318 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1319 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1320 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1321 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1322 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1323 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1324 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1325 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1326 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1327 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1328 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1329 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1330 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1331 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1332 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1333 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1334 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1335 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1336 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1337 bc->bytecode[id++] = 0;
1338 return 0;
1339 }
1340
1341 /* r600 only, r700/eg bits in r700_asm.c */
1342 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1343 {
1344 /* don't replace gpr by pv or ps for destination register */
1345 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1346 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1347 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1348 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1349 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1350 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1351 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1352 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1353 S_SQ_ALU_WORD0_LAST(alu->last);
1354
1355 if (alu->is_op3) {
1356 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1357 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1358 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1359 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1360 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1361 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1362 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1363 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1364 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1365 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1366 } else {
1367 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1368 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1369 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1370 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1371 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1372 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1373 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1374 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1375 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1376 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1377 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1378 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1379 }
1380 return 0;
1381 }
1382
1383 /* common for r600/r700 - eg in eg_asm.c */
1384 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1385 {
1386 unsigned id = cf->id;
1387
1388 switch (cf->inst) {
1389 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1390 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1391 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1392 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1393 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1394 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1395 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1396 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1397
1398 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1399 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1400 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1401 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1402 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1403 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
1404 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1405 break;
1406 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1407 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1408 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1409 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1410 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1411 S_SQ_CF_WORD1_BARRIER(1) |
1412 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1413 break;
1414 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1415 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1416 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1417 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1418 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1419 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1420 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1421 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1422 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1423 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1424 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1425 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1426 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1427 break;
1428 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1429 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1430 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1431 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1432 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1433 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1434 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1435 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1436 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1437 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1438 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1439 S_SQ_CF_WORD1_BARRIER(1) |
1440 S_SQ_CF_WORD1_COND(cf->cond) |
1441 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1442
1443 break;
1444 default:
1445 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1446 return -EINVAL;
1447 }
1448 return 0;
1449 }
1450
1451 int r600_bc_build(struct r600_bc *bc)
1452 {
1453 struct r600_bc_cf *cf;
1454 struct r600_bc_alu *alu;
1455 struct r600_bc_vtx *vtx;
1456 struct r600_bc_tex *tex;
1457 uint32_t literal[4];
1458 unsigned nliteral;
1459 unsigned addr;
1460 int i, r;
1461
1462 if (bc->callstack[0].max > 0)
1463 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1464 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1465 bc->nstack = 1;
1466 }
1467
1468 /* first path compute addr of each CF block */
1469 /* addr start after all the CF instructions */
1470 addr = bc->cf_last->id + 2;
1471 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1472 switch (cf->inst) {
1473 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1474 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1475 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1476 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1477 break;
1478 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1479 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1480 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1481 /* fetch node need to be 16 bytes aligned*/
1482 addr += 3;
1483 addr &= 0xFFFFFFFCUL;
1484 break;
1485 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1486 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1487 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1488 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1489 break;
1490 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1491 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1492 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1493 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1494 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1495 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1496 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1497 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1498 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1499 break;
1500 default:
1501 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1502 return -EINVAL;
1503 }
1504 cf->addr = addr;
1505 addr += cf->ndw;
1506 bc->ndw = cf->addr + cf->ndw;
1507 }
1508 free(bc->bytecode);
1509 bc->bytecode = calloc(1, bc->ndw * 4);
1510 if (bc->bytecode == NULL)
1511 return -ENOMEM;
1512 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1513 addr = cf->addr;
1514 if (bc->chiprev == CHIPREV_EVERGREEN)
1515 r = eg_bc_cf_build(bc, cf);
1516 else
1517 r = r600_bc_cf_build(bc, cf);
1518 if (r)
1519 return r;
1520 switch (cf->inst) {
1521 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1522 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1523 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1524 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1525 nliteral = 0;
1526 memset(literal, 0, sizeof(literal));
1527 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1528 r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1529 if (r)
1530 return r;
1531 r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
1532 switch(bc->chiprev) {
1533 case CHIPREV_R600:
1534 r = r600_bc_alu_build(bc, alu, addr);
1535 break;
1536 case CHIPREV_R700:
1537 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
1538 r = r700_bc_alu_build(bc, alu, addr);
1539 break;
1540 default:
1541 R600_ERR("unknown family %d\n", bc->family);
1542 return -EINVAL;
1543 }
1544 if (r)
1545 return r;
1546 addr += 2;
1547 if (alu->last) {
1548 for (i = 0; i < align(nliteral, 2); ++i) {
1549 bc->bytecode[addr++] = literal[i];
1550 }
1551 nliteral = 0;
1552 memset(literal, 0, sizeof(literal));
1553 }
1554 }
1555 break;
1556 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1557 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1558 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1559 r = r600_bc_vtx_build(bc, vtx, addr);
1560 if (r)
1561 return r;
1562 addr += 4;
1563 }
1564 break;
1565 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1566 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1567 r = r600_bc_tex_build(bc, tex, addr);
1568 if (r)
1569 return r;
1570 addr += 4;
1571 }
1572 break;
1573 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1574 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1575 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1576 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1577 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1578 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1579 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1580 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1581 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1582 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1583 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1584 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1585 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1586 break;
1587 default:
1588 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1589 return -EINVAL;
1590 }
1591 }
1592 return 0;
1593 }
1594
1595 void r600_bc_clear(struct r600_bc *bc)
1596 {
1597 struct r600_bc_cf *cf = NULL, *next_cf;
1598
1599 free(bc->bytecode);
1600 bc->bytecode = NULL;
1601
1602 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1603 struct r600_bc_alu *alu = NULL, *next_alu;
1604 struct r600_bc_tex *tex = NULL, *next_tex;
1605 struct r600_bc_tex *vtx = NULL, *next_vtx;
1606
1607 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1608 free(alu);
1609 }
1610
1611 LIST_INITHEAD(&cf->alu);
1612
1613 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1614 free(tex);
1615 }
1616
1617 LIST_INITHEAD(&cf->tex);
1618
1619 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1620 free(vtx);
1621 }
1622
1623 LIST_INITHEAD(&cf->vtx);
1624
1625 free(cf);
1626 }
1627
1628 LIST_INITHEAD(&cf->list);
1629 }
1630
1631 void r600_bc_dump(struct r600_bc *bc)
1632 {
1633 struct r600_bc_cf *cf = NULL;
1634 struct r600_bc_alu *alu = NULL;
1635 struct r600_bc_vtx *vtx = NULL;
1636 struct r600_bc_tex *tex = NULL;
1637
1638 unsigned i, id;
1639 uint32_t literal[4];
1640 unsigned nliteral;
1641 char chip = '6';
1642
1643 switch (bc->chiprev) {
1644 case 1:
1645 chip = '7';
1646 break;
1647 case 2:
1648 chip = 'E';
1649 break;
1650 case 0:
1651 default:
1652 chip = '6';
1653 break;
1654 }
1655 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1656 fprintf(stderr, " %c\n", chip);
1657
1658 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1659 id = cf->id;
1660
1661 switch (cf->inst) {
1662 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1663 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1664 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1665 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1666 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1667 fprintf(stderr, "ADDR:%d ", cf->addr);
1668 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1669 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1670 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1671 id++;
1672 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1673 fprintf(stderr, "INST:%d ", cf->inst);
1674 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1675 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1676 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1677 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1678 break;
1679 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1680 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1681 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1682 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1683 fprintf(stderr, "ADDR:%d\n", cf->addr);
1684 id++;
1685 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1686 fprintf(stderr, "INST:%d ", cf->inst);
1687 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1688 break;
1689 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1690 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1691 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1692 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1693 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1694 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1695 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1696 id++;
1697 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1698 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1699 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1700 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1701 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1702 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1703 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1704 fprintf(stderr, "INST:%d ", cf->output.inst);
1705 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1706 break;
1707 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1708 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1709 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1710 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1711 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1712 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1713 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1714 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1715 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1716 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1717 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1718 id++;
1719 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1720 fprintf(stderr, "INST:%d ", cf->inst);
1721 fprintf(stderr, "COND:%X ", cf->cond);
1722 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1723 break;
1724 }
1725
1726 id = cf->addr;
1727 nliteral = 0;
1728 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1729 r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1730
1731 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1732 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1733 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1734 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1735 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1736 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1737 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1738 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1739 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1740 fprintf(stderr, "LAST:%d)\n", alu->last);
1741 id++;
1742 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1743 fprintf(stderr, "INST:%d ", alu->inst);
1744 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1745 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1746 fprintf(stderr, "REL:%d ", alu->dst.rel);
1747 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1748 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1749 if (alu->is_op3) {
1750 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1751 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1752 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1753 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1754 } else {
1755 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1756 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1757 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1758 fprintf(stderr, "OMOD:%d ", alu->omod);
1759 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1760 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1761 }
1762
1763 id++;
1764 if (alu->last) {
1765 for (i = 0; i < nliteral; i++, id++) {
1766 float *f = (float*)(bc->bytecode + id);
1767 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1768 }
1769 id += nliteral & 1;
1770 nliteral = 0;
1771 }
1772 }
1773
1774 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1775 //TODO
1776 }
1777
1778 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1779 //TODO
1780 }
1781 }
1782
1783 fprintf(stderr, "--------------------------------------\n");
1784 }
1785
1786 void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1787 {
1788 struct r600_pipe_state *rstate;
1789 unsigned i = 0;
1790
1791 if (count > 8) {
1792 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1793 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1794 S_SQ_CF_WORD1_BARRIER(1) |
1795 S_SQ_CF_WORD1_COUNT(8 - 1);
1796 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1797 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1798 S_SQ_CF_WORD1_BARRIER(1) |
1799 S_SQ_CF_WORD1_COUNT(count - 8 - 1);
1800 } else {
1801 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1802 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1803 S_SQ_CF_WORD1_BARRIER(1) |
1804 S_SQ_CF_WORD1_COUNT(count - 1);
1805 }
1806 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1807 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1808 S_SQ_CF_WORD1_BARRIER(1);
1809
1810 rstate = &ve->rstate;
1811 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1812 rstate->nregs = 0;
1813 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1814 0x00000000, 0xFFFFFFFF, NULL);
1815 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1816 0x00000000, 0xFFFFFFFF, NULL);
1817 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1818 r600_bo_offset(ve->fetch_shader) >> 8,
1819 0xFFFFFFFF, ve->fetch_shader);
1820 }
1821
1822 void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1823 {
1824 struct r600_pipe_state *rstate;
1825 unsigned i = 0;
1826
1827 if (count > 8) {
1828 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1829 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1830 S_SQ_CF_WORD1_BARRIER(1) |
1831 S_SQ_CF_WORD1_COUNT(8 - 1);
1832 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1833 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1834 S_SQ_CF_WORD1_BARRIER(1) |
1835 S_SQ_CF_WORD1_COUNT((count - 8) - 1);
1836 } else {
1837 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1838 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1839 S_SQ_CF_WORD1_BARRIER(1) |
1840 S_SQ_CF_WORD1_COUNT(count - 1);
1841 }
1842 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1843 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1844 S_SQ_CF_WORD1_BARRIER(1);
1845
1846 rstate = &ve->rstate;
1847 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1848 rstate->nregs = 0;
1849 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1850 0x00000000, 0xFFFFFFFF, NULL);
1851 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1852 0x00000000, 0xFFFFFFFF, NULL);
1853 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1854 r600_bo_offset(ve->fetch_shader) >> 8,
1855 0xFFFFFFFF, ve->fetch_shader);
1856 }
1857
1858 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1859 unsigned *num_format, unsigned *format_comp)
1860 {
1861 const struct util_format_description *desc;
1862 unsigned i;
1863
1864 *format = 0;
1865 *num_format = 0;
1866 *format_comp = 0;
1867
1868 desc = util_format_description(pformat);
1869 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1870 goto out_unknown;
1871 }
1872
1873 /* Find the first non-VOID channel. */
1874 for (i = 0; i < 4; i++) {
1875 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1876 break;
1877 }
1878 }
1879
1880 switch (desc->channel[i].type) {
1881 /* Half-floats, floats, doubles */
1882 case UTIL_FORMAT_TYPE_FLOAT:
1883 switch (desc->channel[i].size) {
1884 case 16:
1885 switch (desc->nr_channels) {
1886 case 1:
1887 *format = FMT_16_FLOAT;
1888 break;
1889 case 2:
1890 *format = FMT_16_16_FLOAT;
1891 break;
1892 case 3:
1893 *format = FMT_16_16_16_FLOAT;
1894 break;
1895 case 4:
1896 *format = FMT_16_16_16_16_FLOAT;
1897 break;
1898 }
1899 break;
1900 case 32:
1901 switch (desc->nr_channels) {
1902 case 1:
1903 *format = FMT_32_FLOAT;
1904 break;
1905 case 2:
1906 *format = FMT_32_32_FLOAT;
1907 break;
1908 case 3:
1909 *format = FMT_32_32_32_FLOAT;
1910 break;
1911 case 4:
1912 *format = FMT_32_32_32_32_FLOAT;
1913 break;
1914 }
1915 break;
1916 default:
1917 goto out_unknown;
1918 }
1919 break;
1920 /* Unsigned ints */
1921 case UTIL_FORMAT_TYPE_UNSIGNED:
1922 /* Signed ints */
1923 case UTIL_FORMAT_TYPE_SIGNED:
1924 switch (desc->channel[i].size) {
1925 case 8:
1926 switch (desc->nr_channels) {
1927 case 1:
1928 *format = FMT_8;
1929 break;
1930 case 2:
1931 *format = FMT_8_8;
1932 break;
1933 case 3:
1934 // *format = FMT_8_8_8; /* fails piglit draw-vertices test */
1935 // break;
1936 case 4:
1937 *format = FMT_8_8_8_8;
1938 break;
1939 }
1940 break;
1941 case 16:
1942 switch (desc->nr_channels) {
1943 case 1:
1944 *format = FMT_16;
1945 break;
1946 case 2:
1947 *format = FMT_16_16;
1948 break;
1949 case 3:
1950 // *format = FMT_16_16_16; /* fails piglit draw-vertices test */
1951 // break;
1952 case 4:
1953 *format = FMT_16_16_16_16;
1954 break;
1955 }
1956 break;
1957 case 32:
1958 switch (desc->nr_channels) {
1959 case 1:
1960 *format = FMT_32;
1961 break;
1962 case 2:
1963 *format = FMT_32_32;
1964 break;
1965 case 3:
1966 *format = FMT_32_32_32;
1967 break;
1968 case 4:
1969 *format = FMT_32_32_32_32;
1970 break;
1971 }
1972 break;
1973 default:
1974 goto out_unknown;
1975 }
1976 break;
1977 default:
1978 goto out_unknown;
1979 }
1980
1981 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1982 *format_comp = 1;
1983 }
1984 if (desc->channel[i].normalized) {
1985 *num_format = 0;
1986 } else {
1987 *num_format = 2;
1988 }
1989 return;
1990 out_unknown:
1991 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
1992 }
1993
1994 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
1995 {
1996 unsigned ndw, i;
1997 u32 *bytecode;
1998 unsigned fetch_resource_start = 0, format, num_format, format_comp;
1999 struct pipe_vertex_element *elements = ve->elements;
2000 const struct util_format_description *desc;
2001
2002 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
2003 ndw = 8 + ve->count * 4;
2004 ve->fs_size = ndw * 4;
2005
2006 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
2007 ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
2008 if (ve->fetch_shader == NULL) {
2009 return -ENOMEM;
2010 }
2011
2012 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
2013 if (bytecode == NULL) {
2014 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2015 return -ENOMEM;
2016 }
2017
2018 if (rctx->family >= CHIP_CEDAR) {
2019 eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2020 } else {
2021 r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2022 fetch_resource_start = 160;
2023 }
2024
2025 /* vertex elements offset need special handling, if offset is bigger
2026 * than what we can put in fetch instruction then we need to alterate
2027 * the vertex resource offset. In such case in order to simplify code
2028 * we will bound one resource per elements. It's a worst case scenario.
2029 */
2030 for (i = 0; i < ve->count; i++) {
2031 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2032 if (ve->vbuffer_offset[i]) {
2033 ve->vbuffer_need_offset = 1;
2034 }
2035 }
2036
2037 for (i = 0; i < ve->count; i++) {
2038 unsigned vbuffer_index;
2039 r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
2040 desc = util_format_description(ve->hw_format[i]);
2041 if (desc == NULL) {
2042 R600_ERR("unknown format %d\n", ve->hw_format[i]);
2043 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2044 return -EINVAL;
2045 }
2046
2047 /* see above for vbuffer_need_offset explanation */
2048 vbuffer_index = elements[i].vertex_buffer_index;
2049 if (ve->vbuffer_need_offset) {
2050 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
2051 } else {
2052 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
2053 }
2054 bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
2055 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
2056 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
2057 bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
2058 S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
2059 S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
2060 S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
2061 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
2062 S_SQ_VTX_WORD1_DATA_FORMAT(format) |
2063 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
2064 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
2065 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
2066 S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
2067 bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
2068 S_SQ_VTX_WORD2_MEGA_FETCH(1);
2069 bytecode[8 + i * 4 + 3] = 0;
2070 }
2071 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
2072 return 0;
2073 }