2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
36 #include "sb/sb_public.h"
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
41 static inline bool alu_writes(struct r600_bytecode_alu
*alu
)
43 return alu
->dst
.write
|| alu
->is_op3
;
46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu
*alu
)
48 return r600_isa_alu(alu
->op
)->src_count
;
51 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
53 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
57 LIST_INITHEAD(&cf
->list
);
58 LIST_INITHEAD(&cf
->alu
);
59 LIST_INITHEAD(&cf
->vtx
);
60 LIST_INITHEAD(&cf
->tex
);
61 LIST_INITHEAD(&cf
->gds
);
65 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
67 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
71 LIST_INITHEAD(&alu
->list
);
75 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
77 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
81 LIST_INITHEAD(&vtx
->list
);
85 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
87 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
91 LIST_INITHEAD(&tex
->list
);
95 static struct r600_bytecode_gds
*r600_bytecode_gds(void)
97 struct r600_bytecode_gds
*gds
= CALLOC_STRUCT(r600_bytecode_gds
);
101 LIST_INITHEAD(&gds
->list
);
105 static unsigned stack_entry_size(enum radeon_family chip
) {
107 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
108 * Aruba/Sumo/Sumo2/redwood/juniper
109 * 32: R630/R730/R710/Palm/Cedar
113 * Wavefront Size 16 32 48 64
114 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
115 * Columns per Row (R9xx+) 8 4 4 4 */
118 /* FIXME: are some chips missing here? */
119 /* wavefront size 16 */
124 /* wavefront size 32 */
133 /* wavefront size 64 */
139 void r600_bytecode_init(struct r600_bytecode
*bc
,
140 enum chip_class chip_class
,
141 enum radeon_family family
,
142 bool has_compressed_msaa_texturing
)
144 static unsigned next_shader_id
= 0;
146 bc
->debug_id
= ++next_shader_id
;
148 if ((chip_class
== R600
) &&
149 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
150 bc
->ar_handling
= AR_HANDLE_RV6XX
;
151 bc
->r6xx_nop_after_rel_dst
= 1;
153 bc
->ar_handling
= AR_HANDLE_NORMAL
;
154 bc
->r6xx_nop_after_rel_dst
= 0;
157 LIST_INITHEAD(&bc
->cf
);
158 bc
->chip_class
= chip_class
;
160 bc
->has_compressed_msaa_texturing
= has_compressed_msaa_texturing
;
161 bc
->stack
.entry_size
= stack_entry_size(family
);
164 int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
166 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
170 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
172 cf
->id
= bc
->cf_last
->id
+ 2;
173 if (bc
->cf_last
->eg_alu_extended
) {
174 /* take into account extended alu size */
182 bc
->force_add_cf
= 0;
187 int r600_bytecode_add_output(struct r600_bytecode
*bc
,
188 const struct r600_bytecode_output
*output
)
192 if (output
->gpr
>= bc
->ngpr
)
193 bc
->ngpr
= output
->gpr
+ 1;
195 if (bc
->cf_last
&& (bc
->cf_last
->op
== output
->op
||
196 (bc
->cf_last
->op
== CF_OP_EXPORT
&&
197 output
->op
== CF_OP_EXPORT_DONE
)) &&
198 output
->type
== bc
->cf_last
->output
.type
&&
199 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
200 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
201 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
202 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
203 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
204 output
->comp_mask
== bc
->cf_last
->output
.comp_mask
&&
205 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
207 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
208 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
210 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
211 bc
->cf_last
->output
.gpr
= output
->gpr
;
212 bc
->cf_last
->output
.array_base
= output
->array_base
;
213 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
216 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
217 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
219 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
220 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
225 r
= r600_bytecode_add_cf(bc
);
228 bc
->cf_last
->op
= output
->op
;
229 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
230 bc
->cf_last
->barrier
= 1;
234 /* alu instructions that can ony exits once per group */
235 static int is_alu_once_inst(struct r600_bytecode_alu
*alu
)
237 return r600_isa_alu(alu
->op
)->flags
& (AF_KILL
| AF_PRED
) || alu
->is_lds_idx_op
|| alu
->op
== ALU_OP0_GROUP_BARRIER
;
240 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
242 return (r600_isa_alu(alu
->op
)->flags
& AF_REPL
) &&
243 (r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
) == AF_4V
);
246 static int is_alu_mova_inst(struct r600_bytecode_alu
*alu
)
248 return r600_isa_alu(alu
->op
)->flags
& AF_MOVA
;
251 static int alu_uses_rel(struct r600_bytecode_alu
*alu
)
253 unsigned num_src
= r600_bytecode_get_num_operands(alu
);
260 for (src
= 0; src
< num_src
; ++src
) {
261 if (alu
->src
[src
].rel
) {
268 static int is_lds_read(int sel
)
270 return sel
== EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
|| sel
== EG_V_SQ_ALU_SRC_LDS_OQ_B_POP
;
273 static int alu_uses_lds(struct r600_bytecode_alu
*alu
)
275 unsigned num_src
= r600_bytecode_get_num_operands(alu
);
278 for (src
= 0; src
< num_src
; ++src
) {
279 if (is_lds_read(alu
->src
[src
].sel
)) {
286 static int is_alu_64bit_inst(struct r600_bytecode_alu
*alu
)
288 const struct alu_op_info
*op
= r600_isa_alu(alu
->op
);
289 return (op
->flags
& AF_64
);
292 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
294 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
295 return !(slots
& AF_S
);
298 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
300 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
301 return !(slots
& AF_V
);
304 /* alu instructions that can execute on any unit */
305 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
307 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
308 return slots
== AF_VS
;
311 static int is_nop_inst(struct r600_bytecode_alu
*alu
)
313 return alu
->op
== ALU_OP0_NOP
;
316 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
317 struct r600_bytecode_alu
*assignment
[5])
319 struct r600_bytecode_alu
*alu
;
320 unsigned i
, chan
, trans
;
321 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
323 for (i
= 0; i
< max_slots
; i
++)
324 assignment
[i
] = NULL
;
326 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
327 chan
= alu
->dst
.chan
;
330 else if (is_alu_trans_unit_inst(bc
, alu
))
332 else if (is_alu_vec_unit_inst(bc
, alu
))
334 else if (assignment
[chan
])
335 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
341 assert(0); /* ALU.Trans has already been allocated. */
346 if (assignment
[chan
]) {
347 assert(0); /* ALU.chan has already been allocated. */
350 assignment
[chan
] = alu
;
359 struct alu_bank_swizzle
{
360 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
361 int hw_cfile_addr
[4];
362 int hw_cfile_elem
[4];
365 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
366 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
367 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
368 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
369 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
370 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
371 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
374 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
375 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
376 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
377 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
378 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
381 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
383 int i
, cycle
, component
;
385 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
386 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
387 bs
->hw_gpr
[cycle
][component
] = -1;
388 for (i
= 0; i
< 4; i
++)
389 bs
->hw_cfile_addr
[i
] = -1;
390 for (i
= 0; i
< 4; i
++)
391 bs
->hw_cfile_elem
[i
] = -1;
394 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
396 if (bs
->hw_gpr
[cycle
][chan
] == -1)
397 bs
->hw_gpr
[cycle
][chan
] = sel
;
398 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
399 /* Another scalar operation has already used the GPR read port for the channel. */
405 static int reserve_cfile(const struct r600_bytecode
*bc
,
406 struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
408 int res
, num_res
= 4;
409 if (bc
->chip_class
>= R700
) {
413 for (res
= 0; res
< num_res
; ++res
) {
414 if (bs
->hw_cfile_addr
[res
] == -1) {
415 bs
->hw_cfile_addr
[res
] = sel
;
416 bs
->hw_cfile_elem
[res
] = chan
;
418 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
419 bs
->hw_cfile_elem
[res
] == chan
)
420 return 0; /* Read for this scalar element already reserved, nothing to do here. */
422 /* All cfile read ports are used, cannot reference vector element. */
426 static int is_gpr(unsigned sel
)
431 /* CB constants start at 512, and get translated to a kcache index when ALU
432 * clauses are constructed. Note that we handle kcache constants the same way
433 * as (the now gone) cfile constants, is that really required? */
434 static int is_cfile(unsigned sel
)
436 return (sel
> 255 && sel
< 512) ||
437 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
438 (sel
> 127 && sel
< 192); /* Kcache after translation. */
441 static int is_const(int sel
)
443 return is_cfile(sel
) ||
444 (sel
>= V_SQ_ALU_SRC_0
&&
445 sel
<= V_SQ_ALU_SRC_LITERAL
);
448 static int check_vector(const struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
,
449 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
451 int r
, src
, num_src
, sel
, elem
, cycle
;
453 num_src
= r600_bytecode_get_num_operands(alu
);
454 for (src
= 0; src
< num_src
; src
++) {
455 sel
= alu
->src
[src
].sel
;
456 elem
= alu
->src
[src
].chan
;
458 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
459 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
460 /* Nothing to do; special-case optimization,
461 * second source uses first source’s reservation. */
464 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
468 } else if (is_cfile(sel
)) {
469 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
473 /* No restrictions on PV, PS, literal or special constants. */
478 static int check_scalar(const struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
,
479 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
481 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
483 num_src
= r600_bytecode_get_num_operands(alu
);
484 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
485 sel
= alu
->src
[src
].sel
;
486 elem
= alu
->src
[src
].chan
;
487 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
488 if (const_count
>= 2)
489 /* More than two references to a constant in
490 * transcendental operation. */
496 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
501 for (src
= 0; src
< num_src
; ++src
) {
502 sel
= alu
->src
[src
].sel
;
503 elem
= alu
->src
[src
].chan
;
505 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
506 if (cycle
< const_count
)
507 /* Cycle for GPR load conflicts with
508 * constant load in transcendental operation. */
510 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
514 /* PV PS restrictions */
515 if (const_count
&& (sel
== 254 || sel
== 255)) {
516 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
517 if (cycle
< const_count
)
524 static int check_and_set_bank_swizzle(const struct r600_bytecode
*bc
,
525 struct r600_bytecode_alu
*slots
[5])
527 struct alu_bank_swizzle bs
;
529 int i
, r
= 0, forced
= 1;
530 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
531 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
533 for (i
= 0; i
< max_slots
; i
++) {
535 if (slots
[i
]->bank_swizzle_force
) {
536 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
542 if (i
< 4 && slots
[i
])
548 /* Just check every possible combination of bank swizzle.
549 * Not very efficent, but works on the first try in most of the cases. */
550 for (i
= 0; i
< 4; i
++)
551 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
552 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
554 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
556 bank_swizzle
[4] = SQ_ALU_SCL_210
;
557 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
559 init_bank_swizzle(&bs
);
560 if (scalar_only
== false) {
561 for (i
= 0; i
< 4; i
++) {
563 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
571 if (!r
&& max_slots
== 5 && slots
[4]) {
572 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
575 for (i
= 0; i
< max_slots
; i
++) {
577 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
585 for (i
= 0; i
< max_slots
; i
++) {
586 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
588 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
590 else if (i
< max_slots
- 1)
591 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
599 /* Couldn't find a working swizzle. */
603 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
604 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
606 struct r600_bytecode_alu
*prev
[5];
608 int i
, j
, r
, src
, num_src
;
609 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
611 r
= assign_alu_units(bc
, alu_prev
, prev
);
615 for (i
= 0; i
< max_slots
; ++i
) {
616 if (prev
[i
] && alu_writes(prev
[i
]) && !prev
[i
]->dst
.rel
) {
618 if (is_alu_64bit_inst(prev
[i
])) {
623 gpr
[i
] = prev
[i
]->dst
.sel
;
624 /* cube writes more than PV.X */
625 if (is_alu_reduction_inst(bc
, prev
[i
]))
628 chan
[i
] = prev
[i
]->dst
.chan
;
633 for (i
= 0; i
< max_slots
; ++i
) {
634 struct r600_bytecode_alu
*alu
= slots
[i
];
638 if (is_alu_64bit_inst(alu
))
640 num_src
= r600_bytecode_get_num_operands(alu
);
641 for (src
= 0; src
< num_src
; ++src
) {
642 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
645 if (bc
->chip_class
< CAYMAN
) {
646 if (alu
->src
[src
].sel
== gpr
[4] &&
647 alu
->src
[src
].chan
== chan
[4] &&
648 alu_prev
->pred_sel
== alu
->pred_sel
) {
649 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
650 alu
->src
[src
].chan
= 0;
655 for (j
= 0; j
< 4; ++j
) {
656 if (alu
->src
[src
].sel
== gpr
[j
] &&
657 alu
->src
[src
].chan
== j
&&
658 alu_prev
->pred_sel
== alu
->pred_sel
) {
659 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
660 alu
->src
[src
].chan
= chan
[j
];
670 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
, unsigned abs
)
674 *sel
= V_SQ_ALU_SRC_0
;
677 *sel
= V_SQ_ALU_SRC_1_INT
;
680 *sel
= V_SQ_ALU_SRC_M_1_INT
;
682 case 0x3F800000: /* 1.0f */
683 *sel
= V_SQ_ALU_SRC_1
;
685 case 0x3F000000: /* 0.5f */
686 *sel
= V_SQ_ALU_SRC_0_5
;
688 case 0xBF800000: /* -1.0f */
689 *sel
= V_SQ_ALU_SRC_1
;
692 case 0xBF000000: /* -0.5f */
693 *sel
= V_SQ_ALU_SRC_0_5
;
697 *sel
= V_SQ_ALU_SRC_LITERAL
;
702 /* compute how many literal are needed */
703 static int r600_bytecode_alu_nliterals(struct r600_bytecode_alu
*alu
,
704 uint32_t literal
[4], unsigned *nliteral
)
706 unsigned num_src
= r600_bytecode_get_num_operands(alu
);
709 for (i
= 0; i
< num_src
; ++i
) {
710 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
711 uint32_t value
= alu
->src
[i
].value
;
713 for (j
= 0; j
< *nliteral
; ++j
) {
714 if (literal
[j
] == value
) {
722 literal
[(*nliteral
)++] = value
;
729 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu
*alu
,
730 uint32_t literal
[4], unsigned nliteral
)
732 unsigned num_src
= r600_bytecode_get_num_operands(alu
);
735 for (i
= 0; i
< num_src
; ++i
) {
736 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
737 uint32_t value
= alu
->src
[i
].value
;
738 for (j
= 0; j
< nliteral
; ++j
) {
739 if (literal
[j
] == value
) {
740 alu
->src
[i
].chan
= j
;
748 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
749 struct r600_bytecode_alu
*alu_prev
)
751 struct r600_bytecode_alu
*prev
[5];
752 struct r600_bytecode_alu
*result
[5] = { NULL
};
754 uint32_t literal
[4], prev_literal
[4];
755 unsigned nliteral
= 0, prev_nliteral
= 0;
757 int i
, j
, r
, src
, num_src
;
758 int num_once_inst
= 0;
759 int have_mova
= 0, have_rel
= 0;
760 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
762 r
= assign_alu_units(bc
, alu_prev
, prev
);
766 for (i
= 0; i
< max_slots
; ++i
) {
768 if (prev
[i
]->pred_sel
)
770 if (is_alu_once_inst(prev
[i
]))
774 if (slots
[i
]->pred_sel
)
776 if (is_alu_once_inst(slots
[i
]))
781 for (i
= 0; i
< max_slots
; ++i
) {
782 struct r600_bytecode_alu
*alu
;
784 if (num_once_inst
> 0)
787 /* check number of literals */
789 if (r600_bytecode_alu_nliterals(prev
[i
], literal
, &nliteral
))
791 if (r600_bytecode_alu_nliterals(prev
[i
], prev_literal
, &prev_nliteral
))
793 if (is_alu_mova_inst(prev
[i
])) {
799 if (alu_uses_rel(prev
[i
])) {
805 if (alu_uses_lds(prev
[i
]))
808 num_once_inst
+= is_alu_once_inst(prev
[i
]);
810 if (slots
[i
] && r600_bytecode_alu_nliterals(slots
[i
], literal
, &nliteral
))
813 /* Let's check used slots. */
814 if (prev
[i
] && !slots
[i
]) {
817 } else if (prev
[i
] && slots
[i
]) {
818 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
819 /* Trans unit is still free try to use it. */
820 if (is_alu_any_unit_inst(bc
, slots
[i
]) && !alu_uses_lds(slots
[i
])) {
822 result
[4] = slots
[i
];
823 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
824 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
825 alu_writes(slots
[i
]) &&
829 result
[i
] = slots
[i
];
835 } else if(!slots
[i
]) {
838 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
839 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
840 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
841 alu_writes(slots
[i
]) &&
845 result
[i
] = slots
[i
];
849 num_once_inst
+= is_alu_once_inst(alu
);
851 /* don't reschedule NOPs */
852 if (is_nop_inst(alu
))
855 if (is_alu_mova_inst(alu
)) {
862 if (alu_uses_rel(alu
)) {
869 if (alu
->op
== ALU_OP0_SET_CF_IDX0
||
870 alu
->op
== ALU_OP0_SET_CF_IDX1
)
871 return 0; /* data hazard with MOVA */
873 /* Let's check source gprs */
874 num_src
= r600_bytecode_get_num_operands(alu
);
875 for (src
= 0; src
< num_src
; ++src
) {
877 /* Constants don't matter. */
878 if (!is_gpr(alu
->src
[src
].sel
))
881 for (j
= 0; j
< max_slots
; ++j
) {
882 if (!prev
[j
] || !alu_writes(prev
[j
]))
885 /* If it's relative then we can't determin which gpr is really used. */
886 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
887 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
888 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
894 /* more than one PRED_ or KILL_ ? */
895 if (num_once_inst
> 1)
898 /* check if the result can still be swizzlet */
899 r
= check_and_set_bank_swizzle(bc
, result
);
903 /* looks like everything worked out right, apply the changes */
905 /* undo adding previus literals */
906 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
908 /* sort instructions */
909 for (i
= 0; i
< max_slots
; ++i
) {
910 slots
[i
] = result
[i
];
912 LIST_DEL(&result
[i
]->list
);
914 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
918 /* determine new last instruction */
919 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
921 /* determine new first instruction */
922 for (i
= 0; i
< max_slots
; ++i
) {
924 bc
->cf_last
->curr_bs_head
= result
[i
];
929 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
930 bc
->cf_last
->prev2_bs_head
= NULL
;
935 /* we'll keep kcache sets sorted by bank & addr */
936 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
937 struct r600_bytecode_kcache
*kcache
,
938 unsigned bank
, unsigned line
, unsigned index_mode
)
940 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
942 for (i
= 0; i
< kcache_banks
; i
++) {
943 if (kcache
[i
].mode
) {
946 if (kcache
[i
].bank
< bank
)
949 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
950 kcache
[i
].bank
> bank
) {
951 /* try to insert new line */
952 if (kcache
[kcache_banks
-1].mode
) {
953 /* all sets are in use */
957 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
958 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
959 kcache
[i
].bank
= bank
;
960 kcache
[i
].addr
= line
;
961 kcache
[i
].index_mode
= index_mode
;
965 d
= line
- kcache
[i
].addr
;
969 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
970 /* we are prepending the line to the current set,
971 * discarding the existing second line,
972 * so we'll have to insert line+2 after it */
975 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
976 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
979 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
983 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
987 } else { /* free kcache set - use it */
988 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
989 kcache
[i
].bank
= bank
;
990 kcache
[i
].addr
= line
;
991 kcache
[i
].index_mode
= index_mode
;
998 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
999 struct r600_bytecode_kcache
*kcache
,
1000 struct r600_bytecode_alu
*alu
)
1004 for (i
= 0; i
< 3; i
++) {
1005 unsigned bank
, line
, sel
= alu
->src
[i
].sel
, index_mode
;
1010 bank
= alu
->src
[i
].kc_bank
;
1011 assert(bank
< R600_MAX_HW_CONST_BUFFERS
);
1012 line
= (sel
-512)>>4;
1013 index_mode
= alu
->src
[i
].kc_rel
? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1015 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
, index_mode
)))
1021 static int r600_bytecode_assign_kcache_banks(
1022 struct r600_bytecode_alu
*alu
,
1023 struct r600_bytecode_kcache
* kcache
)
1027 /* Alter the src operands to refer to the kcache. */
1028 for (i
= 0; i
< 3; ++i
) {
1029 static const unsigned int base
[] = {128, 160, 256, 288};
1030 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
1038 for (j
= 0; j
< 4 && !found
; ++j
) {
1039 switch (kcache
[j
].mode
) {
1040 case V_SQ_CF_KCACHE_NOP
:
1041 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
1042 R600_ERR("unexpected kcache line mode\n");
1045 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
1046 kcache
[j
].addr
<= line
&&
1047 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1048 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1049 alu
->src
[i
].sel
+= base
[j
];
1058 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
,
1059 struct r600_bytecode_alu
*alu
,
1062 struct r600_bytecode_kcache kcache_sets
[4];
1063 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1066 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1068 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1069 /* can't alloc, need to start new clause */
1070 if ((r
= r600_bytecode_add_cf(bc
))) {
1073 bc
->cf_last
->op
= type
;
1075 /* retry with the new clause */
1076 kcache
= bc
->cf_last
->kcache
;
1077 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1078 /* can't alloc again- should never happen */
1082 /* update kcache sets */
1083 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1086 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1087 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
||
1088 kcache
[0].index_mode
|| kcache
[1].index_mode
|| kcache
[2].index_mode
|| kcache
[3].index_mode
) {
1089 if (bc
->chip_class
< EVERGREEN
)
1091 bc
->cf_last
->eg_alu_extended
= 1;
1097 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1099 struct r600_bytecode_alu alu
;
1102 for (i
= 0; i
< 4; i
++) {
1103 memset(&alu
, 0, sizeof(alu
));
1104 alu
.op
= ALU_OP0_NOP
;
1105 alu
.src
[0].chan
= i
;
1107 alu
.last
= (i
== 3);
1108 r
= r600_bytecode_add_alu(bc
, &alu
);
1115 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1116 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1118 struct r600_bytecode_alu alu
;
1124 /* hack to avoid making MOVA the last instruction in the clause */
1125 if ((bc
->cf_last
->ndw
>>1) >= 110)
1126 bc
->force_add_cf
= 1;
1128 memset(&alu
, 0, sizeof(alu
));
1129 alu
.op
= ALU_OP1_MOVA_GPR_INT
;
1130 alu
.src
[0].sel
= bc
->ar_reg
;
1131 alu
.src
[0].chan
= bc
->ar_chan
;
1133 alu
.index_mode
= INDEX_MODE_LOOP
;
1134 r
= r600_bytecode_add_alu(bc
, &alu
);
1138 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1143 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1144 static int load_ar(struct r600_bytecode
*bc
)
1146 struct r600_bytecode_alu alu
;
1149 if (bc
->ar_handling
)
1150 return load_ar_r6xx(bc
);
1155 /* hack to avoid making MOVA the last instruction in the clause */
1156 if ((bc
->cf_last
->ndw
>>1) >= 110)
1157 bc
->force_add_cf
= 1;
1159 memset(&alu
, 0, sizeof(alu
));
1160 alu
.op
= ALU_OP1_MOVA_INT
;
1161 alu
.src
[0].sel
= bc
->ar_reg
;
1162 alu
.src
[0].chan
= bc
->ar_chan
;
1164 r
= r600_bytecode_add_alu(bc
, &alu
);
1168 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1173 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
,
1174 const struct r600_bytecode_alu
*alu
, unsigned type
)
1176 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1177 struct r600_bytecode_alu
*lalu
;
1182 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1185 /* will fail later since alu does not support it. */
1186 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1189 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->op
!= type
) {
1190 /* check if we could add it anyway */
1191 if (bc
->cf_last
->op
== CF_OP_ALU
&&
1192 type
== CF_OP_ALU_PUSH_BEFORE
) {
1193 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1194 if (lalu
->execute_mask
) {
1195 bc
->force_add_cf
= 1;
1200 bc
->force_add_cf
= 1;
1203 /* cf can contains only alu or only vtx or only tex */
1204 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1205 r
= r600_bytecode_add_cf(bc
);
1211 bc
->cf_last
->op
= type
;
1213 /* Load index register if required */
1214 if (bc
->chip_class
>= EVERGREEN
) {
1215 for (i
= 0; i
< 3; i
++)
1216 if (nalu
->src
[i
].kc_bank
&& nalu
->src
[i
].kc_rel
)
1217 egcm_load_index_reg(bc
, 0, true);
1220 /* Check AR usage and load it if required */
1221 for (i
= 0; i
< 3; i
++)
1222 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1225 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1228 /* Setup the kcache for this ALU instruction. This will start a new
1229 * ALU clause if needed. */
1230 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1235 if (!bc
->cf_last
->curr_bs_head
) {
1236 bc
->cf_last
->curr_bs_head
= nalu
;
1238 /* number of gpr == the last gpr used in any alu */
1239 for (i
= 0; i
< 3; i
++) {
1240 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1241 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1243 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1244 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1245 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
, nalu
->src
[i
].abs
);
1247 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1248 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1250 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1251 /* each alu use 2 dwords */
1252 bc
->cf_last
->ndw
+= 2;
1255 /* process cur ALU instructions for bank swizzle */
1257 uint32_t literal
[4];
1259 struct r600_bytecode_alu
*slots
[5];
1260 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1261 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1265 if (bc
->cf_last
->prev_bs_head
) {
1266 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1271 if (bc
->cf_last
->prev_bs_head
) {
1272 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1277 r
= check_and_set_bank_swizzle(bc
, slots
);
1281 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1283 r
= r600_bytecode_alu_nliterals(slots
[i
], literal
, &nliteral
);
1288 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1290 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1292 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1293 bc
->force_add_cf
= 1;
1296 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1297 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1298 bc
->cf_last
->curr_bs_head
= NULL
;
1301 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1302 insert_nop_r6xx(bc
);
1307 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1309 return r600_bytecode_add_alu_type(bc
, alu
, CF_OP_ALU
);
1312 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1314 switch (bc
->chip_class
) {
1324 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1329 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1331 return !((r600_isa_cf(bc
->cf_last
->op
)->flags
& CF_FETCH
) &&
1332 bc
->cf_last
->op
!= CF_OP_GDS
&&
1333 (bc
->chip_class
== CAYMAN
||
1334 bc
->cf_last
->op
!= CF_OP_TEX
));
1337 static int r600_bytecode_add_vtx_internal(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
,
1340 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1345 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1347 /* Load index register if required */
1348 if (bc
->chip_class
>= EVERGREEN
) {
1349 if (vtx
->buffer_index_mode
)
1350 egcm_load_index_reg(bc
, vtx
->buffer_index_mode
- 1, false);
1353 /* cf can contains only alu or only vtx or only tex */
1354 if (bc
->cf_last
== NULL
||
1355 last_inst_was_not_vtx_fetch(bc
) ||
1357 r
= r600_bytecode_add_cf(bc
);
1362 switch (bc
->chip_class
) {
1365 bc
->cf_last
->op
= CF_OP_VTX
;
1369 bc
->cf_last
->op
= CF_OP_TEX
;
1371 bc
->cf_last
->op
= CF_OP_VTX
;
1374 bc
->cf_last
->op
= CF_OP_TEX
;
1377 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1382 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1383 /* each fetch use 4 dwords */
1384 bc
->cf_last
->ndw
+= 4;
1386 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1387 bc
->force_add_cf
= 1;
1389 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1390 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1395 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1397 return r600_bytecode_add_vtx_internal(bc
, vtx
, false);
1400 int r600_bytecode_add_vtx_tc(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1402 return r600_bytecode_add_vtx_internal(bc
, vtx
, true);
1405 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1407 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1412 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1414 /* Load index register if required */
1415 if (bc
->chip_class
>= EVERGREEN
) {
1416 if (tex
->sampler_index_mode
|| tex
->resource_index_mode
)
1417 egcm_load_index_reg(bc
, 1, false);
1420 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1421 if (bc
->cf_last
!= NULL
&&
1422 bc
->cf_last
->op
== CF_OP_TEX
) {
1423 struct r600_bytecode_tex
*ttex
;
1424 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1425 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1426 bc
->force_add_cf
= 1;
1430 /* slight hack to make gradients always go into same cf */
1431 if (ntex
->op
== FETCH_OP_SET_GRADIENTS_H
)
1432 bc
->force_add_cf
= 1;
1435 /* cf can contains only alu or only vtx or only tex */
1436 if (bc
->cf_last
== NULL
||
1437 bc
->cf_last
->op
!= CF_OP_TEX
||
1439 r
= r600_bytecode_add_cf(bc
);
1444 bc
->cf_last
->op
= CF_OP_TEX
;
1446 if (ntex
->src_gpr
>= bc
->ngpr
) {
1447 bc
->ngpr
= ntex
->src_gpr
+ 1;
1449 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1450 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1452 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1453 /* each texture fetch use 4 dwords */
1454 bc
->cf_last
->ndw
+= 4;
1456 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1457 bc
->force_add_cf
= 1;
1461 int r600_bytecode_add_gds(struct r600_bytecode
*bc
, const struct r600_bytecode_gds
*gds
)
1463 struct r600_bytecode_gds
*ngds
= r600_bytecode_gds();
1468 memcpy(ngds
, gds
, sizeof(struct r600_bytecode_gds
));
1470 if (bc
->chip_class
>= EVERGREEN
) {
1471 if (gds
->uav_index_mode
)
1472 egcm_load_index_reg(bc
, gds
->uav_index_mode
- 1, false);
1475 if (bc
->cf_last
== NULL
||
1476 bc
->cf_last
->op
!= CF_OP_GDS
||
1478 r
= r600_bytecode_add_cf(bc
);
1483 bc
->cf_last
->op
= CF_OP_GDS
;
1486 LIST_ADDTAIL(&ngds
->list
, &bc
->cf_last
->gds
);
1487 bc
->cf_last
->ndw
+= 4; /* each GDS uses 4 dwords */
1488 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1489 bc
->force_add_cf
= 1;
1493 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, unsigned op
)
1496 r
= r600_bytecode_add_cf(bc
);
1500 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1501 bc
->cf_last
->op
= op
;
1505 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1507 return r600_bytecode_add_cfinst(bc
, CF_OP_CF_END
);
1510 /* common to all 3 families */
1511 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1513 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1514 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1515 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1516 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1517 if (bc
->chip_class
< CAYMAN
)
1518 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1520 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1521 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1522 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1523 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1524 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1525 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1526 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1527 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1528 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1529 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1530 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1531 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1532 if (bc
->chip_class
>= EVERGREEN
)
1533 bc
->bytecode
[id
] |= ((vtx
->buffer_index_mode
& 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1534 if (bc
->chip_class
< CAYMAN
)
1535 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1537 bc
->bytecode
[id
++] = 0;
1541 /* common to all 3 families */
1542 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1544 bc
->bytecode
[id
] = S_SQ_TEX_WORD0_TEX_INST(
1545 r600_isa_fetch_opcode(bc
->isa
->hw_class
, tex
->op
)) |
1546 EG_S_SQ_TEX_WORD0_INST_MOD(tex
->inst_mod
) |
1547 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1548 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1549 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1550 if (bc
->chip_class
>= EVERGREEN
)
1551 bc
->bytecode
[id
] |= ((tex
->sampler_index_mode
& 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1552 ((tex
->resource_index_mode
& 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1554 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1555 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1556 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1557 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1558 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1559 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1560 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1561 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1562 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1563 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1564 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1565 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1566 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1567 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1568 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1569 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1570 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1571 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1572 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1573 bc
->bytecode
[id
++] = 0;
1577 /* r600 only, r700/eg bits in r700_asm.c */
1578 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1580 unsigned opcode
= r600_isa_alu_opcode(bc
->isa
->hw_class
, alu
->op
);
1582 /* don't replace gpr by pv or ps for destination register */
1583 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1584 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1585 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1586 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1587 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1588 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1589 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1590 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1591 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1592 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1593 S_SQ_ALU_WORD0_LAST(alu
->last
);
1596 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1597 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1598 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1599 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1600 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1601 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1602 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1603 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1604 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1605 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode
) |
1606 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1608 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1609 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1610 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1611 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1612 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1613 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1614 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1615 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1616 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode
) |
1617 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1618 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1619 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1624 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1626 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1627 *bytecode
++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600
, cf
->op
)) |
1628 S_SQ_CF_WORD1_BARRIER(1) |
1629 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1)|
1630 S_SQ_CF_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1633 /* common for r600/r700 - eg in eg_asm.c */
1634 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1636 unsigned id
= cf
->id
;
1637 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1638 unsigned opcode
= r600_isa_cf_opcode(bc
->isa
->hw_class
, cf
->op
);
1641 if (cf
->op
== CF_NATIVE
) {
1642 bc
->bytecode
[id
++] = cf
->isa
[0];
1643 bc
->bytecode
[id
++] = cf
->isa
[1];
1644 } else if (cfop
->flags
& CF_ALU
) {
1645 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1646 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1647 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1648 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1650 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode
) |
1651 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1652 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1653 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1654 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1655 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1656 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1657 } else if (cfop
->flags
& CF_FETCH
) {
1658 if (bc
->chip_class
== R700
)
1659 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1661 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1662 } else if (cfop
->flags
& CF_EXP
) {
1663 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1664 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1665 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1666 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1667 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1668 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1669 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1670 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1671 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1672 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1673 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1674 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1675 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1676 } else if (cfop
->flags
& CF_MEM
) {
1677 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1678 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1679 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1680 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1681 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1682 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1683 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1684 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1685 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
) |
1686 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1687 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1689 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1690 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(opcode
) |
1691 S_SQ_CF_WORD1_BARRIER(1) |
1692 S_SQ_CF_WORD1_COND(cf
->cond
) |
1693 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
) |
1694 S_SQ_CF_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1699 int r600_bytecode_build(struct r600_bytecode
*bc
)
1701 struct r600_bytecode_cf
*cf
;
1702 struct r600_bytecode_alu
*alu
;
1703 struct r600_bytecode_vtx
*vtx
;
1704 struct r600_bytecode_tex
*tex
;
1705 struct r600_bytecode_gds
*gds
;
1706 uint32_t literal
[4];
1711 if (!bc
->nstack
) { // If not 0, Stack_size already provided by llvm
1712 if (bc
->stack
.max_entries
)
1713 bc
->nstack
= bc
->stack
.max_entries
;
1714 else if (bc
->type
== PIPE_SHADER_VERTEX
||
1715 bc
->type
== PIPE_SHADER_TESS_EVAL
||
1716 bc
->type
== PIPE_SHADER_TESS_CTRL
)
1720 /* first path compute addr of each CF block */
1721 /* addr start after all the CF instructions */
1722 addr
= bc
->cf_last
->id
+ 2;
1723 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1724 if (r600_isa_cf(cf
->op
)->flags
& CF_FETCH
) {
1726 addr
&= 0xFFFFFFFCUL
;
1730 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1733 bc
->bytecode
= calloc(4, bc
->ndw
);
1734 if (bc
->bytecode
== NULL
)
1736 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1737 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1739 if (bc
->chip_class
>= EVERGREEN
)
1740 r
= eg_bytecode_cf_build(bc
, cf
);
1742 r
= r600_bytecode_cf_build(bc
, cf
);
1745 if (cfop
->flags
& CF_ALU
) {
1747 memset(literal
, 0, sizeof(literal
));
1748 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1749 r
= r600_bytecode_alu_nliterals(alu
, literal
, &nliteral
);
1752 r600_bytecode_alu_adjust_literals(alu
, literal
, nliteral
);
1753 r600_bytecode_assign_kcache_banks(alu
, cf
->kcache
);
1755 switch(bc
->chip_class
) {
1757 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
1760 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
1764 r
= eg_bytecode_alu_build(bc
, alu
, addr
);
1767 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
1774 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
1775 bc
->bytecode
[addr
++] = literal
[i
];
1778 memset(literal
, 0, sizeof(literal
));
1781 } else if (cf
->op
== CF_OP_VTX
) {
1782 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1783 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1788 } else if (cf
->op
== CF_OP_GDS
) {
1789 assert(bc
->chip_class
>= EVERGREEN
);
1790 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
1791 r
= eg_bytecode_gds_build(bc
, gds
, addr
);
1796 } else if (cf
->op
== CF_OP_TEX
) {
1797 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1798 assert(bc
->chip_class
>= EVERGREEN
);
1799 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1804 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1805 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
1815 void r600_bytecode_clear(struct r600_bytecode
*bc
)
1817 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
1820 bc
->bytecode
= NULL
;
1822 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
1823 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
1824 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
1825 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
1826 struct r600_bytecode_gds
*gds
= NULL
, *next_gds
;
1828 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
1832 LIST_INITHEAD(&cf
->alu
);
1834 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
1838 LIST_INITHEAD(&cf
->tex
);
1840 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
1844 LIST_INITHEAD(&cf
->vtx
);
1846 LIST_FOR_EACH_ENTRY_SAFE(gds
, next_gds
, &cf
->gds
, list
) {
1850 LIST_INITHEAD(&cf
->gds
);
1855 LIST_INITHEAD(&cf
->list
);
1858 static int print_swizzle(unsigned swz
)
1860 const char * swzchars
= "xyzw01?_";
1861 assert(swz
<8 && swz
!= 6);
1862 return fprintf(stderr
, "%c", swzchars
[swz
]);
1865 static int print_sel(unsigned sel
, unsigned rel
, unsigned index_mode
,
1866 unsigned need_brackets
)
1869 if (rel
&& index_mode
>= 5 && sel
< 128)
1870 o
+= fprintf(stderr
, "G");
1871 if (rel
|| need_brackets
) {
1872 o
+= fprintf(stderr
, "[");
1874 o
+= fprintf(stderr
, "%d", sel
);
1876 if (index_mode
== 0 || index_mode
== 6)
1877 o
+= fprintf(stderr
, "+AR");
1878 else if (index_mode
== 4)
1879 o
+= fprintf(stderr
, "+AL");
1881 if (rel
|| need_brackets
) {
1882 o
+= fprintf(stderr
, "]");
1887 static int print_dst(struct r600_bytecode_alu
*alu
)
1890 unsigned sel
= alu
->dst
.sel
;
1891 char reg_char
= 'R';
1892 if (sel
> 128 - 4) { /* clause temporary gpr */
1897 if (alu_writes(alu
)) {
1898 o
+= fprintf(stderr
, "%c", reg_char
);
1899 o
+= print_sel(alu
->dst
.sel
, alu
->dst
.rel
, alu
->index_mode
, 0);
1901 o
+= fprintf(stderr
, "__");
1903 o
+= fprintf(stderr
, ".");
1904 o
+= print_swizzle(alu
->dst
.chan
);
1908 static int print_src(struct r600_bytecode_alu
*alu
, unsigned idx
)
1911 struct r600_bytecode_alu_src
*src
= &alu
->src
[idx
];
1912 unsigned sel
= src
->sel
, need_sel
= 1, need_chan
= 1, need_brackets
= 0;
1915 o
+= fprintf(stderr
,"-");
1917 o
+= fprintf(stderr
,"|");
1919 if (sel
< 128 - 4) {
1920 o
+= fprintf(stderr
, "R");
1921 } else if (sel
< 128) {
1922 o
+= fprintf(stderr
, "T");
1924 } else if (sel
< 160) {
1925 o
+= fprintf(stderr
, "KC0");
1928 } else if (sel
< 192) {
1929 o
+= fprintf(stderr
, "KC1");
1932 } else if (sel
>= 512) {
1933 o
+= fprintf(stderr
, "C%d", src
->kc_bank
);
1936 } else if (sel
>= 448) {
1937 o
+= fprintf(stderr
, "Param");
1940 } else if (sel
>= 288) {
1941 o
+= fprintf(stderr
, "KC3");
1944 } else if (sel
>= 256) {
1945 o
+= fprintf(stderr
, "KC2");
1952 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A
:
1953 o
+= fprintf(stderr
, "LDS_A[0x%08X]", src
->value
);
1955 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B
:
1956 o
+= fprintf(stderr
, "LDS_B[0x%08X]", src
->value
);
1958 case EG_V_SQ_ALU_SRC_LDS_OQ_A
:
1959 o
+= fprintf(stderr
, "LDS_OQ_A");
1962 case EG_V_SQ_ALU_SRC_LDS_OQ_B
:
1963 o
+= fprintf(stderr
, "LDS_OQ_B");
1966 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
:
1967 o
+= fprintf(stderr
, "LDS_OQ_A_POP");
1970 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP
:
1971 o
+= fprintf(stderr
, "LDS_OQ_B_POP");
1974 case EG_V_SQ_ALU_SRC_SE_ID
:
1975 o
+= fprintf(stderr
, "SE_ID");
1977 case EG_V_SQ_ALU_SRC_SIMD_ID
:
1978 o
+= fprintf(stderr
, "SIMD_ID");
1980 case EG_V_SQ_ALU_SRC_HW_WAVE_ID
:
1981 o
+= fprintf(stderr
, "HW_WAVE_ID");
1983 case V_SQ_ALU_SRC_PS
:
1984 o
+= fprintf(stderr
, "PS");
1986 case V_SQ_ALU_SRC_PV
:
1987 o
+= fprintf(stderr
, "PV");
1990 case V_SQ_ALU_SRC_LITERAL
:
1991 o
+= fprintf(stderr
, "[0x%08X %f]", src
->value
, u_bitcast_u2f(src
->value
));
1993 case V_SQ_ALU_SRC_0_5
:
1994 o
+= fprintf(stderr
, "0.5");
1996 case V_SQ_ALU_SRC_M_1_INT
:
1997 o
+= fprintf(stderr
, "-1");
1999 case V_SQ_ALU_SRC_1_INT
:
2000 o
+= fprintf(stderr
, "1");
2002 case V_SQ_ALU_SRC_1
:
2003 o
+= fprintf(stderr
, "1.0");
2005 case V_SQ_ALU_SRC_0
:
2006 o
+= fprintf(stderr
, "0");
2009 o
+= fprintf(stderr
, "??IMM_%d", sel
);
2015 o
+= print_sel(sel
, src
->rel
, alu
->index_mode
, need_brackets
);
2018 o
+= fprintf(stderr
, ".");
2019 o
+= print_swizzle(src
->chan
);
2023 o
+= fprintf(stderr
,"|");
2028 static int print_indent(int p
, int c
)
2032 o
+= fprintf(stderr
, " ");
2036 void r600_bytecode_disasm(struct r600_bytecode
*bc
)
2038 const char *index_mode
[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2039 static int index
= 0;
2040 struct r600_bytecode_cf
*cf
= NULL
;
2041 struct r600_bytecode_alu
*alu
= NULL
;
2042 struct r600_bytecode_vtx
*vtx
= NULL
;
2043 struct r600_bytecode_tex
*tex
= NULL
;
2044 struct r600_bytecode_gds
*gds
= NULL
;
2046 unsigned i
, id
, ngr
= 0, last
;
2047 uint32_t literal
[4];
2051 switch (bc
->chip_class
) {
2066 fprintf(stderr
, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2067 bc
->ndw
, bc
->ngpr
, bc
->nstack
);
2068 fprintf(stderr
, "shader %d -- %c\n", index
++, chip
);
2070 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2072 if (cf
->op
== CF_NATIVE
) {
2073 fprintf(stderr
, "%04d %08X %08X CF_NATIVE\n", id
, bc
->bytecode
[id
],
2074 bc
->bytecode
[id
+ 1]);
2076 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
2077 if (cfop
->flags
& CF_ALU
) {
2078 if (cf
->eg_alu_extended
) {
2079 fprintf(stderr
, "%04d %08X %08X %s\n", id
, bc
->bytecode
[id
],
2080 bc
->bytecode
[id
+ 1], "ALU_EXT");
2083 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2084 bc
->bytecode
[id
+ 1], cfop
->name
);
2085 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 2, cf
->addr
);
2086 for (i
= 0; i
< 4; ++i
) {
2087 if (cf
->kcache
[i
].mode
) {
2088 int c_start
= (cf
->kcache
[i
].addr
<< 4);
2089 int c_end
= c_start
+ (cf
->kcache
[i
].mode
<< 4);
2090 fprintf(stderr
, "KC%d[CB%d:%d-%d%s%s] ",
2091 i
, cf
->kcache
[i
].bank
, c_start
, c_end
,
2092 cf
->kcache
[i
].index_mode
? " " : "",
2093 cf
->kcache
[i
].index_mode
? index_mode
[cf
->kcache
[i
].index_mode
] : "");
2096 fprintf(stderr
, "\n");
2097 } else if (cfop
->flags
& CF_FETCH
) {
2098 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2099 bc
->bytecode
[id
+ 1], cfop
->name
);
2100 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 4, cf
->addr
);
2101 fprintf(stderr
, "\n");
2102 if (cf
->end_of_program
)
2103 fprintf(stderr
, "EOP ");
2104 } else if (cfop
->flags
& CF_EXP
) {
2106 const char *exp_type
[] = {"PIXEL", "POS ", "PARAM"};
2107 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2108 bc
->bytecode
[id
+ 1], cfop
->name
);
2109 o
+= print_indent(o
, 43);
2110 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2111 if (cf
->output
.burst_count
> 1) {
2112 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2113 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2115 o
+= print_indent(o
, 55);
2116 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2117 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2119 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2120 o
+= print_indent(o
, 55);
2121 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2124 o
+= print_swizzle(cf
->output
.swizzle_x
);
2125 o
+= print_swizzle(cf
->output
.swizzle_y
);
2126 o
+= print_swizzle(cf
->output
.swizzle_z
);
2127 o
+= print_swizzle(cf
->output
.swizzle_w
);
2129 print_indent(o
, 67);
2131 fprintf(stderr
, " ES:%X ", cf
->output
.elem_size
);
2133 fprintf(stderr
, "MARK ");
2135 fprintf(stderr
, "NO_BARRIER ");
2136 if (cf
->end_of_program
)
2137 fprintf(stderr
, "EOP ");
2138 fprintf(stderr
, "\n");
2139 } else if (r600_isa_cf(cf
->op
)->flags
& CF_MEM
) {
2141 const char *exp_type
[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2143 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
,
2144 bc
->bytecode
[id
], bc
->bytecode
[id
+ 1], cfop
->name
);
2145 o
+= print_indent(o
, 43);
2146 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2148 if (r600_isa_cf(cf
->op
)->flags
& CF_RAT
) {
2149 o
+= fprintf(stderr
, "RAT%d", cf
->rat
.id
);
2150 if (cf
->rat
.index_mode
) {
2151 o
+= fprintf(stderr
, "[IDX%d]", cf
->rat
.index_mode
- 1);
2153 o
+= fprintf(stderr
, " INST: %d ", cf
->rat
.inst
);
2156 if (cf
->output
.burst_count
> 1) {
2157 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2158 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2159 o
+= print_indent(o
, 55);
2160 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2161 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2163 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2164 o
+= print_indent(o
, 55);
2165 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2167 for (i
= 0; i
< 4; ++i
) {
2168 if (cf
->output
.comp_mask
& (1 << i
))
2169 o
+= print_swizzle(i
);
2171 o
+= print_swizzle(7);
2174 if (cf
->output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
||
2175 cf
->output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND
)
2176 o
+= fprintf(stderr
, " R%d", cf
->output
.index_gpr
);
2178 o
+= print_indent(o
, 67);
2180 fprintf(stderr
, " ES:%i ", cf
->output
.elem_size
);
2181 if (cf
->output
.array_size
!= 0xFFF)
2182 fprintf(stderr
, "AS:%i ", cf
->output
.array_size
);
2184 fprintf(stderr
, "MARK ");
2186 fprintf(stderr
, "NO_BARRIER ");
2187 if (cf
->end_of_program
)
2188 fprintf(stderr
, "EOP ");
2189 fprintf(stderr
, "\n");
2191 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2192 bc
->bytecode
[id
+ 1], cfop
->name
);
2193 fprintf(stderr
, "@%d ", cf
->cf_addr
);
2195 fprintf(stderr
, "CND:%X ", cf
->cond
);
2197 fprintf(stderr
, "POP:%X ", cf
->pop_count
);
2198 if (cf
->count
&& (cfop
->flags
& CF_EMIT
))
2199 fprintf(stderr
, "STREAM%d ", cf
->count
);
2200 if (cf
->end_of_program
)
2201 fprintf(stderr
, "EOP ");
2202 fprintf(stderr
, "\n");
2209 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2210 const char *omod_str
[] = {"","*2","*4","/2"};
2211 const struct alu_op_info
*aop
= r600_isa_alu(alu
->op
);
2214 r600_bytecode_alu_nliterals(alu
, literal
, &nliteral
);
2215 o
+= fprintf(stderr
, " %04d %08X %08X ", id
, bc
->bytecode
[id
], bc
->bytecode
[id
+1]);
2217 o
+= fprintf(stderr
, "%4d ", ++ngr
);
2219 o
+= fprintf(stderr
, " ");
2220 o
+= fprintf(stderr
, "%c%c %c ", alu
->execute_mask
? 'M':' ',
2221 alu
->update_pred
? 'P':' ',
2222 alu
->pred_sel
? alu
->pred_sel
==2 ? '0':'1':' ');
2224 o
+= fprintf(stderr
, "%s%s%s ", aop
->name
,
2225 omod_str
[alu
->omod
], alu
->dst
.clamp
? "_sat":"");
2227 o
+= print_indent(o
,60);
2228 o
+= print_dst(alu
);
2229 for (i
= 0; i
< aop
->src_count
; ++i
) {
2230 o
+= fprintf(stderr
, i
== 0 ? ", ": ", ");
2231 o
+= print_src(alu
, i
);
2234 if (alu
->bank_swizzle
) {
2235 o
+= print_indent(o
,75);
2236 o
+= fprintf(stderr
, " BS:%d", alu
->bank_swizzle
);
2239 fprintf(stderr
, "\n");
2243 for (i
= 0; i
< nliteral
; i
++, id
++) {
2244 float *f
= (float*)(bc
->bytecode
+ id
);
2245 o
= fprintf(stderr
, " %04d %08X", id
, bc
->bytecode
[id
]);
2246 print_indent(o
, 60);
2247 fprintf(stderr
, " %f (%d)\n", *f
, *(bc
->bytecode
+ id
));
2255 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2257 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2258 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2260 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(tex
->op
)->name
);
2262 o
+= print_indent(o
, 50);
2264 o
+= fprintf(stderr
, "R%d.", tex
->dst_gpr
);
2265 o
+= print_swizzle(tex
->dst_sel_x
);
2266 o
+= print_swizzle(tex
->dst_sel_y
);
2267 o
+= print_swizzle(tex
->dst_sel_z
);
2268 o
+= print_swizzle(tex
->dst_sel_w
);
2270 o
+= fprintf(stderr
, ", R%d.", tex
->src_gpr
);
2271 o
+= print_swizzle(tex
->src_sel_x
);
2272 o
+= print_swizzle(tex
->src_sel_y
);
2273 o
+= print_swizzle(tex
->src_sel_z
);
2274 o
+= print_swizzle(tex
->src_sel_w
);
2276 o
+= fprintf(stderr
, ", RID:%d", tex
->resource_id
);
2277 o
+= fprintf(stderr
, ", SID:%d ", tex
->sampler_id
);
2279 if (tex
->sampler_index_mode
)
2280 fprintf(stderr
, "SQ_%s ", index_mode
[tex
->sampler_index_mode
]);
2283 fprintf(stderr
, "LB:%d ", tex
->lod_bias
);
2285 fprintf(stderr
, "CT:%c%c%c%c ",
2286 tex
->coord_type_x
? 'N' : 'U',
2287 tex
->coord_type_y
? 'N' : 'U',
2288 tex
->coord_type_z
? 'N' : 'U',
2289 tex
->coord_type_w
? 'N' : 'U');
2292 fprintf(stderr
, "OX:%d ", tex
->offset_x
);
2294 fprintf(stderr
, "OY:%d ", tex
->offset_y
);
2296 fprintf(stderr
, "OZ:%d ", tex
->offset_z
);
2299 fprintf(stderr
, "\n");
2302 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2304 const char * fetch_type
[] = {"VERTEX", "INSTANCE", ""};
2305 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2306 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2308 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(vtx
->op
)->name
);
2310 o
+= print_indent(o
, 50);
2312 o
+= fprintf(stderr
, "R%d.", vtx
->dst_gpr
);
2313 o
+= print_swizzle(vtx
->dst_sel_x
);
2314 o
+= print_swizzle(vtx
->dst_sel_y
);
2315 o
+= print_swizzle(vtx
->dst_sel_z
);
2316 o
+= print_swizzle(vtx
->dst_sel_w
);
2318 o
+= fprintf(stderr
, ", R%d.", vtx
->src_gpr
);
2319 o
+= print_swizzle(vtx
->src_sel_x
);
2322 fprintf(stderr
, " +%db", vtx
->offset
);
2324 o
+= print_indent(o
, 55);
2326 fprintf(stderr
, ", RID:%d ", vtx
->buffer_id
);
2328 fprintf(stderr
, "%s ", fetch_type
[vtx
->fetch_type
]);
2330 if (bc
->chip_class
< CAYMAN
&& vtx
->mega_fetch_count
)
2331 fprintf(stderr
, "MFC:%d ", vtx
->mega_fetch_count
);
2333 if (bc
->chip_class
>= EVERGREEN
&& vtx
->buffer_index_mode
)
2334 fprintf(stderr
, "SQ_%s ", index_mode
[vtx
->buffer_index_mode
]);
2336 fprintf(stderr
, "UCF:%d ", vtx
->use_const_fields
);
2337 fprintf(stderr
, "FMT(DTA:%d ", vtx
->data_format
);
2338 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2339 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2340 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2345 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
2347 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2348 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2350 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(gds
->op
)->name
);
2352 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2353 o
+= fprintf(stderr
, "R%d.", gds
->dst_gpr
);
2354 o
+= print_swizzle(gds
->dst_sel_x
);
2355 o
+= print_swizzle(gds
->dst_sel_y
);
2356 o
+= print_swizzle(gds
->dst_sel_z
);
2357 o
+= print_swizzle(gds
->dst_sel_w
);
2360 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr
);
2361 o
+= print_swizzle(gds
->src_sel_x
);
2362 o
+= print_swizzle(gds
->src_sel_y
);
2363 o
+= print_swizzle(gds
->src_sel_z
);
2365 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2366 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr2
);
2368 if (gds
->alloc_consume
) {
2369 o
+= fprintf(stderr
, " UAV: %d", gds
->uav_id
);
2370 if (gds
->uav_index_mode
)
2371 o
+= fprintf(stderr
, "[%s]", index_mode
[gds
->uav_index_mode
]);
2373 fprintf(stderr
, "\n");
2378 fprintf(stderr
, "--------------------------------------\n");
2381 void r600_vertex_data_type(enum pipe_format pformat
,
2383 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2385 const struct util_format_description
*desc
;
2391 *endian
= ENDIAN_NONE
;
2393 if (pformat
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2394 *format
= FMT_10_11_11_FLOAT
;
2395 *endian
= r600_endian_swap(32);
2399 if (pformat
== PIPE_FORMAT_B5G6R5_UNORM
) {
2400 *format
= FMT_5_6_5
;
2401 *endian
= r600_endian_swap(16);
2405 if (pformat
== PIPE_FORMAT_B5G5R5A1_UNORM
) {
2406 *format
= FMT_1_5_5_5
;
2407 *endian
= r600_endian_swap(16);
2411 desc
= util_format_description(pformat
);
2412 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2416 /* Find the first non-VOID channel. */
2417 for (i
= 0; i
< 4; i
++) {
2418 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2423 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2425 switch (desc
->channel
[i
].type
) {
2426 /* Half-floats, floats, ints */
2427 case UTIL_FORMAT_TYPE_FLOAT
:
2428 switch (desc
->channel
[i
].size
) {
2430 switch (desc
->nr_channels
) {
2432 *format
= FMT_16_FLOAT
;
2435 *format
= FMT_16_16_FLOAT
;
2439 *format
= FMT_16_16_16_16_FLOAT
;
2444 switch (desc
->nr_channels
) {
2446 *format
= FMT_32_FLOAT
;
2449 *format
= FMT_32_32_FLOAT
;
2452 *format
= FMT_32_32_32_FLOAT
;
2455 *format
= FMT_32_32_32_32_FLOAT
;
2464 case UTIL_FORMAT_TYPE_UNSIGNED
:
2466 case UTIL_FORMAT_TYPE_SIGNED
:
2467 switch (desc
->channel
[i
].size
) {
2469 switch (desc
->nr_channels
) {
2478 *format
= FMT_8_8_8_8
;
2483 if (desc
->nr_channels
!= 4)
2486 *format
= FMT_2_10_10_10
;
2489 switch (desc
->nr_channels
) {
2494 *format
= FMT_16_16
;
2498 *format
= FMT_16_16_16_16
;
2503 switch (desc
->nr_channels
) {
2508 *format
= FMT_32_32
;
2511 *format
= FMT_32_32_32
;
2514 *format
= FMT_32_32_32_32
;
2526 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2531 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2532 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2533 if (!desc
->channel
[i
].normalized
) {
2534 if (desc
->channel
[i
].pure_integer
)
2542 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2545 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2547 const struct pipe_vertex_element
*elements
)
2549 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2550 struct r600_bytecode bc
;
2551 struct r600_bytecode_vtx vtx
;
2552 const struct util_format_description
*desc
;
2553 unsigned fetch_resource_start
= rctx
->b
.chip_class
>= EVERGREEN
? 0 : 160;
2554 unsigned format
, num_format
, format_comp
, endian
;
2556 int i
, j
, r
, fs_size
;
2557 struct r600_fetch_shader
*shader
;
2558 unsigned no_sb
= rctx
->screen
->b
.debug_flags
& DBG_NO_SB
;
2559 unsigned sb_disasm
= !no_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
2563 memset(&bc
, 0, sizeof(bc
));
2564 r600_bytecode_init(&bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2565 rctx
->screen
->has_compressed_msaa_texturing
);
2569 for (i
= 0; i
< count
; i
++) {
2570 if (elements
[i
].instance_divisor
> 1) {
2571 if (rctx
->b
.chip_class
== CAYMAN
) {
2572 for (j
= 0; j
< 4; j
++) {
2573 struct r600_bytecode_alu alu
;
2574 memset(&alu
, 0, sizeof(alu
));
2575 alu
.op
= ALU_OP2_MULHI_UINT
;
2577 alu
.src
[0].chan
= 3;
2578 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2579 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2580 alu
.dst
.sel
= i
+ 1;
2582 alu
.dst
.write
= j
== 3;
2584 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2585 r600_bytecode_clear(&bc
);
2590 struct r600_bytecode_alu alu
;
2591 memset(&alu
, 0, sizeof(alu
));
2592 alu
.op
= ALU_OP2_MULHI_UINT
;
2594 alu
.src
[0].chan
= 3;
2595 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2596 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2597 alu
.dst
.sel
= i
+ 1;
2601 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2602 r600_bytecode_clear(&bc
);
2609 for (i
= 0; i
< count
; i
++) {
2610 r600_vertex_data_type(elements
[i
].src_format
,
2611 &format
, &num_format
, &format_comp
, &endian
);
2613 desc
= util_format_description(elements
[i
].src_format
);
2615 r600_bytecode_clear(&bc
);
2616 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2620 if (elements
[i
].src_offset
> 65535) {
2621 r600_bytecode_clear(&bc
);
2622 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2626 memset(&vtx
, 0, sizeof(vtx
));
2627 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2628 vtx
.fetch_type
= elements
[i
].instance_divisor
? SQ_VTX_FETCH_INSTANCE_DATA
: SQ_VTX_FETCH_VERTEX_DATA
;
2629 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2630 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2631 vtx
.mega_fetch_count
= 0x1F;
2632 vtx
.dst_gpr
= i
+ 1;
2633 vtx
.dst_sel_x
= desc
->swizzle
[0];
2634 vtx
.dst_sel_y
= desc
->swizzle
[1];
2635 vtx
.dst_sel_z
= desc
->swizzle
[2];
2636 vtx
.dst_sel_w
= desc
->swizzle
[3];
2637 vtx
.data_format
= format
;
2638 vtx
.num_format_all
= num_format
;
2639 vtx
.format_comp_all
= format_comp
;
2640 vtx
.offset
= elements
[i
].src_offset
;
2641 vtx
.endian
= endian
;
2643 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2644 r600_bytecode_clear(&bc
);
2649 r600_bytecode_add_cfinst(&bc
, CF_OP_RET
);
2651 if ((r
= r600_bytecode_build(&bc
))) {
2652 r600_bytecode_clear(&bc
);
2656 if (rctx
->screen
->b
.debug_flags
& DBG_FS
) {
2657 fprintf(stderr
, "--------------------------------------------------------------\n");
2658 fprintf(stderr
, "Vertex elements state:\n");
2659 for (i
= 0; i
< count
; i
++) {
2660 fprintf(stderr
, " ");
2661 util_dump_vertex_element(stderr
, elements
+i
);
2662 fprintf(stderr
, "\n");
2666 r600_bytecode_disasm(&bc
);
2668 fprintf(stderr
, "______________________________________________________________\n");
2670 r600_sb_bytecode_process(rctx
, &bc
, NULL
, 1 /*dump*/, 0 /*optimize*/);
2676 /* Allocate the CSO. */
2677 shader
= CALLOC_STRUCT(r600_fetch_shader
);
2679 r600_bytecode_clear(&bc
);
2683 u_suballocator_alloc(rctx
->allocator_fetch_shader
, fs_size
, 256,
2685 (struct pipe_resource
**)&shader
->buffer
);
2686 if (!shader
->buffer
) {
2687 r600_bytecode_clear(&bc
);
2692 bytecode
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->buffer
, PIPE_TRANSFER_WRITE
| PIPE_TRANSFER_UNSYNCHRONIZED
);
2693 bytecode
+= shader
->offset
/ 4;
2695 if (R600_BIG_ENDIAN
) {
2696 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2697 bytecode
[i
] = util_cpu_to_le32(bc
.bytecode
[i
]);
2700 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2702 rctx
->b
.ws
->buffer_unmap(shader
->buffer
->buf
);
2704 r600_bytecode_clear(&bc
);
2708 void r600_bytecode_alu_read(struct r600_bytecode
*bc
,
2709 struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2712 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2713 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2714 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2715 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2716 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2717 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2718 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2719 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2720 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2721 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2722 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2725 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2726 if (alu
->bank_swizzle
)
2727 alu
->bank_swizzle_force
= alu
->bank_swizzle
;
2728 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2729 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2730 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2731 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2732 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2735 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2736 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2737 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2738 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2739 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2740 G_SQ_ALU_WORD1_OP3_ALU_INST(word1
), /* is_op3 = */ 1);
2743 else /*ALU_DWORD1_OP2*/
2745 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2746 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2747 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2748 G_SQ_ALU_WORD1_OP2_ALU_INST(word1
), /* is_op3 = */ 0);
2749 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2750 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2751 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2753 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);
2758 void r600_bytecode_export_read(struct r600_bytecode
*bc
,
2759 struct r600_bytecode_output
*output
, uint32_t word0
, uint32_t word1
)
2761 output
->array_base
= G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0
);
2762 output
->type
= G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0
);
2763 output
->gpr
= G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0
);
2764 output
->elem_size
= G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0
);
2766 output
->swizzle_x
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1
);
2767 output
->swizzle_y
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1
);
2768 output
->swizzle_z
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1
);
2769 output
->swizzle_w
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1
);
2770 output
->burst_count
= G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1
);
2771 output
->end_of_program
= G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1
);
2772 output
->op
= r600_isa_cf_by_opcode(bc
->isa
,
2773 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1
), 0);
2774 output
->barrier
= G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1
);
2775 output
->array_size
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1
);
2776 output
->comp_mask
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1
);