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r600g: add support for streams to the assembler.
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
34
35 #include "sb/sb_public.h"
36
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
39
40 static inline unsigned int r600_bytecode_get_num_operands(
41 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
42 {
43 return r600_isa_alu(alu->op)->src_count;
44 }
45
46 int r700_bytecode_alu_build(struct r600_bytecode *bc,
47 struct r600_bytecode_alu *alu, unsigned id);
48
49 static struct r600_bytecode_cf *r600_bytecode_cf(void)
50 {
51 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
52
53 if (cf == NULL)
54 return NULL;
55 LIST_INITHEAD(&cf->list);
56 LIST_INITHEAD(&cf->alu);
57 LIST_INITHEAD(&cf->vtx);
58 LIST_INITHEAD(&cf->tex);
59 return cf;
60 }
61
62 static struct r600_bytecode_alu *r600_bytecode_alu(void)
63 {
64 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
65
66 if (alu == NULL)
67 return NULL;
68 LIST_INITHEAD(&alu->list);
69 return alu;
70 }
71
72 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
73 {
74 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
75
76 if (vtx == NULL)
77 return NULL;
78 LIST_INITHEAD(&vtx->list);
79 return vtx;
80 }
81
82 static struct r600_bytecode_tex *r600_bytecode_tex(void)
83 {
84 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
85
86 if (tex == NULL)
87 return NULL;
88 LIST_INITHEAD(&tex->list);
89 return tex;
90 }
91
92 static unsigned stack_entry_size(enum radeon_family chip) {
93 /* Wavefront size:
94 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
95 * Aruba/Sumo/Sumo2/redwood/juniper
96 * 32: R630/R730/R710/Palm/Cedar
97 * 16: R610/Rs780
98 *
99 * Stack row size:
100 * Wavefront Size 16 32 48 64
101 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
102 * Columns per Row (R9xx+) 8 4 4 4 */
103
104 switch (chip) {
105 /* FIXME: are some chips missing here? */
106 /* wavefront size 16 */
107 case CHIP_RV610:
108 case CHIP_RS780:
109 case CHIP_RV620:
110 case CHIP_RS880:
111 /* wavefront size 32 */
112 case CHIP_RV630:
113 case CHIP_RV635:
114 case CHIP_RV730:
115 case CHIP_RV710:
116 case CHIP_PALM:
117 case CHIP_CEDAR:
118 return 8;
119
120 /* wavefront size 64 */
121 default:
122 return 4;
123 }
124 }
125
126 void r600_bytecode_init(struct r600_bytecode *bc,
127 enum chip_class chip_class,
128 enum radeon_family family,
129 bool has_compressed_msaa_texturing)
130 {
131 static unsigned next_shader_id = 0;
132
133 bc->debug_id = ++next_shader_id;
134
135 if ((chip_class == R600) &&
136 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
137 bc->ar_handling = AR_HANDLE_RV6XX;
138 bc->r6xx_nop_after_rel_dst = 1;
139 } else {
140 bc->ar_handling = AR_HANDLE_NORMAL;
141 bc->r6xx_nop_after_rel_dst = 0;
142 }
143
144 LIST_INITHEAD(&bc->cf);
145 bc->chip_class = chip_class;
146 bc->family = family;
147 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
148 bc->stack.entry_size = stack_entry_size(family);
149 }
150
151 int r600_bytecode_add_cf(struct r600_bytecode *bc)
152 {
153 struct r600_bytecode_cf *cf = r600_bytecode_cf();
154
155 if (cf == NULL)
156 return -ENOMEM;
157 LIST_ADDTAIL(&cf->list, &bc->cf);
158 if (bc->cf_last) {
159 cf->id = bc->cf_last->id + 2;
160 if (bc->cf_last->eg_alu_extended) {
161 /* take into account extended alu size */
162 cf->id += 2;
163 bc->ndw += 2;
164 }
165 }
166 bc->cf_last = cf;
167 bc->ncf++;
168 bc->ndw += 2;
169 bc->force_add_cf = 0;
170 bc->ar_loaded = 0;
171 return 0;
172 }
173
174 int r600_bytecode_add_output(struct r600_bytecode *bc,
175 const struct r600_bytecode_output *output)
176 {
177 int r;
178
179 if (output->gpr >= bc->ngpr)
180 bc->ngpr = output->gpr + 1;
181
182 if (bc->cf_last && (bc->cf_last->op == output->op ||
183 (bc->cf_last->op == CF_OP_EXPORT &&
184 output->op == CF_OP_EXPORT_DONE)) &&
185 output->type == bc->cf_last->output.type &&
186 output->elem_size == bc->cf_last->output.elem_size &&
187 output->swizzle_x == bc->cf_last->output.swizzle_x &&
188 output->swizzle_y == bc->cf_last->output.swizzle_y &&
189 output->swizzle_z == bc->cf_last->output.swizzle_z &&
190 output->swizzle_w == bc->cf_last->output.swizzle_w &&
191 output->comp_mask == bc->cf_last->output.comp_mask &&
192 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
193
194 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
195 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
196
197 bc->cf_last->op = bc->cf_last->output.op = output->op;
198 bc->cf_last->output.gpr = output->gpr;
199 bc->cf_last->output.array_base = output->array_base;
200 bc->cf_last->output.burst_count += output->burst_count;
201 return 0;
202
203 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
204 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
205
206 bc->cf_last->op = bc->cf_last->output.op = output->op;
207 bc->cf_last->output.burst_count += output->burst_count;
208 return 0;
209 }
210 }
211
212 r = r600_bytecode_add_cf(bc);
213 if (r)
214 return r;
215 bc->cf_last->op = output->op;
216 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
217 bc->cf_last->barrier = 1;
218 return 0;
219 }
220
221 /* alu instructions that can ony exits once per group */
222 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
223 {
224 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
225 }
226
227 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
228 {
229 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
230 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
231 }
232
233 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
234 {
235 return r600_isa_alu(alu->op)->flags & AF_MOVA;
236 }
237
238 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
239 {
240 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
241 unsigned src;
242
243 if (alu->dst.rel) {
244 return 1;
245 }
246
247 for (src = 0; src < num_src; ++src) {
248 if (alu->src[src].rel) {
249 return 1;
250 }
251 }
252 return 0;
253 }
254
255 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
256 {
257 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
258 return !(slots & AF_S);
259 }
260
261 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
262 {
263 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
264 return !(slots & AF_V);
265 }
266
267 /* alu instructions that can execute on any unit */
268 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
269 {
270 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
271 return slots == AF_VS;
272 }
273
274 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
275 {
276 return alu->op == ALU_OP0_NOP;
277 }
278
279 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
280 struct r600_bytecode_alu *assignment[5])
281 {
282 struct r600_bytecode_alu *alu;
283 unsigned i, chan, trans;
284 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
285
286 for (i = 0; i < max_slots; i++)
287 assignment[i] = NULL;
288
289 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
290 chan = alu->dst.chan;
291 if (max_slots == 4)
292 trans = 0;
293 else if (is_alu_trans_unit_inst(bc, alu))
294 trans = 1;
295 else if (is_alu_vec_unit_inst(bc, alu))
296 trans = 0;
297 else if (assignment[chan])
298 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
299 else
300 trans = 0;
301
302 if (trans) {
303 if (assignment[4]) {
304 assert(0); /* ALU.Trans has already been allocated. */
305 return -1;
306 }
307 assignment[4] = alu;
308 } else {
309 if (assignment[chan]) {
310 assert(0); /* ALU.chan has already been allocated. */
311 return -1;
312 }
313 assignment[chan] = alu;
314 }
315
316 if (alu->last)
317 break;
318 }
319 return 0;
320 }
321
322 struct alu_bank_swizzle {
323 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
324 int hw_cfile_addr[4];
325 int hw_cfile_elem[4];
326 };
327
328 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
329 [SQ_ALU_VEC_012] = { 0, 1, 2 },
330 [SQ_ALU_VEC_021] = { 0, 2, 1 },
331 [SQ_ALU_VEC_120] = { 1, 2, 0 },
332 [SQ_ALU_VEC_102] = { 1, 0, 2 },
333 [SQ_ALU_VEC_201] = { 2, 0, 1 },
334 [SQ_ALU_VEC_210] = { 2, 1, 0 }
335 };
336
337 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
338 [SQ_ALU_SCL_210] = { 2, 1, 0 },
339 [SQ_ALU_SCL_122] = { 1, 2, 2 },
340 [SQ_ALU_SCL_212] = { 2, 1, 2 },
341 [SQ_ALU_SCL_221] = { 2, 2, 1 }
342 };
343
344 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
345 {
346 int i, cycle, component;
347 /* set up gpr use */
348 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
349 for (component = 0; component < NUM_OF_COMPONENTS; component++)
350 bs->hw_gpr[cycle][component] = -1;
351 for (i = 0; i < 4; i++)
352 bs->hw_cfile_addr[i] = -1;
353 for (i = 0; i < 4; i++)
354 bs->hw_cfile_elem[i] = -1;
355 }
356
357 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
358 {
359 if (bs->hw_gpr[cycle][chan] == -1)
360 bs->hw_gpr[cycle][chan] = sel;
361 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
362 /* Another scalar operation has already used the GPR read port for the channel. */
363 return -1;
364 }
365 return 0;
366 }
367
368 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
369 {
370 int res, num_res = 4;
371 if (bc->chip_class >= R700) {
372 num_res = 2;
373 chan /= 2;
374 }
375 for (res = 0; res < num_res; ++res) {
376 if (bs->hw_cfile_addr[res] == -1) {
377 bs->hw_cfile_addr[res] = sel;
378 bs->hw_cfile_elem[res] = chan;
379 return 0;
380 } else if (bs->hw_cfile_addr[res] == sel &&
381 bs->hw_cfile_elem[res] == chan)
382 return 0; /* Read for this scalar element already reserved, nothing to do here. */
383 }
384 /* All cfile read ports are used, cannot reference vector element. */
385 return -1;
386 }
387
388 static int is_gpr(unsigned sel)
389 {
390 return (sel <= 127);
391 }
392
393 /* CB constants start at 512, and get translated to a kcache index when ALU
394 * clauses are constructed. Note that we handle kcache constants the same way
395 * as (the now gone) cfile constants, is that really required? */
396 static int is_cfile(unsigned sel)
397 {
398 return (sel > 255 && sel < 512) ||
399 (sel > 511 && sel < 4607) || /* Kcache before translation. */
400 (sel > 127 && sel < 192); /* Kcache after translation. */
401 }
402
403 static int is_const(int sel)
404 {
405 return is_cfile(sel) ||
406 (sel >= V_SQ_ALU_SRC_0 &&
407 sel <= V_SQ_ALU_SRC_LITERAL);
408 }
409
410 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
411 struct alu_bank_swizzle *bs, int bank_swizzle)
412 {
413 int r, src, num_src, sel, elem, cycle;
414
415 num_src = r600_bytecode_get_num_operands(bc, alu);
416 for (src = 0; src < num_src; src++) {
417 sel = alu->src[src].sel;
418 elem = alu->src[src].chan;
419 if (is_gpr(sel)) {
420 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
421 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
422 /* Nothing to do; special-case optimization,
423 * second source uses first source’s reservation. */
424 continue;
425 else {
426 r = reserve_gpr(bs, sel, elem, cycle);
427 if (r)
428 return r;
429 }
430 } else if (is_cfile(sel)) {
431 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
432 if (r)
433 return r;
434 }
435 /* No restrictions on PV, PS, literal or special constants. */
436 }
437 return 0;
438 }
439
440 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
441 struct alu_bank_swizzle *bs, int bank_swizzle)
442 {
443 int r, src, num_src, const_count, sel, elem, cycle;
444
445 num_src = r600_bytecode_get_num_operands(bc, alu);
446 for (const_count = 0, src = 0; src < num_src; ++src) {
447 sel = alu->src[src].sel;
448 elem = alu->src[src].chan;
449 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
450 if (const_count >= 2)
451 /* More than two references to a constant in
452 * transcendental operation. */
453 return -1;
454 else
455 const_count++;
456 }
457 if (is_cfile(sel)) {
458 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
459 if (r)
460 return r;
461 }
462 }
463 for (src = 0; src < num_src; ++src) {
464 sel = alu->src[src].sel;
465 elem = alu->src[src].chan;
466 if (is_gpr(sel)) {
467 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
468 if (cycle < const_count)
469 /* Cycle for GPR load conflicts with
470 * constant load in transcendental operation. */
471 return -1;
472 r = reserve_gpr(bs, sel, elem, cycle);
473 if (r)
474 return r;
475 }
476 /* PV PS restrictions */
477 if (const_count && (sel == 254 || sel == 255)) {
478 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
479 if (cycle < const_count)
480 return -1;
481 }
482 }
483 return 0;
484 }
485
486 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
487 struct r600_bytecode_alu *slots[5])
488 {
489 struct alu_bank_swizzle bs;
490 int bank_swizzle[5];
491 int i, r = 0, forced = 1;
492 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
493 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
494
495 for (i = 0; i < max_slots; i++) {
496 if (slots[i]) {
497 if (slots[i]->bank_swizzle_force) {
498 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
499 } else {
500 forced = 0;
501 }
502 }
503
504 if (i < 4 && slots[i])
505 scalar_only = false;
506 }
507 if (forced)
508 return 0;
509
510 /* Just check every possible combination of bank swizzle.
511 * Not very efficent, but works on the first try in most of the cases. */
512 for (i = 0; i < 4; i++)
513 if (!slots[i] || !slots[i]->bank_swizzle_force)
514 bank_swizzle[i] = SQ_ALU_VEC_012;
515 else
516 bank_swizzle[i] = slots[i]->bank_swizzle;
517
518 bank_swizzle[4] = SQ_ALU_SCL_210;
519 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
520
521 init_bank_swizzle(&bs);
522 if (scalar_only == false) {
523 for (i = 0; i < 4; i++) {
524 if (slots[i]) {
525 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
526 if (r)
527 break;
528 }
529 }
530 } else
531 r = 0;
532
533 if (!r && max_slots == 5 && slots[4]) {
534 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
535 }
536 if (!r) {
537 for (i = 0; i < max_slots; i++) {
538 if (slots[i])
539 slots[i]->bank_swizzle = bank_swizzle[i];
540 }
541 return 0;
542 }
543
544 if (scalar_only) {
545 bank_swizzle[4]++;
546 } else {
547 for (i = 0; i < max_slots; i++) {
548 if (!slots[i] || !slots[i]->bank_swizzle_force) {
549 bank_swizzle[i]++;
550 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
551 break;
552 else if (i < max_slots - 1)
553 bank_swizzle[i] = SQ_ALU_VEC_012;
554 else
555 return -1;
556 }
557 }
558 }
559 }
560
561 /* Couldn't find a working swizzle. */
562 return -1;
563 }
564
565 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
566 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
567 {
568 struct r600_bytecode_alu *prev[5];
569 int gpr[5], chan[5];
570 int i, j, r, src, num_src;
571 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
572
573 r = assign_alu_units(bc, alu_prev, prev);
574 if (r)
575 return r;
576
577 for (i = 0; i < max_slots; ++i) {
578 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
579 gpr[i] = prev[i]->dst.sel;
580 /* cube writes more than PV.X */
581 if (is_alu_reduction_inst(bc, prev[i]))
582 chan[i] = 0;
583 else
584 chan[i] = prev[i]->dst.chan;
585 } else
586 gpr[i] = -1;
587 }
588
589 for (i = 0; i < max_slots; ++i) {
590 struct r600_bytecode_alu *alu = slots[i];
591 if(!alu)
592 continue;
593
594 num_src = r600_bytecode_get_num_operands(bc, alu);
595 for (src = 0; src < num_src; ++src) {
596 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
597 continue;
598
599 if (bc->chip_class < CAYMAN) {
600 if (alu->src[src].sel == gpr[4] &&
601 alu->src[src].chan == chan[4] &&
602 alu_prev->pred_sel == alu->pred_sel) {
603 alu->src[src].sel = V_SQ_ALU_SRC_PS;
604 alu->src[src].chan = 0;
605 continue;
606 }
607 }
608
609 for (j = 0; j < 4; ++j) {
610 if (alu->src[src].sel == gpr[j] &&
611 alu->src[src].chan == j &&
612 alu_prev->pred_sel == alu->pred_sel) {
613 alu->src[src].sel = V_SQ_ALU_SRC_PV;
614 alu->src[src].chan = chan[j];
615 break;
616 }
617 }
618 }
619 }
620
621 return 0;
622 }
623
624 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
625 {
626 switch(value) {
627 case 0:
628 *sel = V_SQ_ALU_SRC_0;
629 break;
630 case 1:
631 *sel = V_SQ_ALU_SRC_1_INT;
632 break;
633 case -1:
634 *sel = V_SQ_ALU_SRC_M_1_INT;
635 break;
636 case 0x3F800000: /* 1.0f */
637 *sel = V_SQ_ALU_SRC_1;
638 break;
639 case 0x3F000000: /* 0.5f */
640 *sel = V_SQ_ALU_SRC_0_5;
641 break;
642 case 0xBF800000: /* -1.0f */
643 *sel = V_SQ_ALU_SRC_1;
644 *neg ^= 1;
645 break;
646 case 0xBF000000: /* -0.5f */
647 *sel = V_SQ_ALU_SRC_0_5;
648 *neg ^= 1;
649 break;
650 default:
651 *sel = V_SQ_ALU_SRC_LITERAL;
652 break;
653 }
654 }
655
656 /* compute how many literal are needed */
657 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
658 uint32_t literal[4], unsigned *nliteral)
659 {
660 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
661 unsigned i, j;
662
663 for (i = 0; i < num_src; ++i) {
664 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
665 uint32_t value = alu->src[i].value;
666 unsigned found = 0;
667 for (j = 0; j < *nliteral; ++j) {
668 if (literal[j] == value) {
669 found = 1;
670 break;
671 }
672 }
673 if (!found) {
674 if (*nliteral >= 4)
675 return -EINVAL;
676 literal[(*nliteral)++] = value;
677 }
678 }
679 }
680 return 0;
681 }
682
683 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
684 struct r600_bytecode_alu *alu,
685 uint32_t literal[4], unsigned nliteral)
686 {
687 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
688 unsigned i, j;
689
690 for (i = 0; i < num_src; ++i) {
691 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
692 uint32_t value = alu->src[i].value;
693 for (j = 0; j < nliteral; ++j) {
694 if (literal[j] == value) {
695 alu->src[i].chan = j;
696 break;
697 }
698 }
699 }
700 }
701 }
702
703 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
704 struct r600_bytecode_alu *alu_prev)
705 {
706 struct r600_bytecode_alu *prev[5];
707 struct r600_bytecode_alu *result[5] = { NULL };
708
709 uint32_t literal[4], prev_literal[4];
710 unsigned nliteral = 0, prev_nliteral = 0;
711
712 int i, j, r, src, num_src;
713 int num_once_inst = 0;
714 int have_mova = 0, have_rel = 0;
715 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
716
717 r = assign_alu_units(bc, alu_prev, prev);
718 if (r)
719 return r;
720
721 for (i = 0; i < max_slots; ++i) {
722 if (prev[i]) {
723 if (prev[i]->pred_sel)
724 return 0;
725 if (is_alu_once_inst(bc, prev[i]))
726 return 0;
727 }
728 if (slots[i]) {
729 if (slots[i]->pred_sel)
730 return 0;
731 if (is_alu_once_inst(bc, slots[i]))
732 return 0;
733 }
734 }
735
736 for (i = 0; i < max_slots; ++i) {
737 struct r600_bytecode_alu *alu;
738
739 if (num_once_inst > 0)
740 return 0;
741
742 /* check number of literals */
743 if (prev[i]) {
744 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
745 return 0;
746 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
747 return 0;
748 if (is_alu_mova_inst(bc, prev[i])) {
749 if (have_rel)
750 return 0;
751 have_mova = 1;
752 }
753
754 if (alu_uses_rel(bc, prev[i])) {
755 if (have_mova) {
756 return 0;
757 }
758 have_rel = 1;
759 }
760
761 num_once_inst += is_alu_once_inst(bc, prev[i]);
762 }
763 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
764 return 0;
765
766 /* Let's check used slots. */
767 if (prev[i] && !slots[i]) {
768 result[i] = prev[i];
769 continue;
770 } else if (prev[i] && slots[i]) {
771 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
772 /* Trans unit is still free try to use it. */
773 if (is_alu_any_unit_inst(bc, slots[i])) {
774 result[i] = prev[i];
775 result[4] = slots[i];
776 } else if (is_alu_any_unit_inst(bc, prev[i])) {
777 if (slots[i]->dst.sel == prev[i]->dst.sel &&
778 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
779 (prev[i]->dst.write == 1 || prev[i]->is_op3))
780 return 0;
781
782 result[i] = slots[i];
783 result[4] = prev[i];
784 } else
785 return 0;
786 } else
787 return 0;
788 } else if(!slots[i]) {
789 continue;
790 } else {
791 if (max_slots == 5 && slots[i] && prev[4] &&
792 slots[i]->dst.sel == prev[4]->dst.sel &&
793 slots[i]->dst.chan == prev[4]->dst.chan &&
794 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
795 (prev[4]->dst.write == 1 || prev[4]->is_op3))
796 return 0;
797
798 result[i] = slots[i];
799 }
800
801 alu = slots[i];
802 num_once_inst += is_alu_once_inst(bc, alu);
803
804 /* don't reschedule NOPs */
805 if (is_nop_inst(bc, alu))
806 return 0;
807
808 if (is_alu_mova_inst(bc, alu)) {
809 if (have_rel) {
810 return 0;
811 }
812 have_mova = 1;
813 }
814
815 if (alu_uses_rel(bc, alu)) {
816 if (have_mova) {
817 return 0;
818 }
819 have_rel = 1;
820 }
821
822 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
823 alu->op == ALU_OP0_SET_CF_IDX1)
824 return 0; /* data hazard with MOVA */
825
826 /* Let's check source gprs */
827 num_src = r600_bytecode_get_num_operands(bc, alu);
828 for (src = 0; src < num_src; ++src) {
829
830 /* Constants don't matter. */
831 if (!is_gpr(alu->src[src].sel))
832 continue;
833
834 for (j = 0; j < max_slots; ++j) {
835 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
836 continue;
837
838 /* If it's relative then we can't determin which gpr is really used. */
839 if (prev[j]->dst.chan == alu->src[src].chan &&
840 (prev[j]->dst.sel == alu->src[src].sel ||
841 prev[j]->dst.rel || alu->src[src].rel))
842 return 0;
843 }
844 }
845 }
846
847 /* more than one PRED_ or KILL_ ? */
848 if (num_once_inst > 1)
849 return 0;
850
851 /* check if the result can still be swizzlet */
852 r = check_and_set_bank_swizzle(bc, result);
853 if (r)
854 return 0;
855
856 /* looks like everything worked out right, apply the changes */
857
858 /* undo adding previus literals */
859 bc->cf_last->ndw -= align(prev_nliteral, 2);
860
861 /* sort instructions */
862 for (i = 0; i < max_slots; ++i) {
863 slots[i] = result[i];
864 if (result[i]) {
865 LIST_DEL(&result[i]->list);
866 result[i]->last = 0;
867 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
868 }
869 }
870
871 /* determine new last instruction */
872 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
873
874 /* determine new first instruction */
875 for (i = 0; i < max_slots; ++i) {
876 if (result[i]) {
877 bc->cf_last->curr_bs_head = result[i];
878 break;
879 }
880 }
881
882 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
883 bc->cf_last->prev2_bs_head = NULL;
884
885 return 0;
886 }
887
888 /* we'll keep kcache sets sorted by bank & addr */
889 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
890 struct r600_bytecode_kcache *kcache,
891 unsigned bank, unsigned line, unsigned index_mode)
892 {
893 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
894
895 for (i = 0; i < kcache_banks; i++) {
896 if (kcache[i].mode) {
897 int d;
898
899 if (kcache[i].bank < bank)
900 continue;
901
902 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
903 kcache[i].bank > bank) {
904 /* try to insert new line */
905 if (kcache[kcache_banks-1].mode) {
906 /* all sets are in use */
907 return -ENOMEM;
908 }
909
910 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
911 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
912 kcache[i].bank = bank;
913 kcache[i].addr = line;
914 kcache[i].index_mode = index_mode;
915 return 0;
916 }
917
918 d = line - kcache[i].addr;
919
920 if (d == -1) {
921 kcache[i].addr--;
922 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
923 /* we are prepending the line to the current set,
924 * discarding the existing second line,
925 * so we'll have to insert line+2 after it */
926 line += 2;
927 continue;
928 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
929 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
930 return 0;
931 } else {
932 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
933 return -ENOMEM;
934 }
935 } else if (d == 1) {
936 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
937 return 0;
938 } else if (d == 0)
939 return 0;
940 } else { /* free kcache set - use it */
941 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
942 kcache[i].bank = bank;
943 kcache[i].addr = line;
944 kcache[i].index_mode = index_mode;
945 return 0;
946 }
947 }
948 return -ENOMEM;
949 }
950
951 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
952 struct r600_bytecode_kcache *kcache,
953 struct r600_bytecode_alu *alu)
954 {
955 int i, r;
956
957 for (i = 0; i < 3; i++) {
958 unsigned bank, line, sel = alu->src[i].sel, index_mode;
959
960 if (sel < 512)
961 continue;
962
963 bank = alu->src[i].kc_bank;
964 line = (sel-512)>>4;
965 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
966
967 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
968 return r;
969 }
970 return 0;
971 }
972
973 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
974 struct r600_bytecode_alu *alu,
975 struct r600_bytecode_kcache * kcache)
976 {
977 int i, j;
978
979 /* Alter the src operands to refer to the kcache. */
980 for (i = 0; i < 3; ++i) {
981 static const unsigned int base[] = {128, 160, 256, 288};
982 unsigned int line, sel = alu->src[i].sel, found = 0;
983
984 if (sel < 512)
985 continue;
986
987 sel -= 512;
988 line = sel>>4;
989
990 for (j = 0; j < 4 && !found; ++j) {
991 switch (kcache[j].mode) {
992 case V_SQ_CF_KCACHE_NOP:
993 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
994 R600_ERR("unexpected kcache line mode\n");
995 return -ENOMEM;
996 default:
997 if (kcache[j].bank == alu->src[i].kc_bank &&
998 kcache[j].addr <= line &&
999 line < kcache[j].addr + kcache[j].mode) {
1000 alu->src[i].sel = sel - (kcache[j].addr<<4);
1001 alu->src[i].sel += base[j];
1002 found=1;
1003 }
1004 }
1005 }
1006 }
1007 return 0;
1008 }
1009
1010 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1011 struct r600_bytecode_alu *alu,
1012 unsigned type)
1013 {
1014 struct r600_bytecode_kcache kcache_sets[4];
1015 struct r600_bytecode_kcache *kcache = kcache_sets;
1016 int r;
1017
1018 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1019
1020 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1021 /* can't alloc, need to start new clause */
1022 if ((r = r600_bytecode_add_cf(bc))) {
1023 return r;
1024 }
1025 bc->cf_last->op = type;
1026
1027 /* retry with the new clause */
1028 kcache = bc->cf_last->kcache;
1029 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1030 /* can't alloc again- should never happen */
1031 return r;
1032 }
1033 } else {
1034 /* update kcache sets */
1035 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1036 }
1037
1038 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1039 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1040 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1041 if (bc->chip_class < EVERGREEN)
1042 return -ENOMEM;
1043 bc->cf_last->eg_alu_extended = 1;
1044 }
1045
1046 return 0;
1047 }
1048
1049 static int insert_nop_r6xx(struct r600_bytecode *bc)
1050 {
1051 struct r600_bytecode_alu alu;
1052 int r, i;
1053
1054 for (i = 0; i < 4; i++) {
1055 memset(&alu, 0, sizeof(alu));
1056 alu.op = ALU_OP0_NOP;
1057 alu.src[0].chan = i;
1058 alu.dst.chan = i;
1059 alu.last = (i == 3);
1060 r = r600_bytecode_add_alu(bc, &alu);
1061 if (r)
1062 return r;
1063 }
1064 return 0;
1065 }
1066
1067 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1068 static int load_ar_r6xx(struct r600_bytecode *bc)
1069 {
1070 struct r600_bytecode_alu alu;
1071 int r;
1072
1073 if (bc->ar_loaded)
1074 return 0;
1075
1076 /* hack to avoid making MOVA the last instruction in the clause */
1077 if ((bc->cf_last->ndw>>1) >= 110)
1078 bc->force_add_cf = 1;
1079
1080 memset(&alu, 0, sizeof(alu));
1081 alu.op = ALU_OP1_MOVA_GPR_INT;
1082 alu.src[0].sel = bc->ar_reg;
1083 alu.src[0].chan = bc->ar_chan;
1084 alu.last = 1;
1085 alu.index_mode = INDEX_MODE_LOOP;
1086 r = r600_bytecode_add_alu(bc, &alu);
1087 if (r)
1088 return r;
1089
1090 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1091 bc->ar_loaded = 1;
1092 return 0;
1093 }
1094
1095 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1096 static int load_ar(struct r600_bytecode *bc)
1097 {
1098 struct r600_bytecode_alu alu;
1099 int r;
1100
1101 if (bc->ar_handling)
1102 return load_ar_r6xx(bc);
1103
1104 if (bc->ar_loaded)
1105 return 0;
1106
1107 /* hack to avoid making MOVA the last instruction in the clause */
1108 if ((bc->cf_last->ndw>>1) >= 110)
1109 bc->force_add_cf = 1;
1110
1111 memset(&alu, 0, sizeof(alu));
1112 alu.op = ALU_OP1_MOVA_INT;
1113 alu.src[0].sel = bc->ar_reg;
1114 alu.src[0].chan = bc->ar_chan;
1115 alu.last = 1;
1116 r = r600_bytecode_add_alu(bc, &alu);
1117 if (r)
1118 return r;
1119
1120 bc->cf_last->r6xx_uses_waterfall = 1;
1121 bc->ar_loaded = 1;
1122 return 0;
1123 }
1124
1125 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1126 const struct r600_bytecode_alu *alu, unsigned type)
1127 {
1128 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1129 struct r600_bytecode_alu *lalu;
1130 int i, r;
1131
1132 if (nalu == NULL)
1133 return -ENOMEM;
1134 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1135
1136 if (alu->is_op3) {
1137 /* will fail later since alu does not support it. */
1138 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1139 }
1140
1141 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1142 /* check if we could add it anyway */
1143 if (bc->cf_last->op == CF_OP_ALU &&
1144 type == CF_OP_ALU_PUSH_BEFORE) {
1145 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1146 if (lalu->execute_mask) {
1147 bc->force_add_cf = 1;
1148 break;
1149 }
1150 }
1151 } else
1152 bc->force_add_cf = 1;
1153 }
1154
1155 /* cf can contains only alu or only vtx or only tex */
1156 if (bc->cf_last == NULL || bc->force_add_cf) {
1157 r = r600_bytecode_add_cf(bc);
1158 if (r) {
1159 free(nalu);
1160 return r;
1161 }
1162 }
1163 bc->cf_last->op = type;
1164
1165 /* Load index register if required */
1166 if (bc->chip_class >= EVERGREEN) {
1167 for (i = 0; i < 3; i++)
1168 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1169 egcm_load_index_reg(bc, 0, true);
1170 }
1171
1172 /* Check AR usage and load it if required */
1173 for (i = 0; i < 3; i++)
1174 if (nalu->src[i].rel && !bc->ar_loaded)
1175 load_ar(bc);
1176
1177 if (nalu->dst.rel && !bc->ar_loaded)
1178 load_ar(bc);
1179
1180 /* Setup the kcache for this ALU instruction. This will start a new
1181 * ALU clause if needed. */
1182 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1183 free(nalu);
1184 return r;
1185 }
1186
1187 if (!bc->cf_last->curr_bs_head) {
1188 bc->cf_last->curr_bs_head = nalu;
1189 }
1190 /* number of gpr == the last gpr used in any alu */
1191 for (i = 0; i < 3; i++) {
1192 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1193 bc->ngpr = nalu->src[i].sel + 1;
1194 }
1195 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1196 r600_bytecode_special_constants(nalu->src[i].value,
1197 &nalu->src[i].sel, &nalu->src[i].neg);
1198 }
1199 if (nalu->dst.sel >= bc->ngpr) {
1200 bc->ngpr = nalu->dst.sel + 1;
1201 }
1202 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1203 /* each alu use 2 dwords */
1204 bc->cf_last->ndw += 2;
1205 bc->ndw += 2;
1206
1207 /* process cur ALU instructions for bank swizzle */
1208 if (nalu->last) {
1209 uint32_t literal[4];
1210 unsigned nliteral;
1211 struct r600_bytecode_alu *slots[5];
1212 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1213 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1214 if (r)
1215 return r;
1216
1217 if (bc->cf_last->prev_bs_head) {
1218 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1219 if (r)
1220 return r;
1221 }
1222
1223 if (bc->cf_last->prev_bs_head) {
1224 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1225 if (r)
1226 return r;
1227 }
1228
1229 r = check_and_set_bank_swizzle(bc, slots);
1230 if (r)
1231 return r;
1232
1233 for (i = 0, nliteral = 0; i < max_slots; i++) {
1234 if (slots[i]) {
1235 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1236 if (r)
1237 return r;
1238 }
1239 }
1240 bc->cf_last->ndw += align(nliteral, 2);
1241
1242 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1243 * worst case */
1244 if ((bc->cf_last->ndw >> 1) >= 120) {
1245 bc->force_add_cf = 1;
1246 }
1247
1248 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1249 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1250 bc->cf_last->curr_bs_head = NULL;
1251 }
1252
1253 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1254 insert_nop_r6xx(bc);
1255
1256 return 0;
1257 }
1258
1259 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1260 {
1261 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1262 }
1263
1264 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1265 {
1266 switch (bc->chip_class) {
1267 case R600:
1268 return 8;
1269
1270 case R700:
1271 case EVERGREEN:
1272 case CAYMAN:
1273 return 16;
1274
1275 default:
1276 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1277 return 8;
1278 }
1279 }
1280
1281 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1282 {
1283 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1284 (bc->chip_class == CAYMAN ||
1285 bc->cf_last->op != CF_OP_TEX));
1286 }
1287
1288 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1289 {
1290 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1291 int r;
1292
1293 if (nvtx == NULL)
1294 return -ENOMEM;
1295 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1296
1297 /* Load index register if required */
1298 if (bc->chip_class >= EVERGREEN) {
1299 if (vtx->buffer_index_mode)
1300 egcm_load_index_reg(bc, 0, false);
1301 }
1302
1303 /* cf can contains only alu or only vtx or only tex */
1304 if (bc->cf_last == NULL ||
1305 last_inst_was_not_vtx_fetch(bc) ||
1306 bc->force_add_cf) {
1307 r = r600_bytecode_add_cf(bc);
1308 if (r) {
1309 free(nvtx);
1310 return r;
1311 }
1312 switch (bc->chip_class) {
1313 case R600:
1314 case R700:
1315 case EVERGREEN:
1316 bc->cf_last->op = CF_OP_VTX;
1317 break;
1318 case CAYMAN:
1319 bc->cf_last->op = CF_OP_TEX;
1320 break;
1321 default:
1322 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1323 free(nvtx);
1324 return -EINVAL;
1325 }
1326 }
1327 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1328 /* each fetch use 4 dwords */
1329 bc->cf_last->ndw += 4;
1330 bc->ndw += 4;
1331 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1332 bc->force_add_cf = 1;
1333
1334 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1335 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1336
1337 return 0;
1338 }
1339
1340 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1341 {
1342 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1343 int r;
1344
1345 if (ntex == NULL)
1346 return -ENOMEM;
1347 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1348
1349 /* Load index register if required */
1350 if (bc->chip_class >= EVERGREEN) {
1351 if (tex->sampler_index_mode || tex->resource_index_mode)
1352 egcm_load_index_reg(bc, 1, false);
1353 }
1354
1355 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1356 if (bc->cf_last != NULL &&
1357 bc->cf_last->op == CF_OP_TEX) {
1358 struct r600_bytecode_tex *ttex;
1359 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1360 if (ttex->dst_gpr == ntex->src_gpr) {
1361 bc->force_add_cf = 1;
1362 break;
1363 }
1364 }
1365 /* slight hack to make gradients always go into same cf */
1366 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1367 bc->force_add_cf = 1;
1368 }
1369
1370 /* cf can contains only alu or only vtx or only tex */
1371 if (bc->cf_last == NULL ||
1372 bc->cf_last->op != CF_OP_TEX ||
1373 bc->force_add_cf) {
1374 r = r600_bytecode_add_cf(bc);
1375 if (r) {
1376 free(ntex);
1377 return r;
1378 }
1379 bc->cf_last->op = CF_OP_TEX;
1380 }
1381 if (ntex->src_gpr >= bc->ngpr) {
1382 bc->ngpr = ntex->src_gpr + 1;
1383 }
1384 if (ntex->dst_gpr >= bc->ngpr) {
1385 bc->ngpr = ntex->dst_gpr + 1;
1386 }
1387 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1388 /* each texture fetch use 4 dwords */
1389 bc->cf_last->ndw += 4;
1390 bc->ndw += 4;
1391 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1392 bc->force_add_cf = 1;
1393 return 0;
1394 }
1395
1396 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1397 {
1398 int r;
1399 r = r600_bytecode_add_cf(bc);
1400 if (r)
1401 return r;
1402
1403 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1404 bc->cf_last->op = op;
1405 return 0;
1406 }
1407
1408 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1409 {
1410 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1411 }
1412
1413 /* common to all 3 families */
1414 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1415 {
1416 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1417 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1418 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1419 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1420 if (bc->chip_class < CAYMAN)
1421 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1422 id++;
1423 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1424 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1425 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1426 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1427 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1428 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1429 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1430 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1431 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1432 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1433 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1434 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1435 if (bc->chip_class >= EVERGREEN)
1436 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1437 if (bc->chip_class < CAYMAN)
1438 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1439 id++;
1440 bc->bytecode[id++] = 0;
1441 return 0;
1442 }
1443
1444 /* common to all 3 families */
1445 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1446 {
1447 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1448 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1449 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1450 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1451 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1452 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1453 if (bc->chip_class >= EVERGREEN)
1454 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1455 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1456 id++;
1457 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1458 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1459 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1460 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1461 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1462 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1463 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1464 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1465 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1466 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1467 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1468 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1469 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1470 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1471 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1472 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1473 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1474 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1475 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1476 bc->bytecode[id++] = 0;
1477 return 0;
1478 }
1479
1480 /* r600 only, r700/eg bits in r700_asm.c */
1481 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1482 {
1483 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1484
1485 /* don't replace gpr by pv or ps for destination register */
1486 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1487 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1488 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1489 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1490 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1491 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1492 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1493 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1494 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1495 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1496 S_SQ_ALU_WORD0_LAST(alu->last);
1497
1498 if (alu->is_op3) {
1499 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1500 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1501 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1502 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1503 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1504 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1505 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1506 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1507 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1508 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1509 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1510 } else {
1511 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1512 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1513 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1514 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1515 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1516 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1517 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1518 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1519 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1520 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1521 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1522 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1523 }
1524 return 0;
1525 }
1526
1527 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1528 {
1529 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1530 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1531 S_SQ_CF_WORD1_BARRIER(1) |
1532 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1533 }
1534
1535 /* common for r600/r700 - eg in eg_asm.c */
1536 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1537 {
1538 unsigned id = cf->id;
1539 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1540 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1541
1542
1543 if (cf->op == CF_NATIVE) {
1544 bc->bytecode[id++] = cf->isa[0];
1545 bc->bytecode[id++] = cf->isa[1];
1546 } else if (cfop->flags & CF_ALU) {
1547 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1548 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1549 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1550 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1551
1552 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1553 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1554 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1555 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1556 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1557 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1558 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1559 } else if (cfop->flags & CF_FETCH) {
1560 if (bc->chip_class == R700)
1561 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1562 else
1563 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1564 } else if (cfop->flags & CF_EXP) {
1565 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1566 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1567 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1568 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1569 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1570 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1571 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1572 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1573 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1574 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1575 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1576 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1577 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1578 } else if (cfop->flags & CF_MEM) {
1579 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1580 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1581 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1582 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1583 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1584 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1585 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1586 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1587 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1588 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1589 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1590 } else {
1591 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1592 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1593 S_SQ_CF_WORD1_BARRIER(1) |
1594 S_SQ_CF_WORD1_COND(cf->cond) |
1595 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1596 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1597 }
1598 return 0;
1599 }
1600
1601 int r600_bytecode_build(struct r600_bytecode *bc)
1602 {
1603 struct r600_bytecode_cf *cf;
1604 struct r600_bytecode_alu *alu;
1605 struct r600_bytecode_vtx *vtx;
1606 struct r600_bytecode_tex *tex;
1607 uint32_t literal[4];
1608 unsigned nliteral;
1609 unsigned addr;
1610 int i, r;
1611
1612 if (!bc->nstack) // If not 0, Stack_size already provided by llvm
1613 bc->nstack = bc->stack.max_entries;
1614
1615 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1616 bc->nstack = 1;
1617 }
1618
1619 /* first path compute addr of each CF block */
1620 /* addr start after all the CF instructions */
1621 addr = bc->cf_last->id + 2;
1622 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1623 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1624 addr += 3;
1625 addr &= 0xFFFFFFFCUL;
1626 }
1627 cf->addr = addr;
1628 addr += cf->ndw;
1629 bc->ndw = cf->addr + cf->ndw;
1630 }
1631 free(bc->bytecode);
1632 bc->bytecode = calloc(4, bc->ndw);
1633 if (bc->bytecode == NULL)
1634 return -ENOMEM;
1635 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1636 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1637 addr = cf->addr;
1638 if (bc->chip_class >= EVERGREEN)
1639 r = eg_bytecode_cf_build(bc, cf);
1640 else
1641 r = r600_bytecode_cf_build(bc, cf);
1642 if (r)
1643 return r;
1644 if (cfop->flags & CF_ALU) {
1645 nliteral = 0;
1646 memset(literal, 0, sizeof(literal));
1647 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1648 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1649 if (r)
1650 return r;
1651 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1652 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1653
1654 switch(bc->chip_class) {
1655 case R600:
1656 r = r600_bytecode_alu_build(bc, alu, addr);
1657 break;
1658 case R700:
1659 case EVERGREEN: /* eg alu is same encoding as r700 */
1660 case CAYMAN:
1661 r = r700_bytecode_alu_build(bc, alu, addr);
1662 break;
1663 default:
1664 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1665 return -EINVAL;
1666 }
1667 if (r)
1668 return r;
1669 addr += 2;
1670 if (alu->last) {
1671 for (i = 0; i < align(nliteral, 2); ++i) {
1672 bc->bytecode[addr++] = literal[i];
1673 }
1674 nliteral = 0;
1675 memset(literal, 0, sizeof(literal));
1676 }
1677 }
1678 } else if (cf->op == CF_OP_VTX) {
1679 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1680 r = r600_bytecode_vtx_build(bc, vtx, addr);
1681 if (r)
1682 return r;
1683 addr += 4;
1684 }
1685 } else if (cf->op == CF_OP_TEX) {
1686 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1687 assert(bc->chip_class >= EVERGREEN);
1688 r = r600_bytecode_vtx_build(bc, vtx, addr);
1689 if (r)
1690 return r;
1691 addr += 4;
1692 }
1693 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1694 r = r600_bytecode_tex_build(bc, tex, addr);
1695 if (r)
1696 return r;
1697 addr += 4;
1698 }
1699 }
1700 }
1701 return 0;
1702 }
1703
1704 void r600_bytecode_clear(struct r600_bytecode *bc)
1705 {
1706 struct r600_bytecode_cf *cf = NULL, *next_cf;
1707
1708 free(bc->bytecode);
1709 bc->bytecode = NULL;
1710
1711 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1712 struct r600_bytecode_alu *alu = NULL, *next_alu;
1713 struct r600_bytecode_tex *tex = NULL, *next_tex;
1714 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1715
1716 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1717 free(alu);
1718 }
1719
1720 LIST_INITHEAD(&cf->alu);
1721
1722 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1723 free(tex);
1724 }
1725
1726 LIST_INITHEAD(&cf->tex);
1727
1728 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1729 free(vtx);
1730 }
1731
1732 LIST_INITHEAD(&cf->vtx);
1733
1734 free(cf);
1735 }
1736
1737 LIST_INITHEAD(&cf->list);
1738 }
1739
1740 static int print_swizzle(unsigned swz)
1741 {
1742 const char * swzchars = "xyzw01?_";
1743 assert(swz<8 && swz != 6);
1744 return fprintf(stderr, "%c", swzchars[swz]);
1745 }
1746
1747 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1748 unsigned need_brackets)
1749 {
1750 int o = 0;
1751 if (rel && index_mode >= 5 && sel < 128)
1752 o += fprintf(stderr, "G");
1753 if (rel || need_brackets) {
1754 o += fprintf(stderr, "[");
1755 }
1756 o += fprintf(stderr, "%d", sel);
1757 if (rel) {
1758 if (index_mode == 0 || index_mode == 6)
1759 o += fprintf(stderr, "+AR");
1760 else if (index_mode == 4)
1761 o += fprintf(stderr, "+AL");
1762 }
1763 if (rel || need_brackets) {
1764 o += fprintf(stderr, "]");
1765 }
1766 return o;
1767 }
1768
1769 static int print_dst(struct r600_bytecode_alu *alu)
1770 {
1771 int o = 0;
1772 unsigned sel = alu->dst.sel;
1773 char reg_char = 'R';
1774 if (sel > 128 - 4) { /* clause temporary gpr */
1775 sel -= 128 - 4;
1776 reg_char = 'T';
1777 }
1778
1779 if (alu->dst.write || alu->is_op3) {
1780 o += fprintf(stderr, "%c", reg_char);
1781 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1782 } else {
1783 o += fprintf(stderr, "__");
1784 }
1785 o += fprintf(stderr, ".");
1786 o += print_swizzle(alu->dst.chan);
1787 return o;
1788 }
1789
1790 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1791 {
1792 int o = 0;
1793 struct r600_bytecode_alu_src *src = &alu->src[idx];
1794 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1795
1796 if (src->neg)
1797 o += fprintf(stderr,"-");
1798 if (src->abs)
1799 o += fprintf(stderr,"|");
1800
1801 if (sel < 128 - 4) {
1802 o += fprintf(stderr, "R");
1803 } else if (sel < 128) {
1804 o += fprintf(stderr, "T");
1805 sel -= 128 - 4;
1806 } else if (sel < 160) {
1807 o += fprintf(stderr, "KC0");
1808 need_brackets = 1;
1809 sel -= 128;
1810 } else if (sel < 192) {
1811 o += fprintf(stderr, "KC1");
1812 need_brackets = 1;
1813 sel -= 160;
1814 } else if (sel >= 512) {
1815 o += fprintf(stderr, "C%d", src->kc_bank);
1816 need_brackets = 1;
1817 sel -= 512;
1818 } else if (sel >= 448) {
1819 o += fprintf(stderr, "Param");
1820 sel -= 448;
1821 need_chan = 0;
1822 } else if (sel >= 288) {
1823 o += fprintf(stderr, "KC3");
1824 need_brackets = 1;
1825 sel -= 288;
1826 } else if (sel >= 256) {
1827 o += fprintf(stderr, "KC2");
1828 need_brackets = 1;
1829 sel -= 256;
1830 } else {
1831 need_sel = 0;
1832 need_chan = 0;
1833 switch (sel) {
1834 case V_SQ_ALU_SRC_PS:
1835 o += fprintf(stderr, "PS");
1836 break;
1837 case V_SQ_ALU_SRC_PV:
1838 o += fprintf(stderr, "PV");
1839 need_chan = 1;
1840 break;
1841 case V_SQ_ALU_SRC_LITERAL:
1842 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value);
1843 break;
1844 case V_SQ_ALU_SRC_0_5:
1845 o += fprintf(stderr, "0.5");
1846 break;
1847 case V_SQ_ALU_SRC_M_1_INT:
1848 o += fprintf(stderr, "-1");
1849 break;
1850 case V_SQ_ALU_SRC_1_INT:
1851 o += fprintf(stderr, "1");
1852 break;
1853 case V_SQ_ALU_SRC_1:
1854 o += fprintf(stderr, "1.0");
1855 break;
1856 case V_SQ_ALU_SRC_0:
1857 o += fprintf(stderr, "0");
1858 break;
1859 default:
1860 o += fprintf(stderr, "??IMM_%d", sel);
1861 break;
1862 }
1863 }
1864
1865 if (need_sel)
1866 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
1867
1868 if (need_chan) {
1869 o += fprintf(stderr, ".");
1870 o += print_swizzle(src->chan);
1871 }
1872
1873 if (src->abs)
1874 o += fprintf(stderr,"|");
1875
1876 return o;
1877 }
1878
1879 static int print_indent(int p, int c)
1880 {
1881 int o = 0;
1882 while (p++ < c)
1883 o += fprintf(stderr, " ");
1884 return o;
1885 }
1886
1887 void r600_bytecode_disasm(struct r600_bytecode *bc)
1888 {
1889 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
1890 static int index = 0;
1891 struct r600_bytecode_cf *cf = NULL;
1892 struct r600_bytecode_alu *alu = NULL;
1893 struct r600_bytecode_vtx *vtx = NULL;
1894 struct r600_bytecode_tex *tex = NULL;
1895
1896 unsigned i, id, ngr = 0, last;
1897 uint32_t literal[4];
1898 unsigned nliteral;
1899 char chip = '6';
1900
1901 switch (bc->chip_class) {
1902 case R700:
1903 chip = '7';
1904 break;
1905 case EVERGREEN:
1906 chip = 'E';
1907 break;
1908 case CAYMAN:
1909 chip = 'C';
1910 break;
1911 case R600:
1912 default:
1913 chip = '6';
1914 break;
1915 }
1916 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1917 bc->ndw, bc->ngpr, bc->nstack);
1918 fprintf(stderr, "shader %d -- %c\n", index++, chip);
1919
1920 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1921 id = cf->id;
1922 if (cf->op == CF_NATIVE) {
1923 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
1924 bc->bytecode[id + 1]);
1925 } else {
1926 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1927 if (cfop->flags & CF_ALU) {
1928 if (cf->eg_alu_extended) {
1929 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
1930 bc->bytecode[id + 1], "ALU_EXT");
1931 id += 2;
1932 }
1933 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1934 bc->bytecode[id + 1], cfop->name);
1935 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
1936 for (i = 0; i < 4; ++i) {
1937 if (cf->kcache[i].mode) {
1938 int c_start = (cf->kcache[i].addr << 4);
1939 int c_end = c_start + (cf->kcache[i].mode << 4);
1940 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
1941 i, cf->kcache[i].bank, c_start, c_end,
1942 cf->kcache[i].index_mode ? " " : "",
1943 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
1944 }
1945 }
1946 fprintf(stderr, "\n");
1947 } else if (cfop->flags & CF_FETCH) {
1948 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1949 bc->bytecode[id + 1], cfop->name);
1950 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
1951 fprintf(stderr, "\n");
1952 } else if (cfop->flags & CF_EXP) {
1953 int o = 0;
1954 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
1955 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1956 bc->bytecode[id + 1], cfop->name);
1957 o += print_indent(o, 43);
1958 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1959 if (cf->output.burst_count > 1) {
1960 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1961 cf->output.array_base + cf->output.burst_count - 1);
1962
1963 o += print_indent(o, 55);
1964 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1965 cf->output.gpr + cf->output.burst_count - 1);
1966 } else {
1967 o += fprintf(stderr, "%d ", cf->output.array_base);
1968 o += print_indent(o, 55);
1969 o += fprintf(stderr, "R%d.", cf->output.gpr);
1970 }
1971
1972 o += print_swizzle(cf->output.swizzle_x);
1973 o += print_swizzle(cf->output.swizzle_y);
1974 o += print_swizzle(cf->output.swizzle_z);
1975 o += print_swizzle(cf->output.swizzle_w);
1976
1977 print_indent(o, 67);
1978
1979 fprintf(stderr, " ES:%X ", cf->output.elem_size);
1980 if (!cf->barrier)
1981 fprintf(stderr, "NO_BARRIER ");
1982 if (cf->end_of_program)
1983 fprintf(stderr, "EOP ");
1984 fprintf(stderr, "\n");
1985 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
1986 int o = 0;
1987 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
1988 "WRITE_IND_ACK"};
1989 o += fprintf(stderr, "%04d %08X %08X %s ", id,
1990 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
1991 o += print_indent(o, 43);
1992 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1993 if (cf->output.burst_count > 1) {
1994 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1995 cf->output.array_base + cf->output.burst_count - 1);
1996 o += print_indent(o, 55);
1997 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1998 cf->output.gpr + cf->output.burst_count - 1);
1999 } else {
2000 o += fprintf(stderr, "%d ", cf->output.array_base);
2001 o += print_indent(o, 55);
2002 o += fprintf(stderr, "R%d.", cf->output.gpr);
2003 }
2004 for (i = 0; i < 4; ++i) {
2005 if (cf->output.comp_mask & (1 << i))
2006 o += print_swizzle(i);
2007 else
2008 o += print_swizzle(7);
2009 }
2010
2011 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND)
2012 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2013
2014 o += print_indent(o, 67);
2015
2016 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2017 if (cf->output.array_size != 0xFFF)
2018 fprintf(stderr, "AS:%i ", cf->output.array_size);
2019 if (!cf->barrier)
2020 fprintf(stderr, "NO_BARRIER ");
2021 if (cf->end_of_program)
2022 fprintf(stderr, "EOP ");
2023 fprintf(stderr, "\n");
2024 } else {
2025 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2026 bc->bytecode[id + 1], cfop->name);
2027 fprintf(stderr, "@%d ", cf->cf_addr);
2028 if (cf->cond)
2029 fprintf(stderr, "CND:%X ", cf->cond);
2030 if (cf->pop_count)
2031 fprintf(stderr, "POP:%X ", cf->pop_count);
2032 if (cf->count && (cfop->flags & CF_EMIT))
2033 fprintf(stderr, "STREAM%d ", cf->count);
2034 if (cf->end_of_program)
2035 fprintf(stderr, "EOP ");
2036 fprintf(stderr, "\n");
2037 }
2038 }
2039
2040 id = cf->addr;
2041 nliteral = 0;
2042 last = 1;
2043 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2044 const char *omod_str[] = {"","*2","*4","/2"};
2045 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2046 int o = 0;
2047
2048 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2049 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2050 if (last)
2051 o += fprintf(stderr, "%4d ", ++ngr);
2052 else
2053 o += fprintf(stderr, " ");
2054 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2055 alu->update_pred ? 'P':' ',
2056 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2057
2058 o += fprintf(stderr, "%s%s%s ", aop->name,
2059 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2060
2061 o += print_indent(o,60);
2062 o += print_dst(alu);
2063 for (i = 0; i < aop->src_count; ++i) {
2064 o += fprintf(stderr, i == 0 ? ", ": ", ");
2065 o += print_src(alu, i);
2066 }
2067
2068 if (alu->bank_swizzle) {
2069 o += print_indent(o,75);
2070 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2071 }
2072
2073 fprintf(stderr, "\n");
2074 id += 2;
2075
2076 if (alu->last) {
2077 for (i = 0; i < nliteral; i++, id++) {
2078 float *f = (float*)(bc->bytecode + id);
2079 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2080 print_indent(o, 60);
2081 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2082 }
2083 id += nliteral & 1;
2084 nliteral = 0;
2085 }
2086 last = alu->last;
2087 }
2088
2089 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2090 int o = 0;
2091 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2092 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2093
2094 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2095
2096 o += print_indent(o, 50);
2097
2098 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2099 o += print_swizzle(tex->dst_sel_x);
2100 o += print_swizzle(tex->dst_sel_y);
2101 o += print_swizzle(tex->dst_sel_z);
2102 o += print_swizzle(tex->dst_sel_w);
2103
2104 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2105 o += print_swizzle(tex->src_sel_x);
2106 o += print_swizzle(tex->src_sel_y);
2107 o += print_swizzle(tex->src_sel_z);
2108 o += print_swizzle(tex->src_sel_w);
2109
2110 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2111 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2112
2113 if (tex->sampler_index_mode)
2114 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2115
2116 if (tex->lod_bias)
2117 fprintf(stderr, "LB:%d ", tex->lod_bias);
2118
2119 fprintf(stderr, "CT:%c%c%c%c ",
2120 tex->coord_type_x ? 'N' : 'U',
2121 tex->coord_type_y ? 'N' : 'U',
2122 tex->coord_type_z ? 'N' : 'U',
2123 tex->coord_type_w ? 'N' : 'U');
2124
2125 if (tex->offset_x)
2126 fprintf(stderr, "OX:%d ", tex->offset_x);
2127 if (tex->offset_y)
2128 fprintf(stderr, "OY:%d ", tex->offset_y);
2129 if (tex->offset_z)
2130 fprintf(stderr, "OZ:%d ", tex->offset_z);
2131
2132 id += 4;
2133 fprintf(stderr, "\n");
2134 }
2135
2136 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2137 int o = 0;
2138 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2139 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2140 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2141
2142 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2143
2144 o += print_indent(o, 50);
2145
2146 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2147 o += print_swizzle(vtx->dst_sel_x);
2148 o += print_swizzle(vtx->dst_sel_y);
2149 o += print_swizzle(vtx->dst_sel_z);
2150 o += print_swizzle(vtx->dst_sel_w);
2151
2152 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2153 o += print_swizzle(vtx->src_sel_x);
2154
2155 if (vtx->offset)
2156 fprintf(stderr, " +%db", vtx->offset);
2157
2158 o += print_indent(o, 55);
2159
2160 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2161
2162 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2163
2164 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2165 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2166
2167 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2168 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2169
2170 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2171 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2172 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2173 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2174 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2175
2176 id += 4;
2177 }
2178 }
2179
2180 fprintf(stderr, "--------------------------------------\n");
2181 }
2182
2183 void r600_vertex_data_type(enum pipe_format pformat,
2184 unsigned *format,
2185 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2186 {
2187 const struct util_format_description *desc;
2188 unsigned i;
2189
2190 *format = 0;
2191 *num_format = 0;
2192 *format_comp = 0;
2193 *endian = ENDIAN_NONE;
2194
2195 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2196 *format = FMT_10_11_11_FLOAT;
2197 *endian = r600_endian_swap(32);
2198 return;
2199 }
2200
2201 desc = util_format_description(pformat);
2202 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2203 goto out_unknown;
2204 }
2205
2206 /* Find the first non-VOID channel. */
2207 for (i = 0; i < 4; i++) {
2208 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2209 break;
2210 }
2211 }
2212
2213 *endian = r600_endian_swap(desc->channel[i].size);
2214
2215 switch (desc->channel[i].type) {
2216 /* Half-floats, floats, ints */
2217 case UTIL_FORMAT_TYPE_FLOAT:
2218 switch (desc->channel[i].size) {
2219 case 16:
2220 switch (desc->nr_channels) {
2221 case 1:
2222 *format = FMT_16_FLOAT;
2223 break;
2224 case 2:
2225 *format = FMT_16_16_FLOAT;
2226 break;
2227 case 3:
2228 case 4:
2229 *format = FMT_16_16_16_16_FLOAT;
2230 break;
2231 }
2232 break;
2233 case 32:
2234 switch (desc->nr_channels) {
2235 case 1:
2236 *format = FMT_32_FLOAT;
2237 break;
2238 case 2:
2239 *format = FMT_32_32_FLOAT;
2240 break;
2241 case 3:
2242 *format = FMT_32_32_32_FLOAT;
2243 break;
2244 case 4:
2245 *format = FMT_32_32_32_32_FLOAT;
2246 break;
2247 }
2248 break;
2249 default:
2250 goto out_unknown;
2251 }
2252 break;
2253 /* Unsigned ints */
2254 case UTIL_FORMAT_TYPE_UNSIGNED:
2255 /* Signed ints */
2256 case UTIL_FORMAT_TYPE_SIGNED:
2257 switch (desc->channel[i].size) {
2258 case 8:
2259 switch (desc->nr_channels) {
2260 case 1:
2261 *format = FMT_8;
2262 break;
2263 case 2:
2264 *format = FMT_8_8;
2265 break;
2266 case 3:
2267 case 4:
2268 *format = FMT_8_8_8_8;
2269 break;
2270 }
2271 break;
2272 case 10:
2273 if (desc->nr_channels != 4)
2274 goto out_unknown;
2275
2276 *format = FMT_2_10_10_10;
2277 break;
2278 case 16:
2279 switch (desc->nr_channels) {
2280 case 1:
2281 *format = FMT_16;
2282 break;
2283 case 2:
2284 *format = FMT_16_16;
2285 break;
2286 case 3:
2287 case 4:
2288 *format = FMT_16_16_16_16;
2289 break;
2290 }
2291 break;
2292 case 32:
2293 switch (desc->nr_channels) {
2294 case 1:
2295 *format = FMT_32;
2296 break;
2297 case 2:
2298 *format = FMT_32_32;
2299 break;
2300 case 3:
2301 *format = FMT_32_32_32;
2302 break;
2303 case 4:
2304 *format = FMT_32_32_32_32;
2305 break;
2306 }
2307 break;
2308 default:
2309 goto out_unknown;
2310 }
2311 break;
2312 default:
2313 goto out_unknown;
2314 }
2315
2316 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2317 *format_comp = 1;
2318 }
2319
2320 *num_format = 0;
2321 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2322 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2323 if (!desc->channel[i].normalized) {
2324 if (desc->channel[i].pure_integer)
2325 *num_format = 1;
2326 else
2327 *num_format = 2;
2328 }
2329 }
2330 return;
2331 out_unknown:
2332 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2333 }
2334
2335 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2336 unsigned count,
2337 const struct pipe_vertex_element *elements)
2338 {
2339 struct r600_context *rctx = (struct r600_context *)ctx;
2340 struct r600_bytecode bc;
2341 struct r600_bytecode_vtx vtx;
2342 const struct util_format_description *desc;
2343 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2344 unsigned format, num_format, format_comp, endian;
2345 uint32_t *bytecode;
2346 int i, j, r, fs_size;
2347 struct r600_fetch_shader *shader;
2348 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2349 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2350
2351 assert(count < 32);
2352
2353 memset(&bc, 0, sizeof(bc));
2354 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2355 rctx->screen->has_compressed_msaa_texturing);
2356
2357 bc.isa = rctx->isa;
2358
2359 for (i = 0; i < count; i++) {
2360 if (elements[i].instance_divisor > 1) {
2361 if (rctx->b.chip_class == CAYMAN) {
2362 for (j = 0; j < 4; j++) {
2363 struct r600_bytecode_alu alu;
2364 memset(&alu, 0, sizeof(alu));
2365 alu.op = ALU_OP2_MULHI_UINT;
2366 alu.src[0].sel = 0;
2367 alu.src[0].chan = 3;
2368 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2369 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2370 alu.dst.sel = i + 1;
2371 alu.dst.chan = j;
2372 alu.dst.write = j == 3;
2373 alu.last = j == 3;
2374 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2375 r600_bytecode_clear(&bc);
2376 return NULL;
2377 }
2378 }
2379 } else {
2380 struct r600_bytecode_alu alu;
2381 memset(&alu, 0, sizeof(alu));
2382 alu.op = ALU_OP2_MULHI_UINT;
2383 alu.src[0].sel = 0;
2384 alu.src[0].chan = 3;
2385 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2386 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2387 alu.dst.sel = i + 1;
2388 alu.dst.chan = 3;
2389 alu.dst.write = 1;
2390 alu.last = 1;
2391 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2392 r600_bytecode_clear(&bc);
2393 return NULL;
2394 }
2395 }
2396 }
2397 }
2398
2399 for (i = 0; i < count; i++) {
2400 r600_vertex_data_type(elements[i].src_format,
2401 &format, &num_format, &format_comp, &endian);
2402
2403 desc = util_format_description(elements[i].src_format);
2404 if (desc == NULL) {
2405 r600_bytecode_clear(&bc);
2406 R600_ERR("unknown format %d\n", elements[i].src_format);
2407 return NULL;
2408 }
2409
2410 if (elements[i].src_offset > 65535) {
2411 r600_bytecode_clear(&bc);
2412 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2413 return NULL;
2414 }
2415
2416 memset(&vtx, 0, sizeof(vtx));
2417 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2418 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2419 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2420 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2421 vtx.mega_fetch_count = 0x1F;
2422 vtx.dst_gpr = i + 1;
2423 vtx.dst_sel_x = desc->swizzle[0];
2424 vtx.dst_sel_y = desc->swizzle[1];
2425 vtx.dst_sel_z = desc->swizzle[2];
2426 vtx.dst_sel_w = desc->swizzle[3];
2427 vtx.data_format = format;
2428 vtx.num_format_all = num_format;
2429 vtx.format_comp_all = format_comp;
2430 vtx.offset = elements[i].src_offset;
2431 vtx.endian = endian;
2432
2433 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2434 r600_bytecode_clear(&bc);
2435 return NULL;
2436 }
2437 }
2438
2439 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2440
2441 if ((r = r600_bytecode_build(&bc))) {
2442 r600_bytecode_clear(&bc);
2443 return NULL;
2444 }
2445
2446 if (rctx->screen->b.debug_flags & DBG_FS) {
2447 fprintf(stderr, "--------------------------------------------------------------\n");
2448 fprintf(stderr, "Vertex elements state:\n");
2449 for (i = 0; i < count; i++) {
2450 fprintf(stderr, " ");
2451 util_dump_vertex_element(stderr, elements+i);
2452 fprintf(stderr, "\n");
2453 }
2454
2455 if (!sb_disasm) {
2456 r600_bytecode_disasm(&bc);
2457
2458 fprintf(stderr, "______________________________________________________________\n");
2459 } else {
2460 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2461 }
2462 }
2463
2464 fs_size = bc.ndw*4;
2465
2466 /* Allocate the CSO. */
2467 shader = CALLOC_STRUCT(r600_fetch_shader);
2468 if (!shader) {
2469 r600_bytecode_clear(&bc);
2470 return NULL;
2471 }
2472
2473 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2474 (struct pipe_resource**)&shader->buffer);
2475 if (!shader->buffer) {
2476 r600_bytecode_clear(&bc);
2477 FREE(shader);
2478 return NULL;
2479 }
2480
2481 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2482 bytecode += shader->offset / 4;
2483
2484 if (R600_BIG_ENDIAN) {
2485 for (i = 0; i < fs_size / 4; ++i) {
2486 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2487 }
2488 } else {
2489 memcpy(bytecode, bc.bytecode, fs_size);
2490 }
2491 rctx->b.ws->buffer_unmap(shader->buffer->cs_buf);
2492
2493 r600_bytecode_clear(&bc);
2494 return shader;
2495 }
2496
2497 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2498 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2499 {
2500 /* WORD0 */
2501 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2502 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2503 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2504 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2505 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2506 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2507 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2508 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2509 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2510 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2511 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2512
2513 /* WORD1 */
2514 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2515 if (alu->bank_swizzle)
2516 alu->bank_swizzle_force = alu->bank_swizzle;
2517 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2518 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2519 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2520 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2521 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2522 {
2523 alu->is_op3 = 1;
2524 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2525 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2526 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2527 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2528 alu->op = r600_isa_alu_by_opcode(bc->isa,
2529 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2530
2531 }
2532 else /*ALU_DWORD1_OP2*/
2533 {
2534 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2535 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2536 alu->op = r600_isa_alu_by_opcode(bc->isa,
2537 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2538 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2539 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2540 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2541 alu->execute_mask =
2542 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2543 }
2544 }
2545
2546 #if 0
2547 void r600_bytecode_export_read(struct r600_bytecode *bc,
2548 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2549 {
2550 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2551 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2552 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2553 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2554
2555 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2556 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2557 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2558 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2559 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2560 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2561 output->op = r600_isa_cf_by_opcode(bc->isa,
2562 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2563 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2564 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2565 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2566 }
2567 #endif