2 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_blitter.h>
30 #include <util/u_inlines.h>
31 #include <util/u_memory.h>
32 #include "util/u_surface.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
37 static void r600_blitter_save_states(struct pipe_context
*ctx
)
39 struct r600_context
*rctx
= r600_context(ctx
);
41 util_blitter_save_blend(rctx
->blitter
, rctx
->blend
);
42 util_blitter_save_depth_stencil_alpha(rctx
->blitter
, rctx
->dsa
);
43 if (rctx
->stencil_ref
) {
44 util_blitter_save_stencil_ref(rctx
->blitter
,
45 &rctx
->stencil_ref
->state
.stencil_ref
);
47 util_blitter_save_rasterizer(rctx
->blitter
, rctx
->rasterizer
);
48 util_blitter_save_fragment_shader(rctx
->blitter
, rctx
->ps_shader
);
49 util_blitter_save_vertex_shader(rctx
->blitter
, rctx
->vs_shader
);
50 util_blitter_save_vertex_elements(rctx
->blitter
, rctx
->vertex_elements
);
52 util_blitter_save_viewport(rctx
->blitter
, &rctx
->viewport
->state
.viewport
);
55 util_blitter_save_clip(rctx
->blitter
, &rctx
->clip
->state
.clip
);
57 util_blitter_save_vertex_buffers(rctx
->blitter
, rctx
->nvertex_buffer
,
60 /* remove ptr so they don't get deleted */
63 rctx
->vs_shader
= NULL
;
64 rctx
->ps_shader
= NULL
;
65 rctx
->rasterizer
= NULL
;
67 rctx
->vertex_elements
= NULL
;
70 r600_queries_suspend(ctx
);
73 static void r600_clear(struct pipe_context
*ctx
, unsigned buffers
,
74 const float *rgba
, double depth
, unsigned stencil
)
76 struct r600_context
*rctx
= r600_context(ctx
);
77 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
79 r600_blitter_save_states(ctx
);
80 util_blitter_clear(rctx
->blitter
, fb
->width
, fb
->height
,
81 fb
->nr_cbufs
, buffers
, rgba
, depth
,
84 r600_queries_resume(ctx
);
87 static void r600_clear_render_target(struct pipe_context
*ctx
,
88 struct pipe_surface
*dst
,
90 unsigned dstx
, unsigned dsty
,
91 unsigned width
, unsigned height
)
93 struct r600_context
*rctx
= r600_context(ctx
);
94 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
96 r600_blitter_save_states(ctx
);
97 util_blitter_save_framebuffer(rctx
->blitter
, fb
);
99 util_blitter_clear_render_target(rctx
->blitter
, dst
, rgba
,
100 dstx
, dsty
, width
, height
);
102 r600_queries_resume(ctx
);
105 static void r600_clear_depth_stencil(struct pipe_context
*ctx
,
106 struct pipe_surface
*dst
,
107 unsigned clear_flags
,
110 unsigned dstx
, unsigned dsty
,
111 unsigned width
, unsigned height
)
113 struct r600_context
*rctx
= r600_context(ctx
);
114 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
116 r600_blitter_save_states(ctx
);
117 util_blitter_save_framebuffer(rctx
->blitter
, fb
);
119 util_blitter_clear_depth_stencil(rctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
120 dstx
, dsty
, width
, height
);
122 r600_queries_resume(ctx
);
126 static void r600_resource_copy_region(struct pipe_context
*ctx
,
127 struct pipe_resource
*dst
,
128 struct pipe_subresource subdst
,
129 unsigned dstx
, unsigned dsty
, unsigned dstz
,
130 struct pipe_resource
*src
,
131 struct pipe_subresource subsrc
,
132 unsigned srcx
, unsigned srcy
, unsigned srcz
,
133 unsigned width
, unsigned height
)
135 util_resource_copy_region(ctx
, dst
, subdst
, dstx
, dsty
, dstz
,
136 src
, subsrc
, srcx
, srcy
, srcz
, width
, height
);
139 void r600_init_blit_functions(struct r600_context
*rctx
)
141 rctx
->context
.clear
= r600_clear
;
142 rctx
->context
.clear_render_target
= r600_clear_render_target
;
143 rctx
->context
.clear_depth_stencil
= r600_clear_depth_stencil
;
144 rctx
->context
.resource_copy_region
= r600_resource_copy_region
;
148 struct r600_blit_states
{
149 struct radeon_state rasterizer
;
150 struct radeon_state dsa
;
151 struct radeon_state blend
;
152 struct radeon_state cb_cntl
;
153 struct radeon_state vgt
;
154 struct radeon_state draw
;
155 struct radeon_state vs_constant0
;
156 struct radeon_state vs_constant1
;
157 struct radeon_state vs_constant2
;
158 struct radeon_state vs_constant3
;
159 struct radeon_state ps_shader
;
160 struct radeon_state vs_shader
;
161 struct radeon_state vs_resource0
;
162 struct radeon_state vs_resource1
;
163 struct radeon_state cb_flush
;
164 struct radeon_state db_flush
;
167 static int r600_blit_state_vs_resources(struct r600_screen
*rscreen
, struct r600_blit_states
*bstates
)
169 struct radeon_state
*rstate
;
170 struct radeon_ws_bo
*bo
;
173 -1.0, -1.0, 1.0, 1.0,
183 bo
= radeon_ws_bo(rscreen
->rw
, 128, 4096, 0);
187 data
= radeon_ws_bo_map(rscreen
->rw
, bo
, 0, NULL
);
189 radeon_ws_bo_reference(rscreen
->rw
, &bo
, NULL
);
192 memcpy(data
, vbo
, 128);
193 radeon_ws_bo_unmap(rscreen
->rw
, bo
);
195 rstate
= &bstates
->vs_resource0
;
196 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RESOURCE
, 0, R600_SHADER_VS
);
198 /* set states (most default value are 0 and struct already
199 * initialized to 0, thus avoid resetting them)
201 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD0
] = 0x00000000;
202 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD1
] = 0x00000080;
203 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD2
] = 0x02302000;
204 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD3
] = 0x00000000;
205 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD4
] = 0x00000000;
206 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD5
] = 0x00000000;
207 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD6
] = 0xC0000000;
210 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
211 if (radeon_state_pm4(rstate
)) {
212 radeon_state_fini(rstate
);
216 rstate
= &bstates
->vs_resource1
;
217 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RESOURCE
, 1, R600_SHADER_VS
);
218 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD0
] = 0x00000010;
219 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD1
] = 0x00000070;
220 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD2
] = 0x02302000;
221 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD3
] = 0x00000000;
222 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD4
] = 0x00000000;
223 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD5
] = 0x00000000;
224 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD6
] = 0xC0000000;
225 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[0], bo
);
227 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
228 if (radeon_state_pm4(rstate
)) {
229 radeon_state_fini(rstate
);
236 static void r600_blit_state_vs_shader(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
238 struct radeon_ws_bo
*bo
;
240 u32 shader_bc_r600
[] = {
241 0x00000004, 0x81000400,
242 0x00000008, 0xA01C0000,
243 0xC001A03C, 0x94000688,
244 0xC0024000, 0x94200688,
245 0x7C000000, 0x002D1001,
246 0x00080000, 0x00000000,
247 0x7C000100, 0x002D1002,
248 0x00080000, 0x00000000,
249 0x00000001, 0x00601910,
250 0x00000401, 0x20601910,
251 0x00000801, 0x40601910,
252 0x80000C01, 0x60601910,
253 0x00000002, 0x00801910,
254 0x00000402, 0x20801910,
255 0x00000802, 0x40801910,
256 0x80000C02, 0x60801910
258 u32 shader_bc_r700
[] = {
259 0x00000004, 0x81000400,
260 0x00000008, 0xA01C0000,
261 0xC001A03C, 0x94000688,
262 0xC0024000, 0x94200688,
263 0x7C000000, 0x002D1001,
264 0x00080000, 0x00000000,
265 0x7C000100, 0x002D1002,
266 0x00080000, 0x00000000,
267 0x00000001, 0x00600C90,
268 0x00000401, 0x20600C90,
269 0x00000801, 0x40600C90,
270 0x80000C01, 0x60600C90,
271 0x00000002, 0x00800C90,
272 0x00000402, 0x20800C90,
273 0x00000802, 0x40800C90,
274 0x80000C02, 0x60800C90
278 bo
= radeon_ws_bo(rscreen
->rw
, 128, 4096, 0);
282 data
= radeon_ws_bo_map(rscreen
->rw
, bo
, 0, NULL
);
284 radeon_ws_bo_reference(rscreen
->rw
, &bo
, NULL
);
287 switch (radeon_get_family_class(rscreen
->rw
)) {
289 memcpy(data
, shader_bc_r600
, 128);
292 memcpy(data
, shader_bc_r700
, 128);
295 R600_ERR("unsupported chip family\n");
296 radeon_ws_bo_unmap(rscreen
->rw
, bo
);
297 radeon_ws_bo_reference(rscreen
->rw
, &bo
, NULL
);
300 radeon_ws_bo_unmap(rscreen
->rw
, bo
);
302 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_VS
);
304 /* set states (most default value are 0 and struct already
305 * initialized to 0, thus avoid resetting them)
307 rstate
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
] = 0x03020100;
308 rstate
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_1
] = 0x07060504;
309 rstate
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = 0x00000005;
312 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[1], bo
);
314 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
315 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
317 radeon_state_pm4(rstate
);
320 static void r600_blit_state_ps_shader(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
322 struct radeon_ws_bo
*bo
;
324 u32 shader_bc_r600
[] = {
325 0x00000002, 0xA00C0000,
326 0xC0008000, 0x94200688,
327 0x00000000, 0x00201910,
328 0x00000400, 0x20201910,
329 0x00000800, 0x40201910,
330 0x80000C00, 0x60201910
332 u32 shader_bc_r700
[] = {
333 0x00000002, 0xA00C0000,
334 0xC0008000, 0x94200688,
335 0x00000000, 0x00200C90,
336 0x00000400, 0x20200C90,
337 0x00000800, 0x40200C90,
338 0x80000C00, 0x60200C90
342 bo
= radeon_ws_bo(rscreen
->rw
, 128, 4096, 0);
346 data
= radeon_ws_bo_map(rscreen
->rw
, bo
, 0, NULL
);
348 radeon_ws_bo_reference(rscreen
->rw
, &bo
, NULL
);
351 switch (radeon_get_family_class(rscreen
->rw
)) {
353 memcpy(data
, shader_bc_r600
, 48);
356 memcpy(data
, shader_bc_r700
, 48);
359 R600_ERR("unsupported chip family\n");
360 radeon_ws_bo_unmap(rscreen
->rw
, bo
);
361 radeon_ws_bo_reference(rscreen
->rw
, &bo
, NULL
);
364 radeon_ws_bo_unmap(rscreen
->rw
, bo
);
366 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_PS
);
368 /* set states (most default value are 0 and struct already
369 * initialized to 0, thus avoid resetting them)
371 rstate
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
] = 0x00000C00;
372 rstate
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = 0x10000001;
373 rstate
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = 0x00000002;
374 rstate
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = 0x00000002;
378 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
380 radeon_state_pm4(rstate
);
383 static void r600_blit_state_vgt(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
385 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_VGT
, 0, 0);
387 /* set states (most default value are 0 and struct already
388 * initialized to 0, thus avoid resetting them)
390 rstate
->states
[R600_VGT__VGT_DMA_NUM_INSTANCES
] = 0x00000001;
391 rstate
->states
[R600_VGT__VGT_MAX_VTX_INDX
] = 0x00FFFFFF;
392 rstate
->states
[R600_VGT__VGT_PRIMITIVE_TYPE
] = 0x00000005;
394 radeon_state_pm4(rstate
);
397 static void r600_blit_state_draw(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
399 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DRAW
, 0, 0);
401 /* set states (most default value are 0 and struct already
402 * initialized to 0, thus avoid resetting them)
404 rstate
->states
[R600_DRAW__VGT_DRAW_INITIATOR
] = 0x00000002;
405 rstate
->states
[R600_DRAW__VGT_NUM_INDICES
] = 0x00000004;
407 radeon_state_pm4(rstate
);
410 static void r600_blit_state_vs_constant(struct r600_screen
*rscreen
, struct radeon_state
*rstate
,
411 unsigned id
, float c0
, float c1
, float c2
, float c3
)
413 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CONSTANT
, id
, R600_SHADER_VS
);
415 /* set states (most default value are 0 and struct already
416 * initialized to 0, thus avoid resetting them)
418 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256
] = fui(c0
);
419 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256
] = fui(c1
);
420 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256
] = fui(c2
);
421 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256
] = fui(c3
);
423 radeon_state_pm4(rstate
);
426 static void r600_blit_state_rasterizer(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
428 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RASTERIZER
, 0, 0);
430 /* set states (most default value are 0 and struct already
431 * initialized to 0, thus avoid resetting them)
433 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ
] = 0x3F800000;
434 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ
] = 0x3F800000;
435 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ
] = 0x3F800000;
436 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ
] = 0x3F800000;
437 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_CNTL
] = 0x00000400;
438 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_STIPPLE
] = 0x00000005;
439 rstate
->states
[R600_RASTERIZER__PA_SU_LINE_CNTL
] = 0x00000008;
440 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_MINMAX
] = 0x80000000;
441 rstate
->states
[R600_RASTERIZER__PA_SU_SC_MODE_CNTL
] = 0x00080004;
442 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] = 0x00000001;
444 radeon_state_pm4(rstate
);
447 static void r600_blit_state_dsa(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
449 uint32_t db_render_override
, db_shader_control
;
450 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DSA
, 0, 0);
452 /* set states (most default value are 0 and struct already
453 * initialized to 0, thus avoid resetting them)
455 rstate
->states
[R600_DSA__DB_ALPHA_TO_MASK
] = 0x0000AA00;
456 rstate
->states
[R600_DSA__DB_DEPTH_CLEAR
] = 0x3F800000;
457 rstate
->states
[R600_DSA__DB_RENDER_CONTROL
] = 0x00000060;
459 db_render_override
= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
460 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
461 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
463 db_shader_control
= S_02880C_DUAL_EXPORT_ENABLE(0) |
464 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
466 rstate
->states
[R600_DSA__DB_RENDER_OVERRIDE
] = db_render_override
;
467 rstate
->states
[R600_DSA__DB_SHADER_CONTROL
] = db_shader_control
;
469 radeon_state_pm4(rstate
);
472 static void r600_blit_state_blend(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
474 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_BLEND
, 0, 0);
475 radeon_state_pm4(rstate
);
478 static void r600_blit_state_cb_cntl(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
480 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB_CNTL
, 0, 0);
481 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
482 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
483 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
484 rstate
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = 0x00CC0080;
485 rstate
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = 0x0000000F;
486 rstate
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = 0x0000000F;
487 rstate
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
488 rstate
->states
[R600_CB_CNTL__CB_SHADER_CONTROL
] = 0x1;
489 radeon_state_pm4(rstate
);
492 static void r600_blit_state_cb_flush(struct r600_screen
*rscreen
, struct radeon_state
*rstate
, struct r600_resource_texture
*rtexture
, unsigned cb
, unsigned level
)
494 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB_FLUSH
, 0, 0);
496 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[0], rtexture
->uncompressed
);
498 radeon_state_pm4(rstate
);
501 static void r600_blit_state_db_flush(struct r600_screen
*rscreen
, struct radeon_state
*rstate
, struct r600_resource_texture
*rtexture
, unsigned cb
, unsigned level
)
503 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DB_FLUSH
, 0, 0);
505 radeon_ws_bo_reference(rscreen
->rw
, &rstate
->bo
[0], rtexture
->resource
.bo
);
507 radeon_state_pm4(rstate
);
510 static int r600_blit_states_init(struct pipe_context
*ctx
, struct r600_blit_states
*bstates
)
512 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
514 r600_blit_state_ps_shader(rscreen
, &bstates
->ps_shader
);
515 r600_blit_state_vs_shader(rscreen
, &bstates
->vs_shader
);
516 r600_blit_state_vgt(rscreen
, &bstates
->vgt
);
517 r600_blit_state_draw(rscreen
, &bstates
->draw
);
518 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant0
, 0, 1.0, 0.0, 0.0, 0.0);
519 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant1
, 1, 0.0, 1.0, 0.0, 0.0);
520 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant2
, 2, 0.0, 0.0, -0.00199900055, 0.0);
521 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant3
, 3, 0.0, 0.0, -0.99900049, 1.0);
522 r600_blit_state_rasterizer(rscreen
, &bstates
->rasterizer
);
523 r600_blit_state_dsa(rscreen
, &bstates
->dsa
);
524 r600_blit_state_blend(rscreen
, &bstates
->blend
);
525 r600_blit_state_cb_cntl(rscreen
, &bstates
->cb_cntl
);
526 r600_blit_state_vs_resources(rscreen
, bstates
);
530 static void r600_blit_states_destroy(struct pipe_context
*ctx
, struct r600_blit_states
*bstates
)
532 radeon_state_fini(&bstates
->ps_shader
);
533 radeon_state_fini(&bstates
->vs_shader
);
534 radeon_state_fini(&bstates
->vs_resource0
);
535 radeon_state_fini(&bstates
->vs_resource1
);
538 int r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*rtexture
, unsigned level
)
540 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
541 struct r600_context
*rctx
= r600_context(ctx
);
542 struct radeon_draw draw
;
543 struct r600_blit_states bstates
;
544 enum radeon_family family
;
547 r
= r600_texture_scissor(ctx
, rtexture
, level
);
551 r
= r600_texture_cb(ctx
, rtexture
, 0, level
);
555 r
= r600_texture_db(ctx
, rtexture
, level
);
559 r
= r600_texture_viewport(ctx
, rtexture
, level
);
564 r
= r600_blit_states_init(ctx
, &bstates
);
569 /* for some gpus we need special cases */
570 family
= radeon_get_family(rscreen
->rw
);
571 /* according to R6xx_R7xx_3D.pdf section 6.3.1, these GPUs needs special handling */
572 if (family
== CHIP_RV610
|| family
== CHIP_RV630
|| family
== CHIP_RV620
||
573 family
== CHIP_RV635
) {
574 bstates
.dsa
.states
[R600_DSA__DB_DEPTH_CONTROL
] = S_028800_Z_ENABLE(1) |
575 S_028800_STENCIL_ENABLE(1) | S_028800_ZFUNC(PIPE_FUNC_LEQUAL
) |
576 S_028800_STENCILFUNC(PIPE_FUNC_ALWAYS
) |
577 S_028800_STENCILZPASS(V_028800_STENCIL_KEEP
) |
578 S_028800_STENCILZFAIL(V_028800_STENCIL_INCR
);
580 bstates
.dsa
.states
[R600_DSA__DB_STENCILREFMASK
] = S_028430_STENCILWRITEMASK(0xff);
582 bstates
.dsa
.states
[R600_DSA__DB_RENDER_CONTROL
] = S_028D0C_DEPTH_COPY_ENABLE(1) |
583 S_028D0C_STENCIL_COPY_ENABLE(1) |
584 S_028D0C_COPY_CENTROID(1);
586 bstates
.cb_cntl
.states
[R600_CB_CNTL__CB_TARGET_MASK
] = 0x00000003;
587 r600_blit_state_cb_flush(rscreen
, &bstates
.cb_flush
, rtexture
, 0, 0);
588 r600_blit_state_db_flush(rscreen
, &bstates
.db_flush
, rtexture
, 0, 0);
591 bstates
.dsa
.cpm4
= bstates
.cb_cntl
.cpm4
= 0;
592 if (radeon_state_pm4(&bstates
.dsa
)) {
595 if (radeon_state_pm4(&bstates
.cb_cntl
)) {
599 r
= radeon_draw_init(&draw
, rscreen
->rw
);
601 R600_ERR("failed creating draw for uncompressing textures\n");
605 radeon_draw_bind(&draw
, &bstates
.vs_shader
);
606 radeon_draw_bind(&draw
, &bstates
.ps_shader
);
607 radeon_draw_bind(&draw
, &bstates
.rasterizer
);
608 radeon_draw_bind(&draw
, &bstates
.dsa
);
609 radeon_draw_bind(&draw
, &bstates
.blend
);
610 radeon_draw_bind(&draw
, &bstates
.cb_cntl
);
611 radeon_draw_bind(&draw
, &rctx
->config
);
612 radeon_draw_bind(&draw
, &bstates
.vgt
);
613 radeon_draw_bind(&draw
, &bstates
.draw
);
614 radeon_draw_bind(&draw
, &bstates
.cb_flush
);
615 radeon_draw_bind(&draw
, &bstates
.db_flush
);
616 radeon_draw_bind(&draw
, &bstates
.vs_resource0
);
617 radeon_draw_bind(&draw
, &bstates
.vs_resource1
);
618 radeon_draw_bind(&draw
, &bstates
.vs_constant0
);
619 radeon_draw_bind(&draw
, &bstates
.vs_constant1
);
620 radeon_draw_bind(&draw
, &bstates
.vs_constant2
);
621 radeon_draw_bind(&draw
, &bstates
.vs_constant3
);
622 radeon_draw_bind(&draw
, &rtexture
->viewport
[level
]);
623 radeon_draw_bind(&draw
, &rtexture
->scissor
[level
]);
624 radeon_draw_bind(&draw
, &rtexture
->cb
[0][level
]);
625 radeon_draw_bind(&draw
, &rtexture
->db
[level
]);
627 /* suspend queries */
628 r600_queries_suspend(ctx
);
631 r
= radeon_ctx_set_draw(rctx
->ctx
, &draw
);
633 r600_flush(ctx
, 0, NULL
);
634 r
= radeon_ctx_set_draw(rctx
->ctx
, &draw
);
641 r600_queries_resume(ctx
);
644 r600_blit_states_destroy(ctx
, &bstates
);