src/gallium/drivers/r600/r600_llvm.c

   1 #include "r600_llvm.h"
   2
   3 #include "gallivm/lp_bld_const.h"
   4 #include "gallivm/lp_bld_intr.h"
   5 #include "gallivm/lp_bld_gather.h"
   6 #include "tgsi/tgsi_parse.h"
   7 #include "util/u_double_list.h"
   8 #include "util/u_memory.h"
   9
  10 #include "r600_asm.h"
  11 #include "r600_sq.h"
  12 #include "r600_opcodes.h"
  13 #include "r600_shader.h"
  14 #include "r600_pipe.h"
  15 #include "radeon_llvm.h"
  16 #include "radeon_llvm_emit.h"
  17
  18 #include <stdio.h>
  19
  20 #if defined R600_USE_LLVM || defined HAVE_OPENCL
  21
  22 #define CONSTANT_BUFFER_0_ADDR_SPACE 8
  23 #define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + R600_UCP_CONST_BUFFER)
  24
  25 static LLVMValueRef llvm_fetch_const(
  26         struct lp_build_tgsi_context * bld_base,
  27         const struct tgsi_full_src_register *reg,
  28         enum tgsi_opcode_type type,
  29         unsigned swizzle)
  30 {
  31         LLVMValueRef offset[2] = {
  32                 LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
  33                 lp_build_const_int32(bld_base->base.gallivm, reg->Register.Index)
  34         };
  35         if (reg->Register.Indirect) {
  36                 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
  37                 LLVMValueRef index = LLVMBuildLoad(bld_base->base.gallivm->builder, bld->addr[reg->Indirect.Index][reg->Indirect.SwizzleX], "");
  38                 offset[1] = LLVMBuildAdd(bld_base->base.gallivm->builder, offset[1], index, "");
  39         }
  40         unsigned ConstantAddressSpace = CONSTANT_BUFFER_0_ADDR_SPACE ;
  41         if (reg->Register.Dimension) {
  42                 ConstantAddressSpace += reg->Dimension.Index;
  43         }
  44         LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024),
  45                                                         ConstantAddressSpace);
  46         LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
  47         LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
  48         LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
  49         LLVMValueRef cval = LLVMBuildExtractElement(bld_base->base.gallivm->builder, cvecval, lp_build_const_int32(bld_base->base.gallivm, swizzle), "");
  50         return bitcast(bld_base, type, cval);
  51 }
  52
  53 static void llvm_load_system_value(
  54                 struct radeon_llvm_context * ctx,
  55                 unsigned index,
  56                 const struct tgsi_full_declaration *decl)
  57 {
  58         unsigned chan;
  59
  60         switch (decl->Semantic.Name) {
  61         case TGSI_SEMANTIC_INSTANCEID: chan = 3; break;
  62         case TGSI_SEMANTIC_VERTEXID: chan = 0; break;
  63         default: assert(!"unknown system value");
  64         }
  65
  66         LLVMValueRef reg = lp_build_const_int32(
  67                         ctx->soa.bld_base.base.gallivm, chan);
  68         ctx->system_values[index] = build_intrinsic(
  69                         ctx->soa.bld_base.base.gallivm->builder,
  70                         "llvm.R600.load.input",
  71                         ctx->soa.bld_base.base.elem_type, &reg, 1,
  72                         LLVMReadNoneAttribute);
  73 }
  74
  75 static LLVMValueRef llvm_fetch_system_value(
  76                 struct lp_build_tgsi_context * bld_base,
  77                 const struct tgsi_full_src_register *reg,
  78                 enum tgsi_opcode_type type,
  79                 unsigned swizzle)
  80 {
  81         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
  82         LLVMValueRef cval = ctx->system_values[reg->Register.Index];
  83         return bitcast(bld_base, type, cval);
  84 }
  85
  86 static LLVMValueRef
  87 llvm_load_input_helper(
  88         struct radeon_llvm_context * ctx,
  89         unsigned idx, int interp, int ij_index)
  90 {
  91         const struct lp_build_context * bb = &ctx->soa.bld_base.base;
  92         LLVMValueRef arg[2];
  93         int arg_count;
  94         const char * intrinsic;
  95
  96         arg[0] = lp_build_const_int32(bb->gallivm, idx);
  97
  98         if (interp) {
  99                 intrinsic = "llvm.R600.interp.input";
 100                 arg[1] = lp_build_const_int32(bb->gallivm, ij_index);
 101                 arg_count = 2;
 102         } else {
 103                 intrinsic = "llvm.R600.load.input";
 104                 arg_count = 1;
 105         }
 106
 107         return build_intrinsic(bb->gallivm->builder, intrinsic,
 108                 bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute);
 109 }
 110
 111 static LLVMValueRef
 112 llvm_face_select_helper(
 113         struct radeon_llvm_context * ctx,
 114         unsigned face_loc, LLVMValueRef front_color, LLVMValueRef back_color)
 115 {
 116         const struct lp_build_context * bb = &ctx->soa.bld_base.base;
 117         LLVMValueRef face = llvm_load_input_helper(ctx, face_loc, 0, 0);
 118         LLVMValueRef is_front = LLVMBuildFCmp(
 119                 bb->gallivm->builder, LLVMRealUGT, face,
 120                 lp_build_const_float(bb->gallivm, 0.0f),        "");
 121         return LLVMBuildSelect(bb->gallivm->builder, is_front,
 122                 front_color, back_color, "");
 123 }
 124
 125 static void llvm_load_input(
 126         struct radeon_llvm_context * ctx,
 127         unsigned input_index,
 128         const struct tgsi_full_declaration *decl)
 129 {
 130         const struct r600_shader_io * input = &ctx->r600_inputs[input_index];
 131         unsigned chan;
 132         unsigned interp = 0;
 133         int ij_index;
 134         int two_side = (ctx->two_side && input->name == TGSI_SEMANTIC_COLOR);
 135         LLVMValueRef v;
 136
 137         if (ctx->chip_class >= EVERGREEN && ctx->type == TGSI_PROCESSOR_FRAGMENT &&
 138                         input->spi_sid) {
 139                 interp = 1;
 140                 ij_index = (input->interpolate > 0) ? input->ij_index : -1;
 141         }
 142
 143         for (chan = 0; chan < 4; chan++) {
 144                 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
 145                 int loc;
 146
 147                 if (interp) {
 148                         loc = 4 * input->lds_pos + chan;
 149                 } else {
 150                         if (input->name == TGSI_SEMANTIC_FACE)
 151                                 loc = 4 * ctx->face_gpr;
 152                         else
 153                                 loc = 4 * input->gpr + chan;
 154                 }
 155
 156                 v = llvm_load_input_helper(ctx, loc, interp, ij_index);
 157
 158                 if (two_side) {
 159                         struct r600_shader_io * back_input =
 160                                         &ctx->r600_inputs[input->back_color_input];
 161                         int back_loc = interp ? back_input->lds_pos : back_input->gpr;
 162                         LLVMValueRef v2;
 163
 164                         back_loc = 4 * back_loc + chan;
 165                         v2 = llvm_load_input_helper(ctx, back_loc, interp, ij_index);
 166                         v = llvm_face_select_helper(ctx, 4 * ctx->face_gpr, v, v2);
 167                 } else if (input->name == TGSI_SEMANTIC_POSITION &&
 168                                 ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) {
 169                         /* RCP for fragcoord.w */
 170                         v = LLVMBuildFDiv(ctx->gallivm.builder,
 171                                         lp_build_const_float(&(ctx->gallivm), 1.0f),
 172                                         v, "");
 173                 }
 174
 175                 ctx->inputs[soa_index] = v;
 176         }
 177 }
 178
 179 static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
 180 {
 181         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 182
 183 }
 184
 185 static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 186 {
 187         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 188         struct lp_build_context * base = &bld_base->base;
 189         struct pipe_stream_output_info * so = ctx->stream_outputs;
 190         unsigned i;
 191         unsigned next_pos = 60;
 192         unsigned next_param = 0;
 193
 194         unsigned color_count = 0;
 195         boolean has_color = false;
 196
 197         if (ctx->type == TGSI_PROCESSOR_VERTEX && so->num_outputs) {
 198                 for (i = 0; i < so->num_outputs; i++) {
 199                         unsigned register_index = so->output[i].register_index;
 200                         unsigned start_component = so->output[i].start_component;
 201                         unsigned num_components = so->output[i].num_components;
 202                         unsigned dst_offset = so->output[i].dst_offset;
 203                         unsigned chan;
 204                         LLVMValueRef elements[4];
 205                         if (dst_offset < start_component) {
 206                                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 207                                         elements[chan] = LLVMBuildLoad(base->gallivm->builder,
 208                                                 ctx->soa.outputs[register_index][(chan + start_component) % TGSI_NUM_CHANNELS], "");
 209                                 }
 210                                 start_component = 0;
 211                         } else {
 212                                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 213                                         elements[chan] = LLVMBuildLoad(base->gallivm->builder,
 214                                                 ctx->soa.outputs[register_index][chan], "");
 215                                 }
 216                         }
 217                         LLVMValueRef output = lp_build_gather_values(base->gallivm, elements, 4);
 218                         LLVMValueRef args[4];
 219                         args[0] = output;
 220                         args[1] = lp_build_const_int32(base->gallivm, dst_offset - start_component);
 221                         args[2] = lp_build_const_int32(base->gallivm, so->output[i].output_buffer);
 222                         args[3] = lp_build_const_int32(base->gallivm, ((1 << num_components) - 1) << start_component);
 223                         lp_build_intrinsic(base->gallivm->builder, "llvm.R600.store.stream.output",
 224                                 LLVMVoidTypeInContext(base->gallivm->context), args, 4);
 225                 }
 226         }
 227
 228         /* Add the necessary export instructions */
 229         for (i = 0; i < ctx->output_reg_count; i++) {
 230                 unsigned chan;
 231                 LLVMValueRef elements[4];
 232                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 233                         elements[chan] = LLVMBuildLoad(base->gallivm->builder,
 234                                 ctx->soa.outputs[i][chan], "");
 235                 }
 236                 if (ctx->alpha_to_one && ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->r600_outputs[i].name == TGSI_SEMANTIC_COLOR)
 237                         elements[3] = lp_build_const_float(base->gallivm, 1.0f);
 238                 LLVMValueRef output = lp_build_gather_values(base->gallivm, elements, 4);
 239
 240                 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
 241                         switch (ctx->r600_outputs[i].name) {
 242                         case TGSI_SEMANTIC_POSITION:
 243                         case TGSI_SEMANTIC_PSIZE: {
 244                                 LLVMValueRef args[3];
 245                                 args[0] = output;
 246                                 args[1] = lp_build_const_int32(base->gallivm, next_pos++);
 247                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS);
 248                                 build_intrinsic(
 249                                         base->gallivm->builder,
 250                                         "llvm.R600.store.swizzle",
 251                                         LLVMVoidTypeInContext(base->gallivm->context),
 252                                         args, 3, 0);
 253                                 break;
 254                         }
 255                         case TGSI_SEMANTIC_CLIPVERTEX: {
 256                                 LLVMValueRef args[3];
 257                                 unsigned reg_index;
 258                                 unsigned base_vector_chan;
 259                                 LLVMValueRef adjusted_elements[4];
 260                                 for (reg_index = 0; reg_index < 2; reg_index ++) {
 261                                         for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 262                                                 LLVMValueRef offset[2] = {
 263                                                         LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
 264                                                         lp_build_const_int32(bld_base->base.gallivm, reg_index * 4 + chan)
 265                                                 };
 266                                                 LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024), CONSTANT_BUFFER_1_ADDR_SPACE);
 267                                                 LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
 268                                                 LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
 269                                                 LLVMValueRef base_vector = LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
 270                                                 args[0] = output;
 271                                                 args[1] = base_vector;
 272                                                 adjusted_elements[chan] = build_intrinsic(base->gallivm->builder,
 273                                                         "llvm.AMDGPU.dp4", bld_base->base.elem_type,
 274                                                         args, 2, LLVMReadNoneAttribute);
 275                                         }
 276                                         args[0] = lp_build_gather_values(base->gallivm,
 277                                                 adjusted_elements, 4);
 278                                         args[1] = lp_build_const_int32(base->gallivm, next_pos++);
 279                                         args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS);
 280                                         build_intrinsic(
 281                                                 base->gallivm->builder,
 282                                                 "llvm.R600.store.swizzle",
 283                                                 LLVMVoidTypeInContext(base->gallivm->context),
 284                                                 args, 3, 0);
 285                                 }
 286                                 break;
 287                         }
 288                         case TGSI_SEMANTIC_CLIPDIST : {
 289                                 LLVMValueRef args[3];
 290                                 args[0] = output;
 291                                 args[1] = lp_build_const_int32(base->gallivm, next_pos++);
 292                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS);
 293                                 build_intrinsic(
 294                                         base->gallivm->builder,
 295                                         "llvm.R600.store.swizzle",
 296                                         LLVMVoidTypeInContext(base->gallivm->context),
 297                                         args, 3, 0);
 298                                 args[1] = lp_build_const_int32(base->gallivm, next_param++);
 299                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM);
 300                                 build_intrinsic(
 301                                         base->gallivm->builder,
 302                                         "llvm.R600.store.swizzle",
 303                                         LLVMVoidTypeInContext(base->gallivm->context),
 304                                         args, 3, 0);
 305                                 break;
 306                         }
 307                         case TGSI_SEMANTIC_FOG: {
 308                                 elements[0] = LLVMBuildLoad(base->gallivm->builder,
 309                                         ctx->soa.outputs[i][0], "");
 310                                 elements[1] = elements[2] = lp_build_const_float(base->gallivm, 0.0f);
 311                                 elements[3] = lp_build_const_float(base->gallivm, 1.0f);
 312
 313                                 LLVMValueRef args[3];
 314                                 args[0] = lp_build_gather_values(base->gallivm, elements, 4);
 315                                 args[1] = lp_build_const_int32(base->gallivm, next_param++);
 316                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM);
 317                                 build_intrinsic(
 318                                         base->gallivm->builder,
 319                                         "llvm.R600.store.swizzle",
 320                                         LLVMVoidTypeInContext(base->gallivm->context),
 321                                         args, 3, 0);
 322                                 break;
 323                         }
 324                         default: {
 325                                 LLVMValueRef args[3];
 326                                 args[0] = output;
 327                                 args[1] = lp_build_const_int32(base->gallivm, next_param++);
 328                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM);
 329                                 build_intrinsic(
 330                                         base->gallivm->builder,
 331                                         "llvm.R600.store.swizzle",
 332                                         LLVMVoidTypeInContext(base->gallivm->context),
 333                                         args, 3, 0);
 334                                 break;
 335                         }
 336                         }
 337                 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
 338                         switch (ctx->r600_outputs[i].name) {
 339                         case TGSI_SEMANTIC_COLOR:
 340                                 has_color = true;
 341                                 if ( color_count < ctx->color_buffer_count) {
 342                                         LLVMValueRef args[3];
 343                                         args[0] = output;
 344                                         if (ctx->fs_color_all) {
 345                                                 for (unsigned j = 0; j < ctx->color_buffer_count; j++) {
 346                                                         args[1] = lp_build_const_int32(base->gallivm, j);
 347                                                         args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL);
 348                                                         build_intrinsic(
 349                                                                 base->gallivm->builder,
 350                                                                 "llvm.R600.store.swizzle",
 351                                                                 LLVMVoidTypeInContext(base->gallivm->context),
 352                                                                 args, 3, 0);
 353                                                 }
 354                                         } else {
 355                                                 args[1] = lp_build_const_int32(base->gallivm, color_count++);
 356                                                 args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL);
 357                                                 build_intrinsic(
 358                                                         base->gallivm->builder,
 359                                                         "llvm.R600.store.swizzle",
 360                                                         LLVMVoidTypeInContext(base->gallivm->context),
 361                                                         args, 3, 0);
 362                                         }
 363                                 }
 364                                 break;
 365                         case TGSI_SEMANTIC_POSITION:
 366                                 lp_build_intrinsic_unary(
 367                                         base->gallivm->builder,
 368                                         "llvm.R600.store.pixel.depth",
 369                                         LLVMVoidTypeInContext(base->gallivm->context),
 370                                         LLVMBuildLoad(base->gallivm->builder, ctx->soa.outputs[i][2], ""));
 371                                 break;
 372                         case TGSI_SEMANTIC_STENCIL:
 373                                 lp_build_intrinsic_unary(
 374                                         base->gallivm->builder,
 375                                         "llvm.R600.store.pixel.stencil",
 376                                         LLVMVoidTypeInContext(base->gallivm->context),
 377                                         LLVMBuildLoad(base->gallivm->builder, ctx->soa.outputs[i][1], ""));
 378                                 break;
 379                         }
 380                 }
 381         }
 382         // Add dummy exports
 383         if (ctx->type == TGSI_PROCESSOR_VERTEX) {
 384                 if (!next_param) {
 385                         lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy",
 386                                 LLVMVoidTypeInContext(base->gallivm->context),
 387                                 lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM));
 388                 }
 389                 if (!(next_pos-60)) {
 390                         lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy",
 391                                 LLVMVoidTypeInContext(base->gallivm->context),
 392                                 lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS));
 393                 }
 394         }
 395         if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
 396                 if (!has_color) {
 397                         lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy",
 398                                 LLVMVoidTypeInContext(base->gallivm->context),
 399                                 lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL));
 400                 }
 401         }
 402
 403 }
 404
 405 static void llvm_emit_tex(
 406         const struct lp_build_tgsi_action * action,
 407         struct lp_build_tgsi_context * bld_base,
 408         struct lp_build_emit_data * emit_data)
 409 {
 410         struct gallivm_state * gallivm = bld_base->base.gallivm;
 411         LLVMValueRef args[6];
 412         unsigned c, sampler_src;
 413
 414         if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
 415                 switch (emit_data->inst->Instruction.Opcode) {
 416                 case TGSI_OPCODE_TXQ: {
 417                         LLVMValueRef offset[2] = {
 418                                 LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
 419                                 lp_build_const_int32(bld_base->base.gallivm, 1)
 420                         };
 421                         LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024),
 422                                                                         R600_BUFFER_INFO_CONST_BUFFER);
 423                         LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
 424                         LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
 425                         LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
 426                         emit_data->output[0] = cvecval;
 427                         return;
 428                 }
 429                 case TGSI_OPCODE_TXF: {
 430                         args[0] = LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], lp_build_const_int32(gallivm, 0), "");
 431                         args[1] = lp_build_const_int32(gallivm, R600_MAX_CONST_BUFFERS);
 432                         emit_data->output[0] = build_intrinsic(gallivm->builder,
 433                                                         "llvm.R600.load.texbuf",
 434                                                         emit_data->dst_type, args, 2, LLVMReadNoneAttribute);
 435                 }
 436                         return;
 437                 default:
 438                         break;
 439                 }
 440         }
 441
 442         assert(emit_data->arg_count + 2 <= Elements(args));
 443
 444         for (c = 0; c < emit_data->arg_count; ++c)
 445                 args[c] = emit_data->args[c];
 446
 447         sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
 448
 449         args[c++] = lp_build_const_int32(gallivm,
 450                                         emit_data->inst->Src[sampler_src].Register.Index + R600_MAX_CONST_BUFFERS);
 451         args[c++] = lp_build_const_int32(gallivm,
 452                                         emit_data->inst->Src[sampler_src].Register.Index);
 453         args[c++] = lp_build_const_int32(gallivm,
 454                                         emit_data->inst->Texture.Texture);
 455
 456         emit_data->output[0] = build_intrinsic(gallivm->builder,
 457                                         action->intr_name,
 458                                         emit_data->dst_type, args, c, LLVMReadNoneAttribute);
 459 }
 460
 461 static void emit_cndlt(
 462                 const struct lp_build_tgsi_action * action,
 463                 struct lp_build_tgsi_context * bld_base,
 464                 struct lp_build_emit_data * emit_data)
 465 {
 466         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 467         LLVMValueRef float_zero = lp_build_const_float(
 468                 bld_base->base.gallivm, 0.0f);
 469         LLVMValueRef cmp = LLVMBuildFCmp(
 470                 builder, LLVMRealULT, emit_data->args[0], float_zero, "");
 471         emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
 472                 cmp, emit_data->args[1], emit_data->args[2], "");
 473 }
 474
 475 static void dp_fetch_args(
 476         struct lp_build_tgsi_context * bld_base,
 477         struct lp_build_emit_data * emit_data)
 478 {
 479         struct lp_build_context * base = &bld_base->base;
 480         unsigned chan;
 481         LLVMValueRef elements[2][4];
 482         unsigned opcode = emit_data->inst->Instruction.Opcode;
 483         unsigned dp_components = (opcode == TGSI_OPCODE_DP2 ? 2 :
 484                                         (opcode == TGSI_OPCODE_DP3 ? 3 : 4));
 485         for (chan = 0 ; chan < dp_components; chan++) {
 486                 elements[0][chan] = lp_build_emit_fetch(bld_base,
 487                                                 emit_data->inst, 0, chan);
 488                 elements[1][chan] = lp_build_emit_fetch(bld_base,
 489                                                 emit_data->inst, 1, chan);
 490         }
 491
 492         for ( ; chan < 4; chan++) {
 493                 elements[0][chan] = base->zero;
 494                 elements[1][chan] = base->zero;
 495         }
 496
 497          /* Fix up for DPH */
 498         if (opcode == TGSI_OPCODE_DPH) {
 499                 elements[0][TGSI_CHAN_W] = base->one;
 500         }
 501
 502         emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
 503                                                         elements[0], 4);
 504         emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
 505                                                         elements[1], 4);
 506         emit_data->arg_count = 2;
 507
 508         emit_data->dst_type = base->elem_type;
 509 }
 510
 511 static struct lp_build_tgsi_action dot_action = {
 512         .fetch_args = dp_fetch_args,
 513         .emit = build_tgsi_intrinsic_nomem,
 514         .intr_name = "llvm.AMDGPU.dp4"
 515 };
 516
 517
 518
 519 LLVMModuleRef r600_tgsi_llvm(
 520         struct radeon_llvm_context * ctx,
 521         const struct tgsi_token * tokens)
 522 {
 523         struct tgsi_shader_info shader_info;
 524         struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
 525         radeon_llvm_context_init(ctx);
 526         radeon_llvm_create_func(ctx, NULL, 0);
 527         tgsi_scan_shader(tokens, &shader_info);
 528
 529         bld_base->info = &shader_info;
 530         bld_base->userdata = ctx;
 531         bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = llvm_fetch_const;
 532         bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = llvm_fetch_system_value;
 533         bld_base->emit_prologue = llvm_emit_prologue;
 534         bld_base->emit_epilogue = llvm_emit_epilogue;
 535         ctx->userdata = ctx;
 536         ctx->load_input = llvm_load_input;
 537         ctx->load_system_value = llvm_load_system_value;
 538
 539         bld_base->op_actions[TGSI_OPCODE_DP2] = dot_action;
 540         bld_base->op_actions[TGSI_OPCODE_DP3] = dot_action;
 541         bld_base->op_actions[TGSI_OPCODE_DP4] = dot_action;
 542         bld_base->op_actions[TGSI_OPCODE_DPH] = dot_action;
 543         bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex;
 544         bld_base->op_actions[TGSI_OPCODE_DDY].emit = llvm_emit_tex;
 545         bld_base->op_actions[TGSI_OPCODE_TEX].emit = llvm_emit_tex;
 546         bld_base->op_actions[TGSI_OPCODE_TEX2].emit = llvm_emit_tex;
 547         bld_base->op_actions[TGSI_OPCODE_TXB].emit = llvm_emit_tex;
 548         bld_base->op_actions[TGSI_OPCODE_TXB2].emit = llvm_emit_tex;
 549         bld_base->op_actions[TGSI_OPCODE_TXD].emit = llvm_emit_tex;
 550         bld_base->op_actions[TGSI_OPCODE_TXL].emit = llvm_emit_tex;
 551         bld_base->op_actions[TGSI_OPCODE_TXL2].emit = llvm_emit_tex;
 552         bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex;
 553         bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex;
 554         bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex;
 555         bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cndlt;
 556
 557         lp_build_tgsi_llvm(bld_base, tokens);
 558
 559         radeon_llvm_finalize_module(ctx);
 560
 561         return ctx->gallivm.module;
 562 }
 563
 564 const char * r600_llvm_gpu_string(enum radeon_family family)
 565 {
 566         const char * gpu_family;
 567
 568         switch (family) {
 569         case CHIP_R600:
 570         case CHIP_RV610:
 571         case CHIP_RV630:
 572         case CHIP_RV620:
 573         case CHIP_RV635:
 574         case CHIP_RV670:
 575         case CHIP_RS780:
 576         case CHIP_RS880:
 577                 gpu_family = "r600";
 578                 break;
 579         case CHIP_RV710:
 580                 gpu_family = "rv710";
 581                 break;
 582         case CHIP_RV730:
 583                 gpu_family = "rv730";
 584                 break;
 585         case CHIP_RV740:
 586         case CHIP_RV770:
 587                 gpu_family = "rv770";
 588                 break;
 589         case CHIP_PALM:
 590         case CHIP_CEDAR:
 591                 gpu_family = "cedar";
 592                 break;
 593         case CHIP_SUMO:
 594         case CHIP_SUMO2:
 595         case CHIP_REDWOOD:
 596                 gpu_family = "redwood";
 597                 break;
 598         case CHIP_JUNIPER:
 599                 gpu_family = "juniper";
 600                 break;
 601         case CHIP_HEMLOCK:
 602         case CHIP_CYPRESS:
 603                 gpu_family = "cypress";
 604                 break;
 605         case CHIP_BARTS:
 606                 gpu_family = "barts";
 607                 break;
 608         case CHIP_TURKS:
 609                 gpu_family = "turks";
 610                 break;
 611         case CHIP_CAICOS:
 612                 gpu_family = "caicos";
 613                 break;
 614         case CHIP_CAYMAN:
 615         case CHIP_ARUBA:
 616                 gpu_family = "cayman";
 617                 break;
 618         default:
 619                 gpu_family = "";
 620                 fprintf(stderr, "Chip not supported by r600 llvm "
 621                         "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
 622                 break;
 623         }
 624         return gpu_family;
 625 }
 626
 627 unsigned r600_llvm_compile(
 628         LLVMModuleRef mod,
 629         unsigned char ** inst_bytes,
 630         unsigned * inst_byte_count,
 631         enum radeon_family family,
 632         unsigned dump)
 633 {
 634         const char * gpu_family = r600_llvm_gpu_string(family);
 635         return radeon_llvm_compile(mod, inst_bytes, inst_byte_count,
 636                                                         gpu_family, dump);
 637 }
 638
 639 #endif