src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_video.h"
  42 #include "radeon/radeon_uvd.h"
  43 #include "os/os_time.h"
  44
  45 static const struct debug_named_value r600_debug_options[] = {
  46         /* features */
  47 #if defined(R600_USE_LLVM)
  48         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  49 #endif
  50         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  51         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
  52
  53         /* shader backend */
  54         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  55         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  56         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  57         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  58         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  59         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  60         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  61         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  62
  63         DEBUG_NAMED_VALUE_END /* must be last */
  64 };
  65
  66 /*
  67  * pipe_context
  68  */
  69
  70 static void r600_flush(struct pipe_context *ctx, unsigned flags)
  71 {
  72         struct r600_context *rctx = (struct r600_context *)ctx;
  73         struct pipe_query *render_cond = NULL;
  74         unsigned render_cond_mode = 0;
  75         boolean render_cond_cond = FALSE;
  76
  77         if (rctx->b.rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
  78                 return;
  79
  80         rctx->b.rings.gfx.flushing = true;
  81         /* Disable render condition. */
  82         if (rctx->b.current_render_cond) {
  83                 render_cond = rctx->b.current_render_cond;
  84                 render_cond_cond = rctx->b.current_render_cond_cond;
  85                 render_cond_mode = rctx->b.current_render_cond_mode;
  86                 ctx->render_condition(ctx, NULL, FALSE, 0);
  87         }
  88
  89         r600_context_flush(rctx, flags);
  90         rctx->b.rings.gfx.flushing = false;
  91         r600_begin_new_cs(rctx);
  92
  93         /* Re-enable render condition. */
  94         if (render_cond) {
  95                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  96         }
  97
  98         rctx->initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
  99 }
 100
 101 static void r600_flush_from_st(struct pipe_context *ctx,
 102                                struct pipe_fence_handle **fence,
 103                                unsigned flags)
 104 {
 105         struct r600_context *rctx = (struct r600_context *)ctx;
 106         unsigned fflags;
 107
 108         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 109         if (fence) {
 110                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
 111         }
 112         /* flush gfx & dma ring, order does not matter as only one can be live */
 113         if (rctx->b.rings.dma.cs) {
 114                 rctx->b.rings.dma.flush(rctx, fflags);
 115         }
 116         rctx->b.rings.gfx.flush(rctx, fflags);
 117 }
 118
 119 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 120 {
 121         r600_flush((struct pipe_context*)ctx, flags);
 122 }
 123
 124 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 125 {
 126         struct r600_context *rctx = (struct r600_context *)ctx;
 127         struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
 128
 129         if (!cs->cdw) {
 130                 return;
 131         }
 132
 133         rctx->b.rings.dma.flushing = true;
 134         rctx->b.ws->cs_flush(cs, flags, 0);
 135         rctx->b.rings.dma.flushing = false;
 136 }
 137
 138 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 139 {
 140         struct r600_context *rctx = (struct r600_context *)ctx;
 141
 142         rctx->b.rings.gfx.flush(rctx, flags);
 143 }
 144
 145 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
 146 {
 147         struct r600_context *rctx = (struct r600_context *)ctx;
 148
 149         rctx->b.rings.dma.flush(rctx, flags);
 150 }
 151
 152 static void r600_destroy_context(struct pipe_context *context)
 153 {
 154         struct r600_context *rctx = (struct r600_context *)context;
 155
 156         r600_isa_destroy(rctx->isa);
 157
 158         r600_sb_context_destroy(rctx->sb_context);
 159
 160         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 161         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 162
 163         if (rctx->dummy_pixel_shader) {
 164                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 165         }
 166         if (rctx->custom_dsa_flush) {
 167                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
 168         }
 169         if (rctx->custom_blend_resolve) {
 170                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 171         }
 172         if (rctx->custom_blend_decompress) {
 173                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 174         }
 175         if (rctx->custom_blend_fastclear) {
 176                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 177         }
 178         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 179
 180         if (rctx->blitter) {
 181                 util_blitter_destroy(rctx->blitter);
 182         }
 183         if (rctx->allocator_fetch_shader) {
 184                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 185         }
 186
 187         r600_release_command_buffer(&rctx->start_cs_cmd);
 188
 189         FREE(rctx->start_compute_cs_cmd.buf);
 190
 191         r600_common_context_cleanup(&rctx->b);
 192         FREE(rctx);
 193 }
 194
 195 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 196 {
 197         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 198         struct r600_screen* rscreen = (struct r600_screen *)screen;
 199
 200         if (rctx == NULL)
 201                 return NULL;
 202
 203         rctx->b.b.screen = screen;
 204         rctx->b.b.priv = priv;
 205         rctx->b.b.destroy = r600_destroy_context;
 206         rctx->b.b.flush = r600_flush_from_st;
 207
 208         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 209                 goto fail;
 210
 211         rctx->screen = rscreen;
 212         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 213
 214         r600_init_blit_functions(rctx);
 215
 216         if (rscreen->b.info.has_uvd) {
 217                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 218                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 219         } else {
 220                 rctx->b.b.create_video_codec = vl_create_decoder;
 221                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 222         }
 223
 224         r600_init_common_state_functions(rctx);
 225
 226         switch (rctx->b.chip_class) {
 227         case R600:
 228         case R700:
 229                 r600_init_state_functions(rctx);
 230                 r600_init_atom_start_cs(rctx);
 231                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 232                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 233                                                                       : r600_create_resolve_blend(rctx);
 234                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 235                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 236                                            rctx->b.family == CHIP_RV620 ||
 237                                            rctx->b.family == CHIP_RS780 ||
 238                                            rctx->b.family == CHIP_RS880 ||
 239                                            rctx->b.family == CHIP_RV710);
 240                 break;
 241         case EVERGREEN:
 242         case CAYMAN:
 243                 evergreen_init_state_functions(rctx);
 244                 evergreen_init_atom_start_cs(rctx);
 245                 evergreen_init_atom_start_compute_cs(rctx);
 246                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 247                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 248                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 249                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 250                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 251                                            rctx->b.family == CHIP_PALM ||
 252                                            rctx->b.family == CHIP_SUMO ||
 253                                            rctx->b.family == CHIP_SUMO2 ||
 254                                            rctx->b.family == CHIP_CAICOS ||
 255                                            rctx->b.family == CHIP_CAYMAN ||
 256                                            rctx->b.family == CHIP_ARUBA);
 257                 break;
 258         default:
 259                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 260                 goto fail;
 261         }
 262
 263         if (rscreen->b.trace_bo) {
 264                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, rscreen->b.trace_bo->cs_buf);
 265         } else {
 266                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 267         }
 268         rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
 269         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
 270         rctx->b.rings.gfx.flushing = false;
 271
 272         rctx->b.rings.dma.cs = NULL;
 273         if (rscreen->b.info.r600_has_dma && !(rscreen->b.debug_flags & DBG_NO_ASYNC_DMA)) {
 274                 rctx->b.rings.dma.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_DMA, NULL);
 275                 rctx->b.rings.dma.flush = r600_flush_dma_ring;
 276                 rctx->b.ws->cs_set_flush_callback(rctx->b.rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 277                 rctx->b.rings.dma.flushing = false;
 278         }
 279
 280         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 281                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 282         if (!rctx->allocator_fetch_shader)
 283                 goto fail;
 284
 285         rctx->isa = calloc(1, sizeof(struct r600_isa));
 286         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 287                 goto fail;
 288
 289         rctx->blitter = util_blitter_create(&rctx->b.b);
 290         if (rctx->blitter == NULL)
 291                 goto fail;
 292         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 293         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 294
 295         r600_begin_new_cs(rctx);
 296         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 297
 298         rctx->dummy_pixel_shader =
 299                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 300                                                      TGSI_SEMANTIC_GENERIC,
 301                                                      TGSI_INTERPOLATE_CONSTANT);
 302         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 303
 304         return &rctx->b.b;
 305
 306 fail:
 307         r600_destroy_context(&rctx->b.b);
 308         return NULL;
 309 }
 310
 311 /*
 312  * pipe_screen
 313  */
 314
 315 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 316 {
 317         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 318         enum radeon_family family = rscreen->b.family;
 319
 320         switch (param) {
 321         /* Supported features (boolean caps). */
 322         case PIPE_CAP_NPOT_TEXTURES:
 323         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 324         case PIPE_CAP_TWO_SIDED_STENCIL:
 325         case PIPE_CAP_ANISOTROPIC_FILTER:
 326         case PIPE_CAP_POINT_SPRITE:
 327         case PIPE_CAP_OCCLUSION_QUERY:
 328         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 329         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 330         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 331         case PIPE_CAP_TEXTURE_SWIZZLE:
 332         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 333         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 334         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 335         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 336         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 337         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 338         case PIPE_CAP_SM3:
 339         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 340         case PIPE_CAP_PRIMITIVE_RESTART:
 341         case PIPE_CAP_CONDITIONAL_RENDER:
 342         case PIPE_CAP_TEXTURE_BARRIER:
 343         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 344         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 345         case PIPE_CAP_TGSI_INSTANCEID:
 346         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 347         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 348         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 349         case PIPE_CAP_USER_INDEX_BUFFERS:
 350         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 351         case PIPE_CAP_COMPUTE:
 352         case PIPE_CAP_START_INSTANCE:
 353         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 354         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 355         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 356         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 357         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 358                 return 1;
 359
 360         case PIPE_CAP_TGSI_TEXCOORD:
 361                 return 0;
 362
 363         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 364                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 365
 366         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 367                 return R600_MAP_BUFFER_ALIGNMENT;
 368
 369         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 370                 return 256;
 371
 372         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 373                 return 1;
 374
 375         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 376                 if (family >= CHIP_CEDAR)
 377                    return 330;
 378                 /* pre-evergreen geom shaders need newer kernel */
 379                 if (rscreen->b.info.drm_minor >= 37)
 380                    return 330;
 381                 return 140;
 382
 383         /* Supported except the original R600. */
 384         case PIPE_CAP_INDEP_BLEND_ENABLE:
 385         case PIPE_CAP_INDEP_BLEND_FUNC:
 386                 /* R600 doesn't support per-MRT blends */
 387                 return family == CHIP_R600 ? 0 : 1;
 388
 389         /* Supported on Evergreen. */
 390         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 391         case PIPE_CAP_CUBE_MAP_ARRAY:
 392         case PIPE_CAP_TGSI_VS_LAYER:
 393                 return family >= CHIP_CEDAR ? 1 : 0;
 394
 395         /* Unsupported features. */
 396         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 397         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 398         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 399         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 400         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 401         case PIPE_CAP_USER_VERTEX_BUFFERS:
 402                 return 0;
 403
 404         /* Stream output. */
 405         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 406                 return rscreen->b.has_streamout ? 4 : 0;
 407         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 408                 return rscreen->b.has_streamout ? 1 : 0;
 409         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 410         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 411                 return 32*4;
 412
 413         /* Texturing. */
 414         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 415         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 416         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 417                 if (family >= CHIP_CEDAR)
 418                         return 15;
 419                 else
 420                         return 14;
 421         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 422                 return rscreen->b.info.drm_minor >= 9 ?
 423                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 424
 425         /* Render targets. */
 426         case PIPE_CAP_MAX_RENDER_TARGETS:
 427                 /* XXX some r6xx are buggy and can only do 4 */
 428                 return 8;
 429
 430         case PIPE_CAP_MAX_VIEWPORTS:
 431                 return 1;
 432
 433         /* Timer queries, present when the clock frequency is non zero. */
 434         case PIPE_CAP_QUERY_TIME_ELAPSED:
 435                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 436         case PIPE_CAP_QUERY_TIMESTAMP:
 437                 return rscreen->b.info.drm_minor >= 20 &&
 438                        rscreen->b.info.r600_clock_crystal_freq != 0;
 439
 440         case PIPE_CAP_MIN_TEXEL_OFFSET:
 441                 return -8;
 442
 443         case PIPE_CAP_MAX_TEXEL_OFFSET:
 444                 return 7;
 445
 446         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 447                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 448         case PIPE_CAP_ENDIANNESS:
 449                 return PIPE_ENDIAN_LITTLE;
 450         }
 451         return 0;
 452 }
 453
 454 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 455 {
 456         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 457
 458         switch(shader)
 459         {
 460         case PIPE_SHADER_FRAGMENT:
 461         case PIPE_SHADER_VERTEX:
 462         case PIPE_SHADER_COMPUTE:
 463                 break;
 464         case PIPE_SHADER_GEOMETRY:
 465                 if (rscreen->b.family >= CHIP_CEDAR)
 466                         break;
 467                 /* pre-evergreen geom shaders need newer kernel */
 468                 if (rscreen->b.info.drm_minor >= 37)
 469                         break;
 470                 return 0;
 471         default:
 472                 /* XXX: support tessellation on Evergreen */
 473                 return 0;
 474         }
 475
 476         switch (param) {
 477         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 478         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 479         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 480         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 481                 return 16384;
 482         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 483                 return 32;
 484         case PIPE_SHADER_CAP_MAX_INPUTS:
 485                 return 32;
 486         case PIPE_SHADER_CAP_MAX_TEMPS:
 487                 return 256; /* Max native temporaries. */
 488         case PIPE_SHADER_CAP_MAX_ADDRS:
 489                 /* XXX Isn't this equal to TEMPS? */
 490                 return 1; /* Max native address registers */
 491         case PIPE_SHADER_CAP_MAX_CONSTS:
 492                 return R600_MAX_CONST_BUFFER_SIZE;
 493         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 494                 return R600_MAX_USER_CONST_BUFFERS;
 495         case PIPE_SHADER_CAP_MAX_PREDS:
 496                 return 0; /* nothing uses this */
 497         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 498                 return 1;
 499         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 500                 return 0;
 501         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 502         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 503         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 504         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 505                 return 1;
 506         case PIPE_SHADER_CAP_SUBROUTINES:
 507                 return 0;
 508         case PIPE_SHADER_CAP_INTEGERS:
 509                 return 1;
 510         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 511         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 512                 return 16;
 513         case PIPE_SHADER_CAP_PREFERRED_IR:
 514                 if (shader == PIPE_SHADER_COMPUTE) {
 515                         return PIPE_SHADER_IR_LLVM;
 516                 } else {
 517                         return PIPE_SHADER_IR_TGSI;
 518                 }
 519         }
 520         return 0;
 521 }
 522
 523 static void r600_destroy_screen(struct pipe_screen* pscreen)
 524 {
 525         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 526
 527         if (rscreen == NULL)
 528                 return;
 529
 530         if (!radeon_winsys_unref(rscreen->b.ws))
 531                 return;
 532
 533         if (rscreen->global_pool) {
 534                 compute_memory_pool_delete(rscreen->global_pool);
 535         }
 536
 537         r600_destroy_common_screen(&rscreen->b);
 538 }
 539
 540 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 541                                                   const struct pipe_resource *templ)
 542 {
 543         if (templ->target == PIPE_BUFFER &&
 544             (templ->bind & PIPE_BIND_GLOBAL))
 545                 return r600_compute_global_buffer_create(screen, templ);
 546
 547         return r600_resource_create_common(screen, templ);
 548 }
 549
 550 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 551 {
 552         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 553
 554         if (rscreen == NULL) {
 555                 return NULL;
 556         }
 557
 558         /* Set functions first. */
 559         rscreen->b.b.context_create = r600_create_context;
 560         rscreen->b.b.destroy = r600_destroy_screen;
 561         rscreen->b.b.get_param = r600_get_param;
 562         rscreen->b.b.get_shader_param = r600_get_shader_param;
 563         rscreen->b.b.resource_create = r600_resource_create;
 564
 565         if (!r600_common_screen_init(&rscreen->b, ws)) {
 566                 FREE(rscreen);
 567                 return NULL;
 568         }
 569
 570         if (rscreen->b.info.chip_class >= EVERGREEN) {
 571                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 572         } else {
 573                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 574         }
 575
 576         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 577         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 578                 rscreen->b.debug_flags |= DBG_COMPUTE;
 579         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 580                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 581         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 582                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 583         if (!debug_get_bool_option("R600_LLVM", TRUE))
 584                 rscreen->b.debug_flags |= DBG_NO_LLVM;
 585
 586         if (rscreen->b.family == CHIP_UNKNOWN) {
 587                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 588                 FREE(rscreen);
 589                 return NULL;
 590         }
 591
 592         /* Figure out streamout kernel support. */
 593         switch (rscreen->b.chip_class) {
 594         case R600:
 595                 if (rscreen->b.family < CHIP_RS780) {
 596                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 597                 } else {
 598                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 599                 }
 600                 break;
 601         case R700:
 602                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 603                 break;
 604         case EVERGREEN:
 605         case CAYMAN:
 606                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 607                 break;
 608         default:
 609                 rscreen->b.has_streamout = FALSE;
 610                 break;
 611         }
 612
 613         /* MSAA support. */
 614         switch (rscreen->b.chip_class) {
 615         case R600:
 616         case R700:
 617                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 618                 rscreen->has_compressed_msaa_texturing = false;
 619                 break;
 620         case EVERGREEN:
 621                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 622                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 623                 break;
 624         case CAYMAN:
 625                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 626                 rscreen->has_compressed_msaa_texturing = true;
 627                 break;
 628         default:
 629                 rscreen->has_msaa = FALSE;
 630                 rscreen->has_compressed_msaa_texturing = false;
 631         }
 632
 633         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 634                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 635
 636         rscreen->global_pool = compute_memory_pool_new(rscreen);
 637
 638         /* Create the auxiliary context. This must be done last. */
 639         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 640
 641 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 642         struct pipe_resource templ = {};
 643
 644         templ.width0 = 4;
 645         templ.height0 = 2048;
 646         templ.depth0 = 1;
 647         templ.array_size = 1;
 648         templ.target = PIPE_TEXTURE_2D;
 649         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 650         templ.usage = PIPE_USAGE_DEFAULT;
 651
 652         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 653         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 654
 655         memset(map, 0, 256);
 656
 657         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 658         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 659         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 660         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 661         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 662
 663         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 664
 665         int i;
 666         for (i = 0; i < 256; i++) {
 667                 printf("%02X", map[i]);
 668                 if (i % 16 == 15)
 669                         printf("\n");
 670         }
 671 #endif
 672
 673         return &rscreen->b.b;
 674 }