src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_video.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  47
  48         /* shader backend */
  49         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  50         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  51         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  52         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  53         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  54         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  55         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  56         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  57
  58         DEBUG_NAMED_VALUE_END /* must be last */
  59 };
  60
  61 /*
  62  * pipe_context
  63  */
  64
  65 static void r600_destroy_context(struct pipe_context *context)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)context;
  68         unsigned sh;
  69
  70         r600_isa_destroy(rctx->isa);
  71
  72         r600_sb_context_destroy(rctx->sb_context);
  73
  74         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
  75         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
  76
  77         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  78                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  79                 free(rctx->driver_consts[sh].constants);
  80         }
  81
  82         if (rctx->fixed_func_tcs_shader)
  83                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  84
  85         if (rctx->dummy_pixel_shader) {
  86                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  87         }
  88         if (rctx->custom_dsa_flush) {
  89                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  90         }
  91         if (rctx->custom_blend_resolve) {
  92                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  93         }
  94         if (rctx->custom_blend_decompress) {
  95                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  96         }
  97         if (rctx->custom_blend_fastclear) {
  98                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  99         }
 100         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 101
 102         if (rctx->blitter) {
 103                 util_blitter_destroy(rctx->blitter);
 104         }
 105         if (rctx->allocator_fetch_shader) {
 106                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 107         }
 108
 109         r600_release_command_buffer(&rctx->start_cs_cmd);
 110
 111         FREE(rctx->start_compute_cs_cmd.buf);
 112
 113         r600_common_context_cleanup(&rctx->b);
 114         FREE(rctx);
 115 }
 116
 117 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 118                                                 void *priv, unsigned flags)
 119 {
 120         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 121         struct r600_screen* rscreen = (struct r600_screen *)screen;
 122         struct radeon_winsys *ws = rscreen->b.ws;
 123
 124         if (!rctx)
 125                 return NULL;
 126
 127         rctx->b.b.screen = screen;
 128         rctx->b.b.priv = priv;
 129         rctx->b.b.destroy = r600_destroy_context;
 130         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 131
 132         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 133                 goto fail;
 134
 135         rctx->screen = rscreen;
 136
 137         r600_init_blit_functions(rctx);
 138
 139         if (rscreen->b.info.has_uvd) {
 140                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 141                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 142         } else {
 143                 rctx->b.b.create_video_codec = vl_create_decoder;
 144                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 145         }
 146
 147         r600_init_common_state_functions(rctx);
 148
 149         switch (rctx->b.chip_class) {
 150         case R600:
 151         case R700:
 152                 r600_init_state_functions(rctx);
 153                 r600_init_atom_start_cs(rctx);
 154                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 155                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 156                                                                       : r600_create_resolve_blend(rctx);
 157                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 158                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 159                                            rctx->b.family == CHIP_RV620 ||
 160                                            rctx->b.family == CHIP_RS780 ||
 161                                            rctx->b.family == CHIP_RS880 ||
 162                                            rctx->b.family == CHIP_RV710);
 163                 break;
 164         case EVERGREEN:
 165         case CAYMAN:
 166                 evergreen_init_state_functions(rctx);
 167                 evergreen_init_atom_start_cs(rctx);
 168                 evergreen_init_atom_start_compute_cs(rctx);
 169                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 170                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 171                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 172                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 173                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 174                                            rctx->b.family == CHIP_PALM ||
 175                                            rctx->b.family == CHIP_SUMO ||
 176                                            rctx->b.family == CHIP_SUMO2 ||
 177                                            rctx->b.family == CHIP_CAICOS ||
 178                                            rctx->b.family == CHIP_CAYMAN ||
 179                                            rctx->b.family == CHIP_ARUBA);
 180                 break;
 181         default:
 182                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 183                 goto fail;
 184         }
 185
 186         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 187                                        r600_context_gfx_flush, rctx);
 188         rctx->b.gfx.flush = r600_context_gfx_flush;
 189
 190         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 191                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 192         if (!rctx->allocator_fetch_shader)
 193                 goto fail;
 194
 195         rctx->isa = calloc(1, sizeof(struct r600_isa));
 196         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 197                 goto fail;
 198
 199         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 200                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 201
 202         rctx->blitter = util_blitter_create(&rctx->b.b);
 203         if (rctx->blitter == NULL)
 204                 goto fail;
 205         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 206         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 207
 208         r600_begin_new_cs(rctx);
 209         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 210
 211         rctx->dummy_pixel_shader =
 212                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 213                                                      TGSI_SEMANTIC_GENERIC,
 214                                                      TGSI_INTERPOLATE_CONSTANT);
 215         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 216
 217         return &rctx->b.b;
 218
 219 fail:
 220         r600_destroy_context(&rctx->b.b);
 221         return NULL;
 222 }
 223
 224 /*
 225  * pipe_screen
 226  */
 227
 228 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 229 {
 230         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 231         enum radeon_family family = rscreen->b.family;
 232
 233         switch (param) {
 234         /* Supported features (boolean caps). */
 235         case PIPE_CAP_NPOT_TEXTURES:
 236         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 237         case PIPE_CAP_TWO_SIDED_STENCIL:
 238         case PIPE_CAP_ANISOTROPIC_FILTER:
 239         case PIPE_CAP_POINT_SPRITE:
 240         case PIPE_CAP_OCCLUSION_QUERY:
 241         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 242         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 243         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 244         case PIPE_CAP_TEXTURE_SWIZZLE:
 245         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 246         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 247         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 248         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 249         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 250         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 251         case PIPE_CAP_SM3:
 252         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 253         case PIPE_CAP_PRIMITIVE_RESTART:
 254         case PIPE_CAP_CONDITIONAL_RENDER:
 255         case PIPE_CAP_TEXTURE_BARRIER:
 256         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 257         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 258         case PIPE_CAP_TGSI_INSTANCEID:
 259         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 260         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 261         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 262         case PIPE_CAP_USER_INDEX_BUFFERS:
 263         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 264         case PIPE_CAP_START_INSTANCE:
 265         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 266         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 267         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 268         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 269         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 270         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 271         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 272         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 273         case PIPE_CAP_SAMPLE_SHADING:
 274         case PIPE_CAP_CLIP_HALFZ:
 275         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 276         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 277         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 278         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 279         case PIPE_CAP_TGSI_TXQS:
 280         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 281         case PIPE_CAP_INVALIDATE_BUFFER:
 282         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 283         case PIPE_CAP_QUERY_MEMORY_INFO:
 284         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 285                 return 1;
 286
 287         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 288                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 289
 290         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 291                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 292
 293         case PIPE_CAP_COMPUTE:
 294                 return rscreen->b.chip_class > R700;
 295
 296         case PIPE_CAP_TGSI_TEXCOORD:
 297                 return 0;
 298
 299         case PIPE_CAP_FAKE_SW_MSAA:
 300                 return 0;
 301
 302         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 303                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 304
 305         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 306                 return R600_MAP_BUFFER_ALIGNMENT;
 307
 308         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 309                 return 256;
 310
 311         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 312                 return 1;
 313
 314         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 315                 if (family >= CHIP_CEDAR)
 316                    return 410;
 317                 /* pre-evergreen geom shaders need newer kernel */
 318                 if (rscreen->b.info.drm_minor >= 37)
 319                    return 330;
 320                 return 140;
 321
 322         /* Supported except the original R600. */
 323         case PIPE_CAP_INDEP_BLEND_ENABLE:
 324         case PIPE_CAP_INDEP_BLEND_FUNC:
 325                 /* R600 doesn't support per-MRT blends */
 326                 return family == CHIP_R600 ? 0 : 1;
 327
 328         /* Supported on Evergreen. */
 329         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 330         case PIPE_CAP_CUBE_MAP_ARRAY:
 331         case PIPE_CAP_TEXTURE_GATHER_SM5:
 332         case PIPE_CAP_TEXTURE_QUERY_LOD:
 333         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 334         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 335                 return family >= CHIP_CEDAR ? 1 : 0;
 336         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 337                 return family >= CHIP_CEDAR ? 4 : 0;
 338         case PIPE_CAP_DRAW_INDIRECT:
 339                 /* kernel command checker support is also required */
 340                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 341
 342         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 343                 return family >= CHIP_CEDAR ? 0 : 1;
 344
 345         /* Unsupported features. */
 346         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 347         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 348         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 349         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 350         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 351         case PIPE_CAP_USER_VERTEX_BUFFERS:
 352         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 353         case PIPE_CAP_VERTEXID_NOBASE:
 354         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 355         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 356         case PIPE_CAP_SHAREABLE_SHADERS:
 357         case PIPE_CAP_CLEAR_TEXTURE:
 358         case PIPE_CAP_DRAW_PARAMETERS:
 359         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 360         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 361         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 362         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 363         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 364         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 365         case PIPE_CAP_GENERATE_MIPMAP:
 366         case PIPE_CAP_STRING_MARKER:
 367         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 368         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 369                 return 0;
 370
 371         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 372                 if (family >= CHIP_CEDAR)
 373                         return 30;
 374                 else
 375                         return 0;
 376         /* Stream output. */
 377         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 378                 return rscreen->b.has_streamout ? 4 : 0;
 379         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 380                 return rscreen->b.has_streamout ? 1 : 0;
 381         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 382         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 383                 return 32*4;
 384
 385         /* Geometry shader output. */
 386         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 387                 return 1024;
 388         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 389                 return 16384;
 390         case PIPE_CAP_MAX_VERTEX_STREAMS:
 391                 return family >= CHIP_CEDAR ? 4 : 1;
 392
 393         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 394                 return 2047;
 395
 396         /* Texturing. */
 397         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 398         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 399                 if (family >= CHIP_CEDAR)
 400                         return 15;
 401                 else
 402                         return 14;
 403         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 404                 /* textures support 8192, but layered rendering supports 2048 */
 405                 return 12;
 406         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 407                 /* textures support 8192, but layered rendering supports 2048 */
 408                 return 2048;
 409
 410         /* Render targets. */
 411         case PIPE_CAP_MAX_RENDER_TARGETS:
 412                 /* XXX some r6xx are buggy and can only do 4 */
 413                 return 8;
 414
 415         case PIPE_CAP_MAX_VIEWPORTS:
 416                 return R600_MAX_VIEWPORTS;
 417
 418         /* Timer queries, present when the clock frequency is non zero. */
 419         case PIPE_CAP_QUERY_TIME_ELAPSED:
 420                 return rscreen->b.info.clock_crystal_freq != 0;
 421         case PIPE_CAP_QUERY_TIMESTAMP:
 422                 return rscreen->b.info.drm_minor >= 20 &&
 423                        rscreen->b.info.clock_crystal_freq != 0;
 424
 425         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 426         case PIPE_CAP_MIN_TEXEL_OFFSET:
 427                 return -8;
 428
 429         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 430         case PIPE_CAP_MAX_TEXEL_OFFSET:
 431                 return 7;
 432
 433         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 434                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 435         case PIPE_CAP_ENDIANNESS:
 436                 return PIPE_ENDIAN_LITTLE;
 437
 438         case PIPE_CAP_VENDOR_ID:
 439                 return ATI_VENDOR_ID;
 440         case PIPE_CAP_DEVICE_ID:
 441                 return rscreen->b.info.pci_id;
 442         case PIPE_CAP_ACCELERATED:
 443                 return 1;
 444         case PIPE_CAP_VIDEO_MEMORY:
 445                 return rscreen->b.info.vram_size >> 20;
 446         case PIPE_CAP_UMA:
 447                 return 0;
 448         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 449                 return rscreen->b.chip_class >= R700;
 450         case PIPE_CAP_PCI_GROUP:
 451                 return rscreen->b.info.pci_domain;
 452         case PIPE_CAP_PCI_BUS:
 453                 return rscreen->b.info.pci_bus;
 454         case PIPE_CAP_PCI_DEVICE:
 455                 return rscreen->b.info.pci_dev;
 456         case PIPE_CAP_PCI_FUNCTION:
 457                 return rscreen->b.info.pci_func;
 458         }
 459         return 0;
 460 }
 461
 462 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 463 {
 464         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 465
 466         switch(shader)
 467         {
 468         case PIPE_SHADER_FRAGMENT:
 469         case PIPE_SHADER_VERTEX:
 470         case PIPE_SHADER_COMPUTE:
 471                 break;
 472         case PIPE_SHADER_GEOMETRY:
 473                 if (rscreen->b.family >= CHIP_CEDAR)
 474                         break;
 475                 /* pre-evergreen geom shaders need newer kernel */
 476                 if (rscreen->b.info.drm_minor >= 37)
 477                         break;
 478                 return 0;
 479         case PIPE_SHADER_TESS_CTRL:
 480         case PIPE_SHADER_TESS_EVAL:
 481                 if (rscreen->b.family >= CHIP_CEDAR)
 482                         break;
 483         default:
 484                 return 0;
 485         }
 486
 487         switch (param) {
 488         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 489         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 490         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 491         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 492                 return 16384;
 493         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 494                 return 32;
 495         case PIPE_SHADER_CAP_MAX_INPUTS:
 496                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 497         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 498                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 499         case PIPE_SHADER_CAP_MAX_TEMPS:
 500                 return 256; /* Max native temporaries. */
 501         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 502                 if (shader == PIPE_SHADER_COMPUTE) {
 503                         uint64_t max_const_buffer_size;
 504                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 505                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 506                                 &max_const_buffer_size);
 507                         return max_const_buffer_size;
 508
 509                 } else {
 510                         return R600_MAX_CONST_BUFFER_SIZE;
 511                 }
 512         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 513                 return R600_MAX_USER_CONST_BUFFERS;
 514         case PIPE_SHADER_CAP_MAX_PREDS:
 515                 return 0; /* nothing uses this */
 516         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 517                 return 1;
 518         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 519                 return 1;
 520         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 521         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 522         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 523         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 524                 return 1;
 525         case PIPE_SHADER_CAP_SUBROUTINES:
 526                 return 0;
 527         case PIPE_SHADER_CAP_INTEGERS:
 528         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 529                 return 1;
 530         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 531         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 532                 return 16;
 533         case PIPE_SHADER_CAP_PREFERRED_IR:
 534                 if (shader == PIPE_SHADER_COMPUTE) {
 535                         return PIPE_SHADER_IR_NATIVE;
 536                 } else {
 537                         return PIPE_SHADER_IR_TGSI;
 538                 }
 539         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 540                 return 0;
 541         case PIPE_SHADER_CAP_DOUBLES:
 542                 if (rscreen->b.family == CHIP_CYPRESS ||
 543                         rscreen->b.family == CHIP_CAYMAN || rscreen->b.family == CHIP_ARUBA)
 544                         return 1;
 545                 return 0;
 546         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 547         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 548         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 549         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 550         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 551                 return 0;
 552         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 553                 /* due to a bug in the shader compiler, some loops hang
 554                  * if they are not unrolled, see:
 555                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 556                  */
 557                 return 255;
 558         }
 559         return 0;
 560 }
 561
 562 static void r600_destroy_screen(struct pipe_screen* pscreen)
 563 {
 564         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 565
 566         if (!rscreen)
 567                 return;
 568
 569         if (!rscreen->b.ws->unref(rscreen->b.ws))
 570                 return;
 571
 572         if (rscreen->global_pool) {
 573                 compute_memory_pool_delete(rscreen->global_pool);
 574         }
 575
 576         r600_destroy_common_screen(&rscreen->b);
 577 }
 578
 579 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 580                                                   const struct pipe_resource *templ)
 581 {
 582         if (templ->target == PIPE_BUFFER &&
 583             (templ->bind & PIPE_BIND_GLOBAL))
 584                 return r600_compute_global_buffer_create(screen, templ);
 585
 586         return r600_resource_create_common(screen, templ);
 587 }
 588
 589 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 590 {
 591         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 592
 593         if (!rscreen) {
 594                 return NULL;
 595         }
 596
 597         /* Set functions first. */
 598         rscreen->b.b.context_create = r600_create_context;
 599         rscreen->b.b.destroy = r600_destroy_screen;
 600         rscreen->b.b.get_param = r600_get_param;
 601         rscreen->b.b.get_shader_param = r600_get_shader_param;
 602         rscreen->b.b.resource_create = r600_resource_create;
 603
 604         if (!r600_common_screen_init(&rscreen->b, ws)) {
 605                 FREE(rscreen);
 606                 return NULL;
 607         }
 608
 609         if (rscreen->b.info.chip_class >= EVERGREEN) {
 610                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 611         } else {
 612                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 613         }
 614
 615         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 616         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 617                 rscreen->b.debug_flags |= DBG_COMPUTE;
 618         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 619                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
 620         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 621                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 622
 623         if (rscreen->b.family == CHIP_UNKNOWN) {
 624                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 625                 FREE(rscreen);
 626                 return NULL;
 627         }
 628
 629         /* Figure out streamout kernel support. */
 630         switch (rscreen->b.chip_class) {
 631         case R600:
 632                 if (rscreen->b.family < CHIP_RS780) {
 633                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 634                 } else {
 635                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 636                 }
 637                 break;
 638         case R700:
 639                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 640                 break;
 641         case EVERGREEN:
 642         case CAYMAN:
 643                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 644                 break;
 645         default:
 646                 rscreen->b.has_streamout = FALSE;
 647                 break;
 648         }
 649
 650         /* MSAA support. */
 651         switch (rscreen->b.chip_class) {
 652         case R600:
 653         case R700:
 654                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 655                 rscreen->has_compressed_msaa_texturing = false;
 656                 break;
 657         case EVERGREEN:
 658                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 659                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 660                 break;
 661         case CAYMAN:
 662                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 663                 rscreen->has_compressed_msaa_texturing = true;
 664                 break;
 665         default:
 666                 rscreen->has_msaa = FALSE;
 667                 rscreen->has_compressed_msaa_texturing = false;
 668         }
 669
 670         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 671                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 672
 673         rscreen->global_pool = compute_memory_pool_new(rscreen);
 674
 675         /* Create the auxiliary context. This must be done last. */
 676         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 677
 678 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 679         struct pipe_resource templ = {};
 680
 681         templ.width0 = 4;
 682         templ.height0 = 2048;
 683         templ.depth0 = 1;
 684         templ.array_size = 1;
 685         templ.target = PIPE_TEXTURE_2D;
 686         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 687         templ.usage = PIPE_USAGE_DEFAULT;
 688
 689         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 690         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 691
 692         memset(map, 0, 256);
 693
 694         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 695         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 696         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 697         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 698         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 699
 700         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 701
 702         int i;
 703         for (i = 0; i < 256; i++) {
 704                 printf("%02X", map[i]);
 705                 if (i % 16 == 15)
 706                         printf("\n");
 707         }
 708 #endif
 709
 710         return &rscreen->b.b;
 711 }