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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 56
42
43 #define R600_MAX_IMAGES 8
44 /*
45 * ranges reserved for images on evergreen
46 * first set for the immediate buffers,
47 * second for the actual resources for RESQ.
48 */
49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
51
52 /* read caches */
53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* read-write caches */
57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* engine synchronization */
63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66
67 /* the number of CS dwords for flushing and drawing */
68 #define R600_MAX_FLUSH_CS_DWORDS 18
69 #define R600_MAX_DRAW_CS_DWORDS 58
70 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
71
72 #define R600_MAX_USER_CONST_BUFFERS 13
73 #define R600_MAX_DRIVER_CONST_BUFFERS 3
74 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
75
76 #define EG_MAX_ATOMIC_BUFFERS 8
77
78 /* start driver buffers after user buffers */
79 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
80 #define R600_UCP_SIZE (4*4*8)
81 #define R600_CS_BLOCK_GRID_SIZE (8 * 4)
82 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
83
84 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
85 /*
86 * Note GS doesn't use a constant buffer binding, just a resource index,
87 * so it's fine to have it exist at index 16.
88 */
89 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
90 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
91 * of 16 const buffers.
92 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
93 *
94 * In order to support d3d 11 mandated minimum of 15 user const buffers
95 * we'd have to squash all use cases into one driver buffer.
96 */
97 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
98
99 /* HW stages */
100 #define R600_HW_STAGE_PS 0
101 #define R600_HW_STAGE_VS 1
102 #define R600_HW_STAGE_GS 2
103 #define R600_HW_STAGE_ES 3
104 #define EG_HW_STAGE_LS 4
105 #define EG_HW_STAGE_HS 5
106
107 #define R600_NUM_HW_STAGES 4
108 #define EG_NUM_HW_STAGES 6
109
110 struct r600_context;
111 struct r600_bytecode;
112 union r600_shader_key;
113
114 /* This is an atom containing GPU commands that never change.
115 * This is supposed to be copied directly into the CS. */
116 struct r600_command_buffer {
117 uint32_t *buf;
118 unsigned num_dw;
119 unsigned max_num_dw;
120 unsigned pkt_flags;
121 };
122
123 struct r600_db_state {
124 struct r600_atom atom;
125 struct r600_surface *rsurf;
126 };
127
128 struct r600_db_misc_state {
129 struct r600_atom atom;
130 bool occlusion_queries_disabled;
131 bool flush_depthstencil_through_cb;
132 bool flush_depth_inplace;
133 bool flush_stencil_inplace;
134 bool copy_depth, copy_stencil;
135 unsigned copy_sample;
136 unsigned log_samples;
137 unsigned db_shader_control;
138 bool htile_clear;
139 uint8_t ps_conservative_z;
140 };
141
142 struct r600_cb_misc_state {
143 struct r600_atom atom;
144 unsigned cb_color_control; /* this comes from blend state */
145 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
146 unsigned nr_cbufs;
147 unsigned nr_ps_color_outputs;
148 unsigned nr_image_rats;
149 unsigned nr_buffer_rats;
150 bool multiwrite;
151 bool dual_src_blend;
152 };
153
154 struct r600_clip_misc_state {
155 struct r600_atom atom;
156 unsigned pa_cl_clip_cntl; /* from rasterizer */
157 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
158 unsigned clip_plane_enable; /* from rasterizer */
159 unsigned cc_dist_mask; /* from vertex shader */
160 unsigned clip_dist_write; /* from vertex shader */
161 unsigned cull_dist_write; /* from vertex shader */
162 boolean clip_disable; /* from vertex shader */
163 boolean vs_out_viewport; /* from vertex shader */
164 };
165
166 struct r600_alphatest_state {
167 struct r600_atom atom;
168 unsigned sx_alpha_test_control; /* this comes from dsa state */
169 unsigned sx_alpha_ref; /* this comes from dsa state */
170 bool bypass;
171 bool cb0_export_16bpc; /* from set_framebuffer_state */
172 };
173
174 struct r600_vgt_state {
175 struct r600_atom atom;
176 uint32_t vgt_multi_prim_ib_reset_en;
177 uint32_t vgt_multi_prim_ib_reset_indx;
178 uint32_t vgt_indx_offset;
179 bool last_draw_was_indirect;
180 };
181
182 struct r600_blend_color {
183 struct r600_atom atom;
184 struct pipe_blend_color state;
185 };
186
187 struct r600_clip_state {
188 struct r600_atom atom;
189 struct pipe_clip_state state;
190 };
191
192 struct r600_cs_shader_state {
193 struct r600_atom atom;
194 unsigned kernel_index;
195 unsigned pc;
196 struct r600_pipe_compute *shader;
197 };
198
199 struct r600_framebuffer {
200 struct r600_atom atom;
201 struct pipe_framebuffer_state state;
202 unsigned compressed_cb_mask;
203 unsigned nr_samples;
204 bool export_16bpc;
205 bool cb0_is_integer;
206 bool is_msaa_resolve;
207 bool dual_src_blend;
208 bool do_update_surf_dirtiness;
209 };
210
211 struct r600_sample_mask {
212 struct r600_atom atom;
213 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
214 };
215
216 struct r600_config_state {
217 struct r600_atom atom;
218 unsigned sq_gpr_resource_mgmt_1;
219 unsigned sq_gpr_resource_mgmt_2;
220 unsigned sq_gpr_resource_mgmt_3;
221 bool dyn_gpr_enabled;
222 };
223
224 struct r600_stencil_ref
225 {
226 ubyte ref_value[2];
227 ubyte valuemask[2];
228 ubyte writemask[2];
229 };
230
231 struct r600_stencil_ref_state {
232 struct r600_atom atom;
233 struct r600_stencil_ref state;
234 struct pipe_stencil_ref pipe_state;
235 };
236
237 struct r600_shader_stages_state {
238 struct r600_atom atom;
239 unsigned geom_enable;
240 };
241
242 struct r600_gs_rings_state {
243 struct r600_atom atom;
244 unsigned enable;
245 struct pipe_constant_buffer esgs_ring;
246 struct pipe_constant_buffer gsvs_ring;
247 };
248
249 /* This must start from 16. */
250 /* features */
251 #define DBG_NO_CP_DMA (1 << 30)
252 /* shader backend */
253 #define DBG_NO_SB (1 << 21)
254 #define DBG_SB_CS (1 << 22)
255 #define DBG_SB_DRY_RUN (1 << 23)
256 #define DBG_SB_STAT (1 << 24)
257 #define DBG_SB_DUMP (1 << 25)
258 #define DBG_SB_NO_FALLBACK (1 << 26)
259 #define DBG_SB_DISASM (1 << 27)
260 #define DBG_SB_SAFEMATH (1 << 28)
261
262 struct r600_screen {
263 struct r600_common_screen b;
264 bool has_msaa;
265 bool has_compressed_msaa_texturing;
266 bool has_atomics;
267
268 /*for compute global memory binding, we allocate stuff here, instead of
269 * buffers.
270 * XXX: Not sure if this is the best place for global_pool. Also,
271 * it's not thread safe, so it won't work with multiple contexts. */
272 struct compute_memory_pool *global_pool;
273 };
274
275 struct r600_pipe_sampler_view {
276 struct pipe_sampler_view base;
277 struct list_head list;
278 struct r600_resource *tex_resource;
279 uint32_t tex_resource_words[8];
280 bool skip_mip_address_reloc;
281 bool is_stencil_sampler;
282 };
283
284 struct r600_rasterizer_state {
285 struct r600_command_buffer buffer;
286 boolean flatshade;
287 boolean two_side;
288 unsigned sprite_coord_enable;
289 unsigned clip_plane_enable;
290 unsigned pa_sc_line_stipple;
291 unsigned pa_cl_clip_cntl;
292 unsigned pa_su_sc_mode_cntl;
293 float offset_units;
294 float offset_scale;
295 bool offset_enable;
296 bool offset_units_unscaled;
297 bool scissor_enable;
298 bool multisample_enable;
299 bool clip_halfz;
300 bool rasterizer_discard;
301 };
302
303 struct r600_poly_offset_state {
304 struct r600_atom atom;
305 enum pipe_format zs_format;
306 float offset_units;
307 float offset_scale;
308 bool offset_units_unscaled;
309 };
310
311 struct r600_blend_state {
312 struct r600_command_buffer buffer;
313 struct r600_command_buffer buffer_no_blend;
314 unsigned cb_target_mask;
315 unsigned cb_color_control;
316 unsigned cb_color_control_no_blend;
317 bool dual_src_blend;
318 bool alpha_to_one;
319 };
320
321 struct r600_dsa_state {
322 struct r600_command_buffer buffer;
323 unsigned alpha_ref;
324 ubyte valuemask[2];
325 ubyte writemask[2];
326 unsigned zwritemask;
327 unsigned sx_alpha_test_control;
328 };
329
330 struct r600_pipe_shader;
331
332 struct r600_pipe_shader_selector {
333 struct r600_pipe_shader *current;
334
335 struct tgsi_token *tokens;
336 struct pipe_stream_output_info so;
337 struct tgsi_shader_info info;
338
339 unsigned num_shaders;
340
341 enum pipe_shader_type type;
342
343 /* geometry shader properties */
344 enum pipe_prim_type gs_output_prim;
345 unsigned gs_max_out_vertices;
346 unsigned gs_num_invocations;
347
348 /* TCS/VS */
349 uint64_t lds_patch_outputs_written_mask;
350 uint64_t lds_outputs_written_mask;
351 unsigned nr_ps_max_color_exports;
352 };
353
354 struct r600_pipe_sampler_state {
355 uint32_t tex_sampler_words[3];
356 union pipe_color_union border_color;
357 bool border_color_use;
358 bool seamless_cube_map;
359 };
360
361 /* needed for blitter save */
362 #define NUM_TEX_UNITS 16
363
364 struct r600_seamless_cube_map {
365 struct r600_atom atom;
366 bool enabled;
367 };
368
369 struct r600_samplerview_state {
370 struct r600_atom atom;
371 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
372 uint32_t enabled_mask;
373 uint32_t dirty_mask;
374 uint32_t compressed_depthtex_mask; /* which textures are depth */
375 uint32_t compressed_colortex_mask;
376 boolean dirty_buffer_constants;
377 };
378
379 struct r600_sampler_states {
380 struct r600_atom atom;
381 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
382 uint32_t enabled_mask;
383 uint32_t dirty_mask;
384 uint32_t has_bordercolor_mask; /* which states contain the border color */
385 };
386
387 struct r600_textures_info {
388 struct r600_samplerview_state views;
389 struct r600_sampler_states states;
390 bool is_array_sampler[NUM_TEX_UNITS];
391 };
392
393 struct r600_shader_driver_constants_info {
394 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
395 uint32_t *constants;
396 uint32_t alloc_size;
397 bool vs_ucp_dirty;
398 bool texture_const_dirty;
399 bool ps_sample_pos_dirty;
400 bool cs_block_grid_size_dirty;
401 };
402
403 struct r600_constbuf_state
404 {
405 struct r600_atom atom;
406 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
407 uint32_t enabled_mask;
408 uint32_t dirty_mask;
409 };
410
411 struct r600_vertexbuf_state
412 {
413 struct r600_atom atom;
414 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
415 uint32_t enabled_mask; /* non-NULL buffers */
416 uint32_t dirty_mask;
417 };
418
419 /* CSO (constant state object, in other words, immutable state). */
420 struct r600_cso_state
421 {
422 struct r600_atom atom;
423 void *cso; /* e.g. r600_blend_state */
424 struct r600_command_buffer *cb;
425 };
426
427 struct r600_fetch_shader {
428 struct r600_resource *buffer;
429 unsigned offset;
430 };
431
432 struct r600_shader_state {
433 struct r600_atom atom;
434 struct r600_pipe_shader *shader;
435 };
436
437 struct r600_atomic_buffer_state {
438 uint32_t enabled_mask;
439 uint32_t dirty_mask;
440 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
441 };
442
443 struct r600_image_view {
444 struct pipe_image_view base;
445 uint32_t cb_color_base;
446 uint32_t cb_color_pitch;
447 uint32_t cb_color_slice;
448 uint32_t cb_color_view;
449 uint32_t cb_color_info;
450 uint32_t cb_color_attrib;
451 uint32_t cb_color_dim;
452 uint32_t cb_color_fmask;
453 uint32_t cb_color_fmask_slice;
454 uint32_t immed_resource_words[8];
455 uint32_t resource_words[8];
456 bool skip_mip_address_reloc;
457 uint32_t buf_size;
458 };
459
460 struct r600_image_state {
461 struct r600_atom atom;
462 uint32_t enabled_mask;
463 uint32_t dirty_mask;
464 uint32_t compressed_depthtex_mask;
465 uint32_t compressed_colortex_mask;
466 boolean dirty_buffer_constants;
467 struct r600_image_view views[R600_MAX_IMAGES];
468 };
469
470 struct r600_context {
471 struct r600_common_context b;
472 struct r600_screen *screen;
473 struct blitter_context *blitter;
474 struct u_suballocator *allocator_fetch_shader;
475
476 /* Hardware info. */
477 boolean has_vertex_cache;
478 unsigned default_gprs[EG_NUM_HW_STAGES];
479 unsigned current_gprs[EG_NUM_HW_STAGES];
480 unsigned r6xx_num_clause_temp_gprs;
481
482 /* Miscellaneous state objects. */
483 void *custom_dsa_flush;
484 void *custom_blend_resolve;
485 void *custom_blend_decompress;
486 void *custom_blend_fastclear;
487 /* With rasterizer discard, there doesn't have to be a pixel shader.
488 * In that case, we bind this one: */
489 void *dummy_pixel_shader;
490 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
491 * bug where valid CMASK and FMASK are required to be present to avoid
492 * a hardlock in certain operations but aren't actually used
493 * for anything useful. */
494 struct r600_resource *dummy_fmask;
495 struct r600_resource *dummy_cmask;
496
497 /* State binding slots are here. */
498 struct r600_atom *atoms[R600_NUM_ATOMS];
499 /* Dirty atom bitmask for fast tests */
500 uint64_t dirty_atoms;
501 /* States for CS initialization. */
502 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
503 /** Compute specific registers initializations. The start_cs_cmd atom
504 * must be emitted before start_compute_cs_cmd. */
505 struct r600_command_buffer start_compute_cs_cmd;
506 /* Register states. */
507 struct r600_alphatest_state alphatest_state;
508 struct r600_cso_state blend_state;
509 struct r600_blend_color blend_color;
510 struct r600_cb_misc_state cb_misc_state;
511 struct r600_clip_misc_state clip_misc_state;
512 struct r600_clip_state clip_state;
513 struct r600_db_misc_state db_misc_state;
514 struct r600_db_state db_state;
515 struct r600_cso_state dsa_state;
516 struct r600_framebuffer framebuffer;
517 struct r600_poly_offset_state poly_offset_state;
518 struct r600_cso_state rasterizer_state;
519 struct r600_sample_mask sample_mask;
520 struct r600_seamless_cube_map seamless_cube_map;
521 struct r600_config_state config_state;
522 struct r600_stencil_ref_state stencil_ref;
523 struct r600_vgt_state vgt_state;
524 struct r600_atomic_buffer_state atomic_buffer_state;
525 /* only have images on fragment shader */
526 struct r600_image_state fragment_images;
527 struct r600_image_state compute_images;
528 struct r600_image_state fragment_buffers;
529 struct r600_image_state compute_buffers;
530 /* Shaders and shader resources. */
531 struct r600_cso_state vertex_fetch_shader;
532 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
533 struct r600_cs_shader_state cs_shader_state;
534 struct r600_shader_stages_state shader_stages;
535 struct r600_gs_rings_state gs_rings;
536 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
537 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
538
539 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
540
541 /** Vertex buffers for fetch shaders */
542 struct r600_vertexbuf_state vertex_buffer_state;
543 /** Vertex buffers for compute shaders */
544 struct r600_vertexbuf_state cs_vertex_buffer_state;
545
546 /* Additional context states. */
547 unsigned compute_cb_target_mask;
548 struct r600_pipe_shader_selector *ps_shader;
549 struct r600_pipe_shader_selector *vs_shader;
550 struct r600_pipe_shader_selector *gs_shader;
551
552 struct r600_pipe_shader_selector *tcs_shader;
553 struct r600_pipe_shader_selector *tes_shader;
554
555 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
556
557 struct r600_rasterizer_state *rasterizer;
558 bool alpha_to_one;
559 bool force_blend_disable;
560 bool gs_tri_strip_adj_fix;
561 boolean dual_src_blend;
562 unsigned zwritemask;
563 int ps_iter_samples;
564
565 /* The list of all texture buffer objects in this context.
566 * This list is walked when a buffer is invalidated/reallocated and
567 * the GPU addresses are updated. */
568 struct list_head texture_buffers;
569
570 /* Last draw state (-1 = unset). */
571 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
572 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
573 enum pipe_prim_type last_rast_prim;
574 unsigned last_start_instance;
575
576 void *sb_context;
577 struct r600_isa *isa;
578 float sample_positions[4 * 16];
579 float tess_state[8];
580 uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/
581 bool tess_state_dirty;
582 struct r600_pipe_shader_selector *last_ls;
583 struct r600_pipe_shader_selector *last_tcs;
584 unsigned last_num_tcs_input_cp;
585 unsigned lds_alloc;
586
587 /* Debug state. */
588 bool is_debug;
589 struct radeon_saved_cs last_gfx;
590 struct r600_resource *last_trace_buf;
591 struct r600_resource *trace_buf;
592 unsigned trace_id;
593
594 bool cmd_buf_is_compute;
595 struct pipe_resource *append_fence;
596 uint32_t append_fence_id;
597 };
598
599 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
600 struct r600_command_buffer *cb)
601 {
602 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
603 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
604 cs->current.cdw += cb->num_dw;
605 }
606
607 static inline void r600_set_atom_dirty(struct r600_context *rctx,
608 struct r600_atom *atom,
609 bool dirty)
610 {
611 uint64_t mask;
612
613 assert(atom->id != 0);
614 assert(atom->id < sizeof(mask) * 8);
615 mask = 1ull << atom->id;
616 if (dirty)
617 rctx->dirty_atoms |= mask;
618 else
619 rctx->dirty_atoms &= ~mask;
620 }
621
622 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
623 struct r600_atom *atom)
624 {
625 r600_set_atom_dirty(rctx, atom, true);
626 }
627
628 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
629 {
630 atom->emit(&rctx->b, atom);
631 r600_set_atom_dirty(rctx, atom, false);
632 }
633
634 static inline void r600_set_cso_state(struct r600_context *rctx,
635 struct r600_cso_state *state, void *cso)
636 {
637 state->cso = cso;
638 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
639 }
640
641 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
642 struct r600_cso_state *state, void *cso,
643 struct r600_command_buffer *cb)
644 {
645 state->cb = cb;
646 state->atom.num_dw = cb ? cb->num_dw : 0;
647 r600_set_cso_state(rctx, state, cso);
648 }
649
650 /* compute_memory_pool.c */
651 struct compute_memory_pool;
652 void compute_memory_pool_delete(struct compute_memory_pool* pool);
653 struct compute_memory_pool* compute_memory_pool_new(
654 struct r600_screen *rscreen);
655
656 /* evergreen_state.c */
657 struct pipe_sampler_view *
658 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
659 struct pipe_resource *texture,
660 const struct pipe_sampler_view *state,
661 unsigned width0, unsigned height0,
662 unsigned force_level);
663 void evergreen_init_common_regs(struct r600_context *ctx,
664 struct r600_command_buffer *cb,
665 enum chip_class ctx_chip_class,
666 enum radeon_family ctx_family,
667 int ctx_drm_minor);
668 void cayman_init_common_regs(struct r600_command_buffer *cb,
669 enum chip_class ctx_chip_class,
670 enum radeon_family ctx_family,
671 int ctx_drm_minor);
672
673 void evergreen_init_state_functions(struct r600_context *rctx);
674 void evergreen_init_atom_start_cs(struct r600_context *rctx);
675 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
676 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
677 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
678 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
679 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
680 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
681 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
682 void *evergreen_create_resolve_blend(struct r600_context *rctx);
683 void *evergreen_create_decompress_blend(struct r600_context *rctx);
684 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
685 boolean evergreen_is_format_supported(struct pipe_screen *screen,
686 enum pipe_format format,
687 enum pipe_texture_target target,
688 unsigned sample_count,
689 unsigned usage);
690 void evergreen_init_color_surface(struct r600_context *rctx,
691 struct r600_surface *surf);
692 void evergreen_init_color_surface_rat(struct r600_context *rctx,
693 struct r600_surface *surf);
694 void evergreen_update_db_shader_control(struct r600_context * rctx);
695 bool evergreen_adjust_gprs(struct r600_context *rctx);
696 /* r600_blit.c */
697 void r600_init_blit_functions(struct r600_context *rctx);
698 void r600_decompress_depth_textures(struct r600_context *rctx,
699 struct r600_samplerview_state *textures);
700 void r600_decompress_depth_images(struct r600_context *rctx,
701 struct r600_image_state *images);
702 void r600_decompress_color_textures(struct r600_context *rctx,
703 struct r600_samplerview_state *textures);
704 void r600_decompress_color_images(struct r600_context *rctx,
705 struct r600_image_state *images);
706 void r600_resource_copy_region(struct pipe_context *ctx,
707 struct pipe_resource *dst,
708 unsigned dst_level,
709 unsigned dstx, unsigned dsty, unsigned dstz,
710 struct pipe_resource *src,
711 unsigned src_level,
712 const struct pipe_box *src_box);
713
714 /* r600_shader.c */
715 int r600_pipe_shader_create(struct pipe_context *ctx,
716 struct r600_pipe_shader *shader,
717 union r600_shader_key key);
718
719 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
720
721 /* r600_state.c */
722 struct pipe_sampler_view *
723 r600_create_sampler_view_custom(struct pipe_context *ctx,
724 struct pipe_resource *texture,
725 const struct pipe_sampler_view *state,
726 unsigned width_first_level, unsigned height_first_level);
727 void r600_init_state_functions(struct r600_context *rctx);
728 void r600_init_atom_start_cs(struct r600_context *rctx);
729 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
730 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
731 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
732 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
733 void *r600_create_db_flush_dsa(struct r600_context *rctx);
734 void *r600_create_resolve_blend(struct r600_context *rctx);
735 void *r700_create_resolve_blend(struct r600_context *rctx);
736 void *r600_create_decompress_blend(struct r600_context *rctx);
737 bool r600_adjust_gprs(struct r600_context *rctx);
738 boolean r600_is_format_supported(struct pipe_screen *screen,
739 enum pipe_format format,
740 enum pipe_texture_target target,
741 unsigned sample_count,
742 unsigned usage);
743 void r600_update_db_shader_control(struct r600_context * rctx);
744
745 /* r600_hw_context.c */
746 void r600_context_gfx_flush(void *context, unsigned flags,
747 struct pipe_fence_handle **fence);
748 void r600_begin_new_cs(struct r600_context *ctx);
749 void r600_flush_emit(struct r600_context *ctx);
750 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
751 void r600_emit_pfp_sync_me(struct r600_context *rctx);
752 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
753 struct pipe_resource *dst, uint64_t dst_offset,
754 struct pipe_resource *src, uint64_t src_offset,
755 unsigned size);
756 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
757 struct pipe_resource *dst, uint64_t offset,
758 unsigned size, uint32_t clear_value,
759 enum r600_coherency coher);
760 void r600_dma_copy_buffer(struct r600_context *rctx,
761 struct pipe_resource *dst,
762 struct pipe_resource *src,
763 uint64_t dst_offset,
764 uint64_t src_offset,
765 uint64_t size);
766
767 /*
768 * evergreen_hw_context.c
769 */
770 void evergreen_dma_copy_buffer(struct r600_context *rctx,
771 struct pipe_resource *dst,
772 struct pipe_resource *src,
773 uint64_t dst_offset,
774 uint64_t src_offset,
775 uint64_t size);
776 void evergreen_setup_tess_constants(struct r600_context *rctx,
777 const struct pipe_draw_info *info,
778 unsigned *num_patches);
779 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
780 const struct pipe_draw_info *info,
781 unsigned num_patches);
782 void evergreen_set_ls_hs_config(struct r600_context *rctx,
783 struct radeon_winsys_cs *cs,
784 uint32_t ls_hs_config);
785 void evergreen_set_lds_alloc(struct r600_context *rctx,
786 struct radeon_winsys_cs *cs,
787 uint32_t lds_alloc);
788
789 /* r600_state_common.c */
790 void r600_init_common_state_functions(struct r600_context *rctx);
791 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
792 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
793 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
794 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
795 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
796 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
797 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
798 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
799 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
800 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
801 unsigned num_dw);
802 void r600_vertex_buffers_dirty(struct r600_context *rctx);
803 void r600_sampler_views_dirty(struct r600_context *rctx,
804 struct r600_samplerview_state *state);
805 void r600_sampler_states_dirty(struct r600_context *rctx,
806 struct r600_sampler_states *state);
807 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
808 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
809 uint32_t r600_translate_stencil_op(int s_op);
810 uint32_t r600_translate_fill(uint32_t func);
811 unsigned r600_tex_wrap(unsigned wrap);
812 unsigned r600_tex_mipfilter(unsigned filter);
813 unsigned r600_tex_compare(unsigned compare);
814 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
815 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
816 const unsigned char *swizzle_view,
817 boolean vtx);
818 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
819 const unsigned char *swizzle_view,
820 uint32_t *word4_p, uint32_t *yuv_format_p,
821 bool do_endian_swap);
822 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
823 bool do_endian_swap);
824 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
825
826 /* r600_uvd.c */
827 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
828 const struct pipe_video_codec *decoder);
829
830 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
831 const struct pipe_video_buffer *tmpl);
832
833 /*
834 * Helpers for building command buffers
835 */
836
837 #define PKT3_SET_CONFIG_REG 0x68
838 #define PKT3_SET_CONTEXT_REG 0x69
839 #define PKT3_SET_CTL_CONST 0x6F
840 #define PKT3_SET_LOOP_CONST 0x6C
841
842 #define R600_CONFIG_REG_OFFSET 0x08000
843 #define R600_CONTEXT_REG_OFFSET 0x28000
844 #define R600_CTL_CONST_OFFSET 0x3CFF0
845 #define R600_LOOP_CONST_OFFSET 0X0003E200
846 #define EG_LOOP_CONST_OFFSET 0x0003A200
847
848 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
849 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
850 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
851 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
852 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
853
854 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
855
856 /*Evergreen Compute packet3*/
857 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
858
859 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
860 {
861 cb->buf[cb->num_dw++] = value;
862 }
863
864 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
865 {
866 assert(cb->num_dw+num <= cb->max_num_dw);
867 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
868 cb->num_dw += num;
869 }
870
871 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
872 {
873 assert(reg < R600_CONTEXT_REG_OFFSET);
874 assert(cb->num_dw+2+num <= cb->max_num_dw);
875 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
876 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
877 }
878
879 /**
880 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
881 * shaders.
882 */
883 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
884 {
885 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
886 assert(cb->num_dw+2+num <= cb->max_num_dw);
887 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
888 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
889 }
890
891 /**
892 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
893 * shaders.
894 */
895 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
896 {
897 assert(reg >= R600_CTL_CONST_OFFSET);
898 assert(cb->num_dw+2+num <= cb->max_num_dw);
899 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
900 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
901 }
902
903 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
904 {
905 assert(reg >= R600_LOOP_CONST_OFFSET);
906 assert(cb->num_dw+2+num <= cb->max_num_dw);
907 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
908 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
909 }
910
911 /**
912 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
913 * shaders.
914 */
915 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
916 {
917 assert(reg >= EG_LOOP_CONST_OFFSET);
918 assert(cb->num_dw+2+num <= cb->max_num_dw);
919 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
920 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
921 }
922
923 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
924 {
925 r600_store_config_reg_seq(cb, reg, 1);
926 r600_store_value(cb, value);
927 }
928
929 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
930 {
931 r600_store_context_reg_seq(cb, reg, 1);
932 r600_store_value(cb, value);
933 }
934
935 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
936 {
937 r600_store_ctl_const_seq(cb, reg, 1);
938 r600_store_value(cb, value);
939 }
940
941 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
942 {
943 r600_store_loop_const_seq(cb, reg, 1);
944 r600_store_value(cb, value);
945 }
946
947 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
948 {
949 eg_store_loop_const_seq(cb, reg, 1);
950 r600_store_value(cb, value);
951 }
952
953 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
954 void r600_release_command_buffer(struct r600_command_buffer *cb);
955
956 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
957 {
958 radeon_set_context_reg_seq(cs, reg, num);
959 /* Set the compute bit on the packet header */
960 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
961 }
962
963 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
964 {
965 assert(reg >= R600_CTL_CONST_OFFSET);
966 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
967 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
968 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
969 }
970
971 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
972 {
973 radeon_compute_set_context_reg_seq(cs, reg, 1);
974 radeon_emit(cs, value);
975 }
976
977 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
978 {
979 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
980 radeon_compute_set_context_reg(cs, reg, value);
981 } else {
982 radeon_set_context_reg(cs, reg, value);
983 }
984 }
985
986 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
987 {
988 radeon_set_ctl_const_seq(cs, reg, 1);
989 radeon_emit(cs, value);
990 }
991
992 /*
993 * common helpers
994 */
995
996 /* 12.4 fixed-point */
997 static inline unsigned r600_pack_float_12p4(float x)
998 {
999 return x <= 0 ? 0 :
1000 x >= 4096 ? 0xffff : x * 16;
1001 }
1002
1003 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
1004 {
1005 switch (coher) {
1006 default:
1007 case R600_COHERENCY_NONE:
1008 return 0;
1009 case R600_COHERENCY_SHADER:
1010 return R600_CONTEXT_INV_CONST_CACHE |
1011 R600_CONTEXT_INV_VERTEX_CACHE |
1012 R600_CONTEXT_INV_TEX_CACHE |
1013 R600_CONTEXT_STREAMOUT_FLUSH;
1014 case R600_COHERENCY_CB_META:
1015 return R600_CONTEXT_FLUSH_AND_INV_CB |
1016 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1017 }
1018 }
1019
1020 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1021 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1022 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1023
1024 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1025
1026 void eg_trace_emit(struct r600_context *rctx);
1027 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1028 unsigned flags);
1029
1030 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
1031 const struct tgsi_token *tokens,
1032 unsigned pipe_shader_type);
1033 int r600_shader_select(struct pipe_context *ctx,
1034 struct r600_pipe_shader_selector* sel,
1035 bool *dirty);
1036
1037 void r600_delete_shader_selector(struct pipe_context *ctx,
1038 struct r600_pipe_shader_selector *sel);
1039
1040 struct r600_shader_atomic;
1041 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1042 struct r600_pipe_shader *cs_shader,
1043 struct r600_shader_atomic *combined_atomics,
1044 uint8_t *atomic_used_mask_p);
1045 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1046 bool is_compute,
1047 struct r600_shader_atomic *combined_atomics,
1048 uint8_t *atomic_used_mask_p);
1049 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only);
1050
1051 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type);
1052 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only);
1053 #endif