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util: Change remaining uint32 cache ids to sha1
[mesa.git] / src / gallium / drivers / r600 / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t new_fence, unsigned query_type)
107 {
108 struct radeon_cmdbuf *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112 unsigned sel = EOP_DATA_SEL(data_sel);
113
114 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
115 radeon_emit(cs, op);
116 radeon_emit(cs, va);
117 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
118 radeon_emit(cs, new_fence); /* immediate data */
119 radeon_emit(cs, 0); /* unused */
120
121 if (buf)
122 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
123 RADEON_PRIO_QUERY);
124 }
125
126 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
127 {
128 unsigned dwords = 6;
129
130 if (!screen->info.r600_has_virtual_memory)
131 dwords += 2;
132
133 return dwords;
134 }
135
136 void r600_gfx_wait_fence(struct r600_common_context *ctx,
137 struct r600_resource *buf,
138 uint64_t va, uint32_t ref, uint32_t mask)
139 {
140 struct radeon_cmdbuf *cs = ctx->gfx.cs;
141
142 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
143 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
144 radeon_emit(cs, va);
145 radeon_emit(cs, va >> 32);
146 radeon_emit(cs, ref); /* reference value */
147 radeon_emit(cs, mask); /* mask */
148 radeon_emit(cs, 4); /* poll interval */
149
150 if (buf)
151 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
152 RADEON_PRIO_QUERY);
153 }
154
155 void r600_draw_rectangle(struct blitter_context *blitter,
156 void *vertex_elements_cso,
157 blitter_get_vs_func get_vs,
158 int x1, int y1, int x2, int y2,
159 float depth, unsigned num_instances,
160 enum blitter_attrib_type type,
161 const union blitter_attrib *attrib)
162 {
163 struct r600_common_context *rctx =
164 (struct r600_common_context*)util_blitter_get_pipe(blitter);
165 struct pipe_viewport_state viewport;
166 struct pipe_resource *buf = NULL;
167 unsigned offset = 0;
168 float *vb;
169
170 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
171 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
172
173 /* Some operations (like color resolve on r6xx) don't work
174 * with the conventional primitive types.
175 * One that works is PT_RECTLIST, which we use here. */
176
177 /* setup viewport */
178 viewport.scale[0] = 1.0f;
179 viewport.scale[1] = 1.0f;
180 viewport.scale[2] = 1.0f;
181 viewport.translate[0] = 0.0f;
182 viewport.translate[1] = 0.0f;
183 viewport.translate[2] = 0.0f;
184 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
185
186 /* Upload vertices. The hw rectangle has only 3 vertices,
187 * The 4th one is derived from the first 3.
188 * The vertex specification should match u_blitter's vertex element state. */
189 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
190 rctx->screen->info.tcc_cache_line_size,
191 &offset, &buf, (void**)&vb);
192 if (!buf)
193 return;
194
195 vb[0] = x1;
196 vb[1] = y1;
197 vb[2] = depth;
198 vb[3] = 1;
199
200 vb[8] = x1;
201 vb[9] = y2;
202 vb[10] = depth;
203 vb[11] = 1;
204
205 vb[16] = x2;
206 vb[17] = y1;
207 vb[18] = depth;
208 vb[19] = 1;
209
210 switch (type) {
211 case UTIL_BLITTER_ATTRIB_COLOR:
212 memcpy(vb+4, attrib->color, sizeof(float)*4);
213 memcpy(vb+12, attrib->color, sizeof(float)*4);
214 memcpy(vb+20, attrib->color, sizeof(float)*4);
215 break;
216 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
217 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
218 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
219 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
220 /* fall through */
221 vb[4] = attrib->texcoord.x1;
222 vb[5] = attrib->texcoord.y1;
223 vb[12] = attrib->texcoord.x1;
224 vb[13] = attrib->texcoord.y2;
225 vb[20] = attrib->texcoord.x2;
226 vb[21] = attrib->texcoord.y1;
227 break;
228 default:; /* Nothing to do. */
229 }
230
231 /* draw */
232 struct pipe_vertex_buffer vbuffer = {};
233 vbuffer.buffer.resource = buf;
234 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
235 vbuffer.buffer_offset = offset;
236
237 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
238 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
239 0, num_instances);
240 pipe_resource_reference(&buf, NULL);
241 }
242
243 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
244 {
245 struct radeon_cmdbuf *cs = rctx->dma.cs;
246
247 if (rctx->chip_class >= EVERGREEN)
248 radeon_emit(cs, 0xf0000000); /* NOP */
249 else {
250 /* TODO: R600-R700 should use the FENCE packet.
251 * CS checker support is required. */
252 }
253 }
254
255 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
256 struct r600_resource *dst, struct r600_resource *src)
257 {
258 uint64_t vram = ctx->dma.cs->used_vram;
259 uint64_t gtt = ctx->dma.cs->used_gart;
260
261 if (dst) {
262 vram += dst->vram_usage;
263 gtt += dst->gart_usage;
264 }
265 if (src) {
266 vram += src->vram_usage;
267 gtt += src->gart_usage;
268 }
269
270 /* Flush the GFX IB if DMA depends on it. */
271 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
272 ((dst &&
273 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
274 RADEON_USAGE_READWRITE)) ||
275 (src &&
276 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
277 RADEON_USAGE_WRITE))))
278 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
279
280 /* Flush if there's not enough space, or if the memory usage per IB
281 * is too large.
282 *
283 * IBs using too little memory are limited by the IB submission overhead.
284 * IBs using too much memory are limited by the kernel/TTM overhead.
285 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
286 *
287 * This heuristic makes sure that DMA requests are executed
288 * very soon after the call is made and lowers memory usage.
289 * It improves texture upload performance by keeping the DMA
290 * engine busy while uploads are being submitted.
291 */
292 num_dw++; /* for emit_wait_idle below */
293 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
294 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
295 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
296 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
297 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
298 }
299
300 /* Wait for idle if either buffer has been used in the IB before to
301 * prevent read-after-write hazards.
302 */
303 if ((dst &&
304 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
305 RADEON_USAGE_READWRITE)) ||
306 (src &&
307 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
308 RADEON_USAGE_WRITE)))
309 r600_dma_emit_wait_idle(ctx);
310
311 /* If GPUVM is not supported, the CS checker needs 2 entries
312 * in the buffer list per packet, which has to be done manually.
313 */
314 if (ctx->screen->info.r600_has_virtual_memory) {
315 if (dst)
316 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
317 RADEON_USAGE_WRITE, 0);
318 if (src)
319 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
320 RADEON_USAGE_READ, 0);
321 }
322
323 /* this function is called before all DMA calls, so increment this. */
324 ctx->num_dma_calls++;
325 }
326
327 void r600_preflush_suspend_features(struct r600_common_context *ctx)
328 {
329 /* suspend queries */
330 if (!LIST_IS_EMPTY(&ctx->active_queries))
331 r600_suspend_queries(ctx);
332
333 ctx->streamout.suspended = false;
334 if (ctx->streamout.begin_emitted) {
335 r600_emit_streamout_end(ctx);
336 ctx->streamout.suspended = true;
337 }
338 }
339
340 void r600_postflush_resume_features(struct r600_common_context *ctx)
341 {
342 if (ctx->streamout.suspended) {
343 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
344 r600_streamout_buffers_dirty(ctx);
345 }
346
347 /* resume queries */
348 if (!LIST_IS_EMPTY(&ctx->active_queries))
349 r600_resume_queries(ctx);
350 }
351
352 static void r600_add_fence_dependency(struct r600_common_context *rctx,
353 struct pipe_fence_handle *fence)
354 {
355 struct radeon_winsys *ws = rctx->ws;
356
357 if (rctx->dma.cs)
358 ws->cs_add_fence_dependency(rctx->dma.cs, fence);
359 ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
360 }
361
362 static void r600_fence_server_sync(struct pipe_context *ctx,
363 struct pipe_fence_handle *fence)
364 {
365 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
366 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
367
368 /* Only amdgpu needs to handle fence dependencies (for fence imports).
369 * radeon synchronizes all rings by default and will not implement
370 * fence imports.
371 */
372 if (rctx->screen->info.drm_major == 2)
373 return;
374
375 /* Only imported fences need to be handled by fence_server_sync,
376 * because the winsys handles synchronizations automatically for BOs
377 * within the process.
378 *
379 * Simply skip unflushed fences here, and the winsys will drop no-op
380 * dependencies (i.e. dependencies within the same ring).
381 */
382 if (rfence->gfx_unflushed.ctx)
383 return;
384
385 /* All unflushed commands will not start execution before
386 * this fence dependency is signalled.
387 *
388 * Should we flush the context to allow more GPU parallelism?
389 */
390 if (rfence->sdma)
391 r600_add_fence_dependency(rctx, rfence->sdma);
392 if (rfence->gfx)
393 r600_add_fence_dependency(rctx, rfence->gfx);
394 }
395
396 static void r600_flush_from_st(struct pipe_context *ctx,
397 struct pipe_fence_handle **fence,
398 unsigned flags)
399 {
400 struct pipe_screen *screen = ctx->screen;
401 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
402 struct radeon_winsys *ws = rctx->ws;
403 struct pipe_fence_handle *gfx_fence = NULL;
404 struct pipe_fence_handle *sdma_fence = NULL;
405 bool deferred_fence = false;
406 unsigned rflags = PIPE_FLUSH_ASYNC;
407
408 if (flags & PIPE_FLUSH_END_OF_FRAME)
409 rflags |= PIPE_FLUSH_END_OF_FRAME;
410
411 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
412 if (rctx->dma.cs)
413 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
414
415 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
416 if (fence)
417 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
418 if (!(flags & PIPE_FLUSH_DEFERRED))
419 ws->cs_sync_flush(rctx->gfx.cs);
420 } else {
421 /* Instead of flushing, create a deferred fence. Constraints:
422 * - The state tracker must allow a deferred flush.
423 * - The state tracker must request a fence.
424 * Thread safety in fence_finish must be ensured by the state tracker.
425 */
426 if (flags & PIPE_FLUSH_DEFERRED && fence) {
427 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
428 deferred_fence = true;
429 } else {
430 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
431 }
432 }
433
434 /* Both engines can signal out of order, so we need to keep both fences. */
435 if (fence) {
436 struct r600_multi_fence *multi_fence =
437 CALLOC_STRUCT(r600_multi_fence);
438 if (!multi_fence) {
439 ws->fence_reference(&sdma_fence, NULL);
440 ws->fence_reference(&gfx_fence, NULL);
441 goto finish;
442 }
443
444 multi_fence->reference.count = 1;
445 /* If both fences are NULL, fence_finish will always return true. */
446 multi_fence->gfx = gfx_fence;
447 multi_fence->sdma = sdma_fence;
448
449 if (deferred_fence) {
450 multi_fence->gfx_unflushed.ctx = rctx;
451 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
452 }
453
454 screen->fence_reference(screen, fence, NULL);
455 *fence = (struct pipe_fence_handle*)multi_fence;
456 }
457 finish:
458 if (!(flags & PIPE_FLUSH_DEFERRED)) {
459 if (rctx->dma.cs)
460 ws->cs_sync_flush(rctx->dma.cs);
461 ws->cs_sync_flush(rctx->gfx.cs);
462 }
463 }
464
465 static void r600_flush_dma_ring(void *ctx, unsigned flags,
466 struct pipe_fence_handle **fence)
467 {
468 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
469 struct radeon_cmdbuf *cs = rctx->dma.cs;
470 struct radeon_saved_cs saved;
471 bool check_vm =
472 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
473 rctx->check_vm_faults;
474
475 if (!radeon_emitted(cs, 0)) {
476 if (fence)
477 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
478 return;
479 }
480
481 if (check_vm)
482 radeon_save_cs(rctx->ws, cs, &saved, true);
483
484 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
485 if (fence)
486 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
487
488 if (check_vm) {
489 /* Use conservative timeout 800ms, after which we won't wait any
490 * longer and assume the GPU is hung.
491 */
492 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
493
494 rctx->check_vm_faults(rctx, &saved, RING_DMA);
495 radeon_clear_saved_cs(&saved);
496 }
497 }
498
499 /**
500 * Store a linearized copy of all chunks of \p cs together with the buffer
501 * list in \p saved.
502 */
503 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
504 struct radeon_saved_cs *saved, bool get_buffer_list)
505 {
506 uint32_t *buf;
507 unsigned i;
508
509 /* Save the IB chunks. */
510 saved->num_dw = cs->prev_dw + cs->current.cdw;
511 saved->ib = MALLOC(4 * saved->num_dw);
512 if (!saved->ib)
513 goto oom;
514
515 buf = saved->ib;
516 for (i = 0; i < cs->num_prev; ++i) {
517 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
518 buf += cs->prev[i].cdw;
519 }
520 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
521
522 if (!get_buffer_list)
523 return;
524
525 /* Save the buffer list. */
526 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
527 saved->bo_list = CALLOC(saved->bo_count,
528 sizeof(saved->bo_list[0]));
529 if (!saved->bo_list) {
530 FREE(saved->ib);
531 goto oom;
532 }
533 ws->cs_get_buffer_list(cs, saved->bo_list);
534
535 return;
536
537 oom:
538 fprintf(stderr, "%s: out of memory\n", __func__);
539 memset(saved, 0, sizeof(*saved));
540 }
541
542 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
543 {
544 FREE(saved->ib);
545 FREE(saved->bo_list);
546
547 memset(saved, 0, sizeof(*saved));
548 }
549
550 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
551 {
552 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
553 unsigned latest = rctx->ws->query_value(rctx->ws,
554 RADEON_GPU_RESET_COUNTER);
555
556 if (rctx->gpu_reset_counter == latest)
557 return PIPE_NO_RESET;
558
559 rctx->gpu_reset_counter = latest;
560 return PIPE_UNKNOWN_CONTEXT_RESET;
561 }
562
563 static void r600_set_debug_callback(struct pipe_context *ctx,
564 const struct pipe_debug_callback *cb)
565 {
566 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
567
568 if (cb)
569 rctx->debug = *cb;
570 else
571 memset(&rctx->debug, 0, sizeof(rctx->debug));
572 }
573
574 static void r600_set_device_reset_callback(struct pipe_context *ctx,
575 const struct pipe_device_reset_callback *cb)
576 {
577 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
578
579 if (cb)
580 rctx->device_reset_callback = *cb;
581 else
582 memset(&rctx->device_reset_callback, 0,
583 sizeof(rctx->device_reset_callback));
584 }
585
586 bool r600_check_device_reset(struct r600_common_context *rctx)
587 {
588 enum pipe_reset_status status;
589
590 if (!rctx->device_reset_callback.reset)
591 return false;
592
593 if (!rctx->b.get_device_reset_status)
594 return false;
595
596 status = rctx->b.get_device_reset_status(&rctx->b);
597 if (status == PIPE_NO_RESET)
598 return false;
599
600 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
601 return true;
602 }
603
604 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
605 struct pipe_resource *dst,
606 uint64_t offset, uint64_t size,
607 unsigned value)
608 {
609 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
610
611 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
612 }
613
614 static bool r600_resource_commit(struct pipe_context *pctx,
615 struct pipe_resource *resource,
616 unsigned level, struct pipe_box *box,
617 bool commit)
618 {
619 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
620 struct r600_resource *res = r600_resource(resource);
621
622 /*
623 * Since buffer commitment changes cannot be pipelined, we need to
624 * (a) flush any pending commands that refer to the buffer we're about
625 * to change, and
626 * (b) wait for threaded submit to finish, including those that were
627 * triggered by some other, earlier operation.
628 */
629 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
630 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
631 res->buf, RADEON_USAGE_READWRITE)) {
632 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
633 }
634 if (radeon_emitted(ctx->dma.cs, 0) &&
635 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
636 res->buf, RADEON_USAGE_READWRITE)) {
637 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
638 }
639
640 ctx->ws->cs_sync_flush(ctx->dma.cs);
641 ctx->ws->cs_sync_flush(ctx->gfx.cs);
642
643 assert(resource->target == PIPE_BUFFER);
644
645 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
646 }
647
648 bool r600_common_context_init(struct r600_common_context *rctx,
649 struct r600_common_screen *rscreen,
650 unsigned context_flags)
651 {
652 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
653 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
654
655 rctx->screen = rscreen;
656 rctx->ws = rscreen->ws;
657 rctx->family = rscreen->family;
658 rctx->chip_class = rscreen->chip_class;
659
660 rctx->b.invalidate_resource = r600_invalidate_resource;
661 rctx->b.resource_commit = r600_resource_commit;
662 rctx->b.transfer_map = u_transfer_map_vtbl;
663 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
664 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
665 rctx->b.texture_subdata = u_default_texture_subdata;
666 rctx->b.flush = r600_flush_from_st;
667 rctx->b.set_debug_callback = r600_set_debug_callback;
668 rctx->b.fence_server_sync = r600_fence_server_sync;
669 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
670
671 /* evergreen_compute.c has a special codepath for global buffers.
672 * Everything else can use the direct path.
673 */
674 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
675 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
676 rctx->b.buffer_subdata = u_default_buffer_subdata;
677 else
678 rctx->b.buffer_subdata = r600_buffer_subdata;
679
680 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
681 rctx->b.get_device_reset_status = r600_get_reset_status;
682 rctx->gpu_reset_counter =
683 rctx->ws->query_value(rctx->ws,
684 RADEON_GPU_RESET_COUNTER);
685 }
686
687 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
688
689 r600_init_context_texture_functions(rctx);
690 r600_init_viewport_functions(rctx);
691 r600_streamout_init(rctx);
692 r600_query_init(rctx);
693 cayman_init_msaa(&rctx->b);
694
695 rctx->allocator_zeroed_memory =
696 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
697 0, PIPE_USAGE_DEFAULT, 0, true);
698 if (!rctx->allocator_zeroed_memory)
699 return false;
700
701 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
702 0, PIPE_USAGE_STREAM, 0);
703 if (!rctx->b.stream_uploader)
704 return false;
705
706 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
707 0, PIPE_USAGE_DEFAULT, 0);
708 if (!rctx->b.const_uploader)
709 return false;
710
711 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
712 if (!rctx->ctx)
713 return false;
714
715 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
716 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
717 r600_flush_dma_ring,
718 rctx);
719 rctx->dma.flush = r600_flush_dma_ring;
720 }
721
722 return true;
723 }
724
725 void r600_common_context_cleanup(struct r600_common_context *rctx)
726 {
727 if (rctx->query_result_shader)
728 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
729
730 if (rctx->gfx.cs)
731 rctx->ws->cs_destroy(rctx->gfx.cs);
732 if (rctx->dma.cs)
733 rctx->ws->cs_destroy(rctx->dma.cs);
734 if (rctx->ctx)
735 rctx->ws->ctx_destroy(rctx->ctx);
736
737 if (rctx->b.stream_uploader)
738 u_upload_destroy(rctx->b.stream_uploader);
739 if (rctx->b.const_uploader)
740 u_upload_destroy(rctx->b.const_uploader);
741
742 slab_destroy_child(&rctx->pool_transfers);
743 slab_destroy_child(&rctx->pool_transfers_unsync);
744
745 if (rctx->allocator_zeroed_memory) {
746 u_suballocator_destroy(rctx->allocator_zeroed_memory);
747 }
748 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
749 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
750 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
751 }
752
753 /*
754 * pipe_screen
755 */
756
757 static const struct debug_named_value common_debug_options[] = {
758 /* logging */
759 { "tex", DBG_TEX, "Print texture info" },
760 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
761 { "compute", DBG_COMPUTE, "Print compute info" },
762 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
763 { "info", DBG_INFO, "Print driver information" },
764
765 /* shaders */
766 { "fs", DBG_FS, "Print fetch shaders" },
767 { "vs", DBG_VS, "Print vertex shaders" },
768 { "gs", DBG_GS, "Print geometry shaders" },
769 { "ps", DBG_PS, "Print pixel shaders" },
770 { "cs", DBG_CS, "Print compute shaders" },
771 { "tcs", DBG_TCS, "Print tessellation control shaders" },
772 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
773 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
774 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
775 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
776 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
777 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
778 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
779
780 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
781 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
782 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
783 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
784
785 /* features */
786 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
787 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
788 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
789 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
790 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
791 { "notiling", DBG_NO_TILING, "Disable tiling" },
792 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
793 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
794 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
795 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
796 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
797 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
798
799 DEBUG_NAMED_VALUE_END /* must be last */
800 };
801
802 static const char* r600_get_vendor(struct pipe_screen* pscreen)
803 {
804 return "X.Org";
805 }
806
807 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
808 {
809 return "AMD";
810 }
811
812 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
813 {
814 if (!ws->get_chip_name)
815 return NULL;
816 return ws->get_chip_name(ws);
817 }
818
819 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
820 {
821 switch (rscreen->info.family) {
822 case CHIP_R600: return "AMD R600";
823 case CHIP_RV610: return "AMD RV610";
824 case CHIP_RV630: return "AMD RV630";
825 case CHIP_RV670: return "AMD RV670";
826 case CHIP_RV620: return "AMD RV620";
827 case CHIP_RV635: return "AMD RV635";
828 case CHIP_RS780: return "AMD RS780";
829 case CHIP_RS880: return "AMD RS880";
830 case CHIP_RV770: return "AMD RV770";
831 case CHIP_RV730: return "AMD RV730";
832 case CHIP_RV710: return "AMD RV710";
833 case CHIP_RV740: return "AMD RV740";
834 case CHIP_CEDAR: return "AMD CEDAR";
835 case CHIP_REDWOOD: return "AMD REDWOOD";
836 case CHIP_JUNIPER: return "AMD JUNIPER";
837 case CHIP_CYPRESS: return "AMD CYPRESS";
838 case CHIP_HEMLOCK: return "AMD HEMLOCK";
839 case CHIP_PALM: return "AMD PALM";
840 case CHIP_SUMO: return "AMD SUMO";
841 case CHIP_SUMO2: return "AMD SUMO2";
842 case CHIP_BARTS: return "AMD BARTS";
843 case CHIP_TURKS: return "AMD TURKS";
844 case CHIP_CAICOS: return "AMD CAICOS";
845 case CHIP_CAYMAN: return "AMD CAYMAN";
846 case CHIP_ARUBA: return "AMD ARUBA";
847 default: return "AMD unknown";
848 }
849 }
850
851 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
852 {
853 /* Don't use the cache if shader dumping is enabled. */
854 if (rscreen->debug_flags & DBG_ALL_SHADERS)
855 return;
856
857 struct mesa_sha1 ctx;
858 unsigned char sha1[20];
859 char cache_id[20 * 2 + 1];
860
861 _mesa_sha1_init(&ctx);
862 if (!disk_cache_get_function_identifier(r600_disk_cache_create,
863 &ctx))
864 return;
865
866 _mesa_sha1_final(&ctx, sha1);
867 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
868
869 /* These flags affect shader compilation. */
870 uint64_t shader_debug_flags =
871 rscreen->debug_flags &
872 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
873 DBG_UNSAFE_MATH);
874
875 rscreen->disk_shader_cache =
876 disk_cache_create(r600_get_family_name(rscreen),
877 cache_id,
878 shader_debug_flags);
879 }
880
881 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
882 {
883 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
884 return rscreen->disk_shader_cache;
885 }
886
887 static const char* r600_get_name(struct pipe_screen* pscreen)
888 {
889 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
890
891 return rscreen->renderer_string;
892 }
893
894 static float r600_get_paramf(struct pipe_screen* pscreen,
895 enum pipe_capf param)
896 {
897 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
898
899 switch (param) {
900 case PIPE_CAPF_MAX_LINE_WIDTH:
901 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
902 case PIPE_CAPF_MAX_POINT_WIDTH:
903 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
904 if (rscreen->family >= CHIP_CEDAR)
905 return 16384.0f;
906 else
907 return 8192.0f;
908 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
909 return 16.0f;
910 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
911 return 16.0f;
912 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
913 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
914 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
915 return 0.0f;
916 }
917 return 0.0f;
918 }
919
920 static int r600_get_video_param(struct pipe_screen *screen,
921 enum pipe_video_profile profile,
922 enum pipe_video_entrypoint entrypoint,
923 enum pipe_video_cap param)
924 {
925 switch (param) {
926 case PIPE_VIDEO_CAP_SUPPORTED:
927 return vl_profile_supported(screen, profile, entrypoint);
928 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
929 return 1;
930 case PIPE_VIDEO_CAP_MAX_WIDTH:
931 case PIPE_VIDEO_CAP_MAX_HEIGHT:
932 return vl_video_buffer_max_size(screen);
933 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
934 return PIPE_FORMAT_NV12;
935 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
936 return false;
937 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
938 return false;
939 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
940 return true;
941 case PIPE_VIDEO_CAP_MAX_LEVEL:
942 return vl_level_supported(screen, profile);
943 default:
944 return 0;
945 }
946 }
947
948 const char *r600_get_llvm_processor_name(enum radeon_family family)
949 {
950 switch (family) {
951 case CHIP_R600:
952 case CHIP_RV630:
953 case CHIP_RV635:
954 case CHIP_RV670:
955 return "r600";
956 case CHIP_RV610:
957 case CHIP_RV620:
958 case CHIP_RS780:
959 case CHIP_RS880:
960 return "rs880";
961 case CHIP_RV710:
962 return "rv710";
963 case CHIP_RV730:
964 return "rv730";
965 case CHIP_RV740:
966 case CHIP_RV770:
967 return "rv770";
968 case CHIP_PALM:
969 case CHIP_CEDAR:
970 return "cedar";
971 case CHIP_SUMO:
972 case CHIP_SUMO2:
973 return "sumo";
974 case CHIP_REDWOOD:
975 return "redwood";
976 case CHIP_JUNIPER:
977 return "juniper";
978 case CHIP_HEMLOCK:
979 case CHIP_CYPRESS:
980 return "cypress";
981 case CHIP_BARTS:
982 return "barts";
983 case CHIP_TURKS:
984 return "turks";
985 case CHIP_CAICOS:
986 return "caicos";
987 case CHIP_CAYMAN:
988 case CHIP_ARUBA:
989 return "cayman";
990
991 default:
992 return "";
993 }
994 }
995
996 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
997 enum pipe_shader_ir ir_type)
998 {
999 if (ir_type != PIPE_SHADER_IR_TGSI)
1000 return 256;
1001 if (screen->chip_class >= EVERGREEN)
1002 return 1024;
1003 return 256;
1004 }
1005
1006 static int r600_get_compute_param(struct pipe_screen *screen,
1007 enum pipe_shader_ir ir_type,
1008 enum pipe_compute_cap param,
1009 void *ret)
1010 {
1011 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1012
1013 //TODO: select these params by asic
1014 switch (param) {
1015 case PIPE_COMPUTE_CAP_IR_TARGET: {
1016 const char *gpu;
1017 const char *triple = "r600--";
1018 gpu = r600_get_llvm_processor_name(rscreen->family);
1019 if (ret) {
1020 sprintf(ret, "%s-%s", gpu, triple);
1021 }
1022 /* +2 for dash and terminating NIL byte */
1023 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1024 }
1025 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1026 if (ret) {
1027 uint64_t *grid_dimension = ret;
1028 grid_dimension[0] = 3;
1029 }
1030 return 1 * sizeof(uint64_t);
1031
1032 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1033 if (ret) {
1034 uint64_t *grid_size = ret;
1035 grid_size[0] = 65535;
1036 grid_size[1] = 65535;
1037 grid_size[2] = 65535;
1038 }
1039 return 3 * sizeof(uint64_t) ;
1040
1041 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1042 if (ret) {
1043 uint64_t *block_size = ret;
1044 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1045 block_size[0] = threads_per_block;
1046 block_size[1] = threads_per_block;
1047 block_size[2] = threads_per_block;
1048 }
1049 return 3 * sizeof(uint64_t);
1050
1051 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1052 if (ret) {
1053 uint64_t *max_threads_per_block = ret;
1054 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1055 }
1056 return sizeof(uint64_t);
1057 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1058 if (ret) {
1059 uint32_t *address_bits = ret;
1060 address_bits[0] = 32;
1061 }
1062 return 1 * sizeof(uint32_t);
1063
1064 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1065 if (ret) {
1066 uint64_t *max_global_size = ret;
1067 uint64_t max_mem_alloc_size;
1068
1069 r600_get_compute_param(screen, ir_type,
1070 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1071 &max_mem_alloc_size);
1072
1073 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1074 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1075 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1076 * make sure we never report more than
1077 * 4 * MAX_MEM_ALLOC_SIZE.
1078 */
1079 *max_global_size = MIN2(4 * max_mem_alloc_size,
1080 MAX2(rscreen->info.gart_size,
1081 rscreen->info.vram_size));
1082 }
1083 return sizeof(uint64_t);
1084
1085 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1086 if (ret) {
1087 uint64_t *max_local_size = ret;
1088 /* Value reported by the closed source driver. */
1089 *max_local_size = 32768;
1090 }
1091 return sizeof(uint64_t);
1092
1093 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1094 if (ret) {
1095 uint64_t *max_input_size = ret;
1096 /* Value reported by the closed source driver. */
1097 *max_input_size = 1024;
1098 }
1099 return sizeof(uint64_t);
1100
1101 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1102 if (ret) {
1103 uint64_t *max_mem_alloc_size = ret;
1104
1105 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1106 }
1107 return sizeof(uint64_t);
1108
1109 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1110 if (ret) {
1111 uint32_t *max_clock_frequency = ret;
1112 *max_clock_frequency = rscreen->info.max_shader_clock;
1113 }
1114 return sizeof(uint32_t);
1115
1116 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1117 if (ret) {
1118 uint32_t *max_compute_units = ret;
1119 *max_compute_units = rscreen->info.num_good_compute_units;
1120 }
1121 return sizeof(uint32_t);
1122
1123 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1124 if (ret) {
1125 uint32_t *images_supported = ret;
1126 *images_supported = 0;
1127 }
1128 return sizeof(uint32_t);
1129 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1130 break; /* unused */
1131 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1132 if (ret) {
1133 uint32_t *subgroup_size = ret;
1134 *subgroup_size = r600_wavefront_size(rscreen->family);
1135 }
1136 return sizeof(uint32_t);
1137 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1138 if (ret) {
1139 uint64_t *max_variable_threads_per_block = ret;
1140 *max_variable_threads_per_block = 0;
1141 }
1142 return sizeof(uint64_t);
1143 }
1144
1145 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1146 return 0;
1147 }
1148
1149 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1150 {
1151 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1152
1153 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1154 rscreen->info.clock_crystal_freq;
1155 }
1156
1157 static void r600_fence_reference(struct pipe_screen *screen,
1158 struct pipe_fence_handle **dst,
1159 struct pipe_fence_handle *src)
1160 {
1161 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1162 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1163 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1164
1165 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1166 ws->fence_reference(&(*rdst)->gfx, NULL);
1167 ws->fence_reference(&(*rdst)->sdma, NULL);
1168 FREE(*rdst);
1169 }
1170 *rdst = rsrc;
1171 }
1172
1173 static boolean r600_fence_finish(struct pipe_screen *screen,
1174 struct pipe_context *ctx,
1175 struct pipe_fence_handle *fence,
1176 uint64_t timeout)
1177 {
1178 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1179 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1180 struct r600_common_context *rctx;
1181 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1182
1183 ctx = threaded_context_unwrap_sync(ctx);
1184 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1185
1186 if (rfence->sdma) {
1187 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1188 return false;
1189
1190 /* Recompute the timeout after waiting. */
1191 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1192 int64_t time = os_time_get_nano();
1193 timeout = abs_timeout > time ? abs_timeout - time : 0;
1194 }
1195 }
1196
1197 if (!rfence->gfx)
1198 return true;
1199
1200 /* Flush the gfx IB if it hasn't been flushed yet. */
1201 if (rctx &&
1202 rfence->gfx_unflushed.ctx == rctx &&
1203 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1204 rctx->gfx.flush(rctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
1205 rfence->gfx_unflushed.ctx = NULL;
1206
1207 if (!timeout)
1208 return false;
1209
1210 /* Recompute the timeout after all that. */
1211 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1212 int64_t time = os_time_get_nano();
1213 timeout = abs_timeout > time ? abs_timeout - time : 0;
1214 }
1215 }
1216
1217 return rws->fence_wait(rws, rfence->gfx, timeout);
1218 }
1219
1220 static void r600_query_memory_info(struct pipe_screen *screen,
1221 struct pipe_memory_info *info)
1222 {
1223 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1224 struct radeon_winsys *ws = rscreen->ws;
1225 unsigned vram_usage, gtt_usage;
1226
1227 info->total_device_memory = rscreen->info.vram_size / 1024;
1228 info->total_staging_memory = rscreen->info.gart_size / 1024;
1229
1230 /* The real TTM memory usage is somewhat random, because:
1231 *
1232 * 1) TTM delays freeing memory, because it can only free it after
1233 * fences expire.
1234 *
1235 * 2) The memory usage can be really low if big VRAM evictions are
1236 * taking place, but the real usage is well above the size of VRAM.
1237 *
1238 * Instead, return statistics of this process.
1239 */
1240 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1241 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1242
1243 info->avail_device_memory =
1244 vram_usage <= info->total_device_memory ?
1245 info->total_device_memory - vram_usage : 0;
1246 info->avail_staging_memory =
1247 gtt_usage <= info->total_staging_memory ?
1248 info->total_staging_memory - gtt_usage : 0;
1249
1250 info->device_memory_evicted =
1251 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1252
1253 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1254 info->nr_device_memory_evictions =
1255 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1256 else
1257 /* Just return the number of evicted 64KB pages. */
1258 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1259 }
1260
1261 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1262 const struct pipe_resource *templ)
1263 {
1264 if (templ->target == PIPE_BUFFER) {
1265 return r600_buffer_create(screen, templ, 256);
1266 } else {
1267 return r600_texture_create(screen, templ);
1268 }
1269 }
1270
1271 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1272 struct radeon_winsys *ws)
1273 {
1274 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1275 struct utsname uname_data;
1276 const char *chip_name;
1277
1278 ws->query_info(ws, &rscreen->info);
1279 rscreen->ws = ws;
1280
1281 if ((chip_name = r600_get_marketing_name(ws)))
1282 snprintf(family_name, sizeof(family_name), "%s / ",
1283 r600_get_family_name(rscreen) + 4);
1284 else
1285 chip_name = r600_get_family_name(rscreen);
1286
1287 if (uname(&uname_data) == 0)
1288 snprintf(kernel_version, sizeof(kernel_version),
1289 " / %s", uname_data.release);
1290
1291 if (HAVE_LLVM > 0) {
1292 snprintf(llvm_string, sizeof(llvm_string),
1293 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1294 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1295 }
1296
1297 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1298 "%s (%sDRM %i.%i.%i%s%s)",
1299 chip_name, family_name, rscreen->info.drm_major,
1300 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1301 kernel_version, llvm_string);
1302
1303 rscreen->b.get_name = r600_get_name;
1304 rscreen->b.get_vendor = r600_get_vendor;
1305 rscreen->b.get_device_vendor = r600_get_device_vendor;
1306 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1307 rscreen->b.get_compute_param = r600_get_compute_param;
1308 rscreen->b.get_paramf = r600_get_paramf;
1309 rscreen->b.get_timestamp = r600_get_timestamp;
1310 rscreen->b.fence_finish = r600_fence_finish;
1311 rscreen->b.fence_reference = r600_fence_reference;
1312 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1313 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1314 rscreen->b.query_memory_info = r600_query_memory_info;
1315
1316 if (rscreen->info.has_hw_decode) {
1317 rscreen->b.get_video_param = rvid_get_video_param;
1318 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1319 } else {
1320 rscreen->b.get_video_param = r600_get_video_param;
1321 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1322 }
1323
1324 r600_init_screen_texture_functions(rscreen);
1325 r600_init_screen_query_functions(rscreen);
1326
1327 rscreen->family = rscreen->info.family;
1328 rscreen->chip_class = rscreen->info.chip_class;
1329 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1330
1331 r600_disk_cache_create(rscreen);
1332
1333 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1334
1335 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1336 if (rscreen->force_aniso >= 0) {
1337 printf("radeon: Forcing anisotropy filter to %ix\n",
1338 /* round down to a power of two */
1339 1 << util_logbase2(rscreen->force_aniso));
1340 }
1341
1342 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1343 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1344
1345 if (rscreen->debug_flags & DBG_INFO) {
1346 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1347 rscreen->info.pci_domain, rscreen->info.pci_bus,
1348 rscreen->info.pci_dev, rscreen->info.pci_func);
1349 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1350 printf("family = %i (%s)\n", rscreen->info.family,
1351 r600_get_family_name(rscreen));
1352 printf("chip_class = %i\n", rscreen->info.chip_class);
1353 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1354 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1355 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1356 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1357 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1358 printf("max_alloc_size = %i MB\n",
1359 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1360 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1361 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1362 printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory);
1363 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1364 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1365 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1366 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1367 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1368 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1369 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1370 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1371 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1372 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1373 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1374 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1375 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1376 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1377 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1378 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1379
1380 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1381 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1382 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1383 printf("max_se = %i\n", rscreen->info.max_se);
1384 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1385
1386 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1387 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1388 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1389 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1390 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1391 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1392 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1393 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1394 }
1395 return true;
1396 }
1397
1398 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1399 {
1400 r600_perfcounters_destroy(rscreen);
1401 r600_gpu_load_kill_thread(rscreen);
1402
1403 mtx_destroy(&rscreen->gpu_load_mutex);
1404 mtx_destroy(&rscreen->aux_context_lock);
1405 rscreen->aux_context->destroy(rscreen->aux_context);
1406
1407 slab_destroy_parent(&rscreen->pool_transfers);
1408
1409 disk_cache_destroy(rscreen->disk_shader_cache);
1410 rscreen->ws->destroy(rscreen->ws);
1411 FREE(rscreen);
1412 }
1413
1414 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1415 unsigned processor)
1416 {
1417 return rscreen->debug_flags & (1 << processor);
1418 }
1419
1420 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1421 {
1422 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1423 r600_can_dump_shader(rscreen, processor);
1424 }
1425
1426 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1427 uint64_t offset, uint64_t size, unsigned value)
1428 {
1429 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1430
1431 mtx_lock(&rscreen->aux_context_lock);
1432 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1433 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1434 mtx_unlock(&rscreen->aux_context_lock);
1435 }