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ac: add radeon_info::is_amdgpu instead of checking drm_major == 3
[mesa.git] / src / gallium / drivers / r600 / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 struct r600_multi_fence {
51 struct pipe_reference reference;
52 struct pipe_fence_handle *gfx;
53 struct pipe_fence_handle *sdma;
54
55 /* If the context wasn't flushed at fence creation, this is non-NULL. */
56 struct {
57 struct r600_common_context *ctx;
58 unsigned ib_index;
59 } gfx_unflushed;
60 };
61
62 /*
63 * shader binary helpers.
64 */
65 void radeon_shader_binary_init(struct ac_shader_binary *b)
66 {
67 memset(b, 0, sizeof(*b));
68 }
69
70 void radeon_shader_binary_clean(struct ac_shader_binary *b)
71 {
72 if (!b)
73 return;
74 FREE(b->code);
75 FREE(b->config);
76 FREE(b->rodata);
77 FREE(b->global_symbol_offsets);
78 FREE(b->relocs);
79 FREE(b->disasm_string);
80 FREE(b->llvm_ir_string);
81 }
82
83 /*
84 * pipe_context
85 */
86
87 /**
88 * Write an EOP event.
89 *
90 * \param event EVENT_TYPE_*
91 * \param event_flags Optional cache flush flags (TC)
92 * \param data_sel 1 = fence, 3 = timestamp
93 * \param buf Buffer
94 * \param va GPU address
95 * \param old_value Previous fence value (for a bug workaround)
96 * \param new_value Fence value to write for this event.
97 */
98 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
99 unsigned event, unsigned event_flags,
100 unsigned data_sel,
101 struct r600_resource *buf, uint64_t va,
102 uint32_t new_fence, unsigned query_type)
103 {
104 struct radeon_cmdbuf *cs = ctx->gfx.cs;
105 unsigned op = EVENT_TYPE(event) |
106 EVENT_INDEX(5) |
107 event_flags;
108 unsigned sel = EOP_DATA_SEL(data_sel);
109
110 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
111 radeon_emit(cs, op);
112 radeon_emit(cs, va);
113 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
114 radeon_emit(cs, new_fence); /* immediate data */
115 radeon_emit(cs, 0); /* unused */
116
117 if (buf)
118 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
119 RADEON_PRIO_QUERY);
120 }
121
122 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
123 {
124 unsigned dwords = 6;
125
126 if (!screen->info.r600_has_virtual_memory)
127 dwords += 2;
128
129 return dwords;
130 }
131
132 void r600_gfx_wait_fence(struct r600_common_context *ctx,
133 struct r600_resource *buf,
134 uint64_t va, uint32_t ref, uint32_t mask)
135 {
136 struct radeon_cmdbuf *cs = ctx->gfx.cs;
137
138 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
139 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
140 radeon_emit(cs, va);
141 radeon_emit(cs, va >> 32);
142 radeon_emit(cs, ref); /* reference value */
143 radeon_emit(cs, mask); /* mask */
144 radeon_emit(cs, 4); /* poll interval */
145
146 if (buf)
147 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
148 RADEON_PRIO_QUERY);
149 }
150
151 void r600_draw_rectangle(struct blitter_context *blitter,
152 void *vertex_elements_cso,
153 blitter_get_vs_func get_vs,
154 int x1, int y1, int x2, int y2,
155 float depth, unsigned num_instances,
156 enum blitter_attrib_type type,
157 const union blitter_attrib *attrib)
158 {
159 struct r600_common_context *rctx =
160 (struct r600_common_context*)util_blitter_get_pipe(blitter);
161 struct pipe_viewport_state viewport;
162 struct pipe_resource *buf = NULL;
163 unsigned offset = 0;
164 float *vb;
165
166 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
167 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
168
169 /* Some operations (like color resolve on r6xx) don't work
170 * with the conventional primitive types.
171 * One that works is PT_RECTLIST, which we use here. */
172
173 /* setup viewport */
174 viewport.scale[0] = 1.0f;
175 viewport.scale[1] = 1.0f;
176 viewport.scale[2] = 1.0f;
177 viewport.translate[0] = 0.0f;
178 viewport.translate[1] = 0.0f;
179 viewport.translate[2] = 0.0f;
180 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
181
182 /* Upload vertices. The hw rectangle has only 3 vertices,
183 * The 4th one is derived from the first 3.
184 * The vertex specification should match u_blitter's vertex element state. */
185 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
186 rctx->screen->info.tcc_cache_line_size,
187 &offset, &buf, (void**)&vb);
188 if (!buf)
189 return;
190
191 vb[0] = x1;
192 vb[1] = y1;
193 vb[2] = depth;
194 vb[3] = 1;
195
196 vb[8] = x1;
197 vb[9] = y2;
198 vb[10] = depth;
199 vb[11] = 1;
200
201 vb[16] = x2;
202 vb[17] = y1;
203 vb[18] = depth;
204 vb[19] = 1;
205
206 switch (type) {
207 case UTIL_BLITTER_ATTRIB_COLOR:
208 memcpy(vb+4, attrib->color, sizeof(float)*4);
209 memcpy(vb+12, attrib->color, sizeof(float)*4);
210 memcpy(vb+20, attrib->color, sizeof(float)*4);
211 break;
212 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
213 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
214 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
215 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
216 /* fall through */
217 vb[4] = attrib->texcoord.x1;
218 vb[5] = attrib->texcoord.y1;
219 vb[12] = attrib->texcoord.x1;
220 vb[13] = attrib->texcoord.y2;
221 vb[20] = attrib->texcoord.x2;
222 vb[21] = attrib->texcoord.y1;
223 break;
224 default:; /* Nothing to do. */
225 }
226
227 /* draw */
228 struct pipe_vertex_buffer vbuffer = {};
229 vbuffer.buffer.resource = buf;
230 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
231 vbuffer.buffer_offset = offset;
232
233 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
234 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
235 0, num_instances);
236 pipe_resource_reference(&buf, NULL);
237 }
238
239 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
240 {
241 struct radeon_cmdbuf *cs = rctx->dma.cs;
242
243 if (rctx->chip_class >= EVERGREEN)
244 radeon_emit(cs, 0xf0000000); /* NOP */
245 else {
246 /* TODO: R600-R700 should use the FENCE packet.
247 * CS checker support is required. */
248 }
249 }
250
251 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
252 struct r600_resource *dst, struct r600_resource *src)
253 {
254 uint64_t vram = ctx->dma.cs->used_vram;
255 uint64_t gtt = ctx->dma.cs->used_gart;
256
257 if (dst) {
258 vram += dst->vram_usage;
259 gtt += dst->gart_usage;
260 }
261 if (src) {
262 vram += src->vram_usage;
263 gtt += src->gart_usage;
264 }
265
266 /* Flush the GFX IB if DMA depends on it. */
267 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
268 ((dst &&
269 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
270 RADEON_USAGE_READWRITE)) ||
271 (src &&
272 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
273 RADEON_USAGE_WRITE))))
274 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
275
276 /* Flush if there's not enough space, or if the memory usage per IB
277 * is too large.
278 *
279 * IBs using too little memory are limited by the IB submission overhead.
280 * IBs using too much memory are limited by the kernel/TTM overhead.
281 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
282 *
283 * This heuristic makes sure that DMA requests are executed
284 * very soon after the call is made and lowers memory usage.
285 * It improves texture upload performance by keeping the DMA
286 * engine busy while uploads are being submitted.
287 */
288 num_dw++; /* for emit_wait_idle below */
289 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw, false) ||
290 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
291 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
292 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
293 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
294 }
295
296 /* Wait for idle if either buffer has been used in the IB before to
297 * prevent read-after-write hazards.
298 */
299 if ((dst &&
300 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
301 RADEON_USAGE_READWRITE)) ||
302 (src &&
303 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
304 RADEON_USAGE_WRITE)))
305 r600_dma_emit_wait_idle(ctx);
306
307 /* If GPUVM is not supported, the CS checker needs 2 entries
308 * in the buffer list per packet, which has to be done manually.
309 */
310 if (ctx->screen->info.r600_has_virtual_memory) {
311 if (dst)
312 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
313 RADEON_USAGE_WRITE, 0);
314 if (src)
315 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
316 RADEON_USAGE_READ, 0);
317 }
318
319 /* this function is called before all DMA calls, so increment this. */
320 ctx->num_dma_calls++;
321 }
322
323 void r600_preflush_suspend_features(struct r600_common_context *ctx)
324 {
325 /* suspend queries */
326 if (!LIST_IS_EMPTY(&ctx->active_queries))
327 r600_suspend_queries(ctx);
328
329 ctx->streamout.suspended = false;
330 if (ctx->streamout.begin_emitted) {
331 r600_emit_streamout_end(ctx);
332 ctx->streamout.suspended = true;
333 }
334 }
335
336 void r600_postflush_resume_features(struct r600_common_context *ctx)
337 {
338 if (ctx->streamout.suspended) {
339 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
340 r600_streamout_buffers_dirty(ctx);
341 }
342
343 /* resume queries */
344 if (!LIST_IS_EMPTY(&ctx->active_queries))
345 r600_resume_queries(ctx);
346 }
347
348 static void r600_fence_server_sync(struct pipe_context *ctx,
349 struct pipe_fence_handle *fence)
350 {
351 /* radeon synchronizes all rings by default and will not implement
352 * fence imports.
353 */
354 }
355
356 static void r600_flush_from_st(struct pipe_context *ctx,
357 struct pipe_fence_handle **fence,
358 unsigned flags)
359 {
360 struct pipe_screen *screen = ctx->screen;
361 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
362 struct radeon_winsys *ws = rctx->ws;
363 struct pipe_fence_handle *gfx_fence = NULL;
364 struct pipe_fence_handle *sdma_fence = NULL;
365 bool deferred_fence = false;
366 unsigned rflags = PIPE_FLUSH_ASYNC;
367
368 if (flags & PIPE_FLUSH_END_OF_FRAME)
369 rflags |= PIPE_FLUSH_END_OF_FRAME;
370
371 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
372 if (rctx->dma.cs)
373 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
374
375 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
376 if (fence)
377 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
378 if (!(flags & PIPE_FLUSH_DEFERRED))
379 ws->cs_sync_flush(rctx->gfx.cs);
380 } else {
381 /* Instead of flushing, create a deferred fence. Constraints:
382 * - The state tracker must allow a deferred flush.
383 * - The state tracker must request a fence.
384 * Thread safety in fence_finish must be ensured by the state tracker.
385 */
386 if (flags & PIPE_FLUSH_DEFERRED && fence) {
387 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
388 deferred_fence = true;
389 } else {
390 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
391 }
392 }
393
394 /* Both engines can signal out of order, so we need to keep both fences. */
395 if (fence) {
396 struct r600_multi_fence *multi_fence =
397 CALLOC_STRUCT(r600_multi_fence);
398 if (!multi_fence) {
399 ws->fence_reference(&sdma_fence, NULL);
400 ws->fence_reference(&gfx_fence, NULL);
401 goto finish;
402 }
403
404 multi_fence->reference.count = 1;
405 /* If both fences are NULL, fence_finish will always return true. */
406 multi_fence->gfx = gfx_fence;
407 multi_fence->sdma = sdma_fence;
408
409 if (deferred_fence) {
410 multi_fence->gfx_unflushed.ctx = rctx;
411 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
412 }
413
414 screen->fence_reference(screen, fence, NULL);
415 *fence = (struct pipe_fence_handle*)multi_fence;
416 }
417 finish:
418 if (!(flags & PIPE_FLUSH_DEFERRED)) {
419 if (rctx->dma.cs)
420 ws->cs_sync_flush(rctx->dma.cs);
421 ws->cs_sync_flush(rctx->gfx.cs);
422 }
423 }
424
425 static void r600_flush_dma_ring(void *ctx, unsigned flags,
426 struct pipe_fence_handle **fence)
427 {
428 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
429 struct radeon_cmdbuf *cs = rctx->dma.cs;
430 struct radeon_saved_cs saved;
431 bool check_vm =
432 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
433 rctx->check_vm_faults;
434
435 if (!radeon_emitted(cs, 0)) {
436 if (fence)
437 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
438 return;
439 }
440
441 if (check_vm)
442 radeon_save_cs(rctx->ws, cs, &saved, true);
443
444 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
445 if (fence)
446 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
447
448 if (check_vm) {
449 /* Use conservative timeout 800ms, after which we won't wait any
450 * longer and assume the GPU is hung.
451 */
452 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
453
454 rctx->check_vm_faults(rctx, &saved, RING_DMA);
455 radeon_clear_saved_cs(&saved);
456 }
457 }
458
459 /**
460 * Store a linearized copy of all chunks of \p cs together with the buffer
461 * list in \p saved.
462 */
463 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
464 struct radeon_saved_cs *saved, bool get_buffer_list)
465 {
466 uint32_t *buf;
467 unsigned i;
468
469 /* Save the IB chunks. */
470 saved->num_dw = cs->prev_dw + cs->current.cdw;
471 saved->ib = MALLOC(4 * saved->num_dw);
472 if (!saved->ib)
473 goto oom;
474
475 buf = saved->ib;
476 for (i = 0; i < cs->num_prev; ++i) {
477 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
478 buf += cs->prev[i].cdw;
479 }
480 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
481
482 if (!get_buffer_list)
483 return;
484
485 /* Save the buffer list. */
486 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
487 saved->bo_list = CALLOC(saved->bo_count,
488 sizeof(saved->bo_list[0]));
489 if (!saved->bo_list) {
490 FREE(saved->ib);
491 goto oom;
492 }
493 ws->cs_get_buffer_list(cs, saved->bo_list);
494
495 return;
496
497 oom:
498 fprintf(stderr, "%s: out of memory\n", __func__);
499 memset(saved, 0, sizeof(*saved));
500 }
501
502 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
503 {
504 FREE(saved->ib);
505 FREE(saved->bo_list);
506
507 memset(saved, 0, sizeof(*saved));
508 }
509
510 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
511 {
512 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
513
514 return rctx->ws->ctx_query_reset_status(rctx->ctx);
515 }
516
517 static void r600_set_debug_callback(struct pipe_context *ctx,
518 const struct pipe_debug_callback *cb)
519 {
520 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
521
522 if (cb)
523 rctx->debug = *cb;
524 else
525 memset(&rctx->debug, 0, sizeof(rctx->debug));
526 }
527
528 static void r600_set_device_reset_callback(struct pipe_context *ctx,
529 const struct pipe_device_reset_callback *cb)
530 {
531 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
532
533 if (cb)
534 rctx->device_reset_callback = *cb;
535 else
536 memset(&rctx->device_reset_callback, 0,
537 sizeof(rctx->device_reset_callback));
538 }
539
540 bool r600_check_device_reset(struct r600_common_context *rctx)
541 {
542 enum pipe_reset_status status;
543
544 if (!rctx->device_reset_callback.reset)
545 return false;
546
547 if (!rctx->b.get_device_reset_status)
548 return false;
549
550 status = rctx->b.get_device_reset_status(&rctx->b);
551 if (status == PIPE_NO_RESET)
552 return false;
553
554 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
555 return true;
556 }
557
558 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
559 struct pipe_resource *dst,
560 uint64_t offset, uint64_t size,
561 unsigned value)
562 {
563 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
564
565 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
566 }
567
568 static bool r600_resource_commit(struct pipe_context *pctx,
569 struct pipe_resource *resource,
570 unsigned level, struct pipe_box *box,
571 bool commit)
572 {
573 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
574 struct r600_resource *res = r600_resource(resource);
575
576 /*
577 * Since buffer commitment changes cannot be pipelined, we need to
578 * (a) flush any pending commands that refer to the buffer we're about
579 * to change, and
580 * (b) wait for threaded submit to finish, including those that were
581 * triggered by some other, earlier operation.
582 */
583 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
584 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
585 res->buf, RADEON_USAGE_READWRITE)) {
586 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
587 }
588 if (radeon_emitted(ctx->dma.cs, 0) &&
589 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
590 res->buf, RADEON_USAGE_READWRITE)) {
591 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
592 }
593
594 ctx->ws->cs_sync_flush(ctx->dma.cs);
595 ctx->ws->cs_sync_flush(ctx->gfx.cs);
596
597 assert(resource->target == PIPE_BUFFER);
598
599 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
600 }
601
602 bool r600_common_context_init(struct r600_common_context *rctx,
603 struct r600_common_screen *rscreen,
604 unsigned context_flags)
605 {
606 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
607 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
608
609 rctx->screen = rscreen;
610 rctx->ws = rscreen->ws;
611 rctx->family = rscreen->family;
612 rctx->chip_class = rscreen->chip_class;
613
614 rctx->b.invalidate_resource = r600_invalidate_resource;
615 rctx->b.resource_commit = r600_resource_commit;
616 rctx->b.transfer_map = u_transfer_map_vtbl;
617 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
618 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
619 rctx->b.texture_subdata = u_default_texture_subdata;
620 rctx->b.flush = r600_flush_from_st;
621 rctx->b.set_debug_callback = r600_set_debug_callback;
622 rctx->b.fence_server_sync = r600_fence_server_sync;
623 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
624
625 /* evergreen_compute.c has a special codepath for global buffers.
626 * Everything else can use the direct path.
627 */
628 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
629 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
630 rctx->b.buffer_subdata = u_default_buffer_subdata;
631 else
632 rctx->b.buffer_subdata = r600_buffer_subdata;
633
634 rctx->b.get_device_reset_status = r600_get_reset_status;
635 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
636
637 r600_init_context_texture_functions(rctx);
638 r600_init_viewport_functions(rctx);
639 r600_streamout_init(rctx);
640 r600_query_init(rctx);
641 cayman_init_msaa(&rctx->b);
642
643 rctx->allocator_zeroed_memory =
644 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
645 0, PIPE_USAGE_DEFAULT, 0, true);
646 if (!rctx->allocator_zeroed_memory)
647 return false;
648
649 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
650 0, PIPE_USAGE_STREAM, 0);
651 if (!rctx->b.stream_uploader)
652 return false;
653
654 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
655 0, PIPE_USAGE_DEFAULT, 0);
656 if (!rctx->b.const_uploader)
657 return false;
658
659 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
660 if (!rctx->ctx)
661 return false;
662
663 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
664 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
665 r600_flush_dma_ring,
666 rctx, false);
667 rctx->dma.flush = r600_flush_dma_ring;
668 }
669
670 return true;
671 }
672
673 void r600_common_context_cleanup(struct r600_common_context *rctx)
674 {
675 if (rctx->query_result_shader)
676 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
677
678 if (rctx->gfx.cs)
679 rctx->ws->cs_destroy(rctx->gfx.cs);
680 if (rctx->dma.cs)
681 rctx->ws->cs_destroy(rctx->dma.cs);
682 if (rctx->ctx)
683 rctx->ws->ctx_destroy(rctx->ctx);
684
685 if (rctx->b.stream_uploader)
686 u_upload_destroy(rctx->b.stream_uploader);
687 if (rctx->b.const_uploader)
688 u_upload_destroy(rctx->b.const_uploader);
689
690 slab_destroy_child(&rctx->pool_transfers);
691 slab_destroy_child(&rctx->pool_transfers_unsync);
692
693 if (rctx->allocator_zeroed_memory) {
694 u_suballocator_destroy(rctx->allocator_zeroed_memory);
695 }
696 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
697 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
698 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
699 }
700
701 /*
702 * pipe_screen
703 */
704
705 static const struct debug_named_value common_debug_options[] = {
706 /* logging */
707 { "tex", DBG_TEX, "Print texture info" },
708 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
709 { "compute", DBG_COMPUTE, "Print compute info" },
710 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
711 { "info", DBG_INFO, "Print driver information" },
712
713 /* shaders */
714 { "fs", DBG_FS, "Print fetch shaders" },
715 { "vs", DBG_VS, "Print vertex shaders" },
716 { "gs", DBG_GS, "Print geometry shaders" },
717 { "ps", DBG_PS, "Print pixel shaders" },
718 { "cs", DBG_CS, "Print compute shaders" },
719 { "tcs", DBG_TCS, "Print tessellation control shaders" },
720 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
721 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
722 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
723 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
724 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
725 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
726 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
727
728 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
729 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
730 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
731 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
732
733 /* features */
734 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
735 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
736 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
737 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
738 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
739 { "notiling", DBG_NO_TILING, "Disable tiling" },
740 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
741 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
742 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
743 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
744 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
745 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
746
747 DEBUG_NAMED_VALUE_END /* must be last */
748 };
749
750 static const char* r600_get_vendor(struct pipe_screen* pscreen)
751 {
752 return "X.Org";
753 }
754
755 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
756 {
757 return "AMD";
758 }
759
760 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
761 {
762 switch (rscreen->info.family) {
763 case CHIP_R600: return "AMD R600";
764 case CHIP_RV610: return "AMD RV610";
765 case CHIP_RV630: return "AMD RV630";
766 case CHIP_RV670: return "AMD RV670";
767 case CHIP_RV620: return "AMD RV620";
768 case CHIP_RV635: return "AMD RV635";
769 case CHIP_RS780: return "AMD RS780";
770 case CHIP_RS880: return "AMD RS880";
771 case CHIP_RV770: return "AMD RV770";
772 case CHIP_RV730: return "AMD RV730";
773 case CHIP_RV710: return "AMD RV710";
774 case CHIP_RV740: return "AMD RV740";
775 case CHIP_CEDAR: return "AMD CEDAR";
776 case CHIP_REDWOOD: return "AMD REDWOOD";
777 case CHIP_JUNIPER: return "AMD JUNIPER";
778 case CHIP_CYPRESS: return "AMD CYPRESS";
779 case CHIP_HEMLOCK: return "AMD HEMLOCK";
780 case CHIP_PALM: return "AMD PALM";
781 case CHIP_SUMO: return "AMD SUMO";
782 case CHIP_SUMO2: return "AMD SUMO2";
783 case CHIP_BARTS: return "AMD BARTS";
784 case CHIP_TURKS: return "AMD TURKS";
785 case CHIP_CAICOS: return "AMD CAICOS";
786 case CHIP_CAYMAN: return "AMD CAYMAN";
787 case CHIP_ARUBA: return "AMD ARUBA";
788 default: return "AMD unknown";
789 }
790 }
791
792 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
793 {
794 /* Don't use the cache if shader dumping is enabled. */
795 if (rscreen->debug_flags & DBG_ALL_SHADERS)
796 return;
797
798 struct mesa_sha1 ctx;
799 unsigned char sha1[20];
800 char cache_id[20 * 2 + 1];
801
802 _mesa_sha1_init(&ctx);
803 if (!disk_cache_get_function_identifier(r600_disk_cache_create,
804 &ctx))
805 return;
806
807 _mesa_sha1_final(&ctx, sha1);
808 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
809
810 /* These flags affect shader compilation. */
811 uint64_t shader_debug_flags =
812 rscreen->debug_flags &
813 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
814 DBG_UNSAFE_MATH);
815
816 rscreen->disk_shader_cache =
817 disk_cache_create(r600_get_family_name(rscreen),
818 cache_id,
819 shader_debug_flags);
820 }
821
822 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
823 {
824 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
825 return rscreen->disk_shader_cache;
826 }
827
828 static const char* r600_get_name(struct pipe_screen* pscreen)
829 {
830 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
831
832 return rscreen->renderer_string;
833 }
834
835 static float r600_get_paramf(struct pipe_screen* pscreen,
836 enum pipe_capf param)
837 {
838 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
839
840 switch (param) {
841 case PIPE_CAPF_MAX_LINE_WIDTH:
842 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
843 case PIPE_CAPF_MAX_POINT_WIDTH:
844 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
845 if (rscreen->family >= CHIP_CEDAR)
846 return 16384.0f;
847 else
848 return 8192.0f;
849 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
850 return 16.0f;
851 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
852 return 16.0f;
853 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
854 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
855 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
856 return 0.0f;
857 }
858 return 0.0f;
859 }
860
861 static int r600_get_video_param(struct pipe_screen *screen,
862 enum pipe_video_profile profile,
863 enum pipe_video_entrypoint entrypoint,
864 enum pipe_video_cap param)
865 {
866 switch (param) {
867 case PIPE_VIDEO_CAP_SUPPORTED:
868 return vl_profile_supported(screen, profile, entrypoint);
869 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
870 return 1;
871 case PIPE_VIDEO_CAP_MAX_WIDTH:
872 case PIPE_VIDEO_CAP_MAX_HEIGHT:
873 return vl_video_buffer_max_size(screen);
874 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
875 return PIPE_FORMAT_NV12;
876 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
877 return false;
878 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
879 return false;
880 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
881 return true;
882 case PIPE_VIDEO_CAP_MAX_LEVEL:
883 return vl_level_supported(screen, profile);
884 default:
885 return 0;
886 }
887 }
888
889 const char *r600_get_llvm_processor_name(enum radeon_family family)
890 {
891 switch (family) {
892 case CHIP_R600:
893 case CHIP_RV630:
894 case CHIP_RV635:
895 case CHIP_RV670:
896 return "r600";
897 case CHIP_RV610:
898 case CHIP_RV620:
899 case CHIP_RS780:
900 case CHIP_RS880:
901 return "rs880";
902 case CHIP_RV710:
903 return "rv710";
904 case CHIP_RV730:
905 return "rv730";
906 case CHIP_RV740:
907 case CHIP_RV770:
908 return "rv770";
909 case CHIP_PALM:
910 case CHIP_CEDAR:
911 return "cedar";
912 case CHIP_SUMO:
913 case CHIP_SUMO2:
914 return "sumo";
915 case CHIP_REDWOOD:
916 return "redwood";
917 case CHIP_JUNIPER:
918 return "juniper";
919 case CHIP_HEMLOCK:
920 case CHIP_CYPRESS:
921 return "cypress";
922 case CHIP_BARTS:
923 return "barts";
924 case CHIP_TURKS:
925 return "turks";
926 case CHIP_CAICOS:
927 return "caicos";
928 case CHIP_CAYMAN:
929 case CHIP_ARUBA:
930 return "cayman";
931
932 default:
933 return "";
934 }
935 }
936
937 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
938 enum pipe_shader_ir ir_type)
939 {
940 if (ir_type != PIPE_SHADER_IR_TGSI)
941 return 256;
942 if (screen->chip_class >= EVERGREEN)
943 return 1024;
944 return 256;
945 }
946
947 static int r600_get_compute_param(struct pipe_screen *screen,
948 enum pipe_shader_ir ir_type,
949 enum pipe_compute_cap param,
950 void *ret)
951 {
952 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
953
954 //TODO: select these params by asic
955 switch (param) {
956 case PIPE_COMPUTE_CAP_IR_TARGET: {
957 const char *gpu;
958 const char *triple = "r600--";
959 gpu = r600_get_llvm_processor_name(rscreen->family);
960 if (ret) {
961 sprintf(ret, "%s-%s", gpu, triple);
962 }
963 /* +2 for dash and terminating NIL byte */
964 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
965 }
966 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
967 if (ret) {
968 uint64_t *grid_dimension = ret;
969 grid_dimension[0] = 3;
970 }
971 return 1 * sizeof(uint64_t);
972
973 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
974 if (ret) {
975 uint64_t *grid_size = ret;
976 grid_size[0] = 65535;
977 grid_size[1] = 65535;
978 grid_size[2] = 65535;
979 }
980 return 3 * sizeof(uint64_t) ;
981
982 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
983 if (ret) {
984 uint64_t *block_size = ret;
985 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
986 block_size[0] = threads_per_block;
987 block_size[1] = threads_per_block;
988 block_size[2] = threads_per_block;
989 }
990 return 3 * sizeof(uint64_t);
991
992 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
993 if (ret) {
994 uint64_t *max_threads_per_block = ret;
995 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
996 }
997 return sizeof(uint64_t);
998 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
999 if (ret) {
1000 uint32_t *address_bits = ret;
1001 address_bits[0] = 32;
1002 }
1003 return 1 * sizeof(uint32_t);
1004
1005 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1006 if (ret) {
1007 uint64_t *max_global_size = ret;
1008 uint64_t max_mem_alloc_size;
1009
1010 r600_get_compute_param(screen, ir_type,
1011 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1012 &max_mem_alloc_size);
1013
1014 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1015 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1016 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1017 * make sure we never report more than
1018 * 4 * MAX_MEM_ALLOC_SIZE.
1019 */
1020 *max_global_size = MIN2(4 * max_mem_alloc_size,
1021 MAX2(rscreen->info.gart_size,
1022 rscreen->info.vram_size));
1023 }
1024 return sizeof(uint64_t);
1025
1026 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1027 if (ret) {
1028 uint64_t *max_local_size = ret;
1029 /* Value reported by the closed source driver. */
1030 *max_local_size = 32768;
1031 }
1032 return sizeof(uint64_t);
1033
1034 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1035 if (ret) {
1036 uint64_t *max_input_size = ret;
1037 /* Value reported by the closed source driver. */
1038 *max_input_size = 1024;
1039 }
1040 return sizeof(uint64_t);
1041
1042 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1043 if (ret) {
1044 uint64_t *max_mem_alloc_size = ret;
1045
1046 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1047 }
1048 return sizeof(uint64_t);
1049
1050 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1051 if (ret) {
1052 uint32_t *max_clock_frequency = ret;
1053 *max_clock_frequency = rscreen->info.max_shader_clock;
1054 }
1055 return sizeof(uint32_t);
1056
1057 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1058 if (ret) {
1059 uint32_t *max_compute_units = ret;
1060 *max_compute_units = rscreen->info.num_good_compute_units;
1061 }
1062 return sizeof(uint32_t);
1063
1064 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1065 if (ret) {
1066 uint32_t *images_supported = ret;
1067 *images_supported = 0;
1068 }
1069 return sizeof(uint32_t);
1070 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1071 break; /* unused */
1072 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1073 if (ret) {
1074 uint32_t *subgroup_size = ret;
1075 *subgroup_size = r600_wavefront_size(rscreen->family);
1076 }
1077 return sizeof(uint32_t);
1078 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1079 if (ret) {
1080 uint64_t *max_variable_threads_per_block = ret;
1081 *max_variable_threads_per_block = 0;
1082 }
1083 return sizeof(uint64_t);
1084 }
1085
1086 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1087 return 0;
1088 }
1089
1090 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1091 {
1092 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1093
1094 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1095 rscreen->info.clock_crystal_freq;
1096 }
1097
1098 static void r600_fence_reference(struct pipe_screen *screen,
1099 struct pipe_fence_handle **dst,
1100 struct pipe_fence_handle *src)
1101 {
1102 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1103 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1104 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1105
1106 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1107 ws->fence_reference(&(*rdst)->gfx, NULL);
1108 ws->fence_reference(&(*rdst)->sdma, NULL);
1109 FREE(*rdst);
1110 }
1111 *rdst = rsrc;
1112 }
1113
1114 static boolean r600_fence_finish(struct pipe_screen *screen,
1115 struct pipe_context *ctx,
1116 struct pipe_fence_handle *fence,
1117 uint64_t timeout)
1118 {
1119 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1120 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1121 struct r600_common_context *rctx;
1122 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1123
1124 ctx = threaded_context_unwrap_sync(ctx);
1125 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1126
1127 if (rfence->sdma) {
1128 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1129 return false;
1130
1131 /* Recompute the timeout after waiting. */
1132 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1133 int64_t time = os_time_get_nano();
1134 timeout = abs_timeout > time ? abs_timeout - time : 0;
1135 }
1136 }
1137
1138 if (!rfence->gfx)
1139 return true;
1140
1141 /* Flush the gfx IB if it hasn't been flushed yet. */
1142 if (rctx &&
1143 rfence->gfx_unflushed.ctx == rctx &&
1144 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1145 rctx->gfx.flush(rctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
1146 rfence->gfx_unflushed.ctx = NULL;
1147
1148 if (!timeout)
1149 return false;
1150
1151 /* Recompute the timeout after all that. */
1152 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1153 int64_t time = os_time_get_nano();
1154 timeout = abs_timeout > time ? abs_timeout - time : 0;
1155 }
1156 }
1157
1158 return rws->fence_wait(rws, rfence->gfx, timeout);
1159 }
1160
1161 static void r600_query_memory_info(struct pipe_screen *screen,
1162 struct pipe_memory_info *info)
1163 {
1164 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1165 struct radeon_winsys *ws = rscreen->ws;
1166 unsigned vram_usage, gtt_usage;
1167
1168 info->total_device_memory = rscreen->info.vram_size / 1024;
1169 info->total_staging_memory = rscreen->info.gart_size / 1024;
1170
1171 /* The real TTM memory usage is somewhat random, because:
1172 *
1173 * 1) TTM delays freeing memory, because it can only free it after
1174 * fences expire.
1175 *
1176 * 2) The memory usage can be really low if big VRAM evictions are
1177 * taking place, but the real usage is well above the size of VRAM.
1178 *
1179 * Instead, return statistics of this process.
1180 */
1181 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1182 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1183
1184 info->avail_device_memory =
1185 vram_usage <= info->total_device_memory ?
1186 info->total_device_memory - vram_usage : 0;
1187 info->avail_staging_memory =
1188 gtt_usage <= info->total_staging_memory ?
1189 info->total_staging_memory - gtt_usage : 0;
1190
1191 info->device_memory_evicted =
1192 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1193
1194 /* Just return the number of evicted 64KB pages. */
1195 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1196 }
1197
1198 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1199 const struct pipe_resource *templ)
1200 {
1201 if (templ->target == PIPE_BUFFER) {
1202 return r600_buffer_create(screen, templ, 256);
1203 } else {
1204 return r600_texture_create(screen, templ);
1205 }
1206 }
1207
1208 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1209 struct radeon_winsys *ws)
1210 {
1211 char family_name[32] = {}, kernel_version[128] = {};
1212 struct utsname uname_data;
1213 const char *chip_name;
1214
1215 ws->query_info(ws, &rscreen->info);
1216 rscreen->ws = ws;
1217
1218 chip_name = r600_get_family_name(rscreen);
1219
1220 if (uname(&uname_data) == 0)
1221 snprintf(kernel_version, sizeof(kernel_version),
1222 " / %s", uname_data.release);
1223
1224 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1225 "%s (%sDRM %i.%i.%i%s"
1226 #if HAVE_LLVM > 0
1227 ", LLVM " MESA_LLVM_VERSION_STRING
1228 #endif
1229 ")",
1230 chip_name, family_name, rscreen->info.drm_major,
1231 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1232 kernel_version);
1233
1234 rscreen->b.get_name = r600_get_name;
1235 rscreen->b.get_vendor = r600_get_vendor;
1236 rscreen->b.get_device_vendor = r600_get_device_vendor;
1237 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1238 rscreen->b.get_compute_param = r600_get_compute_param;
1239 rscreen->b.get_paramf = r600_get_paramf;
1240 rscreen->b.get_timestamp = r600_get_timestamp;
1241 rscreen->b.fence_finish = r600_fence_finish;
1242 rscreen->b.fence_reference = r600_fence_reference;
1243 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1244 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1245 rscreen->b.query_memory_info = r600_query_memory_info;
1246
1247 if (rscreen->info.has_hw_decode) {
1248 rscreen->b.get_video_param = rvid_get_video_param;
1249 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1250 } else {
1251 rscreen->b.get_video_param = r600_get_video_param;
1252 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1253 }
1254
1255 r600_init_screen_texture_functions(rscreen);
1256 r600_init_screen_query_functions(rscreen);
1257
1258 rscreen->family = rscreen->info.family;
1259 rscreen->chip_class = rscreen->info.chip_class;
1260 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1261
1262 r600_disk_cache_create(rscreen);
1263
1264 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1265
1266 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1267 if (rscreen->force_aniso >= 0) {
1268 printf("radeon: Forcing anisotropy filter to %ix\n",
1269 /* round down to a power of two */
1270 1 << util_logbase2(rscreen->force_aniso));
1271 }
1272
1273 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1274 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1275
1276 if (rscreen->debug_flags & DBG_INFO) {
1277 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1278 rscreen->info.pci_domain, rscreen->info.pci_bus,
1279 rscreen->info.pci_dev, rscreen->info.pci_func);
1280 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1281 printf("family = %i (%s)\n", rscreen->info.family,
1282 r600_get_family_name(rscreen));
1283 printf("chip_class = %i\n", rscreen->info.chip_class);
1284 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1285 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1286 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1287 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1288 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1289 printf("max_alloc_size = %i MB\n",
1290 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1291 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1292 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1293 printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory);
1294 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1295 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1296 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1297 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1298 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1299 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1300 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1301 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1302 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1303 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1304 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1305 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1306 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1307 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1308 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1309 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1310
1311 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1312 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1313 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1314 printf("max_se = %i\n", rscreen->info.max_se);
1315 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1316
1317 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1318 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1319 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1320 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1321 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1322 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1323 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1324 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1325 }
1326 return true;
1327 }
1328
1329 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1330 {
1331 r600_perfcounters_destroy(rscreen);
1332 r600_gpu_load_kill_thread(rscreen);
1333
1334 mtx_destroy(&rscreen->gpu_load_mutex);
1335 mtx_destroy(&rscreen->aux_context_lock);
1336 rscreen->aux_context->destroy(rscreen->aux_context);
1337
1338 slab_destroy_parent(&rscreen->pool_transfers);
1339
1340 disk_cache_destroy(rscreen->disk_shader_cache);
1341 rscreen->ws->destroy(rscreen->ws);
1342 FREE(rscreen);
1343 }
1344
1345 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1346 unsigned processor)
1347 {
1348 return rscreen->debug_flags & (1 << processor);
1349 }
1350
1351 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1352 {
1353 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1354 r600_can_dump_shader(rscreen, processor);
1355 }
1356
1357 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1358 uint64_t offset, uint64_t size, unsigned value)
1359 {
1360 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1361
1362 mtx_lock(&rscreen->aux_context_lock);
1363 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1364 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1365 mtx_unlock(&rscreen->aux_context_lock);
1366 }