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amd/common: move ac_shader_{binary,reloc} into r600 and rename
[mesa.git] / src / gallium / drivers / r600 / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 struct r600_multi_fence {
51 struct pipe_reference reference;
52 struct pipe_fence_handle *gfx;
53 struct pipe_fence_handle *sdma;
54
55 /* If the context wasn't flushed at fence creation, this is non-NULL. */
56 struct {
57 struct r600_common_context *ctx;
58 unsigned ib_index;
59 } gfx_unflushed;
60 };
61
62 /*
63 * pipe_context
64 */
65
66 /**
67 * Write an EOP event.
68 *
69 * \param event EVENT_TYPE_*
70 * \param event_flags Optional cache flush flags (TC)
71 * \param data_sel 1 = fence, 3 = timestamp
72 * \param buf Buffer
73 * \param va GPU address
74 * \param old_value Previous fence value (for a bug workaround)
75 * \param new_value Fence value to write for this event.
76 */
77 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
78 unsigned event, unsigned event_flags,
79 unsigned data_sel,
80 struct r600_resource *buf, uint64_t va,
81 uint32_t new_fence, unsigned query_type)
82 {
83 struct radeon_cmdbuf *cs = ctx->gfx.cs;
84 unsigned op = EVENT_TYPE(event) |
85 EVENT_INDEX(5) |
86 event_flags;
87 unsigned sel = EOP_DATA_SEL(data_sel);
88
89 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
90 radeon_emit(cs, op);
91 radeon_emit(cs, va);
92 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
93 radeon_emit(cs, new_fence); /* immediate data */
94 radeon_emit(cs, 0); /* unused */
95
96 if (buf)
97 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
98 RADEON_PRIO_QUERY);
99 }
100
101 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
102 {
103 unsigned dwords = 6;
104
105 if (!screen->info.r600_has_virtual_memory)
106 dwords += 2;
107
108 return dwords;
109 }
110
111 void r600_gfx_wait_fence(struct r600_common_context *ctx,
112 struct r600_resource *buf,
113 uint64_t va, uint32_t ref, uint32_t mask)
114 {
115 struct radeon_cmdbuf *cs = ctx->gfx.cs;
116
117 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
118 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
119 radeon_emit(cs, va);
120 radeon_emit(cs, va >> 32);
121 radeon_emit(cs, ref); /* reference value */
122 radeon_emit(cs, mask); /* mask */
123 radeon_emit(cs, 4); /* poll interval */
124
125 if (buf)
126 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
127 RADEON_PRIO_QUERY);
128 }
129
130 void r600_draw_rectangle(struct blitter_context *blitter,
131 void *vertex_elements_cso,
132 blitter_get_vs_func get_vs,
133 int x1, int y1, int x2, int y2,
134 float depth, unsigned num_instances,
135 enum blitter_attrib_type type,
136 const union blitter_attrib *attrib)
137 {
138 struct r600_common_context *rctx =
139 (struct r600_common_context*)util_blitter_get_pipe(blitter);
140 struct pipe_viewport_state viewport;
141 struct pipe_resource *buf = NULL;
142 unsigned offset = 0;
143 float *vb;
144
145 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
146 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
147
148 /* Some operations (like color resolve on r6xx) don't work
149 * with the conventional primitive types.
150 * One that works is PT_RECTLIST, which we use here. */
151
152 /* setup viewport */
153 viewport.scale[0] = 1.0f;
154 viewport.scale[1] = 1.0f;
155 viewport.scale[2] = 1.0f;
156 viewport.translate[0] = 0.0f;
157 viewport.translate[1] = 0.0f;
158 viewport.translate[2] = 0.0f;
159 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
160
161 /* Upload vertices. The hw rectangle has only 3 vertices,
162 * The 4th one is derived from the first 3.
163 * The vertex specification should match u_blitter's vertex element state. */
164 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
165 rctx->screen->info.tcc_cache_line_size,
166 &offset, &buf, (void**)&vb);
167 if (!buf)
168 return;
169
170 vb[0] = x1;
171 vb[1] = y1;
172 vb[2] = depth;
173 vb[3] = 1;
174
175 vb[8] = x1;
176 vb[9] = y2;
177 vb[10] = depth;
178 vb[11] = 1;
179
180 vb[16] = x2;
181 vb[17] = y1;
182 vb[18] = depth;
183 vb[19] = 1;
184
185 switch (type) {
186 case UTIL_BLITTER_ATTRIB_COLOR:
187 memcpy(vb+4, attrib->color, sizeof(float)*4);
188 memcpy(vb+12, attrib->color, sizeof(float)*4);
189 memcpy(vb+20, attrib->color, sizeof(float)*4);
190 break;
191 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
192 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
193 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
194 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
195 /* fall through */
196 vb[4] = attrib->texcoord.x1;
197 vb[5] = attrib->texcoord.y1;
198 vb[12] = attrib->texcoord.x1;
199 vb[13] = attrib->texcoord.y2;
200 vb[20] = attrib->texcoord.x2;
201 vb[21] = attrib->texcoord.y1;
202 break;
203 default:; /* Nothing to do. */
204 }
205
206 /* draw */
207 struct pipe_vertex_buffer vbuffer = {};
208 vbuffer.buffer.resource = buf;
209 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
210 vbuffer.buffer_offset = offset;
211
212 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
213 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
214 0, num_instances);
215 pipe_resource_reference(&buf, NULL);
216 }
217
218 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
219 {
220 struct radeon_cmdbuf *cs = rctx->dma.cs;
221
222 if (rctx->chip_class >= EVERGREEN)
223 radeon_emit(cs, 0xf0000000); /* NOP */
224 else {
225 /* TODO: R600-R700 should use the FENCE packet.
226 * CS checker support is required. */
227 }
228 }
229
230 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
231 struct r600_resource *dst, struct r600_resource *src)
232 {
233 uint64_t vram = ctx->dma.cs->used_vram;
234 uint64_t gtt = ctx->dma.cs->used_gart;
235
236 if (dst) {
237 vram += dst->vram_usage;
238 gtt += dst->gart_usage;
239 }
240 if (src) {
241 vram += src->vram_usage;
242 gtt += src->gart_usage;
243 }
244
245 /* Flush the GFX IB if DMA depends on it. */
246 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
247 ((dst &&
248 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
249 RADEON_USAGE_READWRITE)) ||
250 (src &&
251 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
252 RADEON_USAGE_WRITE))))
253 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
254
255 /* Flush if there's not enough space, or if the memory usage per IB
256 * is too large.
257 *
258 * IBs using too little memory are limited by the IB submission overhead.
259 * IBs using too much memory are limited by the kernel/TTM overhead.
260 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
261 *
262 * This heuristic makes sure that DMA requests are executed
263 * very soon after the call is made and lowers memory usage.
264 * It improves texture upload performance by keeping the DMA
265 * engine busy while uploads are being submitted.
266 */
267 num_dw++; /* for emit_wait_idle below */
268 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw, false) ||
269 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
270 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
271 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
272 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
273 }
274
275 /* Wait for idle if either buffer has been used in the IB before to
276 * prevent read-after-write hazards.
277 */
278 if ((dst &&
279 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
280 RADEON_USAGE_READWRITE)) ||
281 (src &&
282 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
283 RADEON_USAGE_WRITE)))
284 r600_dma_emit_wait_idle(ctx);
285
286 /* If GPUVM is not supported, the CS checker needs 2 entries
287 * in the buffer list per packet, which has to be done manually.
288 */
289 if (ctx->screen->info.r600_has_virtual_memory) {
290 if (dst)
291 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
292 RADEON_USAGE_WRITE, 0);
293 if (src)
294 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
295 RADEON_USAGE_READ, 0);
296 }
297
298 /* this function is called before all DMA calls, so increment this. */
299 ctx->num_dma_calls++;
300 }
301
302 void r600_preflush_suspend_features(struct r600_common_context *ctx)
303 {
304 /* suspend queries */
305 if (!LIST_IS_EMPTY(&ctx->active_queries))
306 r600_suspend_queries(ctx);
307
308 ctx->streamout.suspended = false;
309 if (ctx->streamout.begin_emitted) {
310 r600_emit_streamout_end(ctx);
311 ctx->streamout.suspended = true;
312 }
313 }
314
315 void r600_postflush_resume_features(struct r600_common_context *ctx)
316 {
317 if (ctx->streamout.suspended) {
318 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
319 r600_streamout_buffers_dirty(ctx);
320 }
321
322 /* resume queries */
323 if (!LIST_IS_EMPTY(&ctx->active_queries))
324 r600_resume_queries(ctx);
325 }
326
327 static void r600_fence_server_sync(struct pipe_context *ctx,
328 struct pipe_fence_handle *fence)
329 {
330 /* radeon synchronizes all rings by default and will not implement
331 * fence imports.
332 */
333 }
334
335 static void r600_flush_from_st(struct pipe_context *ctx,
336 struct pipe_fence_handle **fence,
337 unsigned flags)
338 {
339 struct pipe_screen *screen = ctx->screen;
340 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
341 struct radeon_winsys *ws = rctx->ws;
342 struct pipe_fence_handle *gfx_fence = NULL;
343 struct pipe_fence_handle *sdma_fence = NULL;
344 bool deferred_fence = false;
345 unsigned rflags = PIPE_FLUSH_ASYNC;
346
347 if (flags & PIPE_FLUSH_END_OF_FRAME)
348 rflags |= PIPE_FLUSH_END_OF_FRAME;
349
350 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
351 if (rctx->dma.cs)
352 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
353
354 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
355 if (fence)
356 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
357 if (!(flags & PIPE_FLUSH_DEFERRED))
358 ws->cs_sync_flush(rctx->gfx.cs);
359 } else {
360 /* Instead of flushing, create a deferred fence. Constraints:
361 * - The state tracker must allow a deferred flush.
362 * - The state tracker must request a fence.
363 * Thread safety in fence_finish must be ensured by the state tracker.
364 */
365 if (flags & PIPE_FLUSH_DEFERRED && fence) {
366 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
367 deferred_fence = true;
368 } else {
369 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
370 }
371 }
372
373 /* Both engines can signal out of order, so we need to keep both fences. */
374 if (fence) {
375 struct r600_multi_fence *multi_fence =
376 CALLOC_STRUCT(r600_multi_fence);
377 if (!multi_fence) {
378 ws->fence_reference(&sdma_fence, NULL);
379 ws->fence_reference(&gfx_fence, NULL);
380 goto finish;
381 }
382
383 multi_fence->reference.count = 1;
384 /* If both fences are NULL, fence_finish will always return true. */
385 multi_fence->gfx = gfx_fence;
386 multi_fence->sdma = sdma_fence;
387
388 if (deferred_fence) {
389 multi_fence->gfx_unflushed.ctx = rctx;
390 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
391 }
392
393 screen->fence_reference(screen, fence, NULL);
394 *fence = (struct pipe_fence_handle*)multi_fence;
395 }
396 finish:
397 if (!(flags & PIPE_FLUSH_DEFERRED)) {
398 if (rctx->dma.cs)
399 ws->cs_sync_flush(rctx->dma.cs);
400 ws->cs_sync_flush(rctx->gfx.cs);
401 }
402 }
403
404 static void r600_flush_dma_ring(void *ctx, unsigned flags,
405 struct pipe_fence_handle **fence)
406 {
407 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
408 struct radeon_cmdbuf *cs = rctx->dma.cs;
409 struct radeon_saved_cs saved;
410 bool check_vm =
411 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
412 rctx->check_vm_faults;
413
414 if (!radeon_emitted(cs, 0)) {
415 if (fence)
416 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
417 return;
418 }
419
420 if (check_vm)
421 radeon_save_cs(rctx->ws, cs, &saved, true);
422
423 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
424 if (fence)
425 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
426
427 if (check_vm) {
428 /* Use conservative timeout 800ms, after which we won't wait any
429 * longer and assume the GPU is hung.
430 */
431 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
432
433 rctx->check_vm_faults(rctx, &saved, RING_DMA);
434 radeon_clear_saved_cs(&saved);
435 }
436 }
437
438 /**
439 * Store a linearized copy of all chunks of \p cs together with the buffer
440 * list in \p saved.
441 */
442 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
443 struct radeon_saved_cs *saved, bool get_buffer_list)
444 {
445 uint32_t *buf;
446 unsigned i;
447
448 /* Save the IB chunks. */
449 saved->num_dw = cs->prev_dw + cs->current.cdw;
450 saved->ib = MALLOC(4 * saved->num_dw);
451 if (!saved->ib)
452 goto oom;
453
454 buf = saved->ib;
455 for (i = 0; i < cs->num_prev; ++i) {
456 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
457 buf += cs->prev[i].cdw;
458 }
459 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
460
461 if (!get_buffer_list)
462 return;
463
464 /* Save the buffer list. */
465 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
466 saved->bo_list = CALLOC(saved->bo_count,
467 sizeof(saved->bo_list[0]));
468 if (!saved->bo_list) {
469 FREE(saved->ib);
470 goto oom;
471 }
472 ws->cs_get_buffer_list(cs, saved->bo_list);
473
474 return;
475
476 oom:
477 fprintf(stderr, "%s: out of memory\n", __func__);
478 memset(saved, 0, sizeof(*saved));
479 }
480
481 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
482 {
483 FREE(saved->ib);
484 FREE(saved->bo_list);
485
486 memset(saved, 0, sizeof(*saved));
487 }
488
489 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
490 {
491 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
492
493 return rctx->ws->ctx_query_reset_status(rctx->ctx);
494 }
495
496 static void r600_set_debug_callback(struct pipe_context *ctx,
497 const struct pipe_debug_callback *cb)
498 {
499 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
500
501 if (cb)
502 rctx->debug = *cb;
503 else
504 memset(&rctx->debug, 0, sizeof(rctx->debug));
505 }
506
507 static void r600_set_device_reset_callback(struct pipe_context *ctx,
508 const struct pipe_device_reset_callback *cb)
509 {
510 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
511
512 if (cb)
513 rctx->device_reset_callback = *cb;
514 else
515 memset(&rctx->device_reset_callback, 0,
516 sizeof(rctx->device_reset_callback));
517 }
518
519 bool r600_check_device_reset(struct r600_common_context *rctx)
520 {
521 enum pipe_reset_status status;
522
523 if (!rctx->device_reset_callback.reset)
524 return false;
525
526 if (!rctx->b.get_device_reset_status)
527 return false;
528
529 status = rctx->b.get_device_reset_status(&rctx->b);
530 if (status == PIPE_NO_RESET)
531 return false;
532
533 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
534 return true;
535 }
536
537 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
538 struct pipe_resource *dst,
539 uint64_t offset, uint64_t size,
540 unsigned value)
541 {
542 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
543
544 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
545 }
546
547 static bool r600_resource_commit(struct pipe_context *pctx,
548 struct pipe_resource *resource,
549 unsigned level, struct pipe_box *box,
550 bool commit)
551 {
552 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
553 struct r600_resource *res = r600_resource(resource);
554
555 /*
556 * Since buffer commitment changes cannot be pipelined, we need to
557 * (a) flush any pending commands that refer to the buffer we're about
558 * to change, and
559 * (b) wait for threaded submit to finish, including those that were
560 * triggered by some other, earlier operation.
561 */
562 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
563 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
564 res->buf, RADEON_USAGE_READWRITE)) {
565 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
566 }
567 if (radeon_emitted(ctx->dma.cs, 0) &&
568 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
569 res->buf, RADEON_USAGE_READWRITE)) {
570 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
571 }
572
573 ctx->ws->cs_sync_flush(ctx->dma.cs);
574 ctx->ws->cs_sync_flush(ctx->gfx.cs);
575
576 assert(resource->target == PIPE_BUFFER);
577
578 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
579 }
580
581 bool r600_common_context_init(struct r600_common_context *rctx,
582 struct r600_common_screen *rscreen,
583 unsigned context_flags)
584 {
585 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
586 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
587
588 rctx->screen = rscreen;
589 rctx->ws = rscreen->ws;
590 rctx->family = rscreen->family;
591 rctx->chip_class = rscreen->chip_class;
592
593 rctx->b.invalidate_resource = r600_invalidate_resource;
594 rctx->b.resource_commit = r600_resource_commit;
595 rctx->b.transfer_map = u_transfer_map_vtbl;
596 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
597 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
598 rctx->b.texture_subdata = u_default_texture_subdata;
599 rctx->b.flush = r600_flush_from_st;
600 rctx->b.set_debug_callback = r600_set_debug_callback;
601 rctx->b.fence_server_sync = r600_fence_server_sync;
602 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
603
604 /* evergreen_compute.c has a special codepath for global buffers.
605 * Everything else can use the direct path.
606 */
607 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
608 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
609 rctx->b.buffer_subdata = u_default_buffer_subdata;
610 else
611 rctx->b.buffer_subdata = r600_buffer_subdata;
612
613 rctx->b.get_device_reset_status = r600_get_reset_status;
614 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
615
616 r600_init_context_texture_functions(rctx);
617 r600_init_viewport_functions(rctx);
618 r600_streamout_init(rctx);
619 r600_query_init(rctx);
620 cayman_init_msaa(&rctx->b);
621
622 rctx->allocator_zeroed_memory =
623 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
624 0, PIPE_USAGE_DEFAULT, 0, true);
625 if (!rctx->allocator_zeroed_memory)
626 return false;
627
628 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
629 0, PIPE_USAGE_STREAM, 0);
630 if (!rctx->b.stream_uploader)
631 return false;
632
633 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
634 0, PIPE_USAGE_DEFAULT, 0);
635 if (!rctx->b.const_uploader)
636 return false;
637
638 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
639 if (!rctx->ctx)
640 return false;
641
642 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
643 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
644 r600_flush_dma_ring,
645 rctx, false);
646 rctx->dma.flush = r600_flush_dma_ring;
647 }
648
649 return true;
650 }
651
652 void r600_common_context_cleanup(struct r600_common_context *rctx)
653 {
654 if (rctx->query_result_shader)
655 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
656
657 if (rctx->gfx.cs)
658 rctx->ws->cs_destroy(rctx->gfx.cs);
659 if (rctx->dma.cs)
660 rctx->ws->cs_destroy(rctx->dma.cs);
661 if (rctx->ctx)
662 rctx->ws->ctx_destroy(rctx->ctx);
663
664 if (rctx->b.stream_uploader)
665 u_upload_destroy(rctx->b.stream_uploader);
666 if (rctx->b.const_uploader)
667 u_upload_destroy(rctx->b.const_uploader);
668
669 slab_destroy_child(&rctx->pool_transfers);
670 slab_destroy_child(&rctx->pool_transfers_unsync);
671
672 if (rctx->allocator_zeroed_memory) {
673 u_suballocator_destroy(rctx->allocator_zeroed_memory);
674 }
675 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
676 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
677 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
678 }
679
680 /*
681 * pipe_screen
682 */
683
684 static const struct debug_named_value common_debug_options[] = {
685 /* logging */
686 { "tex", DBG_TEX, "Print texture info" },
687 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
688 { "compute", DBG_COMPUTE, "Print compute info" },
689 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
690 { "info", DBG_INFO, "Print driver information" },
691
692 /* shaders */
693 { "fs", DBG_FS, "Print fetch shaders" },
694 { "vs", DBG_VS, "Print vertex shaders" },
695 { "gs", DBG_GS, "Print geometry shaders" },
696 { "ps", DBG_PS, "Print pixel shaders" },
697 { "cs", DBG_CS, "Print compute shaders" },
698 { "tcs", DBG_TCS, "Print tessellation control shaders" },
699 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
700 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
701 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
702 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
703 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
704 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
705 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
706
707 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
708 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
709 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
710 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
711
712 /* features */
713 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
714 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
715 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
716 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
717 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
718 { "notiling", DBG_NO_TILING, "Disable tiling" },
719 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
720 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
721 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
722 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
723 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
724 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
725
726 DEBUG_NAMED_VALUE_END /* must be last */
727 };
728
729 static const char* r600_get_vendor(struct pipe_screen* pscreen)
730 {
731 return "X.Org";
732 }
733
734 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
735 {
736 return "AMD";
737 }
738
739 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
740 {
741 switch (rscreen->info.family) {
742 case CHIP_R600: return "AMD R600";
743 case CHIP_RV610: return "AMD RV610";
744 case CHIP_RV630: return "AMD RV630";
745 case CHIP_RV670: return "AMD RV670";
746 case CHIP_RV620: return "AMD RV620";
747 case CHIP_RV635: return "AMD RV635";
748 case CHIP_RS780: return "AMD RS780";
749 case CHIP_RS880: return "AMD RS880";
750 case CHIP_RV770: return "AMD RV770";
751 case CHIP_RV730: return "AMD RV730";
752 case CHIP_RV710: return "AMD RV710";
753 case CHIP_RV740: return "AMD RV740";
754 case CHIP_CEDAR: return "AMD CEDAR";
755 case CHIP_REDWOOD: return "AMD REDWOOD";
756 case CHIP_JUNIPER: return "AMD JUNIPER";
757 case CHIP_CYPRESS: return "AMD CYPRESS";
758 case CHIP_HEMLOCK: return "AMD HEMLOCK";
759 case CHIP_PALM: return "AMD PALM";
760 case CHIP_SUMO: return "AMD SUMO";
761 case CHIP_SUMO2: return "AMD SUMO2";
762 case CHIP_BARTS: return "AMD BARTS";
763 case CHIP_TURKS: return "AMD TURKS";
764 case CHIP_CAICOS: return "AMD CAICOS";
765 case CHIP_CAYMAN: return "AMD CAYMAN";
766 case CHIP_ARUBA: return "AMD ARUBA";
767 default: return "AMD unknown";
768 }
769 }
770
771 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
772 {
773 /* Don't use the cache if shader dumping is enabled. */
774 if (rscreen->debug_flags & DBG_ALL_SHADERS)
775 return;
776
777 struct mesa_sha1 ctx;
778 unsigned char sha1[20];
779 char cache_id[20 * 2 + 1];
780
781 _mesa_sha1_init(&ctx);
782 if (!disk_cache_get_function_identifier(r600_disk_cache_create,
783 &ctx))
784 return;
785
786 _mesa_sha1_final(&ctx, sha1);
787 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
788
789 /* These flags affect shader compilation. */
790 uint64_t shader_debug_flags =
791 rscreen->debug_flags &
792 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
793 DBG_UNSAFE_MATH);
794
795 rscreen->disk_shader_cache =
796 disk_cache_create(r600_get_family_name(rscreen),
797 cache_id,
798 shader_debug_flags);
799 }
800
801 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
802 {
803 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
804 return rscreen->disk_shader_cache;
805 }
806
807 static const char* r600_get_name(struct pipe_screen* pscreen)
808 {
809 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
810
811 return rscreen->renderer_string;
812 }
813
814 static float r600_get_paramf(struct pipe_screen* pscreen,
815 enum pipe_capf param)
816 {
817 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
818
819 switch (param) {
820 case PIPE_CAPF_MAX_LINE_WIDTH:
821 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
822 case PIPE_CAPF_MAX_POINT_WIDTH:
823 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
824 if (rscreen->family >= CHIP_CEDAR)
825 return 16384.0f;
826 else
827 return 8192.0f;
828 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
829 return 16.0f;
830 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
831 return 16.0f;
832 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
833 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
834 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
835 return 0.0f;
836 }
837 return 0.0f;
838 }
839
840 static int r600_get_video_param(struct pipe_screen *screen,
841 enum pipe_video_profile profile,
842 enum pipe_video_entrypoint entrypoint,
843 enum pipe_video_cap param)
844 {
845 switch (param) {
846 case PIPE_VIDEO_CAP_SUPPORTED:
847 return vl_profile_supported(screen, profile, entrypoint);
848 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
849 return 1;
850 case PIPE_VIDEO_CAP_MAX_WIDTH:
851 case PIPE_VIDEO_CAP_MAX_HEIGHT:
852 return vl_video_buffer_max_size(screen);
853 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
854 return PIPE_FORMAT_NV12;
855 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
856 return false;
857 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
858 return false;
859 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
860 return true;
861 case PIPE_VIDEO_CAP_MAX_LEVEL:
862 return vl_level_supported(screen, profile);
863 default:
864 return 0;
865 }
866 }
867
868 const char *r600_get_llvm_processor_name(enum radeon_family family)
869 {
870 switch (family) {
871 case CHIP_R600:
872 case CHIP_RV630:
873 case CHIP_RV635:
874 case CHIP_RV670:
875 return "r600";
876 case CHIP_RV610:
877 case CHIP_RV620:
878 case CHIP_RS780:
879 case CHIP_RS880:
880 return "rs880";
881 case CHIP_RV710:
882 return "rv710";
883 case CHIP_RV730:
884 return "rv730";
885 case CHIP_RV740:
886 case CHIP_RV770:
887 return "rv770";
888 case CHIP_PALM:
889 case CHIP_CEDAR:
890 return "cedar";
891 case CHIP_SUMO:
892 case CHIP_SUMO2:
893 return "sumo";
894 case CHIP_REDWOOD:
895 return "redwood";
896 case CHIP_JUNIPER:
897 return "juniper";
898 case CHIP_HEMLOCK:
899 case CHIP_CYPRESS:
900 return "cypress";
901 case CHIP_BARTS:
902 return "barts";
903 case CHIP_TURKS:
904 return "turks";
905 case CHIP_CAICOS:
906 return "caicos";
907 case CHIP_CAYMAN:
908 case CHIP_ARUBA:
909 return "cayman";
910
911 default:
912 return "";
913 }
914 }
915
916 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
917 enum pipe_shader_ir ir_type)
918 {
919 if (ir_type != PIPE_SHADER_IR_TGSI)
920 return 256;
921 if (screen->chip_class >= EVERGREEN)
922 return 1024;
923 return 256;
924 }
925
926 static int r600_get_compute_param(struct pipe_screen *screen,
927 enum pipe_shader_ir ir_type,
928 enum pipe_compute_cap param,
929 void *ret)
930 {
931 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
932
933 //TODO: select these params by asic
934 switch (param) {
935 case PIPE_COMPUTE_CAP_IR_TARGET: {
936 const char *gpu;
937 const char *triple = "r600--";
938 gpu = r600_get_llvm_processor_name(rscreen->family);
939 if (ret) {
940 sprintf(ret, "%s-%s", gpu, triple);
941 }
942 /* +2 for dash and terminating NIL byte */
943 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
944 }
945 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
946 if (ret) {
947 uint64_t *grid_dimension = ret;
948 grid_dimension[0] = 3;
949 }
950 return 1 * sizeof(uint64_t);
951
952 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
953 if (ret) {
954 uint64_t *grid_size = ret;
955 grid_size[0] = 65535;
956 grid_size[1] = 65535;
957 grid_size[2] = 65535;
958 }
959 return 3 * sizeof(uint64_t) ;
960
961 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
962 if (ret) {
963 uint64_t *block_size = ret;
964 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
965 block_size[0] = threads_per_block;
966 block_size[1] = threads_per_block;
967 block_size[2] = threads_per_block;
968 }
969 return 3 * sizeof(uint64_t);
970
971 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
972 if (ret) {
973 uint64_t *max_threads_per_block = ret;
974 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
975 }
976 return sizeof(uint64_t);
977 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
978 if (ret) {
979 uint32_t *address_bits = ret;
980 address_bits[0] = 32;
981 }
982 return 1 * sizeof(uint32_t);
983
984 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
985 if (ret) {
986 uint64_t *max_global_size = ret;
987 uint64_t max_mem_alloc_size;
988
989 r600_get_compute_param(screen, ir_type,
990 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
991 &max_mem_alloc_size);
992
993 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
994 * 1/4 of the MAX_GLOBAL_SIZE. Since the
995 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
996 * make sure we never report more than
997 * 4 * MAX_MEM_ALLOC_SIZE.
998 */
999 *max_global_size = MIN2(4 * max_mem_alloc_size,
1000 MAX2(rscreen->info.gart_size,
1001 rscreen->info.vram_size));
1002 }
1003 return sizeof(uint64_t);
1004
1005 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1006 if (ret) {
1007 uint64_t *max_local_size = ret;
1008 /* Value reported by the closed source driver. */
1009 *max_local_size = 32768;
1010 }
1011 return sizeof(uint64_t);
1012
1013 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1014 if (ret) {
1015 uint64_t *max_input_size = ret;
1016 /* Value reported by the closed source driver. */
1017 *max_input_size = 1024;
1018 }
1019 return sizeof(uint64_t);
1020
1021 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1022 if (ret) {
1023 uint64_t *max_mem_alloc_size = ret;
1024
1025 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1026 }
1027 return sizeof(uint64_t);
1028
1029 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1030 if (ret) {
1031 uint32_t *max_clock_frequency = ret;
1032 *max_clock_frequency = rscreen->info.max_shader_clock;
1033 }
1034 return sizeof(uint32_t);
1035
1036 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1037 if (ret) {
1038 uint32_t *max_compute_units = ret;
1039 *max_compute_units = rscreen->info.num_good_compute_units;
1040 }
1041 return sizeof(uint32_t);
1042
1043 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1044 if (ret) {
1045 uint32_t *images_supported = ret;
1046 *images_supported = 0;
1047 }
1048 return sizeof(uint32_t);
1049 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1050 break; /* unused */
1051 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1052 if (ret) {
1053 uint32_t *subgroup_size = ret;
1054 *subgroup_size = r600_wavefront_size(rscreen->family);
1055 }
1056 return sizeof(uint32_t);
1057 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1058 if (ret) {
1059 uint64_t *max_variable_threads_per_block = ret;
1060 *max_variable_threads_per_block = 0;
1061 }
1062 return sizeof(uint64_t);
1063 }
1064
1065 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1066 return 0;
1067 }
1068
1069 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1070 {
1071 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1072
1073 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1074 rscreen->info.clock_crystal_freq;
1075 }
1076
1077 static void r600_fence_reference(struct pipe_screen *screen,
1078 struct pipe_fence_handle **dst,
1079 struct pipe_fence_handle *src)
1080 {
1081 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1082 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1083 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1084
1085 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1086 ws->fence_reference(&(*rdst)->gfx, NULL);
1087 ws->fence_reference(&(*rdst)->sdma, NULL);
1088 FREE(*rdst);
1089 }
1090 *rdst = rsrc;
1091 }
1092
1093 static boolean r600_fence_finish(struct pipe_screen *screen,
1094 struct pipe_context *ctx,
1095 struct pipe_fence_handle *fence,
1096 uint64_t timeout)
1097 {
1098 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1099 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1100 struct r600_common_context *rctx;
1101 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1102
1103 ctx = threaded_context_unwrap_sync(ctx);
1104 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1105
1106 if (rfence->sdma) {
1107 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1108 return false;
1109
1110 /* Recompute the timeout after waiting. */
1111 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1112 int64_t time = os_time_get_nano();
1113 timeout = abs_timeout > time ? abs_timeout - time : 0;
1114 }
1115 }
1116
1117 if (!rfence->gfx)
1118 return true;
1119
1120 /* Flush the gfx IB if it hasn't been flushed yet. */
1121 if (rctx &&
1122 rfence->gfx_unflushed.ctx == rctx &&
1123 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1124 rctx->gfx.flush(rctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
1125 rfence->gfx_unflushed.ctx = NULL;
1126
1127 if (!timeout)
1128 return false;
1129
1130 /* Recompute the timeout after all that. */
1131 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1132 int64_t time = os_time_get_nano();
1133 timeout = abs_timeout > time ? abs_timeout - time : 0;
1134 }
1135 }
1136
1137 return rws->fence_wait(rws, rfence->gfx, timeout);
1138 }
1139
1140 static void r600_query_memory_info(struct pipe_screen *screen,
1141 struct pipe_memory_info *info)
1142 {
1143 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1144 struct radeon_winsys *ws = rscreen->ws;
1145 unsigned vram_usage, gtt_usage;
1146
1147 info->total_device_memory = rscreen->info.vram_size / 1024;
1148 info->total_staging_memory = rscreen->info.gart_size / 1024;
1149
1150 /* The real TTM memory usage is somewhat random, because:
1151 *
1152 * 1) TTM delays freeing memory, because it can only free it after
1153 * fences expire.
1154 *
1155 * 2) The memory usage can be really low if big VRAM evictions are
1156 * taking place, but the real usage is well above the size of VRAM.
1157 *
1158 * Instead, return statistics of this process.
1159 */
1160 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1161 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1162
1163 info->avail_device_memory =
1164 vram_usage <= info->total_device_memory ?
1165 info->total_device_memory - vram_usage : 0;
1166 info->avail_staging_memory =
1167 gtt_usage <= info->total_staging_memory ?
1168 info->total_staging_memory - gtt_usage : 0;
1169
1170 info->device_memory_evicted =
1171 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1172
1173 /* Just return the number of evicted 64KB pages. */
1174 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1175 }
1176
1177 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1178 const struct pipe_resource *templ)
1179 {
1180 if (templ->target == PIPE_BUFFER) {
1181 return r600_buffer_create(screen, templ, 256);
1182 } else {
1183 return r600_texture_create(screen, templ);
1184 }
1185 }
1186
1187 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1188 struct radeon_winsys *ws)
1189 {
1190 char family_name[32] = {}, kernel_version[128] = {};
1191 struct utsname uname_data;
1192 const char *chip_name;
1193
1194 ws->query_info(ws, &rscreen->info);
1195 rscreen->ws = ws;
1196
1197 chip_name = r600_get_family_name(rscreen);
1198
1199 if (uname(&uname_data) == 0)
1200 snprintf(kernel_version, sizeof(kernel_version),
1201 " / %s", uname_data.release);
1202
1203 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1204 "%s (%sDRM %i.%i.%i%s"
1205 #if HAVE_LLVM > 0
1206 ", LLVM " MESA_LLVM_VERSION_STRING
1207 #endif
1208 ")",
1209 chip_name, family_name, rscreen->info.drm_major,
1210 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1211 kernel_version);
1212
1213 rscreen->b.get_name = r600_get_name;
1214 rscreen->b.get_vendor = r600_get_vendor;
1215 rscreen->b.get_device_vendor = r600_get_device_vendor;
1216 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1217 rscreen->b.get_compute_param = r600_get_compute_param;
1218 rscreen->b.get_paramf = r600_get_paramf;
1219 rscreen->b.get_timestamp = r600_get_timestamp;
1220 rscreen->b.fence_finish = r600_fence_finish;
1221 rscreen->b.fence_reference = r600_fence_reference;
1222 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1223 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1224 rscreen->b.query_memory_info = r600_query_memory_info;
1225
1226 if (rscreen->info.has_hw_decode) {
1227 rscreen->b.get_video_param = rvid_get_video_param;
1228 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1229 } else {
1230 rscreen->b.get_video_param = r600_get_video_param;
1231 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1232 }
1233
1234 r600_init_screen_texture_functions(rscreen);
1235 r600_init_screen_query_functions(rscreen);
1236
1237 rscreen->family = rscreen->info.family;
1238 rscreen->chip_class = rscreen->info.chip_class;
1239 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1240
1241 r600_disk_cache_create(rscreen);
1242
1243 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1244
1245 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1246 if (rscreen->force_aniso >= 0) {
1247 printf("radeon: Forcing anisotropy filter to %ix\n",
1248 /* round down to a power of two */
1249 1 << util_logbase2(rscreen->force_aniso));
1250 }
1251
1252 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1253 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1254
1255 if (rscreen->debug_flags & DBG_INFO) {
1256 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1257 rscreen->info.pci_domain, rscreen->info.pci_bus,
1258 rscreen->info.pci_dev, rscreen->info.pci_func);
1259 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1260 printf("family = %i (%s)\n", rscreen->info.family,
1261 r600_get_family_name(rscreen));
1262 printf("chip_class = %i\n", rscreen->info.chip_class);
1263 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1264 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1265 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1266 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1267 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1268 printf("max_alloc_size = %i MB\n",
1269 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1270 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1271 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1272 printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory);
1273 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1274 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1275 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1276 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1277 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1278 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1279 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1280 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1281 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1282 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1283 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1284 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1285 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1286 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1287 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1288 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1289
1290 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1291 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1292 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1293 printf("max_se = %i\n", rscreen->info.max_se);
1294 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1295
1296 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1297 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1298 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1299 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1300 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1301 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1302 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1303 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1304 }
1305 return true;
1306 }
1307
1308 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1309 {
1310 r600_perfcounters_destroy(rscreen);
1311 r600_gpu_load_kill_thread(rscreen);
1312
1313 mtx_destroy(&rscreen->gpu_load_mutex);
1314 mtx_destroy(&rscreen->aux_context_lock);
1315 rscreen->aux_context->destroy(rscreen->aux_context);
1316
1317 slab_destroy_parent(&rscreen->pool_transfers);
1318
1319 disk_cache_destroy(rscreen->disk_shader_cache);
1320 rscreen->ws->destroy(rscreen->ws);
1321 FREE(rscreen);
1322 }
1323
1324 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1325 unsigned processor)
1326 {
1327 return rscreen->debug_flags & (1 << processor);
1328 }
1329
1330 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1331 {
1332 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1333 r600_can_dump_shader(rscreen, processor);
1334 }
1335
1336 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1337 uint64_t offset, uint64_t size, unsigned value)
1338 {
1339 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1340
1341 mtx_lock(&rscreen->aux_context_lock);
1342 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1343 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1344 mtx_unlock(&rscreen->aux_context_lock);
1345 }