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r600: replace binary HAVE_LLVM checks with LLVM_AVAILABLE
[mesa.git] / src / gallium / drivers / r600 / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifdef LLVM_AVAILABLE
43 #include <llvm-c/TargetMachine.h>
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct {
53 struct r600_common_context *ctx;
54 unsigned ib_index;
55 } gfx_unflushed;
56 };
57
58 /*
59 * pipe_context
60 */
61
62 /**
63 * Write an EOP event.
64 *
65 * \param event EVENT_TYPE_*
66 * \param event_flags Optional cache flush flags (TC)
67 * \param data_sel 1 = fence, 3 = timestamp
68 * \param buf Buffer
69 * \param va GPU address
70 * \param old_value Previous fence value (for a bug workaround)
71 * \param new_value Fence value to write for this event.
72 */
73 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
74 unsigned event, unsigned event_flags,
75 unsigned data_sel,
76 struct r600_resource *buf, uint64_t va,
77 uint32_t new_fence, unsigned query_type)
78 {
79 struct radeon_cmdbuf *cs = ctx->gfx.cs;
80 unsigned op = EVENT_TYPE(event) |
81 EVENT_INDEX(5) |
82 event_flags;
83 unsigned sel = EOP_DATA_SEL(data_sel);
84
85 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
86 radeon_emit(cs, op);
87 radeon_emit(cs, va);
88 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
89 radeon_emit(cs, new_fence); /* immediate data */
90 radeon_emit(cs, 0); /* unused */
91
92 if (buf)
93 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
94 RADEON_PRIO_QUERY);
95 }
96
97 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
98 {
99 unsigned dwords = 6;
100
101 if (!screen->info.r600_has_virtual_memory)
102 dwords += 2;
103
104 return dwords;
105 }
106
107 void r600_gfx_wait_fence(struct r600_common_context *ctx,
108 struct r600_resource *buf,
109 uint64_t va, uint32_t ref, uint32_t mask)
110 {
111 struct radeon_cmdbuf *cs = ctx->gfx.cs;
112
113 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
114 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
115 radeon_emit(cs, va);
116 radeon_emit(cs, va >> 32);
117 radeon_emit(cs, ref); /* reference value */
118 radeon_emit(cs, mask); /* mask */
119 radeon_emit(cs, 4); /* poll interval */
120
121 if (buf)
122 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
123 RADEON_PRIO_QUERY);
124 }
125
126 void r600_draw_rectangle(struct blitter_context *blitter,
127 void *vertex_elements_cso,
128 blitter_get_vs_func get_vs,
129 int x1, int y1, int x2, int y2,
130 float depth, unsigned num_instances,
131 enum blitter_attrib_type type,
132 const union blitter_attrib *attrib)
133 {
134 struct r600_common_context *rctx =
135 (struct r600_common_context*)util_blitter_get_pipe(blitter);
136 struct pipe_viewport_state viewport;
137 struct pipe_resource *buf = NULL;
138 unsigned offset = 0;
139 float *vb;
140
141 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
142 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
143
144 /* Some operations (like color resolve on r6xx) don't work
145 * with the conventional primitive types.
146 * One that works is PT_RECTLIST, which we use here. */
147
148 /* setup viewport */
149 viewport.scale[0] = 1.0f;
150 viewport.scale[1] = 1.0f;
151 viewport.scale[2] = 1.0f;
152 viewport.translate[0] = 0.0f;
153 viewport.translate[1] = 0.0f;
154 viewport.translate[2] = 0.0f;
155 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
156
157 /* Upload vertices. The hw rectangle has only 3 vertices,
158 * The 4th one is derived from the first 3.
159 * The vertex specification should match u_blitter's vertex element state. */
160 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
161 rctx->screen->info.tcc_cache_line_size,
162 &offset, &buf, (void**)&vb);
163 if (!buf)
164 return;
165
166 vb[0] = x1;
167 vb[1] = y1;
168 vb[2] = depth;
169 vb[3] = 1;
170
171 vb[8] = x1;
172 vb[9] = y2;
173 vb[10] = depth;
174 vb[11] = 1;
175
176 vb[16] = x2;
177 vb[17] = y1;
178 vb[18] = depth;
179 vb[19] = 1;
180
181 switch (type) {
182 case UTIL_BLITTER_ATTRIB_COLOR:
183 memcpy(vb+4, attrib->color, sizeof(float)*4);
184 memcpy(vb+12, attrib->color, sizeof(float)*4);
185 memcpy(vb+20, attrib->color, sizeof(float)*4);
186 break;
187 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
188 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
189 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
190 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
191 /* fall through */
192 vb[4] = attrib->texcoord.x1;
193 vb[5] = attrib->texcoord.y1;
194 vb[12] = attrib->texcoord.x1;
195 vb[13] = attrib->texcoord.y2;
196 vb[20] = attrib->texcoord.x2;
197 vb[21] = attrib->texcoord.y1;
198 break;
199 default:; /* Nothing to do. */
200 }
201
202 /* draw */
203 struct pipe_vertex_buffer vbuffer = {};
204 vbuffer.buffer.resource = buf;
205 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
206 vbuffer.buffer_offset = offset;
207
208 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
209 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
210 0, num_instances);
211 pipe_resource_reference(&buf, NULL);
212 }
213
214 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
215 {
216 struct radeon_cmdbuf *cs = rctx->dma.cs;
217
218 if (rctx->chip_class >= EVERGREEN)
219 radeon_emit(cs, 0xf0000000); /* NOP */
220 else {
221 /* TODO: R600-R700 should use the FENCE packet.
222 * CS checker support is required. */
223 }
224 }
225
226 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
227 struct r600_resource *dst, struct r600_resource *src)
228 {
229 uint64_t vram = ctx->dma.cs->used_vram;
230 uint64_t gtt = ctx->dma.cs->used_gart;
231
232 if (dst) {
233 vram += dst->vram_usage;
234 gtt += dst->gart_usage;
235 }
236 if (src) {
237 vram += src->vram_usage;
238 gtt += src->gart_usage;
239 }
240
241 /* Flush the GFX IB if DMA depends on it. */
242 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
243 ((dst &&
244 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
245 RADEON_USAGE_READWRITE)) ||
246 (src &&
247 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
248 RADEON_USAGE_WRITE))))
249 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
250
251 /* Flush if there's not enough space, or if the memory usage per IB
252 * is too large.
253 *
254 * IBs using too little memory are limited by the IB submission overhead.
255 * IBs using too much memory are limited by the kernel/TTM overhead.
256 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
257 *
258 * This heuristic makes sure that DMA requests are executed
259 * very soon after the call is made and lowers memory usage.
260 * It improves texture upload performance by keeping the DMA
261 * engine busy while uploads are being submitted.
262 */
263 num_dw++; /* for emit_wait_idle below */
264 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw, false) ||
265 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
266 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
267 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
268 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
269 }
270
271 /* Wait for idle if either buffer has been used in the IB before to
272 * prevent read-after-write hazards.
273 */
274 if ((dst &&
275 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
276 RADEON_USAGE_READWRITE)) ||
277 (src &&
278 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
279 RADEON_USAGE_WRITE)))
280 r600_dma_emit_wait_idle(ctx);
281
282 /* If GPUVM is not supported, the CS checker needs 2 entries
283 * in the buffer list per packet, which has to be done manually.
284 */
285 if (ctx->screen->info.r600_has_virtual_memory) {
286 if (dst)
287 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
288 RADEON_USAGE_WRITE, 0);
289 if (src)
290 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
291 RADEON_USAGE_READ, 0);
292 }
293
294 /* this function is called before all DMA calls, so increment this. */
295 ctx->num_dma_calls++;
296 }
297
298 void r600_preflush_suspend_features(struct r600_common_context *ctx)
299 {
300 /* suspend queries */
301 if (!LIST_IS_EMPTY(&ctx->active_queries))
302 r600_suspend_queries(ctx);
303
304 ctx->streamout.suspended = false;
305 if (ctx->streamout.begin_emitted) {
306 r600_emit_streamout_end(ctx);
307 ctx->streamout.suspended = true;
308 }
309 }
310
311 void r600_postflush_resume_features(struct r600_common_context *ctx)
312 {
313 if (ctx->streamout.suspended) {
314 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
315 r600_streamout_buffers_dirty(ctx);
316 }
317
318 /* resume queries */
319 if (!LIST_IS_EMPTY(&ctx->active_queries))
320 r600_resume_queries(ctx);
321 }
322
323 static void r600_fence_server_sync(struct pipe_context *ctx,
324 struct pipe_fence_handle *fence)
325 {
326 /* radeon synchronizes all rings by default and will not implement
327 * fence imports.
328 */
329 }
330
331 static void r600_flush_from_st(struct pipe_context *ctx,
332 struct pipe_fence_handle **fence,
333 unsigned flags)
334 {
335 struct pipe_screen *screen = ctx->screen;
336 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
337 struct radeon_winsys *ws = rctx->ws;
338 struct pipe_fence_handle *gfx_fence = NULL;
339 struct pipe_fence_handle *sdma_fence = NULL;
340 bool deferred_fence = false;
341 unsigned rflags = PIPE_FLUSH_ASYNC;
342
343 if (flags & PIPE_FLUSH_END_OF_FRAME)
344 rflags |= PIPE_FLUSH_END_OF_FRAME;
345
346 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
347 if (rctx->dma.cs)
348 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
349
350 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
351 if (fence)
352 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
353 if (!(flags & PIPE_FLUSH_DEFERRED))
354 ws->cs_sync_flush(rctx->gfx.cs);
355 } else {
356 /* Instead of flushing, create a deferred fence. Constraints:
357 * - The state tracker must allow a deferred flush.
358 * - The state tracker must request a fence.
359 * Thread safety in fence_finish must be ensured by the state tracker.
360 */
361 if (flags & PIPE_FLUSH_DEFERRED && fence) {
362 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
363 deferred_fence = true;
364 } else {
365 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
366 }
367 }
368
369 /* Both engines can signal out of order, so we need to keep both fences. */
370 if (fence) {
371 struct r600_multi_fence *multi_fence =
372 CALLOC_STRUCT(r600_multi_fence);
373 if (!multi_fence) {
374 ws->fence_reference(&sdma_fence, NULL);
375 ws->fence_reference(&gfx_fence, NULL);
376 goto finish;
377 }
378
379 multi_fence->reference.count = 1;
380 /* If both fences are NULL, fence_finish will always return true. */
381 multi_fence->gfx = gfx_fence;
382 multi_fence->sdma = sdma_fence;
383
384 if (deferred_fence) {
385 multi_fence->gfx_unflushed.ctx = rctx;
386 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
387 }
388
389 screen->fence_reference(screen, fence, NULL);
390 *fence = (struct pipe_fence_handle*)multi_fence;
391 }
392 finish:
393 if (!(flags & PIPE_FLUSH_DEFERRED)) {
394 if (rctx->dma.cs)
395 ws->cs_sync_flush(rctx->dma.cs);
396 ws->cs_sync_flush(rctx->gfx.cs);
397 }
398 }
399
400 static void r600_flush_dma_ring(void *ctx, unsigned flags,
401 struct pipe_fence_handle **fence)
402 {
403 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
404 struct radeon_cmdbuf *cs = rctx->dma.cs;
405 struct radeon_saved_cs saved;
406 bool check_vm =
407 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
408 rctx->check_vm_faults;
409
410 if (!radeon_emitted(cs, 0)) {
411 if (fence)
412 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
413 return;
414 }
415
416 if (check_vm)
417 radeon_save_cs(rctx->ws, cs, &saved, true);
418
419 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
420 if (fence)
421 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
422
423 if (check_vm) {
424 /* Use conservative timeout 800ms, after which we won't wait any
425 * longer and assume the GPU is hung.
426 */
427 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
428
429 rctx->check_vm_faults(rctx, &saved, RING_DMA);
430 radeon_clear_saved_cs(&saved);
431 }
432 }
433
434 /**
435 * Store a linearized copy of all chunks of \p cs together with the buffer
436 * list in \p saved.
437 */
438 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
439 struct radeon_saved_cs *saved, bool get_buffer_list)
440 {
441 uint32_t *buf;
442 unsigned i;
443
444 /* Save the IB chunks. */
445 saved->num_dw = cs->prev_dw + cs->current.cdw;
446 saved->ib = MALLOC(4 * saved->num_dw);
447 if (!saved->ib)
448 goto oom;
449
450 buf = saved->ib;
451 for (i = 0; i < cs->num_prev; ++i) {
452 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
453 buf += cs->prev[i].cdw;
454 }
455 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
456
457 if (!get_buffer_list)
458 return;
459
460 /* Save the buffer list. */
461 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
462 saved->bo_list = CALLOC(saved->bo_count,
463 sizeof(saved->bo_list[0]));
464 if (!saved->bo_list) {
465 FREE(saved->ib);
466 goto oom;
467 }
468 ws->cs_get_buffer_list(cs, saved->bo_list);
469
470 return;
471
472 oom:
473 fprintf(stderr, "%s: out of memory\n", __func__);
474 memset(saved, 0, sizeof(*saved));
475 }
476
477 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
478 {
479 FREE(saved->ib);
480 FREE(saved->bo_list);
481
482 memset(saved, 0, sizeof(*saved));
483 }
484
485 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
486 {
487 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
488
489 return rctx->ws->ctx_query_reset_status(rctx->ctx);
490 }
491
492 static void r600_set_debug_callback(struct pipe_context *ctx,
493 const struct pipe_debug_callback *cb)
494 {
495 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
496
497 if (cb)
498 rctx->debug = *cb;
499 else
500 memset(&rctx->debug, 0, sizeof(rctx->debug));
501 }
502
503 static void r600_set_device_reset_callback(struct pipe_context *ctx,
504 const struct pipe_device_reset_callback *cb)
505 {
506 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
507
508 if (cb)
509 rctx->device_reset_callback = *cb;
510 else
511 memset(&rctx->device_reset_callback, 0,
512 sizeof(rctx->device_reset_callback));
513 }
514
515 bool r600_check_device_reset(struct r600_common_context *rctx)
516 {
517 enum pipe_reset_status status;
518
519 if (!rctx->device_reset_callback.reset)
520 return false;
521
522 if (!rctx->b.get_device_reset_status)
523 return false;
524
525 status = rctx->b.get_device_reset_status(&rctx->b);
526 if (status == PIPE_NO_RESET)
527 return false;
528
529 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
530 return true;
531 }
532
533 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
534 struct pipe_resource *dst,
535 uint64_t offset, uint64_t size,
536 unsigned value)
537 {
538 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
539
540 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
541 }
542
543 static bool r600_resource_commit(struct pipe_context *pctx,
544 struct pipe_resource *resource,
545 unsigned level, struct pipe_box *box,
546 bool commit)
547 {
548 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
549 struct r600_resource *res = r600_resource(resource);
550
551 /*
552 * Since buffer commitment changes cannot be pipelined, we need to
553 * (a) flush any pending commands that refer to the buffer we're about
554 * to change, and
555 * (b) wait for threaded submit to finish, including those that were
556 * triggered by some other, earlier operation.
557 */
558 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
559 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
560 res->buf, RADEON_USAGE_READWRITE)) {
561 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
562 }
563 if (radeon_emitted(ctx->dma.cs, 0) &&
564 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
565 res->buf, RADEON_USAGE_READWRITE)) {
566 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
567 }
568
569 ctx->ws->cs_sync_flush(ctx->dma.cs);
570 ctx->ws->cs_sync_flush(ctx->gfx.cs);
571
572 assert(resource->target == PIPE_BUFFER);
573
574 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
575 }
576
577 bool r600_common_context_init(struct r600_common_context *rctx,
578 struct r600_common_screen *rscreen,
579 unsigned context_flags)
580 {
581 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
582 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
583
584 rctx->screen = rscreen;
585 rctx->ws = rscreen->ws;
586 rctx->family = rscreen->family;
587 rctx->chip_class = rscreen->chip_class;
588
589 rctx->b.invalidate_resource = r600_invalidate_resource;
590 rctx->b.resource_commit = r600_resource_commit;
591 rctx->b.transfer_map = u_transfer_map_vtbl;
592 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
593 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
594 rctx->b.texture_subdata = u_default_texture_subdata;
595 rctx->b.flush = r600_flush_from_st;
596 rctx->b.set_debug_callback = r600_set_debug_callback;
597 rctx->b.fence_server_sync = r600_fence_server_sync;
598 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
599
600 /* evergreen_compute.c has a special codepath for global buffers.
601 * Everything else can use the direct path.
602 */
603 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
604 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
605 rctx->b.buffer_subdata = u_default_buffer_subdata;
606 else
607 rctx->b.buffer_subdata = r600_buffer_subdata;
608
609 rctx->b.get_device_reset_status = r600_get_reset_status;
610 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
611
612 r600_init_context_texture_functions(rctx);
613 r600_init_viewport_functions(rctx);
614 r600_streamout_init(rctx);
615 r600_query_init(rctx);
616 cayman_init_msaa(&rctx->b);
617
618 rctx->allocator_zeroed_memory =
619 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
620 0, PIPE_USAGE_DEFAULT, 0, true);
621 if (!rctx->allocator_zeroed_memory)
622 return false;
623
624 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
625 0, PIPE_USAGE_STREAM, 0);
626 if (!rctx->b.stream_uploader)
627 return false;
628
629 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
630 0, PIPE_USAGE_DEFAULT, 0);
631 if (!rctx->b.const_uploader)
632 return false;
633
634 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
635 if (!rctx->ctx)
636 return false;
637
638 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
639 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
640 r600_flush_dma_ring,
641 rctx, false);
642 rctx->dma.flush = r600_flush_dma_ring;
643 }
644
645 return true;
646 }
647
648 void r600_common_context_cleanup(struct r600_common_context *rctx)
649 {
650 if (rctx->query_result_shader)
651 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
652
653 if (rctx->gfx.cs)
654 rctx->ws->cs_destroy(rctx->gfx.cs);
655 if (rctx->dma.cs)
656 rctx->ws->cs_destroy(rctx->dma.cs);
657 if (rctx->ctx)
658 rctx->ws->ctx_destroy(rctx->ctx);
659
660 if (rctx->b.stream_uploader)
661 u_upload_destroy(rctx->b.stream_uploader);
662 if (rctx->b.const_uploader)
663 u_upload_destroy(rctx->b.const_uploader);
664
665 slab_destroy_child(&rctx->pool_transfers);
666 slab_destroy_child(&rctx->pool_transfers_unsync);
667
668 if (rctx->allocator_zeroed_memory) {
669 u_suballocator_destroy(rctx->allocator_zeroed_memory);
670 }
671 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
672 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
673 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
674 }
675
676 /*
677 * pipe_screen
678 */
679
680 static const struct debug_named_value common_debug_options[] = {
681 /* logging */
682 { "tex", DBG_TEX, "Print texture info" },
683 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
684 { "compute", DBG_COMPUTE, "Print compute info" },
685 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
686 { "info", DBG_INFO, "Print driver information" },
687
688 /* shaders */
689 { "fs", DBG_FS, "Print fetch shaders" },
690 { "vs", DBG_VS, "Print vertex shaders" },
691 { "gs", DBG_GS, "Print geometry shaders" },
692 { "ps", DBG_PS, "Print pixel shaders" },
693 { "cs", DBG_CS, "Print compute shaders" },
694 { "tcs", DBG_TCS, "Print tessellation control shaders" },
695 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
696 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
697 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
698 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
699 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
700 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
701 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
702
703 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
704 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
705 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
706 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
707
708 /* features */
709 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
710 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
711 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
712 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
713 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
714 { "notiling", DBG_NO_TILING, "Disable tiling" },
715 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
716 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
717 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
718 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
719 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
720 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
721
722 DEBUG_NAMED_VALUE_END /* must be last */
723 };
724
725 static const char* r600_get_vendor(struct pipe_screen* pscreen)
726 {
727 return "X.Org";
728 }
729
730 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
731 {
732 return "AMD";
733 }
734
735 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
736 {
737 switch (rscreen->info.family) {
738 case CHIP_R600: return "AMD R600";
739 case CHIP_RV610: return "AMD RV610";
740 case CHIP_RV630: return "AMD RV630";
741 case CHIP_RV670: return "AMD RV670";
742 case CHIP_RV620: return "AMD RV620";
743 case CHIP_RV635: return "AMD RV635";
744 case CHIP_RS780: return "AMD RS780";
745 case CHIP_RS880: return "AMD RS880";
746 case CHIP_RV770: return "AMD RV770";
747 case CHIP_RV730: return "AMD RV730";
748 case CHIP_RV710: return "AMD RV710";
749 case CHIP_RV740: return "AMD RV740";
750 case CHIP_CEDAR: return "AMD CEDAR";
751 case CHIP_REDWOOD: return "AMD REDWOOD";
752 case CHIP_JUNIPER: return "AMD JUNIPER";
753 case CHIP_CYPRESS: return "AMD CYPRESS";
754 case CHIP_HEMLOCK: return "AMD HEMLOCK";
755 case CHIP_PALM: return "AMD PALM";
756 case CHIP_SUMO: return "AMD SUMO";
757 case CHIP_SUMO2: return "AMD SUMO2";
758 case CHIP_BARTS: return "AMD BARTS";
759 case CHIP_TURKS: return "AMD TURKS";
760 case CHIP_CAICOS: return "AMD CAICOS";
761 case CHIP_CAYMAN: return "AMD CAYMAN";
762 case CHIP_ARUBA: return "AMD ARUBA";
763 default: return "AMD unknown";
764 }
765 }
766
767 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
768 {
769 /* Don't use the cache if shader dumping is enabled. */
770 if (rscreen->debug_flags & DBG_ALL_SHADERS)
771 return;
772
773 struct mesa_sha1 ctx;
774 unsigned char sha1[20];
775 char cache_id[20 * 2 + 1];
776
777 _mesa_sha1_init(&ctx);
778 if (!disk_cache_get_function_identifier(r600_disk_cache_create,
779 &ctx))
780 return;
781
782 _mesa_sha1_final(&ctx, sha1);
783 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
784
785 /* These flags affect shader compilation. */
786 uint64_t shader_debug_flags =
787 rscreen->debug_flags &
788 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
789 DBG_UNSAFE_MATH);
790
791 rscreen->disk_shader_cache =
792 disk_cache_create(r600_get_family_name(rscreen),
793 cache_id,
794 shader_debug_flags);
795 }
796
797 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
798 {
799 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
800 return rscreen->disk_shader_cache;
801 }
802
803 static const char* r600_get_name(struct pipe_screen* pscreen)
804 {
805 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
806
807 return rscreen->renderer_string;
808 }
809
810 static float r600_get_paramf(struct pipe_screen* pscreen,
811 enum pipe_capf param)
812 {
813 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
814
815 switch (param) {
816 case PIPE_CAPF_MAX_LINE_WIDTH:
817 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
818 case PIPE_CAPF_MAX_POINT_WIDTH:
819 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
820 if (rscreen->family >= CHIP_CEDAR)
821 return 16384.0f;
822 else
823 return 8192.0f;
824 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
825 return 16.0f;
826 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
827 return 16.0f;
828 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
829 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
830 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
831 return 0.0f;
832 }
833 return 0.0f;
834 }
835
836 static int r600_get_video_param(struct pipe_screen *screen,
837 enum pipe_video_profile profile,
838 enum pipe_video_entrypoint entrypoint,
839 enum pipe_video_cap param)
840 {
841 switch (param) {
842 case PIPE_VIDEO_CAP_SUPPORTED:
843 return vl_profile_supported(screen, profile, entrypoint);
844 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
845 return 1;
846 case PIPE_VIDEO_CAP_MAX_WIDTH:
847 case PIPE_VIDEO_CAP_MAX_HEIGHT:
848 return vl_video_buffer_max_size(screen);
849 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
850 return PIPE_FORMAT_NV12;
851 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
852 return false;
853 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
854 return false;
855 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
856 return true;
857 case PIPE_VIDEO_CAP_MAX_LEVEL:
858 return vl_level_supported(screen, profile);
859 default:
860 return 0;
861 }
862 }
863
864 const char *r600_get_llvm_processor_name(enum radeon_family family)
865 {
866 switch (family) {
867 case CHIP_R600:
868 case CHIP_RV630:
869 case CHIP_RV635:
870 case CHIP_RV670:
871 return "r600";
872 case CHIP_RV610:
873 case CHIP_RV620:
874 case CHIP_RS780:
875 case CHIP_RS880:
876 return "rs880";
877 case CHIP_RV710:
878 return "rv710";
879 case CHIP_RV730:
880 return "rv730";
881 case CHIP_RV740:
882 case CHIP_RV770:
883 return "rv770";
884 case CHIP_PALM:
885 case CHIP_CEDAR:
886 return "cedar";
887 case CHIP_SUMO:
888 case CHIP_SUMO2:
889 return "sumo";
890 case CHIP_REDWOOD:
891 return "redwood";
892 case CHIP_JUNIPER:
893 return "juniper";
894 case CHIP_HEMLOCK:
895 case CHIP_CYPRESS:
896 return "cypress";
897 case CHIP_BARTS:
898 return "barts";
899 case CHIP_TURKS:
900 return "turks";
901 case CHIP_CAICOS:
902 return "caicos";
903 case CHIP_CAYMAN:
904 case CHIP_ARUBA:
905 return "cayman";
906
907 default:
908 return "";
909 }
910 }
911
912 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
913 enum pipe_shader_ir ir_type)
914 {
915 if (ir_type != PIPE_SHADER_IR_TGSI)
916 return 256;
917 if (screen->chip_class >= EVERGREEN)
918 return 1024;
919 return 256;
920 }
921
922 static int r600_get_compute_param(struct pipe_screen *screen,
923 enum pipe_shader_ir ir_type,
924 enum pipe_compute_cap param,
925 void *ret)
926 {
927 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
928
929 //TODO: select these params by asic
930 switch (param) {
931 case PIPE_COMPUTE_CAP_IR_TARGET: {
932 const char *gpu;
933 const char *triple = "r600--";
934 gpu = r600_get_llvm_processor_name(rscreen->family);
935 if (ret) {
936 sprintf(ret, "%s-%s", gpu, triple);
937 }
938 /* +2 for dash and terminating NIL byte */
939 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
940 }
941 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
942 if (ret) {
943 uint64_t *grid_dimension = ret;
944 grid_dimension[0] = 3;
945 }
946 return 1 * sizeof(uint64_t);
947
948 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
949 if (ret) {
950 uint64_t *grid_size = ret;
951 grid_size[0] = 65535;
952 grid_size[1] = 65535;
953 grid_size[2] = 65535;
954 }
955 return 3 * sizeof(uint64_t) ;
956
957 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
958 if (ret) {
959 uint64_t *block_size = ret;
960 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
961 block_size[0] = threads_per_block;
962 block_size[1] = threads_per_block;
963 block_size[2] = threads_per_block;
964 }
965 return 3 * sizeof(uint64_t);
966
967 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
968 if (ret) {
969 uint64_t *max_threads_per_block = ret;
970 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
971 }
972 return sizeof(uint64_t);
973 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
974 if (ret) {
975 uint32_t *address_bits = ret;
976 address_bits[0] = 32;
977 }
978 return 1 * sizeof(uint32_t);
979
980 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
981 if (ret) {
982 uint64_t *max_global_size = ret;
983 uint64_t max_mem_alloc_size;
984
985 r600_get_compute_param(screen, ir_type,
986 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
987 &max_mem_alloc_size);
988
989 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
990 * 1/4 of the MAX_GLOBAL_SIZE. Since the
991 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
992 * make sure we never report more than
993 * 4 * MAX_MEM_ALLOC_SIZE.
994 */
995 *max_global_size = MIN2(4 * max_mem_alloc_size,
996 MAX2(rscreen->info.gart_size,
997 rscreen->info.vram_size));
998 }
999 return sizeof(uint64_t);
1000
1001 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1002 if (ret) {
1003 uint64_t *max_local_size = ret;
1004 /* Value reported by the closed source driver. */
1005 *max_local_size = 32768;
1006 }
1007 return sizeof(uint64_t);
1008
1009 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1010 if (ret) {
1011 uint64_t *max_input_size = ret;
1012 /* Value reported by the closed source driver. */
1013 *max_input_size = 1024;
1014 }
1015 return sizeof(uint64_t);
1016
1017 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1018 if (ret) {
1019 uint64_t *max_mem_alloc_size = ret;
1020
1021 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1022 }
1023 return sizeof(uint64_t);
1024
1025 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1026 if (ret) {
1027 uint32_t *max_clock_frequency = ret;
1028 *max_clock_frequency = rscreen->info.max_shader_clock;
1029 }
1030 return sizeof(uint32_t);
1031
1032 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1033 if (ret) {
1034 uint32_t *max_compute_units = ret;
1035 *max_compute_units = rscreen->info.num_good_compute_units;
1036 }
1037 return sizeof(uint32_t);
1038
1039 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1040 if (ret) {
1041 uint32_t *images_supported = ret;
1042 *images_supported = 0;
1043 }
1044 return sizeof(uint32_t);
1045 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1046 break; /* unused */
1047 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1048 if (ret) {
1049 uint32_t *subgroup_size = ret;
1050 *subgroup_size = r600_wavefront_size(rscreen->family);
1051 }
1052 return sizeof(uint32_t);
1053 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1054 if (ret) {
1055 uint64_t *max_variable_threads_per_block = ret;
1056 *max_variable_threads_per_block = 0;
1057 }
1058 return sizeof(uint64_t);
1059 }
1060
1061 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1062 return 0;
1063 }
1064
1065 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1066 {
1067 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1068
1069 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1070 rscreen->info.clock_crystal_freq;
1071 }
1072
1073 static void r600_fence_reference(struct pipe_screen *screen,
1074 struct pipe_fence_handle **dst,
1075 struct pipe_fence_handle *src)
1076 {
1077 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1078 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1079 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1080
1081 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1082 ws->fence_reference(&(*rdst)->gfx, NULL);
1083 ws->fence_reference(&(*rdst)->sdma, NULL);
1084 FREE(*rdst);
1085 }
1086 *rdst = rsrc;
1087 }
1088
1089 static bool r600_fence_finish(struct pipe_screen *screen,
1090 struct pipe_context *ctx,
1091 struct pipe_fence_handle *fence,
1092 uint64_t timeout)
1093 {
1094 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1095 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1096 struct r600_common_context *rctx;
1097 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1098
1099 ctx = threaded_context_unwrap_sync(ctx);
1100 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1101
1102 if (rfence->sdma) {
1103 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1104 return false;
1105
1106 /* Recompute the timeout after waiting. */
1107 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1108 int64_t time = os_time_get_nano();
1109 timeout = abs_timeout > time ? abs_timeout - time : 0;
1110 }
1111 }
1112
1113 if (!rfence->gfx)
1114 return true;
1115
1116 /* Flush the gfx IB if it hasn't been flushed yet. */
1117 if (rctx &&
1118 rfence->gfx_unflushed.ctx == rctx &&
1119 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1120 rctx->gfx.flush(rctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
1121 rfence->gfx_unflushed.ctx = NULL;
1122
1123 if (!timeout)
1124 return false;
1125
1126 /* Recompute the timeout after all that. */
1127 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1128 int64_t time = os_time_get_nano();
1129 timeout = abs_timeout > time ? abs_timeout - time : 0;
1130 }
1131 }
1132
1133 return rws->fence_wait(rws, rfence->gfx, timeout);
1134 }
1135
1136 static void r600_query_memory_info(struct pipe_screen *screen,
1137 struct pipe_memory_info *info)
1138 {
1139 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1140 struct radeon_winsys *ws = rscreen->ws;
1141 unsigned vram_usage, gtt_usage;
1142
1143 info->total_device_memory = rscreen->info.vram_size / 1024;
1144 info->total_staging_memory = rscreen->info.gart_size / 1024;
1145
1146 /* The real TTM memory usage is somewhat random, because:
1147 *
1148 * 1) TTM delays freeing memory, because it can only free it after
1149 * fences expire.
1150 *
1151 * 2) The memory usage can be really low if big VRAM evictions are
1152 * taking place, but the real usage is well above the size of VRAM.
1153 *
1154 * Instead, return statistics of this process.
1155 */
1156 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1157 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1158
1159 info->avail_device_memory =
1160 vram_usage <= info->total_device_memory ?
1161 info->total_device_memory - vram_usage : 0;
1162 info->avail_staging_memory =
1163 gtt_usage <= info->total_staging_memory ?
1164 info->total_staging_memory - gtt_usage : 0;
1165
1166 info->device_memory_evicted =
1167 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1168
1169 /* Just return the number of evicted 64KB pages. */
1170 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1171 }
1172
1173 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1174 const struct pipe_resource *templ)
1175 {
1176 if (templ->target == PIPE_BUFFER) {
1177 return r600_buffer_create(screen, templ, 256);
1178 } else {
1179 return r600_texture_create(screen, templ);
1180 }
1181 }
1182
1183 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1184 struct radeon_winsys *ws)
1185 {
1186 char family_name[32] = {}, kernel_version[128] = {};
1187 struct utsname uname_data;
1188 const char *chip_name;
1189
1190 ws->query_info(ws, &rscreen->info);
1191 rscreen->ws = ws;
1192
1193 chip_name = r600_get_family_name(rscreen);
1194
1195 if (uname(&uname_data) == 0)
1196 snprintf(kernel_version, sizeof(kernel_version),
1197 " / %s", uname_data.release);
1198
1199 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1200 "%s (%sDRM %i.%i.%i%s"
1201 #ifdef LLVM_AVAILABLE
1202 ", LLVM " MESA_LLVM_VERSION_STRING
1203 #endif
1204 ")",
1205 chip_name, family_name, rscreen->info.drm_major,
1206 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1207 kernel_version);
1208
1209 rscreen->b.get_name = r600_get_name;
1210 rscreen->b.get_vendor = r600_get_vendor;
1211 rscreen->b.get_device_vendor = r600_get_device_vendor;
1212 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1213 rscreen->b.get_compute_param = r600_get_compute_param;
1214 rscreen->b.get_paramf = r600_get_paramf;
1215 rscreen->b.get_timestamp = r600_get_timestamp;
1216 rscreen->b.fence_finish = r600_fence_finish;
1217 rscreen->b.fence_reference = r600_fence_reference;
1218 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1219 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1220 rscreen->b.query_memory_info = r600_query_memory_info;
1221
1222 if (rscreen->info.has_hw_decode) {
1223 rscreen->b.get_video_param = rvid_get_video_param;
1224 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1225 } else {
1226 rscreen->b.get_video_param = r600_get_video_param;
1227 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1228 }
1229
1230 r600_init_screen_texture_functions(rscreen);
1231 r600_init_screen_query_functions(rscreen);
1232
1233 rscreen->family = rscreen->info.family;
1234 rscreen->chip_class = rscreen->info.chip_class;
1235 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1236
1237 r600_disk_cache_create(rscreen);
1238
1239 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1240
1241 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1242 if (rscreen->force_aniso >= 0) {
1243 printf("radeon: Forcing anisotropy filter to %ix\n",
1244 /* round down to a power of two */
1245 1 << util_logbase2(rscreen->force_aniso));
1246 }
1247
1248 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1249 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1250
1251 if (rscreen->debug_flags & DBG_INFO) {
1252 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1253 rscreen->info.pci_domain, rscreen->info.pci_bus,
1254 rscreen->info.pci_dev, rscreen->info.pci_func);
1255 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1256 printf("family = %i (%s)\n", rscreen->info.family,
1257 r600_get_family_name(rscreen));
1258 printf("chip_class = %i\n", rscreen->info.chip_class);
1259 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1260 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1261 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1262 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1263 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1264 printf("max_alloc_size = %i MB\n",
1265 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1266 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1267 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1268 printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory);
1269 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1270 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1271 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1272 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1273 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1274 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1275 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1276 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1277 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1278 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1279 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1280 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1281 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1282 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1283 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1284 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1285
1286 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1287 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1288 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1289 printf("max_se = %i\n", rscreen->info.max_se);
1290 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1291
1292 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1293 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1294 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1295 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1296 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1297 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1298 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1299 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1300 }
1301 return true;
1302 }
1303
1304 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1305 {
1306 r600_perfcounters_destroy(rscreen);
1307 r600_gpu_load_kill_thread(rscreen);
1308
1309 mtx_destroy(&rscreen->gpu_load_mutex);
1310 mtx_destroy(&rscreen->aux_context_lock);
1311 rscreen->aux_context->destroy(rscreen->aux_context);
1312
1313 slab_destroy_parent(&rscreen->pool_transfers);
1314
1315 disk_cache_destroy(rscreen->disk_shader_cache);
1316 rscreen->ws->destroy(rscreen->ws);
1317 FREE(rscreen);
1318 }
1319
1320 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1321 unsigned processor)
1322 {
1323 return rscreen->debug_flags & (1 << processor);
1324 }
1325
1326 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1327 {
1328 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1329 r600_can_dump_shader(rscreen, processor);
1330 }
1331
1332 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1333 uint64_t offset, uint64_t size, unsigned value)
1334 {
1335 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1336
1337 mtx_lock(&rscreen->aux_context_lock);
1338 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1339 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1340 mtx_unlock(&rscreen->aux_context_lock);
1341 }