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r600g: Update some comments for Evergreen.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 r600_pipe_state_add_reg(rstate,
186 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
187 0xFFFFFFFF, NULL);
188 }
189
190 int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
191 {
192 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
193 struct r600_shader *rshader = &shader->shader;
194 void *ptr;
195
196 /* copy new shader */
197 if (shader->bo == NULL) {
198 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
199 if (shader->bo == NULL) {
200 return -ENOMEM;
201 }
202 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
203 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
204 r600_bo_unmap(rctx->radeon, shader->bo);
205 }
206 /* build state */
207 switch (rshader->processor_type) {
208 case TGSI_PROCESSOR_VERTEX:
209 if (rshader->family >= CHIP_CEDAR) {
210 evergreen_pipe_shader_vs(ctx, shader);
211 } else {
212 r600_pipe_shader_vs(ctx, shader);
213 }
214 break;
215 case TGSI_PROCESSOR_FRAGMENT:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_ps(ctx, shader);
218 } else {
219 r600_pipe_shader_ps(ctx, shader);
220 }
221 break;
222 default:
223 return -EINVAL;
224 }
225 return 0;
226 }
227
228 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
229 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
230 {
231 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
232 int r;
233
234 //fprintf(stderr, "--------------------------------------------------------------\n");
235 //tgsi_dump(tokens, 0);
236 shader->shader.family = r600_get_family(rctx->radeon);
237 r = r600_shader_from_tgsi(tokens, &shader->shader);
238 if (r) {
239 R600_ERR("translation from TGSI failed !\n");
240 return r;
241 }
242 r = r600_bc_build(&shader->shader.bc);
243 if (r) {
244 R600_ERR("building bytecode failed !\n");
245 return r;
246 }
247 //r600_bc_dump(&shader->shader.bc);
248 //fprintf(stderr, "______________________________________________________________\n");
249 return r600_pipe_shader(ctx, shader);
250 }
251
252 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
253 {
254 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
255
256 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
257 r600_bc_clear(&shader->shader.bc);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_ctx {
266 struct tgsi_shader_info info;
267 struct tgsi_parse_context parse;
268 const struct tgsi_token *tokens;
269 unsigned type;
270 unsigned file_offset[TGSI_FILE_COUNT];
271 unsigned temp_reg;
272 struct r600_shader_tgsi_instruction *inst_info;
273 struct r600_bc *bc;
274 struct r600_shader *shader;
275 u32 value[4];
276 u32 *literals;
277 u32 nliterals;
278 u32 max_driver_temp_used;
279 /* needed for evergreen interpolation */
280 boolean input_centroid;
281 boolean input_linear;
282 boolean input_perspective;
283 int num_interp_gpr;
284 };
285
286 struct r600_shader_tgsi_instruction {
287 unsigned tgsi_opcode;
288 unsigned is_op3;
289 unsigned r600_opcode;
290 int (*process)(struct r600_shader_ctx *ctx);
291 };
292
293 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
294 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
295
296 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
297 {
298 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
299 int j;
300
301 if (i->Instruction.NumDstRegs > 1) {
302 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
303 return -EINVAL;
304 }
305 if (i->Instruction.Predicate) {
306 R600_ERR("predicate unsupported\n");
307 return -EINVAL;
308 }
309 #if 0
310 if (i->Instruction.Label) {
311 R600_ERR("label unsupported\n");
312 return -EINVAL;
313 }
314 #endif
315 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
316 if (i->Src[j].Register.Dimension) {
317 R600_ERR("unsupported src %d (dimension %d)\n", j,
318 i->Src[j].Register.Dimension);
319 return -EINVAL;
320 }
321 }
322 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
323 if (i->Dst[j].Register.Dimension) {
324 R600_ERR("unsupported dst (dimension)\n");
325 return -EINVAL;
326 }
327 }
328 return 0;
329 }
330
331 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
332 {
333 int i, r;
334 struct r600_bc_alu alu;
335 int gpr = 0, base_chan = 0;
336 int ij_index = 0;
337
338 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
339 ij_index = 0;
340 if (ctx->shader->input[input].centroid)
341 ij_index++;
342 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
343 ij_index = 0;
344 /* if we have perspective add one */
345 if (ctx->input_perspective) {
346 ij_index++;
347 /* if we have perspective centroid */
348 if (ctx->input_centroid)
349 ij_index++;
350 }
351 if (ctx->shader->input[input].centroid)
352 ij_index++;
353 }
354
355 /* work out gpr and base_chan from index */
356 gpr = ij_index / 2;
357 base_chan = (2 * (ij_index % 2)) + 1;
358
359 for (i = 0; i < 8; i++) {
360 memset(&alu, 0, sizeof(struct r600_bc_alu));
361
362 if (i < 4)
363 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
364 else
365 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
366
367 if ((i > 1) && (i < 6)) {
368 alu.dst.sel = ctx->shader->input[input].gpr;
369 alu.dst.write = 1;
370 }
371
372 alu.dst.chan = i % 4;
373
374 alu.src[0].sel = gpr;
375 alu.src[0].chan = (base_chan - (i % 2));
376
377 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
378
379 alu.bank_swizzle_force = SQ_ALU_VEC_210;
380 if ((i % 4) == 3)
381 alu.last = 1;
382 r = r600_bc_add_alu(ctx->bc, &alu);
383 if (r)
384 return r;
385 }
386 return 0;
387 }
388
389
390 static int tgsi_declaration(struct r600_shader_ctx *ctx)
391 {
392 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
393 unsigned i;
394
395 switch (d->Declaration.File) {
396 case TGSI_FILE_INPUT:
397 i = ctx->shader->ninput++;
398 ctx->shader->input[i].name = d->Semantic.Name;
399 ctx->shader->input[i].sid = d->Semantic.Index;
400 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
401 ctx->shader->input[i].centroid = d->Declaration.Centroid;
402 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
403 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
404 /* turn input into interpolate on EG */
405 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
406 if (ctx->shader->input[i].interpolate > 0) {
407 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
408 evergreen_interp_alu(ctx, i);
409 }
410 }
411 }
412 break;
413 case TGSI_FILE_OUTPUT:
414 i = ctx->shader->noutput++;
415 ctx->shader->output[i].name = d->Semantic.Name;
416 ctx->shader->output[i].sid = d->Semantic.Index;
417 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
418 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
419 break;
420 case TGSI_FILE_CONSTANT:
421 case TGSI_FILE_TEMPORARY:
422 case TGSI_FILE_SAMPLER:
423 case TGSI_FILE_ADDRESS:
424 break;
425 default:
426 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
427 return -EINVAL;
428 }
429 return 0;
430 }
431
432 static int r600_get_temp(struct r600_shader_ctx *ctx)
433 {
434 return ctx->temp_reg + ctx->max_driver_temp_used++;
435 }
436
437 /*
438 * for evergreen we need to scan the shader to find the number of GPRs we need to
439 * reserve for interpolation.
440 *
441 * we need to know if we are going to emit
442 * any centroid inputs
443 * if perspective and linear are required
444 */
445 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
446 {
447 int i;
448 int num_baryc;
449
450 ctx->input_linear = FALSE;
451 ctx->input_perspective = FALSE;
452 ctx->input_centroid = FALSE;
453 ctx->num_interp_gpr = 1;
454
455 /* any centroid inputs */
456 for (i = 0; i < ctx->info.num_inputs; i++) {
457 /* skip position/face */
458 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
459 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
460 continue;
461 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
462 ctx->input_linear = TRUE;
463 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
464 ctx->input_perspective = TRUE;
465 if (ctx->info.input_centroid[i])
466 ctx->input_centroid = TRUE;
467 }
468
469 num_baryc = 0;
470 /* ignoring sample for now */
471 if (ctx->input_perspective)
472 num_baryc++;
473 if (ctx->input_linear)
474 num_baryc++;
475 if (ctx->input_centroid)
476 num_baryc *= 2;
477
478 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
479
480 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
481 return ctx->num_interp_gpr;
482 }
483
484 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
485 {
486 struct tgsi_full_immediate *immediate;
487 struct r600_shader_ctx ctx;
488 struct r600_bc_output output[32];
489 unsigned output_done, noutput;
490 unsigned opcode;
491 int i, r = 0, pos0;
492
493 ctx.bc = &shader->bc;
494 ctx.shader = shader;
495 r = r600_bc_init(ctx.bc, shader->family);
496 if (r)
497 return r;
498 ctx.tokens = tokens;
499 tgsi_scan_shader(tokens, &ctx.info);
500 tgsi_parse_init(&ctx.parse, tokens);
501 ctx.type = ctx.parse.FullHeader.Processor.Processor;
502 shader->processor_type = ctx.type;
503 ctx.bc->type = shader->processor_type;
504
505 /* register allocations */
506 /* Values [0,127] correspond to GPR[0..127].
507 * Values [128,159] correspond to constant buffer bank 0
508 * Values [160,191] correspond to constant buffer bank 1
509 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
510 * Values [256,287] correspond to constant buffer bank 2 (EG)
511 * Values [288,319] correspond to constant buffer bank 3 (EG)
512 * Other special values are shown in the list below.
513 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
514 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
515 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
516 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
517 * 248 SQ_ALU_SRC_0: special constant 0.0.
518 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
519 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
520 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
521 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
522 * 253 SQ_ALU_SRC_LITERAL: literal constant.
523 * 254 SQ_ALU_SRC_PV: previous vector result.
524 * 255 SQ_ALU_SRC_PS: previous scalar result.
525 */
526 for (i = 0; i < TGSI_FILE_COUNT; i++) {
527 ctx.file_offset[i] = 0;
528 }
529 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
530 ctx.file_offset[TGSI_FILE_INPUT] = 1;
531 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
532 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
533 } else {
534 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
535 }
536 }
537 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
538 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
539 }
540 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
541 ctx.info.file_count[TGSI_FILE_INPUT];
542 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
543 ctx.info.file_count[TGSI_FILE_OUTPUT];
544
545 /* Outside the GPR range. This will be translated to one of the
546 * kcache banks later. */
547 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
548
549 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
550 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
551 ctx.info.file_count[TGSI_FILE_TEMPORARY];
552
553 ctx.nliterals = 0;
554 ctx.literals = NULL;
555
556 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
557 tgsi_parse_token(&ctx.parse);
558 switch (ctx.parse.FullToken.Token.Type) {
559 case TGSI_TOKEN_TYPE_IMMEDIATE:
560 immediate = &ctx.parse.FullToken.FullImmediate;
561 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
562 if(ctx.literals == NULL) {
563 r = -ENOMEM;
564 goto out_err;
565 }
566 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
567 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
568 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
569 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
570 ctx.nliterals++;
571 break;
572 case TGSI_TOKEN_TYPE_DECLARATION:
573 r = tgsi_declaration(&ctx);
574 if (r)
575 goto out_err;
576 break;
577 case TGSI_TOKEN_TYPE_INSTRUCTION:
578 r = tgsi_is_supported(&ctx);
579 if (r)
580 goto out_err;
581 ctx.max_driver_temp_used = 0;
582 /* reserve first tmp for everyone */
583 r600_get_temp(&ctx);
584 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
585 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
586 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
587 else
588 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
589 r = ctx.inst_info->process(&ctx);
590 if (r)
591 goto out_err;
592 r = r600_bc_add_literal(ctx.bc, ctx.value);
593 if (r)
594 goto out_err;
595 break;
596 case TGSI_TOKEN_TYPE_PROPERTY:
597 break;
598 default:
599 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
600 r = -EINVAL;
601 goto out_err;
602 }
603 }
604 /* export output */
605 noutput = shader->noutput;
606 for (i = 0, pos0 = 0; i < noutput; i++) {
607 memset(&output[i], 0, sizeof(struct r600_bc_output));
608 output[i].gpr = shader->output[i].gpr;
609 output[i].elem_size = 3;
610 output[i].swizzle_x = 0;
611 output[i].swizzle_y = 1;
612 output[i].swizzle_z = 2;
613 output[i].swizzle_w = 3;
614 output[i].barrier = 1;
615 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
616 output[i].array_base = i - pos0;
617 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
618 switch (ctx.type) {
619 case TGSI_PROCESSOR_VERTEX:
620 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
621 output[i].array_base = 60;
622 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
623 /* position doesn't count in array_base */
624 pos0++;
625 }
626 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
627 output[i].array_base = 61;
628 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
629 /* position doesn't count in array_base */
630 pos0++;
631 }
632 break;
633 case TGSI_PROCESSOR_FRAGMENT:
634 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
635 output[i].array_base = shader->output[i].sid;
636 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
637 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
638 output[i].array_base = 61;
639 output[i].swizzle_x = 2;
640 output[i].swizzle_y = 7;
641 output[i].swizzle_z = output[i].swizzle_w = 7;
642 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
643 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
644 output[i].array_base = 61;
645 output[i].swizzle_x = 7;
646 output[i].swizzle_y = 1;
647 output[i].swizzle_z = output[i].swizzle_w = 7;
648 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
649 } else {
650 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
651 r = -EINVAL;
652 goto out_err;
653 }
654 break;
655 default:
656 R600_ERR("unsupported processor type %d\n", ctx.type);
657 r = -EINVAL;
658 goto out_err;
659 }
660 }
661 /* add fake param output for vertex shader if no param is exported */
662 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
663 for (i = 0, pos0 = 0; i < noutput; i++) {
664 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
665 pos0 = 1;
666 break;
667 }
668 }
669 if (!pos0) {
670 memset(&output[i], 0, sizeof(struct r600_bc_output));
671 output[i].gpr = 0;
672 output[i].elem_size = 3;
673 output[i].swizzle_x = 0;
674 output[i].swizzle_y = 1;
675 output[i].swizzle_z = 2;
676 output[i].swizzle_w = 3;
677 output[i].barrier = 1;
678 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
679 output[i].array_base = 0;
680 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
681 noutput++;
682 }
683 }
684 /* add fake pixel export */
685 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
686 memset(&output[0], 0, sizeof(struct r600_bc_output));
687 output[0].gpr = 0;
688 output[0].elem_size = 3;
689 output[0].swizzle_x = 7;
690 output[0].swizzle_y = 7;
691 output[0].swizzle_z = 7;
692 output[0].swizzle_w = 7;
693 output[0].barrier = 1;
694 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
695 output[0].array_base = 0;
696 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
697 noutput++;
698 }
699 /* set export done on last export of each type */
700 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
701 if (i == (noutput - 1)) {
702 output[i].end_of_program = 1;
703 }
704 if (!(output_done & (1 << output[i].type))) {
705 output_done |= (1 << output[i].type);
706 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
707 }
708 }
709 /* add output to bytecode */
710 for (i = 0; i < noutput; i++) {
711 r = r600_bc_add_output(ctx.bc, &output[i]);
712 if (r)
713 goto out_err;
714 }
715 free(ctx.literals);
716 tgsi_parse_free(&ctx.parse);
717 return 0;
718 out_err:
719 free(ctx.literals);
720 tgsi_parse_free(&ctx.parse);
721 return r;
722 }
723
724 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
725 {
726 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
727 return -EINVAL;
728 }
729
730 static int tgsi_end(struct r600_shader_ctx *ctx)
731 {
732 return 0;
733 }
734
735 static int tgsi_src(struct r600_shader_ctx *ctx,
736 const struct tgsi_full_src_register *tgsi_src,
737 struct r600_bc_alu_src *r600_src)
738 {
739 int index;
740 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
741 r600_src->sel = tgsi_src->Register.Index;
742 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
743 r600_src->sel = 0;
744 index = tgsi_src->Register.Index;
745 ctx->value[0] = ctx->literals[index * 4 + 0];
746 ctx->value[1] = ctx->literals[index * 4 + 1];
747 ctx->value[2] = ctx->literals[index * 4 + 2];
748 ctx->value[3] = ctx->literals[index * 4 + 3];
749 }
750 if (tgsi_src->Register.Indirect)
751 r600_src->rel = V_SQ_REL_RELATIVE;
752 r600_src->neg = tgsi_src->Register.Negate;
753 r600_src->abs = tgsi_src->Register.Absolute;
754 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
755 return 0;
756 }
757
758 static int tgsi_dst(struct r600_shader_ctx *ctx,
759 const struct tgsi_full_dst_register *tgsi_dst,
760 unsigned swizzle,
761 struct r600_bc_alu_dst *r600_dst)
762 {
763 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
764
765 r600_dst->sel = tgsi_dst->Register.Index;
766 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
767 r600_dst->chan = swizzle;
768 r600_dst->write = 1;
769 if (tgsi_dst->Register.Indirect)
770 r600_dst->rel = V_SQ_REL_RELATIVE;
771 if (inst->Instruction.Saturate) {
772 r600_dst->clamp = 1;
773 }
774 return 0;
775 }
776
777 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
778 {
779 switch (swizzle) {
780 case 0:
781 return tgsi_src->Register.SwizzleX;
782 case 1:
783 return tgsi_src->Register.SwizzleY;
784 case 2:
785 return tgsi_src->Register.SwizzleZ;
786 case 3:
787 return tgsi_src->Register.SwizzleW;
788 default:
789 return 0;
790 }
791 }
792
793 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
794 {
795 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
796 struct r600_bc_alu alu;
797 int i, j, k, nconst, r;
798
799 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
800 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
801 nconst++;
802 }
803 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
804 if (r) {
805 return r;
806 }
807 }
808 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
809 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
810 int treg = r600_get_temp(ctx);
811 for (k = 0; k < 4; k++) {
812 memset(&alu, 0, sizeof(struct r600_bc_alu));
813 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
814 alu.src[0].sel = r600_src[i].sel;
815 alu.src[0].chan = k;
816 alu.src[0].rel = r600_src[i].rel;
817 alu.dst.sel = treg;
818 alu.dst.chan = k;
819 alu.dst.write = 1;
820 if (k == 3)
821 alu.last = 1;
822 r = r600_bc_add_alu(ctx->bc, &alu);
823 if (r)
824 return r;
825 }
826 r600_src[i].sel = treg;
827 r600_src[i].rel =0;
828 j--;
829 }
830 }
831 return 0;
832 }
833
834 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
835 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
836 {
837 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
838 struct r600_bc_alu alu;
839 int i, j, k, nliteral, r;
840
841 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
842 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
843 nliteral++;
844 }
845 }
846 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
847 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
848 int treg = r600_get_temp(ctx);
849 for (k = 0; k < 4; k++) {
850 memset(&alu, 0, sizeof(struct r600_bc_alu));
851 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
852 alu.src[0].sel = r600_src[i].sel;
853 alu.src[0].chan = k;
854 alu.dst.sel = treg;
855 alu.dst.chan = k;
856 alu.dst.write = 1;
857 if (k == 3)
858 alu.last = 1;
859 r = r600_bc_add_alu(ctx->bc, &alu);
860 if (r)
861 return r;
862 }
863 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
864 if (r)
865 return r;
866 r600_src[i].sel = treg;
867 j--;
868 }
869 }
870 return 0;
871 }
872
873 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
874 {
875 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
876 struct r600_bc_alu_src r600_src[3];
877 struct r600_bc_alu alu;
878 int i, j, r;
879 int lasti = 0;
880
881 for (i = 0; i < 4; i++) {
882 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
883 lasti = i;
884 }
885 }
886
887 r = tgsi_split_constant(ctx, r600_src);
888 if (r)
889 return r;
890 r = tgsi_split_literal_constant(ctx, r600_src);
891 if (r)
892 return r;
893 for (i = 0; i < lasti + 1; i++) {
894 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
895 continue;
896
897 memset(&alu, 0, sizeof(struct r600_bc_alu));
898 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
899 if (r)
900 return r;
901
902 alu.inst = ctx->inst_info->r600_opcode;
903 if (!swap) {
904 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
905 alu.src[j] = r600_src[j];
906 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
907 }
908 } else {
909 alu.src[0] = r600_src[1];
910 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
911
912 alu.src[1] = r600_src[0];
913 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
914 }
915 /* handle some special cases */
916 switch (ctx->inst_info->tgsi_opcode) {
917 case TGSI_OPCODE_SUB:
918 alu.src[1].neg = 1;
919 break;
920 case TGSI_OPCODE_ABS:
921 alu.src[0].abs = 1;
922 break;
923 default:
924 break;
925 }
926 if (i == lasti) {
927 alu.last = 1;
928 }
929 r = r600_bc_add_alu(ctx->bc, &alu);
930 if (r)
931 return r;
932 }
933 return 0;
934 }
935
936 static int tgsi_op2(struct r600_shader_ctx *ctx)
937 {
938 return tgsi_op2_s(ctx, 0);
939 }
940
941 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
942 {
943 return tgsi_op2_s(ctx, 1);
944 }
945
946 /*
947 * r600 - trunc to -PI..PI range
948 * r700 - normalize by dividing by 2PI
949 * see fdo bug 27901
950 */
951 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
952 struct r600_bc_alu_src r600_src[3])
953 {
954 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
955 int r;
956 uint32_t lit_vals[4];
957 struct r600_bc_alu alu;
958
959 memset(lit_vals, 0, 4*4);
960 r = tgsi_split_constant(ctx, r600_src);
961 if (r)
962 return r;
963 r = tgsi_split_literal_constant(ctx, r600_src);
964 if (r)
965 return r;
966
967 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
968 lit_vals[1] = fui(0.5f);
969
970 memset(&alu, 0, sizeof(struct r600_bc_alu));
971 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
972 alu.is_op3 = 1;
973
974 alu.dst.chan = 0;
975 alu.dst.sel = ctx->temp_reg;
976 alu.dst.write = 1;
977
978 alu.src[0] = r600_src[0];
979 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
980
981 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
982 alu.src[1].chan = 0;
983 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
984 alu.src[2].chan = 1;
985 alu.last = 1;
986 r = r600_bc_add_alu(ctx->bc, &alu);
987 if (r)
988 return r;
989 r = r600_bc_add_literal(ctx->bc, lit_vals);
990 if (r)
991 return r;
992
993 memset(&alu, 0, sizeof(struct r600_bc_alu));
994 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
995
996 alu.dst.chan = 0;
997 alu.dst.sel = ctx->temp_reg;
998 alu.dst.write = 1;
999
1000 alu.src[0].sel = ctx->temp_reg;
1001 alu.src[0].chan = 0;
1002 alu.last = 1;
1003 r = r600_bc_add_alu(ctx->bc, &alu);
1004 if (r)
1005 return r;
1006
1007 if (ctx->bc->chiprev == CHIPREV_R600) {
1008 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1009 lit_vals[1] = fui(-3.1415926535897f);
1010 } else {
1011 lit_vals[0] = fui(1.0f);
1012 lit_vals[1] = fui(-0.5f);
1013 }
1014
1015 memset(&alu, 0, sizeof(struct r600_bc_alu));
1016 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1017 alu.is_op3 = 1;
1018
1019 alu.dst.chan = 0;
1020 alu.dst.sel = ctx->temp_reg;
1021 alu.dst.write = 1;
1022
1023 alu.src[0].sel = ctx->temp_reg;
1024 alu.src[0].chan = 0;
1025
1026 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1027 alu.src[1].chan = 0;
1028 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1029 alu.src[2].chan = 1;
1030 alu.last = 1;
1031 r = r600_bc_add_alu(ctx->bc, &alu);
1032 if (r)
1033 return r;
1034 r = r600_bc_add_literal(ctx->bc, lit_vals);
1035 if (r)
1036 return r;
1037 return 0;
1038 }
1039
1040 static int tgsi_trig(struct r600_shader_ctx *ctx)
1041 {
1042 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1043 struct r600_bc_alu_src r600_src[3];
1044 struct r600_bc_alu alu;
1045 int i, r;
1046 int lasti = 0;
1047
1048 r = tgsi_setup_trig(ctx, r600_src);
1049 if (r)
1050 return r;
1051
1052 memset(&alu, 0, sizeof(struct r600_bc_alu));
1053 alu.inst = ctx->inst_info->r600_opcode;
1054 alu.dst.chan = 0;
1055 alu.dst.sel = ctx->temp_reg;
1056 alu.dst.write = 1;
1057
1058 alu.src[0].sel = ctx->temp_reg;
1059 alu.src[0].chan = 0;
1060 alu.last = 1;
1061 r = r600_bc_add_alu(ctx->bc, &alu);
1062 if (r)
1063 return r;
1064
1065 /* replicate result */
1066 for (i = 0; i < 4; i++) {
1067 if (inst->Dst[0].Register.WriteMask & (1 << i))
1068 lasti = i;
1069 }
1070 for (i = 0; i < lasti + 1; i++) {
1071 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1072 continue;
1073
1074 memset(&alu, 0, sizeof(struct r600_bc_alu));
1075 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1076
1077 alu.src[0].sel = ctx->temp_reg;
1078 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1079 if (r)
1080 return r;
1081 if (i == lasti)
1082 alu.last = 1;
1083 r = r600_bc_add_alu(ctx->bc, &alu);
1084 if (r)
1085 return r;
1086 }
1087 return 0;
1088 }
1089
1090 static int tgsi_scs(struct r600_shader_ctx *ctx)
1091 {
1092 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1093 struct r600_bc_alu_src r600_src[3];
1094 struct r600_bc_alu alu;
1095 int r;
1096
1097 /* We'll only need the trig stuff if we are going to write to the
1098 * X or Y components of the destination vector.
1099 */
1100 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1101 r = tgsi_setup_trig(ctx, r600_src);
1102 if (r)
1103 return r;
1104 }
1105
1106 /* dst.x = COS */
1107 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1108 memset(&alu, 0, sizeof(struct r600_bc_alu));
1109 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1110 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1111 if (r)
1112 return r;
1113
1114 alu.src[0].sel = ctx->temp_reg;
1115 alu.src[0].chan = 0;
1116 alu.last = 1;
1117 r = r600_bc_add_alu(ctx->bc, &alu);
1118 if (r)
1119 return r;
1120 }
1121
1122 /* dst.y = SIN */
1123 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1124 memset(&alu, 0, sizeof(struct r600_bc_alu));
1125 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1126 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1127 if (r)
1128 return r;
1129
1130 alu.src[0].sel = ctx->temp_reg;
1131 alu.src[0].chan = 0;
1132 alu.last = 1;
1133 r = r600_bc_add_alu(ctx->bc, &alu);
1134 if (r)
1135 return r;
1136 }
1137
1138 /* dst.z = 0.0; */
1139 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1140 memset(&alu, 0, sizeof(struct r600_bc_alu));
1141
1142 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1143
1144 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1145 if (r)
1146 return r;
1147
1148 alu.src[0].sel = V_SQ_ALU_SRC_0;
1149 alu.src[0].chan = 0;
1150
1151 alu.last = 1;
1152
1153 r = r600_bc_add_alu(ctx->bc, &alu);
1154 if (r)
1155 return r;
1156
1157 r = r600_bc_add_literal(ctx->bc, ctx->value);
1158 if (r)
1159 return r;
1160 }
1161
1162 /* dst.w = 1.0; */
1163 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1164 memset(&alu, 0, sizeof(struct r600_bc_alu));
1165
1166 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1167
1168 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1169 if (r)
1170 return r;
1171
1172 alu.src[0].sel = V_SQ_ALU_SRC_1;
1173 alu.src[0].chan = 0;
1174
1175 alu.last = 1;
1176
1177 r = r600_bc_add_alu(ctx->bc, &alu);
1178 if (r)
1179 return r;
1180
1181 r = r600_bc_add_literal(ctx->bc, ctx->value);
1182 if (r)
1183 return r;
1184 }
1185
1186 return 0;
1187 }
1188
1189 static int tgsi_kill(struct r600_shader_ctx *ctx)
1190 {
1191 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1192 struct r600_bc_alu alu;
1193 int i, r;
1194
1195 for (i = 0; i < 4; i++) {
1196 memset(&alu, 0, sizeof(struct r600_bc_alu));
1197 alu.inst = ctx->inst_info->r600_opcode;
1198
1199 alu.dst.chan = i;
1200
1201 alu.src[0].sel = V_SQ_ALU_SRC_0;
1202
1203 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1204 alu.src[1].sel = V_SQ_ALU_SRC_1;
1205 alu.src[1].neg = 1;
1206 } else {
1207 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1208 if (r)
1209 return r;
1210 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1211 }
1212 if (i == 3) {
1213 alu.last = 1;
1214 }
1215 r = r600_bc_add_alu(ctx->bc, &alu);
1216 if (r)
1217 return r;
1218 }
1219 r = r600_bc_add_literal(ctx->bc, ctx->value);
1220 if (r)
1221 return r;
1222
1223 /* kill must be last in ALU */
1224 ctx->bc->force_add_cf = 1;
1225 ctx->shader->uses_kill = TRUE;
1226 return 0;
1227 }
1228
1229 static int tgsi_lit(struct r600_shader_ctx *ctx)
1230 {
1231 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1232 struct r600_bc_alu alu;
1233 struct r600_bc_alu_src r600_src[3];
1234 int r;
1235
1236 r = tgsi_split_constant(ctx, r600_src);
1237 if (r)
1238 return r;
1239 r = tgsi_split_literal_constant(ctx, r600_src);
1240 if (r)
1241 return r;
1242
1243 /* dst.x, <- 1.0 */
1244 memset(&alu, 0, sizeof(struct r600_bc_alu));
1245 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1246 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1247 alu.src[0].chan = 0;
1248 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1249 if (r)
1250 return r;
1251 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1252 r = r600_bc_add_alu(ctx->bc, &alu);
1253 if (r)
1254 return r;
1255
1256 /* dst.y = max(src.x, 0.0) */
1257 memset(&alu, 0, sizeof(struct r600_bc_alu));
1258 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1259 alu.src[0] = r600_src[0];
1260 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1261 alu.src[1].chan = 0;
1262 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1263 if (r)
1264 return r;
1265 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1266 r = r600_bc_add_alu(ctx->bc, &alu);
1267 if (r)
1268 return r;
1269
1270 /* dst.w, <- 1.0 */
1271 memset(&alu, 0, sizeof(struct r600_bc_alu));
1272 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1273 alu.src[0].sel = V_SQ_ALU_SRC_1;
1274 alu.src[0].chan = 0;
1275 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1276 if (r)
1277 return r;
1278 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1279 alu.last = 1;
1280 r = r600_bc_add_alu(ctx->bc, &alu);
1281 if (r)
1282 return r;
1283
1284 r = r600_bc_add_literal(ctx->bc, ctx->value);
1285 if (r)
1286 return r;
1287
1288 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1289 {
1290 int chan;
1291 int sel;
1292
1293 /* dst.z = log(src.y) */
1294 memset(&alu, 0, sizeof(struct r600_bc_alu));
1295 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1296 alu.src[0] = r600_src[0];
1297 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1298 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1299 if (r)
1300 return r;
1301 alu.last = 1;
1302 r = r600_bc_add_alu(ctx->bc, &alu);
1303 if (r)
1304 return r;
1305
1306 r = r600_bc_add_literal(ctx->bc, ctx->value);
1307 if (r)
1308 return r;
1309
1310 chan = alu.dst.chan;
1311 sel = alu.dst.sel;
1312
1313 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1314 memset(&alu, 0, sizeof(struct r600_bc_alu));
1315 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1316 alu.src[0] = r600_src[0];
1317 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1318 alu.src[1].sel = sel;
1319 alu.src[1].chan = chan;
1320
1321 alu.src[2] = r600_src[0];
1322 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1323 alu.dst.sel = ctx->temp_reg;
1324 alu.dst.chan = 0;
1325 alu.dst.write = 1;
1326 alu.is_op3 = 1;
1327 alu.last = 1;
1328 r = r600_bc_add_alu(ctx->bc, &alu);
1329 if (r)
1330 return r;
1331
1332 r = r600_bc_add_literal(ctx->bc, ctx->value);
1333 if (r)
1334 return r;
1335 /* dst.z = exp(tmp.x) */
1336 memset(&alu, 0, sizeof(struct r600_bc_alu));
1337 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1338 alu.src[0].sel = ctx->temp_reg;
1339 alu.src[0].chan = 0;
1340 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1341 if (r)
1342 return r;
1343 alu.last = 1;
1344 r = r600_bc_add_alu(ctx->bc, &alu);
1345 if (r)
1346 return r;
1347 }
1348 return 0;
1349 }
1350
1351 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1352 {
1353 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1354 struct r600_bc_alu alu;
1355 int i, r;
1356
1357 memset(&alu, 0, sizeof(struct r600_bc_alu));
1358
1359 /* FIXME:
1360 * For state trackers other than OpenGL, we'll want to use
1361 * _RECIPSQRT_IEEE instead.
1362 */
1363 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1364
1365 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1366 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1367 if (r)
1368 return r;
1369 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1370 alu.src[i].abs = 1;
1371 }
1372 alu.dst.sel = ctx->temp_reg;
1373 alu.dst.write = 1;
1374 alu.last = 1;
1375 r = r600_bc_add_alu(ctx->bc, &alu);
1376 if (r)
1377 return r;
1378 r = r600_bc_add_literal(ctx->bc, ctx->value);
1379 if (r)
1380 return r;
1381 /* replicate result */
1382 return tgsi_helper_tempx_replicate(ctx);
1383 }
1384
1385 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1386 {
1387 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1388 struct r600_bc_alu alu;
1389 int i, r;
1390
1391 for (i = 0; i < 4; i++) {
1392 memset(&alu, 0, sizeof(struct r600_bc_alu));
1393 alu.src[0].sel = ctx->temp_reg;
1394 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1395 alu.dst.chan = i;
1396 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1397 if (r)
1398 return r;
1399 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1400 if (i == 3)
1401 alu.last = 1;
1402 r = r600_bc_add_alu(ctx->bc, &alu);
1403 if (r)
1404 return r;
1405 }
1406 return 0;
1407 }
1408
1409 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1410 {
1411 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1412 struct r600_bc_alu alu;
1413 int i, r;
1414
1415 memset(&alu, 0, sizeof(struct r600_bc_alu));
1416 alu.inst = ctx->inst_info->r600_opcode;
1417 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1418 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1419 if (r)
1420 return r;
1421 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1422 }
1423 alu.dst.sel = ctx->temp_reg;
1424 alu.dst.write = 1;
1425 alu.last = 1;
1426 r = r600_bc_add_alu(ctx->bc, &alu);
1427 if (r)
1428 return r;
1429 r = r600_bc_add_literal(ctx->bc, ctx->value);
1430 if (r)
1431 return r;
1432 /* replicate result */
1433 return tgsi_helper_tempx_replicate(ctx);
1434 }
1435
1436 static int tgsi_pow(struct r600_shader_ctx *ctx)
1437 {
1438 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1439 struct r600_bc_alu alu;
1440 int r;
1441
1442 /* LOG2(a) */
1443 memset(&alu, 0, sizeof(struct r600_bc_alu));
1444 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1445 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1446 if (r)
1447 return r;
1448 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1449 alu.dst.sel = ctx->temp_reg;
1450 alu.dst.write = 1;
1451 alu.last = 1;
1452 r = r600_bc_add_alu(ctx->bc, &alu);
1453 if (r)
1454 return r;
1455 r = r600_bc_add_literal(ctx->bc,ctx->value);
1456 if (r)
1457 return r;
1458 /* b * LOG2(a) */
1459 memset(&alu, 0, sizeof(struct r600_bc_alu));
1460 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1461 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1462 if (r)
1463 return r;
1464 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1465 alu.src[1].sel = ctx->temp_reg;
1466 alu.dst.sel = ctx->temp_reg;
1467 alu.dst.write = 1;
1468 alu.last = 1;
1469 r = r600_bc_add_alu(ctx->bc, &alu);
1470 if (r)
1471 return r;
1472 r = r600_bc_add_literal(ctx->bc,ctx->value);
1473 if (r)
1474 return r;
1475 /* POW(a,b) = EXP2(b * LOG2(a))*/
1476 memset(&alu, 0, sizeof(struct r600_bc_alu));
1477 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1478 alu.src[0].sel = ctx->temp_reg;
1479 alu.dst.sel = ctx->temp_reg;
1480 alu.dst.write = 1;
1481 alu.last = 1;
1482 r = r600_bc_add_alu(ctx->bc, &alu);
1483 if (r)
1484 return r;
1485 r = r600_bc_add_literal(ctx->bc,ctx->value);
1486 if (r)
1487 return r;
1488 return tgsi_helper_tempx_replicate(ctx);
1489 }
1490
1491 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1492 {
1493 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1494 struct r600_bc_alu alu;
1495 struct r600_bc_alu_src r600_src[3];
1496 int i, r;
1497
1498 r = tgsi_split_constant(ctx, r600_src);
1499 if (r)
1500 return r;
1501 r = tgsi_split_literal_constant(ctx, r600_src);
1502 if (r)
1503 return r;
1504
1505 /* tmp = (src > 0 ? 1 : src) */
1506 for (i = 0; i < 4; i++) {
1507 memset(&alu, 0, sizeof(struct r600_bc_alu));
1508 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1509 alu.is_op3 = 1;
1510
1511 alu.dst.sel = ctx->temp_reg;
1512 alu.dst.chan = i;
1513
1514 alu.src[0] = r600_src[0];
1515 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1516
1517 alu.src[1].sel = V_SQ_ALU_SRC_1;
1518
1519 alu.src[2] = r600_src[0];
1520 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1521 if (i == 3)
1522 alu.last = 1;
1523 r = r600_bc_add_alu(ctx->bc, &alu);
1524 if (r)
1525 return r;
1526 }
1527 r = r600_bc_add_literal(ctx->bc, ctx->value);
1528 if (r)
1529 return r;
1530
1531 /* dst = (-tmp > 0 ? -1 : tmp) */
1532 for (i = 0; i < 4; i++) {
1533 memset(&alu, 0, sizeof(struct r600_bc_alu));
1534 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1535 alu.is_op3 = 1;
1536 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1537 if (r)
1538 return r;
1539
1540 alu.src[0].sel = ctx->temp_reg;
1541 alu.src[0].chan = i;
1542 alu.src[0].neg = 1;
1543
1544 alu.src[1].sel = V_SQ_ALU_SRC_1;
1545 alu.src[1].neg = 1;
1546
1547 alu.src[2].sel = ctx->temp_reg;
1548 alu.src[2].chan = i;
1549
1550 if (i == 3)
1551 alu.last = 1;
1552 r = r600_bc_add_alu(ctx->bc, &alu);
1553 if (r)
1554 return r;
1555 }
1556 return 0;
1557 }
1558
1559 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1560 {
1561 struct r600_bc_alu alu;
1562 int i, r;
1563
1564 r = r600_bc_add_literal(ctx->bc, ctx->value);
1565 if (r)
1566 return r;
1567 for (i = 0; i < 4; i++) {
1568 memset(&alu, 0, sizeof(struct r600_bc_alu));
1569 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1570 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1571 alu.dst.chan = i;
1572 } else {
1573 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1574 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1575 if (r)
1576 return r;
1577 alu.src[0].sel = ctx->temp_reg;
1578 alu.src[0].chan = i;
1579 }
1580 if (i == 3) {
1581 alu.last = 1;
1582 }
1583 r = r600_bc_add_alu(ctx->bc, &alu);
1584 if (r)
1585 return r;
1586 }
1587 return 0;
1588 }
1589
1590 static int tgsi_op3(struct r600_shader_ctx *ctx)
1591 {
1592 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1593 struct r600_bc_alu_src r600_src[3];
1594 struct r600_bc_alu alu;
1595 int i, j, r;
1596
1597 r = tgsi_split_constant(ctx, r600_src);
1598 if (r)
1599 return r;
1600 r = tgsi_split_literal_constant(ctx, r600_src);
1601 if (r)
1602 return r;
1603 /* do it in 2 step as op3 doesn't support writemask */
1604 for (i = 0; i < 4; i++) {
1605 memset(&alu, 0, sizeof(struct r600_bc_alu));
1606 alu.inst = ctx->inst_info->r600_opcode;
1607 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1608 alu.src[j] = r600_src[j];
1609 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1610 }
1611 alu.dst.sel = ctx->temp_reg;
1612 alu.dst.chan = i;
1613 alu.dst.write = 1;
1614 alu.is_op3 = 1;
1615 if (i == 3) {
1616 alu.last = 1;
1617 }
1618 r = r600_bc_add_alu(ctx->bc, &alu);
1619 if (r)
1620 return r;
1621 }
1622 return tgsi_helper_copy(ctx, inst);
1623 }
1624
1625 static int tgsi_dp(struct r600_shader_ctx *ctx)
1626 {
1627 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1628 struct r600_bc_alu_src r600_src[3];
1629 struct r600_bc_alu alu;
1630 int i, j, r;
1631
1632 r = tgsi_split_constant(ctx, r600_src);
1633 if (r)
1634 return r;
1635 r = tgsi_split_literal_constant(ctx, r600_src);
1636 if (r)
1637 return r;
1638 for (i = 0; i < 4; i++) {
1639 memset(&alu, 0, sizeof(struct r600_bc_alu));
1640 alu.inst = ctx->inst_info->r600_opcode;
1641 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1642 alu.src[j] = r600_src[j];
1643 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1644 }
1645 alu.dst.sel = ctx->temp_reg;
1646 alu.dst.chan = i;
1647 alu.dst.write = 1;
1648 /* handle some special cases */
1649 switch (ctx->inst_info->tgsi_opcode) {
1650 case TGSI_OPCODE_DP2:
1651 if (i > 1) {
1652 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1653 alu.src[0].chan = alu.src[1].chan = 0;
1654 }
1655 break;
1656 case TGSI_OPCODE_DP3:
1657 if (i > 2) {
1658 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1659 alu.src[0].chan = alu.src[1].chan = 0;
1660 }
1661 break;
1662 case TGSI_OPCODE_DPH:
1663 if (i == 3) {
1664 alu.src[0].sel = V_SQ_ALU_SRC_1;
1665 alu.src[0].chan = 0;
1666 alu.src[0].neg = 0;
1667 }
1668 break;
1669 default:
1670 break;
1671 }
1672 if (i == 3) {
1673 alu.last = 1;
1674 }
1675 r = r600_bc_add_alu(ctx->bc, &alu);
1676 if (r)
1677 return r;
1678 }
1679 return tgsi_helper_copy(ctx, inst);
1680 }
1681
1682 static int tgsi_tex(struct r600_shader_ctx *ctx)
1683 {
1684 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1685 struct r600_bc_tex tex;
1686 struct r600_bc_alu alu;
1687 unsigned src_gpr;
1688 int r, i;
1689 int opcode;
1690 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1691 uint32_t lit_vals[4];
1692
1693 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1694
1695 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1696 /* Add perspective divide */
1697 memset(&alu, 0, sizeof(struct r600_bc_alu));
1698 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1699 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1700 if (r)
1701 return r;
1702
1703 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1704 alu.dst.sel = ctx->temp_reg;
1705 alu.dst.chan = 3;
1706 alu.last = 1;
1707 alu.dst.write = 1;
1708 r = r600_bc_add_alu(ctx->bc, &alu);
1709 if (r)
1710 return r;
1711
1712 for (i = 0; i < 3; i++) {
1713 memset(&alu, 0, sizeof(struct r600_bc_alu));
1714 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1715 alu.src[0].sel = ctx->temp_reg;
1716 alu.src[0].chan = 3;
1717 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1718 if (r)
1719 return r;
1720 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1721 alu.dst.sel = ctx->temp_reg;
1722 alu.dst.chan = i;
1723 alu.dst.write = 1;
1724 r = r600_bc_add_alu(ctx->bc, &alu);
1725 if (r)
1726 return r;
1727 }
1728 memset(&alu, 0, sizeof(struct r600_bc_alu));
1729 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1730 alu.src[0].sel = V_SQ_ALU_SRC_1;
1731 alu.src[0].chan = 0;
1732 alu.dst.sel = ctx->temp_reg;
1733 alu.dst.chan = 3;
1734 alu.last = 1;
1735 alu.dst.write = 1;
1736 r = r600_bc_add_alu(ctx->bc, &alu);
1737 if (r)
1738 return r;
1739 src_not_temp = FALSE;
1740 src_gpr = ctx->temp_reg;
1741 }
1742
1743 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1744 int src_chan, src2_chan;
1745
1746 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1747 for (i = 0; i < 4; i++) {
1748 memset(&alu, 0, sizeof(struct r600_bc_alu));
1749 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1750 switch (i) {
1751 case 0:
1752 src_chan = 2;
1753 src2_chan = 1;
1754 break;
1755 case 1:
1756 src_chan = 2;
1757 src2_chan = 0;
1758 break;
1759 case 2:
1760 src_chan = 0;
1761 src2_chan = 2;
1762 break;
1763 case 3:
1764 src_chan = 1;
1765 src2_chan = 2;
1766 break;
1767 default:
1768 assert(0);
1769 src_chan = 0;
1770 src2_chan = 0;
1771 break;
1772 }
1773 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1774 if (r)
1775 return r;
1776 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1777 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1778 if (r)
1779 return r;
1780 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1781 alu.dst.sel = ctx->temp_reg;
1782 alu.dst.chan = i;
1783 if (i == 3)
1784 alu.last = 1;
1785 alu.dst.write = 1;
1786 r = r600_bc_add_alu(ctx->bc, &alu);
1787 if (r)
1788 return r;
1789 }
1790
1791 /* tmp1.z = RCP_e(|tmp1.z|) */
1792 memset(&alu, 0, sizeof(struct r600_bc_alu));
1793 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1794 alu.src[0].sel = ctx->temp_reg;
1795 alu.src[0].chan = 2;
1796 alu.src[0].abs = 1;
1797 alu.dst.sel = ctx->temp_reg;
1798 alu.dst.chan = 2;
1799 alu.dst.write = 1;
1800 alu.last = 1;
1801 r = r600_bc_add_alu(ctx->bc, &alu);
1802 if (r)
1803 return r;
1804
1805 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1806 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1807 * muladd has no writemask, have to use another temp
1808 */
1809 memset(&alu, 0, sizeof(struct r600_bc_alu));
1810 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1811 alu.is_op3 = 1;
1812
1813 alu.src[0].sel = ctx->temp_reg;
1814 alu.src[0].chan = 0;
1815 alu.src[1].sel = ctx->temp_reg;
1816 alu.src[1].chan = 2;
1817
1818 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1819 alu.src[2].chan = 0;
1820
1821 alu.dst.sel = ctx->temp_reg;
1822 alu.dst.chan = 0;
1823 alu.dst.write = 1;
1824
1825 r = r600_bc_add_alu(ctx->bc, &alu);
1826 if (r)
1827 return r;
1828
1829 memset(&alu, 0, sizeof(struct r600_bc_alu));
1830 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1831 alu.is_op3 = 1;
1832
1833 alu.src[0].sel = ctx->temp_reg;
1834 alu.src[0].chan = 1;
1835 alu.src[1].sel = ctx->temp_reg;
1836 alu.src[1].chan = 2;
1837
1838 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1839 alu.src[2].chan = 0;
1840
1841 alu.dst.sel = ctx->temp_reg;
1842 alu.dst.chan = 1;
1843 alu.dst.write = 1;
1844
1845 alu.last = 1;
1846 r = r600_bc_add_alu(ctx->bc, &alu);
1847 if (r)
1848 return r;
1849
1850 lit_vals[0] = fui(1.5f);
1851
1852 r = r600_bc_add_literal(ctx->bc, lit_vals);
1853 if (r)
1854 return r;
1855 src_not_temp = FALSE;
1856 src_gpr = ctx->temp_reg;
1857 }
1858
1859 if (src_not_temp) {
1860 for (i = 0; i < 4; i++) {
1861 memset(&alu, 0, sizeof(struct r600_bc_alu));
1862 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1863 alu.src[0].sel = src_gpr;
1864 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1865 alu.dst.sel = ctx->temp_reg;
1866 alu.dst.chan = i;
1867 if (i == 3)
1868 alu.last = 1;
1869 alu.dst.write = 1;
1870 r = r600_bc_add_alu(ctx->bc, &alu);
1871 if (r)
1872 return r;
1873 }
1874 src_gpr = ctx->temp_reg;
1875 }
1876
1877 opcode = ctx->inst_info->r600_opcode;
1878 if (opcode == SQ_TEX_INST_SAMPLE &&
1879 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1880 opcode = SQ_TEX_INST_SAMPLE_C;
1881
1882 memset(&tex, 0, sizeof(struct r600_bc_tex));
1883 tex.inst = opcode;
1884 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1885 tex.resource_id = tex.sampler_id;
1886 tex.src_gpr = src_gpr;
1887 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1888 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1889 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1890 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1891 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1892 tex.src_sel_x = 0;
1893 tex.src_sel_y = 1;
1894 tex.src_sel_z = 2;
1895 tex.src_sel_w = 3;
1896
1897 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1898 tex.src_sel_x = 1;
1899 tex.src_sel_y = 0;
1900 tex.src_sel_z = 3;
1901 tex.src_sel_w = 1;
1902 }
1903
1904 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1905 tex.coord_type_x = 1;
1906 tex.coord_type_y = 1;
1907 tex.coord_type_z = 1;
1908 tex.coord_type_w = 1;
1909 }
1910
1911 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1912 tex.src_sel_w = 2;
1913
1914 r = r600_bc_add_tex(ctx->bc, &tex);
1915 if (r)
1916 return r;
1917
1918 /* add shadow ambient support - gallium doesn't do it yet */
1919 return 0;
1920 }
1921
1922 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1923 {
1924 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1925 struct r600_bc_alu_src r600_src[3];
1926 struct r600_bc_alu alu;
1927 unsigned i;
1928 int r;
1929
1930 r = tgsi_split_constant(ctx, r600_src);
1931 if (r)
1932 return r;
1933 r = tgsi_split_literal_constant(ctx, r600_src);
1934 if (r)
1935 return r;
1936 /* 1 - src0 */
1937 for (i = 0; i < 4; i++) {
1938 memset(&alu, 0, sizeof(struct r600_bc_alu));
1939 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1940 alu.src[0].sel = V_SQ_ALU_SRC_1;
1941 alu.src[0].chan = 0;
1942 alu.src[1] = r600_src[0];
1943 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1944 alu.src[1].neg = 1;
1945 alu.dst.sel = ctx->temp_reg;
1946 alu.dst.chan = i;
1947 if (i == 3) {
1948 alu.last = 1;
1949 }
1950 alu.dst.write = 1;
1951 r = r600_bc_add_alu(ctx->bc, &alu);
1952 if (r)
1953 return r;
1954 }
1955 r = r600_bc_add_literal(ctx->bc, ctx->value);
1956 if (r)
1957 return r;
1958
1959 /* (1 - src0) * src2 */
1960 for (i = 0; i < 4; i++) {
1961 memset(&alu, 0, sizeof(struct r600_bc_alu));
1962 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1963 alu.src[0].sel = ctx->temp_reg;
1964 alu.src[0].chan = i;
1965 alu.src[1] = r600_src[2];
1966 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1967 alu.dst.sel = ctx->temp_reg;
1968 alu.dst.chan = i;
1969 if (i == 3) {
1970 alu.last = 1;
1971 }
1972 alu.dst.write = 1;
1973 r = r600_bc_add_alu(ctx->bc, &alu);
1974 if (r)
1975 return r;
1976 }
1977 r = r600_bc_add_literal(ctx->bc, ctx->value);
1978 if (r)
1979 return r;
1980
1981 /* src0 * src1 + (1 - src0) * src2 */
1982 for (i = 0; i < 4; i++) {
1983 memset(&alu, 0, sizeof(struct r600_bc_alu));
1984 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1985 alu.is_op3 = 1;
1986 alu.src[0] = r600_src[0];
1987 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1988 alu.src[1] = r600_src[1];
1989 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1990 alu.src[2].sel = ctx->temp_reg;
1991 alu.src[2].chan = i;
1992 alu.dst.sel = ctx->temp_reg;
1993 alu.dst.chan = i;
1994 if (i == 3) {
1995 alu.last = 1;
1996 }
1997 r = r600_bc_add_alu(ctx->bc, &alu);
1998 if (r)
1999 return r;
2000 }
2001 return tgsi_helper_copy(ctx, inst);
2002 }
2003
2004 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2005 {
2006 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2007 struct r600_bc_alu_src r600_src[3];
2008 struct r600_bc_alu alu;
2009 int use_temp = 0;
2010 int i, r;
2011
2012 r = tgsi_split_constant(ctx, r600_src);
2013 if (r)
2014 return r;
2015 r = tgsi_split_literal_constant(ctx, r600_src);
2016 if (r)
2017 return r;
2018
2019 if (inst->Dst[0].Register.WriteMask != 0xf)
2020 use_temp = 1;
2021
2022 for (i = 0; i < 4; i++) {
2023 memset(&alu, 0, sizeof(struct r600_bc_alu));
2024 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2025 alu.src[0] = r600_src[0];
2026 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2027
2028 alu.src[1] = r600_src[2];
2029 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2030
2031 alu.src[2] = r600_src[1];
2032 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2033
2034 if (use_temp)
2035 alu.dst.sel = ctx->temp_reg;
2036 else {
2037 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2038 if (r)
2039 return r;
2040 }
2041 alu.dst.chan = i;
2042 alu.dst.write = 1;
2043 alu.is_op3 = 1;
2044 if (i == 3)
2045 alu.last = 1;
2046 r = r600_bc_add_alu(ctx->bc, &alu);
2047 if (r)
2048 return r;
2049 }
2050 if (use_temp)
2051 return tgsi_helper_copy(ctx, inst);
2052 return 0;
2053 }
2054
2055 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2056 {
2057 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2058 struct r600_bc_alu_src r600_src[3];
2059 struct r600_bc_alu alu;
2060 uint32_t use_temp = 0;
2061 int i, r;
2062
2063 if (inst->Dst[0].Register.WriteMask != 0xf)
2064 use_temp = 1;
2065
2066 r = tgsi_split_constant(ctx, r600_src);
2067 if (r)
2068 return r;
2069 r = tgsi_split_literal_constant(ctx, r600_src);
2070 if (r)
2071 return r;
2072
2073 for (i = 0; i < 4; i++) {
2074 memset(&alu, 0, sizeof(struct r600_bc_alu));
2075 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2076
2077 alu.src[0] = r600_src[0];
2078 switch (i) {
2079 case 0:
2080 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2081 break;
2082 case 1:
2083 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2084 break;
2085 case 2:
2086 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2087 break;
2088 case 3:
2089 alu.src[0].sel = V_SQ_ALU_SRC_0;
2090 alu.src[0].chan = i;
2091 }
2092
2093 alu.src[1] = r600_src[1];
2094 switch (i) {
2095 case 0:
2096 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2097 break;
2098 case 1:
2099 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2100 break;
2101 case 2:
2102 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2103 break;
2104 case 3:
2105 alu.src[1].sel = V_SQ_ALU_SRC_0;
2106 alu.src[1].chan = i;
2107 }
2108
2109 alu.dst.sel = ctx->temp_reg;
2110 alu.dst.chan = i;
2111 alu.dst.write = 1;
2112
2113 if (i == 3)
2114 alu.last = 1;
2115 r = r600_bc_add_alu(ctx->bc, &alu);
2116 if (r)
2117 return r;
2118
2119 r = r600_bc_add_literal(ctx->bc, ctx->value);
2120 if (r)
2121 return r;
2122 }
2123
2124 for (i = 0; i < 4; i++) {
2125 memset(&alu, 0, sizeof(struct r600_bc_alu));
2126 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2127
2128 alu.src[0] = r600_src[0];
2129 switch (i) {
2130 case 0:
2131 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2132 break;
2133 case 1:
2134 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2135 break;
2136 case 2:
2137 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2138 break;
2139 case 3:
2140 alu.src[0].sel = V_SQ_ALU_SRC_0;
2141 alu.src[0].chan = i;
2142 }
2143
2144 alu.src[1] = r600_src[1];
2145 switch (i) {
2146 case 0:
2147 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2148 break;
2149 case 1:
2150 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2151 break;
2152 case 2:
2153 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2154 break;
2155 case 3:
2156 alu.src[1].sel = V_SQ_ALU_SRC_0;
2157 alu.src[1].chan = i;
2158 }
2159
2160 alu.src[2].sel = ctx->temp_reg;
2161 alu.src[2].neg = 1;
2162 alu.src[2].chan = i;
2163
2164 if (use_temp)
2165 alu.dst.sel = ctx->temp_reg;
2166 else {
2167 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2168 if (r)
2169 return r;
2170 }
2171 alu.dst.chan = i;
2172 alu.dst.write = 1;
2173 alu.is_op3 = 1;
2174 if (i == 3)
2175 alu.last = 1;
2176 r = r600_bc_add_alu(ctx->bc, &alu);
2177 if (r)
2178 return r;
2179
2180 r = r600_bc_add_literal(ctx->bc, ctx->value);
2181 if (r)
2182 return r;
2183 }
2184 if (use_temp)
2185 return tgsi_helper_copy(ctx, inst);
2186 return 0;
2187 }
2188
2189 static int tgsi_exp(struct r600_shader_ctx *ctx)
2190 {
2191 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2192 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2193 struct r600_bc_alu alu;
2194 int r;
2195
2196 /* result.x = 2^floor(src); */
2197 if (inst->Dst[0].Register.WriteMask & 1) {
2198 memset(&alu, 0, sizeof(struct r600_bc_alu));
2199
2200 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2201 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2202 if (r)
2203 return r;
2204
2205 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2206
2207 alu.dst.sel = ctx->temp_reg;
2208 alu.dst.chan = 0;
2209 alu.dst.write = 1;
2210 alu.last = 1;
2211 r = r600_bc_add_alu(ctx->bc, &alu);
2212 if (r)
2213 return r;
2214
2215 r = r600_bc_add_literal(ctx->bc, ctx->value);
2216 if (r)
2217 return r;
2218
2219 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2220 alu.src[0].sel = ctx->temp_reg;
2221 alu.src[0].chan = 0;
2222
2223 alu.dst.sel = ctx->temp_reg;
2224 alu.dst.chan = 0;
2225 alu.dst.write = 1;
2226 alu.last = 1;
2227 r = r600_bc_add_alu(ctx->bc, &alu);
2228 if (r)
2229 return r;
2230
2231 r = r600_bc_add_literal(ctx->bc, ctx->value);
2232 if (r)
2233 return r;
2234 }
2235
2236 /* result.y = tmp - floor(tmp); */
2237 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2238 memset(&alu, 0, sizeof(struct r600_bc_alu));
2239
2240 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2241 alu.src[0] = r600_src[0];
2242 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2243 if (r)
2244 return r;
2245 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2246
2247 alu.dst.sel = ctx->temp_reg;
2248 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2249 // if (r)
2250 // return r;
2251 alu.dst.write = 1;
2252 alu.dst.chan = 1;
2253
2254 alu.last = 1;
2255
2256 r = r600_bc_add_alu(ctx->bc, &alu);
2257 if (r)
2258 return r;
2259 r = r600_bc_add_literal(ctx->bc, ctx->value);
2260 if (r)
2261 return r;
2262 }
2263
2264 /* result.z = RoughApprox2ToX(tmp);*/
2265 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2266 memset(&alu, 0, sizeof(struct r600_bc_alu));
2267 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2268 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2269 if (r)
2270 return r;
2271 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2272
2273 alu.dst.sel = ctx->temp_reg;
2274 alu.dst.write = 1;
2275 alu.dst.chan = 2;
2276
2277 alu.last = 1;
2278
2279 r = r600_bc_add_alu(ctx->bc, &alu);
2280 if (r)
2281 return r;
2282 r = r600_bc_add_literal(ctx->bc, ctx->value);
2283 if (r)
2284 return r;
2285 }
2286
2287 /* result.w = 1.0;*/
2288 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2289 memset(&alu, 0, sizeof(struct r600_bc_alu));
2290
2291 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2292 alu.src[0].sel = V_SQ_ALU_SRC_1;
2293 alu.src[0].chan = 0;
2294
2295 alu.dst.sel = ctx->temp_reg;
2296 alu.dst.chan = 3;
2297 alu.dst.write = 1;
2298 alu.last = 1;
2299 r = r600_bc_add_alu(ctx->bc, &alu);
2300 if (r)
2301 return r;
2302 r = r600_bc_add_literal(ctx->bc, ctx->value);
2303 if (r)
2304 return r;
2305 }
2306 return tgsi_helper_copy(ctx, inst);
2307 }
2308
2309 static int tgsi_log(struct r600_shader_ctx *ctx)
2310 {
2311 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2312 struct r600_bc_alu alu;
2313 int r;
2314
2315 /* result.x = floor(log2(src)); */
2316 if (inst->Dst[0].Register.WriteMask & 1) {
2317 memset(&alu, 0, sizeof(struct r600_bc_alu));
2318
2319 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2320 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2321 if (r)
2322 return r;
2323
2324 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2325
2326 alu.dst.sel = ctx->temp_reg;
2327 alu.dst.chan = 0;
2328 alu.dst.write = 1;
2329 alu.last = 1;
2330 r = r600_bc_add_alu(ctx->bc, &alu);
2331 if (r)
2332 return r;
2333
2334 r = r600_bc_add_literal(ctx->bc, ctx->value);
2335 if (r)
2336 return r;
2337
2338 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2339 alu.src[0].sel = ctx->temp_reg;
2340 alu.src[0].chan = 0;
2341
2342 alu.dst.sel = ctx->temp_reg;
2343 alu.dst.chan = 0;
2344 alu.dst.write = 1;
2345 alu.last = 1;
2346
2347 r = r600_bc_add_alu(ctx->bc, &alu);
2348 if (r)
2349 return r;
2350
2351 r = r600_bc_add_literal(ctx->bc, ctx->value);
2352 if (r)
2353 return r;
2354 }
2355
2356 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2357 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2358 memset(&alu, 0, sizeof(struct r600_bc_alu));
2359
2360 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2361 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2362 if (r)
2363 return r;
2364
2365 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2366
2367 alu.dst.sel = ctx->temp_reg;
2368 alu.dst.chan = 1;
2369 alu.dst.write = 1;
2370 alu.last = 1;
2371
2372 r = r600_bc_add_alu(ctx->bc, &alu);
2373 if (r)
2374 return r;
2375
2376 r = r600_bc_add_literal(ctx->bc, ctx->value);
2377 if (r)
2378 return r;
2379
2380 memset(&alu, 0, sizeof(struct r600_bc_alu));
2381
2382 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2383 alu.src[0].sel = ctx->temp_reg;
2384 alu.src[0].chan = 1;
2385
2386 alu.dst.sel = ctx->temp_reg;
2387 alu.dst.chan = 1;
2388 alu.dst.write = 1;
2389 alu.last = 1;
2390
2391 r = r600_bc_add_alu(ctx->bc, &alu);
2392 if (r)
2393 return r;
2394
2395 r = r600_bc_add_literal(ctx->bc, ctx->value);
2396 if (r)
2397 return r;
2398
2399 memset(&alu, 0, sizeof(struct r600_bc_alu));
2400
2401 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2402 alu.src[0].sel = ctx->temp_reg;
2403 alu.src[0].chan = 1;
2404
2405 alu.dst.sel = ctx->temp_reg;
2406 alu.dst.chan = 1;
2407 alu.dst.write = 1;
2408 alu.last = 1;
2409
2410 r = r600_bc_add_alu(ctx->bc, &alu);
2411 if (r)
2412 return r;
2413
2414 r = r600_bc_add_literal(ctx->bc, ctx->value);
2415 if (r)
2416 return r;
2417
2418 memset(&alu, 0, sizeof(struct r600_bc_alu));
2419
2420 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2421 alu.src[0].sel = ctx->temp_reg;
2422 alu.src[0].chan = 1;
2423
2424 alu.dst.sel = ctx->temp_reg;
2425 alu.dst.chan = 1;
2426 alu.dst.write = 1;
2427 alu.last = 1;
2428
2429 r = r600_bc_add_alu(ctx->bc, &alu);
2430 if (r)
2431 return r;
2432
2433 r = r600_bc_add_literal(ctx->bc, ctx->value);
2434 if (r)
2435 return r;
2436
2437 memset(&alu, 0, sizeof(struct r600_bc_alu));
2438
2439 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2440
2441 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2442 if (r)
2443 return r;
2444
2445 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2446
2447 alu.src[1].sel = ctx->temp_reg;
2448 alu.src[1].chan = 1;
2449
2450 alu.dst.sel = ctx->temp_reg;
2451 alu.dst.chan = 1;
2452 alu.dst.write = 1;
2453 alu.last = 1;
2454
2455 r = r600_bc_add_alu(ctx->bc, &alu);
2456 if (r)
2457 return r;
2458
2459 r = r600_bc_add_literal(ctx->bc, ctx->value);
2460 if (r)
2461 return r;
2462 }
2463
2464 /* result.z = log2(src);*/
2465 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2466 memset(&alu, 0, sizeof(struct r600_bc_alu));
2467
2468 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2469 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2470 if (r)
2471 return r;
2472
2473 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2474
2475 alu.dst.sel = ctx->temp_reg;
2476 alu.dst.write = 1;
2477 alu.dst.chan = 2;
2478 alu.last = 1;
2479
2480 r = r600_bc_add_alu(ctx->bc, &alu);
2481 if (r)
2482 return r;
2483
2484 r = r600_bc_add_literal(ctx->bc, ctx->value);
2485 if (r)
2486 return r;
2487 }
2488
2489 /* result.w = 1.0; */
2490 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2491 memset(&alu, 0, sizeof(struct r600_bc_alu));
2492
2493 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2494 alu.src[0].sel = V_SQ_ALU_SRC_1;
2495 alu.src[0].chan = 0;
2496
2497 alu.dst.sel = ctx->temp_reg;
2498 alu.dst.chan = 3;
2499 alu.dst.write = 1;
2500 alu.last = 1;
2501
2502 r = r600_bc_add_alu(ctx->bc, &alu);
2503 if (r)
2504 return r;
2505
2506 r = r600_bc_add_literal(ctx->bc, ctx->value);
2507 if (r)
2508 return r;
2509 }
2510
2511 return tgsi_helper_copy(ctx, inst);
2512 }
2513
2514 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2515 {
2516 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2517 struct r600_bc_alu alu;
2518 int r;
2519 memset(&alu, 0, sizeof(struct r600_bc_alu));
2520
2521 switch (inst->Instruction.Opcode) {
2522 case TGSI_OPCODE_ARL:
2523 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2524 break;
2525 case TGSI_OPCODE_ARR:
2526 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2527 break;
2528 default:
2529 assert(0);
2530 return -1;
2531 }
2532
2533 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2534 if (r)
2535 return r;
2536 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2537 alu.last = 1;
2538 alu.dst.chan = 0;
2539 alu.dst.sel = ctx->temp_reg;
2540 alu.dst.write = 1;
2541 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2542 if (r)
2543 return r;
2544 memset(&alu, 0, sizeof(struct r600_bc_alu));
2545 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2546 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2547 if (r)
2548 return r;
2549 alu.src[0].sel = ctx->temp_reg;
2550 alu.src[0].chan = 0;
2551 alu.last = 1;
2552 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2553 if (r)
2554 return r;
2555 return 0;
2556 }
2557 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2558 {
2559 /* TODO from r600c, ar values don't persist between clauses */
2560 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2561 struct r600_bc_alu alu;
2562 int r;
2563 memset(&alu, 0, sizeof(struct r600_bc_alu));
2564
2565 switch (inst->Instruction.Opcode) {
2566 case TGSI_OPCODE_ARL:
2567 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2568 break;
2569 case TGSI_OPCODE_ARR:
2570 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2571 break;
2572 default:
2573 assert(0);
2574 return -1;
2575 }
2576
2577
2578 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2579 if (r)
2580 return r;
2581 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2582
2583 alu.last = 1;
2584
2585 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2586 if (r)
2587 return r;
2588 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2589 return 0;
2590 }
2591
2592 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2593 {
2594 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2595 struct r600_bc_alu alu;
2596 int i, r = 0;
2597
2598 for (i = 0; i < 4; i++) {
2599 memset(&alu, 0, sizeof(struct r600_bc_alu));
2600
2601 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2602 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2603 if (r)
2604 return r;
2605
2606 if (i == 0 || i == 3) {
2607 alu.src[0].sel = V_SQ_ALU_SRC_1;
2608 } else {
2609 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2610 if (r)
2611 return r;
2612 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2613 }
2614
2615 if (i == 0 || i == 2) {
2616 alu.src[1].sel = V_SQ_ALU_SRC_1;
2617 } else {
2618 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2619 if (r)
2620 return r;
2621 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2622 }
2623 if (i == 3)
2624 alu.last = 1;
2625 r = r600_bc_add_alu(ctx->bc, &alu);
2626 if (r)
2627 return r;
2628 }
2629 return 0;
2630 }
2631
2632 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2633 {
2634 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2635 struct r600_bc_alu alu;
2636 int r;
2637
2638 memset(&alu, 0, sizeof(struct r600_bc_alu));
2639 alu.inst = opcode;
2640 alu.predicate = 1;
2641
2642 alu.dst.sel = ctx->temp_reg;
2643 alu.dst.write = 1;
2644 alu.dst.chan = 0;
2645
2646 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2647 if (r)
2648 return r;
2649 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2650 alu.src[1].sel = V_SQ_ALU_SRC_0;
2651 alu.src[1].chan = 0;
2652
2653 alu.last = 1;
2654
2655 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2656 if (r)
2657 return r;
2658 return 0;
2659 }
2660
2661 static int pops(struct r600_shader_ctx *ctx, int pops)
2662 {
2663 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2664 ctx->bc->cf_last->pop_count = pops;
2665 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2666 return 0;
2667 }
2668
2669 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2670 {
2671 switch(reason) {
2672 case FC_PUSH_VPM:
2673 ctx->bc->callstack[ctx->bc->call_sp].current--;
2674 break;
2675 case FC_PUSH_WQM:
2676 case FC_LOOP:
2677 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2678 break;
2679 case FC_REP:
2680 /* TOODO : for 16 vp asic should -= 2; */
2681 ctx->bc->callstack[ctx->bc->call_sp].current --;
2682 break;
2683 }
2684 }
2685
2686 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2687 {
2688 if (check_max_only) {
2689 int diff;
2690 switch (reason) {
2691 case FC_PUSH_VPM:
2692 diff = 1;
2693 break;
2694 case FC_PUSH_WQM:
2695 diff = 4;
2696 break;
2697 default:
2698 assert(0);
2699 diff = 0;
2700 }
2701 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2702 ctx->bc->callstack[ctx->bc->call_sp].max) {
2703 ctx->bc->callstack[ctx->bc->call_sp].max =
2704 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2705 }
2706 return;
2707 }
2708 switch (reason) {
2709 case FC_PUSH_VPM:
2710 ctx->bc->callstack[ctx->bc->call_sp].current++;
2711 break;
2712 case FC_PUSH_WQM:
2713 case FC_LOOP:
2714 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2715 break;
2716 case FC_REP:
2717 ctx->bc->callstack[ctx->bc->call_sp].current++;
2718 break;
2719 }
2720
2721 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2722 ctx->bc->callstack[ctx->bc->call_sp].max) {
2723 ctx->bc->callstack[ctx->bc->call_sp].max =
2724 ctx->bc->callstack[ctx->bc->call_sp].current;
2725 }
2726 }
2727
2728 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2729 {
2730 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2731
2732 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2733 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2734 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2735 sp->num_mid++;
2736 }
2737
2738 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2739 {
2740 ctx->bc->fc_sp++;
2741 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2742 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2743 }
2744
2745 static void fc_poplevel(struct r600_shader_ctx *ctx)
2746 {
2747 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2748 if (sp->mid) {
2749 free(sp->mid);
2750 sp->mid = NULL;
2751 }
2752 sp->num_mid = 0;
2753 sp->start = NULL;
2754 sp->type = 0;
2755 ctx->bc->fc_sp--;
2756 }
2757
2758 #if 0
2759 static int emit_return(struct r600_shader_ctx *ctx)
2760 {
2761 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2762 return 0;
2763 }
2764
2765 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2766 {
2767
2768 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2769 ctx->bc->cf_last->pop_count = pops;
2770 /* TODO work out offset */
2771 return 0;
2772 }
2773
2774 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2775 {
2776 return 0;
2777 }
2778
2779 static void emit_testflag(struct r600_shader_ctx *ctx)
2780 {
2781
2782 }
2783
2784 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2785 {
2786 emit_testflag(ctx);
2787 emit_jump_to_offset(ctx, 1, 4);
2788 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2789 pops(ctx, ifidx + 1);
2790 emit_return(ctx);
2791 }
2792
2793 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2794 {
2795 emit_testflag(ctx);
2796
2797 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2798 ctx->bc->cf_last->pop_count = 1;
2799
2800 fc_set_mid(ctx, fc_sp);
2801
2802 pops(ctx, 1);
2803 }
2804 #endif
2805
2806 static int tgsi_if(struct r600_shader_ctx *ctx)
2807 {
2808 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2809
2810 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2811
2812 fc_pushlevel(ctx, FC_IF);
2813
2814 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2815 return 0;
2816 }
2817
2818 static int tgsi_else(struct r600_shader_ctx *ctx)
2819 {
2820 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2821 ctx->bc->cf_last->pop_count = 1;
2822
2823 fc_set_mid(ctx, ctx->bc->fc_sp);
2824 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2825 return 0;
2826 }
2827
2828 static int tgsi_endif(struct r600_shader_ctx *ctx)
2829 {
2830 pops(ctx, 1);
2831 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2832 R600_ERR("if/endif unbalanced in shader\n");
2833 return -1;
2834 }
2835
2836 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2837 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2838 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2839 } else {
2840 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2841 }
2842 fc_poplevel(ctx);
2843
2844 callstack_decrease_current(ctx, FC_PUSH_VPM);
2845 return 0;
2846 }
2847
2848 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2849 {
2850 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2851
2852 fc_pushlevel(ctx, FC_LOOP);
2853
2854 /* check stack depth */
2855 callstack_check_depth(ctx, FC_LOOP, 0);
2856 return 0;
2857 }
2858
2859 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2860 {
2861 int i;
2862
2863 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2864
2865 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2866 R600_ERR("loop/endloop in shader code are not paired.\n");
2867 return -EINVAL;
2868 }
2869
2870 /* fixup loop pointers - from r600isa
2871 LOOP END points to CF after LOOP START,
2872 LOOP START point to CF after LOOP END
2873 BRK/CONT point to LOOP END CF
2874 */
2875 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2876
2877 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2878
2879 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2880 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2881 }
2882 /* TODO add LOOPRET support */
2883 fc_poplevel(ctx);
2884 callstack_decrease_current(ctx, FC_LOOP);
2885 return 0;
2886 }
2887
2888 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2889 {
2890 unsigned int fscp;
2891
2892 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2893 {
2894 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2895 break;
2896 }
2897
2898 if (fscp == 0) {
2899 R600_ERR("Break not inside loop/endloop pair\n");
2900 return -EINVAL;
2901 }
2902
2903 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2904 ctx->bc->cf_last->pop_count = 1;
2905
2906 fc_set_mid(ctx, fscp);
2907
2908 pops(ctx, 1);
2909 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2910 return 0;
2911 }
2912
2913 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2914 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2915 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2916 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2917
2918 /* FIXME:
2919 * For state trackers other than OpenGL, we'll want to use
2920 * _RECIP_IEEE instead.
2921 */
2922 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2923
2924 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2925 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2926 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2927 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2928 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2929 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2930 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2931 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2932 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2933 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2934 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2935 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2936 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2937 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2938 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2939 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 /* gap */
2941 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 /* gap */
2944 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2947 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2949 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2951 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2952 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2953 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2954 /* gap */
2955 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2957 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2959 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2960 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2961 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2962 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2963 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2969 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2971 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2972 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2973 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2974 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2976 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2978 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2985 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2989 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2990 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2991 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2992 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2995 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2996 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2997 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2998 /* gap */
2999 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3002 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3003 /* gap */
3004 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3012 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 /* gap */
3014 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3023 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3026 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3028 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 /* gap */
3030 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 /* gap */
3036 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3041 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3042 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3043 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3045 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3046 /* gap */
3047 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3051 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3056 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 };
3076
3077 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3078 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3079 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3080 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3081 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3082 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3083 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3084 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3086 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3087 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3088 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3089 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3090 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3091 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3092 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3093 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3094 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3095 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3096 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3097 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 /* gap */
3099 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 /* gap */
3102 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3105 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3107 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3109 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3110 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3111 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3112 /* gap */
3113 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3115 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3117 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3118 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3119 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3120 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3121 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3127 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3129 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3130 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3131 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3132 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3134 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3136 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3143 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3147 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3148 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3149 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3150 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3153 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3154 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3155 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3156 /* gap */
3157 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3160 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3161 /* gap */
3162 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3168 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3170 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 /* gap */
3172 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3179 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3180 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3181 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3182 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3183 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3184 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3185 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3186 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3187 /* gap */
3188 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3189 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3190 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3191 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3192 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3193 /* gap */
3194 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3195 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3196 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3197 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3198 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3199 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3200 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3201 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3202 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3203 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3204 /* gap */
3205 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3206 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3207 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3208 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3209 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3210 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3211 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3212 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3213 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3214 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3215 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3216 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3217 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3218 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3219 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3220 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3221 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3222 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3223 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3224 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3225 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3226 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3227 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3228 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3229 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3230 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3231 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3232 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3233 };