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r600g: Split ALU clauses based on used constant cache lines.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 r600_pipe_state_add_reg(rstate,
186 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
187 0xFFFFFFFF, NULL);
188 }
189
190 int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
191 {
192 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
193 struct r600_shader *rshader = &shader->shader;
194 void *ptr;
195
196 /* copy new shader */
197 if (shader->bo == NULL) {
198 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
199 if (shader->bo == NULL) {
200 return -ENOMEM;
201 }
202 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
203 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
204 r600_bo_unmap(rctx->radeon, shader->bo);
205 }
206 /* build state */
207 switch (rshader->processor_type) {
208 case TGSI_PROCESSOR_VERTEX:
209 if (rshader->family >= CHIP_CEDAR) {
210 evergreen_pipe_shader_vs(ctx, shader);
211 } else {
212 r600_pipe_shader_vs(ctx, shader);
213 }
214 break;
215 case TGSI_PROCESSOR_FRAGMENT:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_ps(ctx, shader);
218 } else {
219 r600_pipe_shader_ps(ctx, shader);
220 }
221 break;
222 default:
223 return -EINVAL;
224 }
225 return 0;
226 }
227
228 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
229 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
230 {
231 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
232 int r;
233
234 //fprintf(stderr, "--------------------------------------------------------------\n");
235 //tgsi_dump(tokens, 0);
236 shader->shader.family = r600_get_family(rctx->radeon);
237 r = r600_shader_from_tgsi(tokens, &shader->shader);
238 if (r) {
239 R600_ERR("translation from TGSI failed !\n");
240 return r;
241 }
242 r = r600_bc_build(&shader->shader.bc);
243 if (r) {
244 R600_ERR("building bytecode failed !\n");
245 return r;
246 }
247 //r600_bc_dump(&shader->shader.bc);
248 //fprintf(stderr, "______________________________________________________________\n");
249 return r600_pipe_shader(ctx, shader);
250 }
251
252 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
253 {
254 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
255
256 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
257 r600_bc_clear(&shader->shader.bc);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_ctx {
266 struct tgsi_shader_info info;
267 struct tgsi_parse_context parse;
268 const struct tgsi_token *tokens;
269 unsigned type;
270 unsigned file_offset[TGSI_FILE_COUNT];
271 unsigned temp_reg;
272 struct r600_shader_tgsi_instruction *inst_info;
273 struct r600_bc *bc;
274 struct r600_shader *shader;
275 u32 value[4];
276 u32 *literals;
277 u32 nliterals;
278 u32 max_driver_temp_used;
279 /* needed for evergreen interpolation */
280 boolean input_centroid;
281 boolean input_linear;
282 boolean input_perspective;
283 int num_interp_gpr;
284 };
285
286 struct r600_shader_tgsi_instruction {
287 unsigned tgsi_opcode;
288 unsigned is_op3;
289 unsigned r600_opcode;
290 int (*process)(struct r600_shader_ctx *ctx);
291 };
292
293 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
294 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
295
296 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
297 {
298 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
299 int j;
300
301 if (i->Instruction.NumDstRegs > 1) {
302 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
303 return -EINVAL;
304 }
305 if (i->Instruction.Predicate) {
306 R600_ERR("predicate unsupported\n");
307 return -EINVAL;
308 }
309 #if 0
310 if (i->Instruction.Label) {
311 R600_ERR("label unsupported\n");
312 return -EINVAL;
313 }
314 #endif
315 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
316 if (i->Src[j].Register.Dimension) {
317 R600_ERR("unsupported src %d (dimension %d)\n", j,
318 i->Src[j].Register.Dimension);
319 return -EINVAL;
320 }
321 }
322 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
323 if (i->Dst[j].Register.Dimension) {
324 R600_ERR("unsupported dst (dimension)\n");
325 return -EINVAL;
326 }
327 }
328 return 0;
329 }
330
331 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
332 {
333 int i, r;
334 struct r600_bc_alu alu;
335 int gpr = 0, base_chan = 0;
336 int ij_index = 0;
337
338 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
339 ij_index = 0;
340 if (ctx->shader->input[input].centroid)
341 ij_index++;
342 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
343 ij_index = 0;
344 /* if we have perspective add one */
345 if (ctx->input_perspective) {
346 ij_index++;
347 /* if we have perspective centroid */
348 if (ctx->input_centroid)
349 ij_index++;
350 }
351 if (ctx->shader->input[input].centroid)
352 ij_index++;
353 }
354
355 /* work out gpr and base_chan from index */
356 gpr = ij_index / 2;
357 base_chan = (2 * (ij_index % 2)) + 1;
358
359 for (i = 0; i < 8; i++) {
360 memset(&alu, 0, sizeof(struct r600_bc_alu));
361
362 if (i < 4)
363 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
364 else
365 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
366
367 if ((i > 1) && (i < 6)) {
368 alu.dst.sel = ctx->shader->input[input].gpr;
369 alu.dst.write = 1;
370 }
371
372 alu.dst.chan = i % 4;
373
374 alu.src[0].sel = gpr;
375 alu.src[0].chan = (base_chan - (i % 2));
376
377 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
378
379 alu.bank_swizzle_force = SQ_ALU_VEC_210;
380 if ((i % 4) == 3)
381 alu.last = 1;
382 r = r600_bc_add_alu(ctx->bc, &alu);
383 if (r)
384 return r;
385 }
386 return 0;
387 }
388
389
390 static int tgsi_declaration(struct r600_shader_ctx *ctx)
391 {
392 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
393 unsigned i;
394
395 switch (d->Declaration.File) {
396 case TGSI_FILE_INPUT:
397 i = ctx->shader->ninput++;
398 ctx->shader->input[i].name = d->Semantic.Name;
399 ctx->shader->input[i].sid = d->Semantic.Index;
400 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
401 ctx->shader->input[i].centroid = d->Declaration.Centroid;
402 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
403 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
404 /* turn input into interpolate on EG */
405 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
406 if (ctx->shader->input[i].interpolate > 0) {
407 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
408 evergreen_interp_alu(ctx, i);
409 }
410 }
411 }
412 break;
413 case TGSI_FILE_OUTPUT:
414 i = ctx->shader->noutput++;
415 ctx->shader->output[i].name = d->Semantic.Name;
416 ctx->shader->output[i].sid = d->Semantic.Index;
417 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
418 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
419 break;
420 case TGSI_FILE_CONSTANT:
421 case TGSI_FILE_TEMPORARY:
422 case TGSI_FILE_SAMPLER:
423 case TGSI_FILE_ADDRESS:
424 break;
425 default:
426 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
427 return -EINVAL;
428 }
429 return 0;
430 }
431
432 static int r600_get_temp(struct r600_shader_ctx *ctx)
433 {
434 return ctx->temp_reg + ctx->max_driver_temp_used++;
435 }
436
437 /*
438 * for evergreen we need to scan the shader to find the number of GPRs we need to
439 * reserve for interpolation.
440 *
441 * we need to know if we are going to emit
442 * any centroid inputs
443 * if perspective and linear are required
444 */
445 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
446 {
447 int i;
448 int num_baryc;
449
450 ctx->input_linear = FALSE;
451 ctx->input_perspective = FALSE;
452 ctx->input_centroid = FALSE;
453 ctx->num_interp_gpr = 1;
454
455 /* any centroid inputs */
456 for (i = 0; i < ctx->info.num_inputs; i++) {
457 /* skip position/face */
458 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
459 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
460 continue;
461 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
462 ctx->input_linear = TRUE;
463 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
464 ctx->input_perspective = TRUE;
465 if (ctx->info.input_centroid[i])
466 ctx->input_centroid = TRUE;
467 }
468
469 num_baryc = 0;
470 /* ignoring sample for now */
471 if (ctx->input_perspective)
472 num_baryc++;
473 if (ctx->input_linear)
474 num_baryc++;
475 if (ctx->input_centroid)
476 num_baryc *= 2;
477
478 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
479
480 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
481 return ctx->num_interp_gpr;
482 }
483
484 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
485 {
486 struct tgsi_full_immediate *immediate;
487 struct r600_shader_ctx ctx;
488 struct r600_bc_output output[32];
489 unsigned output_done, noutput;
490 unsigned opcode;
491 int i, r = 0, pos0;
492
493 ctx.bc = &shader->bc;
494 ctx.shader = shader;
495 r = r600_bc_init(ctx.bc, shader->family);
496 if (r)
497 return r;
498 ctx.tokens = tokens;
499 tgsi_scan_shader(tokens, &ctx.info);
500 tgsi_parse_init(&ctx.parse, tokens);
501 ctx.type = ctx.parse.FullHeader.Processor.Processor;
502 shader->processor_type = ctx.type;
503 ctx.bc->type = shader->processor_type;
504
505 /* register allocations */
506 /* Values [0,127] correspond to GPR[0..127].
507 * Values [128,159] correspond to constant buffer bank 0
508 * Values [160,191] correspond to constant buffer bank 1
509 * Values [256,511] correspond to cfile constants c[0..255].
510 * Other special values are shown in the list below.
511 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
512 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
513 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
514 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
515 * 248 SQ_ALU_SRC_0: special constant 0.0.
516 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
517 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
518 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
519 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
520 * 253 SQ_ALU_SRC_LITERAL: literal constant.
521 * 254 SQ_ALU_SRC_PV: previous vector result.
522 * 255 SQ_ALU_SRC_PS: previous scalar result.
523 */
524 for (i = 0; i < TGSI_FILE_COUNT; i++) {
525 ctx.file_offset[i] = 0;
526 }
527 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
528 ctx.file_offset[TGSI_FILE_INPUT] = 1;
529 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
530 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
531 } else {
532 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
533 }
534 }
535 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
536 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
537 }
538 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
539 ctx.info.file_count[TGSI_FILE_INPUT];
540 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
541 ctx.info.file_count[TGSI_FILE_OUTPUT];
542
543 /* Outside the GPR range. This will be translated to one of the
544 * kcache banks later. */
545 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
546
547 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
548 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
549 ctx.info.file_count[TGSI_FILE_TEMPORARY];
550
551 ctx.nliterals = 0;
552 ctx.literals = NULL;
553
554 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
555 tgsi_parse_token(&ctx.parse);
556 switch (ctx.parse.FullToken.Token.Type) {
557 case TGSI_TOKEN_TYPE_IMMEDIATE:
558 immediate = &ctx.parse.FullToken.FullImmediate;
559 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
560 if(ctx.literals == NULL) {
561 r = -ENOMEM;
562 goto out_err;
563 }
564 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
565 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
566 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
567 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
568 ctx.nliterals++;
569 break;
570 case TGSI_TOKEN_TYPE_DECLARATION:
571 r = tgsi_declaration(&ctx);
572 if (r)
573 goto out_err;
574 break;
575 case TGSI_TOKEN_TYPE_INSTRUCTION:
576 r = tgsi_is_supported(&ctx);
577 if (r)
578 goto out_err;
579 ctx.max_driver_temp_used = 0;
580 /* reserve first tmp for everyone */
581 r600_get_temp(&ctx);
582 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
583 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
584 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
585 else
586 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
587 r = ctx.inst_info->process(&ctx);
588 if (r)
589 goto out_err;
590 r = r600_bc_add_literal(ctx.bc, ctx.value);
591 if (r)
592 goto out_err;
593 break;
594 case TGSI_TOKEN_TYPE_PROPERTY:
595 break;
596 default:
597 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
598 r = -EINVAL;
599 goto out_err;
600 }
601 }
602 /* export output */
603 noutput = shader->noutput;
604 for (i = 0, pos0 = 0; i < noutput; i++) {
605 memset(&output[i], 0, sizeof(struct r600_bc_output));
606 output[i].gpr = shader->output[i].gpr;
607 output[i].elem_size = 3;
608 output[i].swizzle_x = 0;
609 output[i].swizzle_y = 1;
610 output[i].swizzle_z = 2;
611 output[i].swizzle_w = 3;
612 output[i].barrier = 1;
613 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
614 output[i].array_base = i - pos0;
615 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
616 switch (ctx.type) {
617 case TGSI_PROCESSOR_VERTEX:
618 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
619 output[i].array_base = 60;
620 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
621 /* position doesn't count in array_base */
622 pos0++;
623 }
624 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
625 output[i].array_base = 61;
626 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
627 /* position doesn't count in array_base */
628 pos0++;
629 }
630 break;
631 case TGSI_PROCESSOR_FRAGMENT:
632 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
633 output[i].array_base = shader->output[i].sid;
634 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
635 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
636 output[i].array_base = 61;
637 output[i].swizzle_x = 2;
638 output[i].swizzle_y = 7;
639 output[i].swizzle_z = output[i].swizzle_w = 7;
640 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
641 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
642 output[i].array_base = 61;
643 output[i].swizzle_x = 7;
644 output[i].swizzle_y = 1;
645 output[i].swizzle_z = output[i].swizzle_w = 7;
646 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
647 } else {
648 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
649 r = -EINVAL;
650 goto out_err;
651 }
652 break;
653 default:
654 R600_ERR("unsupported processor type %d\n", ctx.type);
655 r = -EINVAL;
656 goto out_err;
657 }
658 }
659 /* add fake param output for vertex shader if no param is exported */
660 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
661 for (i = 0, pos0 = 0; i < noutput; i++) {
662 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
663 pos0 = 1;
664 break;
665 }
666 }
667 if (!pos0) {
668 memset(&output[i], 0, sizeof(struct r600_bc_output));
669 output[i].gpr = 0;
670 output[i].elem_size = 3;
671 output[i].swizzle_x = 0;
672 output[i].swizzle_y = 1;
673 output[i].swizzle_z = 2;
674 output[i].swizzle_w = 3;
675 output[i].barrier = 1;
676 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
677 output[i].array_base = 0;
678 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
679 noutput++;
680 }
681 }
682 /* add fake pixel export */
683 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
684 memset(&output[0], 0, sizeof(struct r600_bc_output));
685 output[0].gpr = 0;
686 output[0].elem_size = 3;
687 output[0].swizzle_x = 7;
688 output[0].swizzle_y = 7;
689 output[0].swizzle_z = 7;
690 output[0].swizzle_w = 7;
691 output[0].barrier = 1;
692 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
693 output[0].array_base = 0;
694 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
695 noutput++;
696 }
697 /* set export done on last export of each type */
698 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
699 if (i == (noutput - 1)) {
700 output[i].end_of_program = 1;
701 }
702 if (!(output_done & (1 << output[i].type))) {
703 output_done |= (1 << output[i].type);
704 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
705 }
706 }
707 /* add output to bytecode */
708 for (i = 0; i < noutput; i++) {
709 r = r600_bc_add_output(ctx.bc, &output[i]);
710 if (r)
711 goto out_err;
712 }
713 free(ctx.literals);
714 tgsi_parse_free(&ctx.parse);
715 return 0;
716 out_err:
717 free(ctx.literals);
718 tgsi_parse_free(&ctx.parse);
719 return r;
720 }
721
722 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
723 {
724 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
725 return -EINVAL;
726 }
727
728 static int tgsi_end(struct r600_shader_ctx *ctx)
729 {
730 return 0;
731 }
732
733 static int tgsi_src(struct r600_shader_ctx *ctx,
734 const struct tgsi_full_src_register *tgsi_src,
735 struct r600_bc_alu_src *r600_src)
736 {
737 int index;
738 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
739 r600_src->sel = tgsi_src->Register.Index;
740 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
741 r600_src->sel = 0;
742 index = tgsi_src->Register.Index;
743 ctx->value[0] = ctx->literals[index * 4 + 0];
744 ctx->value[1] = ctx->literals[index * 4 + 1];
745 ctx->value[2] = ctx->literals[index * 4 + 2];
746 ctx->value[3] = ctx->literals[index * 4 + 3];
747 }
748 if (tgsi_src->Register.Indirect)
749 r600_src->rel = V_SQ_REL_RELATIVE;
750 r600_src->neg = tgsi_src->Register.Negate;
751 r600_src->abs = tgsi_src->Register.Absolute;
752 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
753 return 0;
754 }
755
756 static int tgsi_dst(struct r600_shader_ctx *ctx,
757 const struct tgsi_full_dst_register *tgsi_dst,
758 unsigned swizzle,
759 struct r600_bc_alu_dst *r600_dst)
760 {
761 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
762
763 r600_dst->sel = tgsi_dst->Register.Index;
764 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
765 r600_dst->chan = swizzle;
766 r600_dst->write = 1;
767 if (tgsi_dst->Register.Indirect)
768 r600_dst->rel = V_SQ_REL_RELATIVE;
769 if (inst->Instruction.Saturate) {
770 r600_dst->clamp = 1;
771 }
772 return 0;
773 }
774
775 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
776 {
777 switch (swizzle) {
778 case 0:
779 return tgsi_src->Register.SwizzleX;
780 case 1:
781 return tgsi_src->Register.SwizzleY;
782 case 2:
783 return tgsi_src->Register.SwizzleZ;
784 case 3:
785 return tgsi_src->Register.SwizzleW;
786 default:
787 return 0;
788 }
789 }
790
791 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
792 {
793 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
794 struct r600_bc_alu alu;
795 int i, j, k, nconst, r;
796
797 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
798 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
799 nconst++;
800 }
801 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
802 if (r) {
803 return r;
804 }
805 }
806 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
807 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
808 int treg = r600_get_temp(ctx);
809 for (k = 0; k < 4; k++) {
810 memset(&alu, 0, sizeof(struct r600_bc_alu));
811 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
812 alu.src[0].sel = r600_src[i].sel;
813 alu.src[0].chan = k;
814 alu.src[0].rel = r600_src[i].rel;
815 alu.dst.sel = treg;
816 alu.dst.chan = k;
817 alu.dst.write = 1;
818 if (k == 3)
819 alu.last = 1;
820 r = r600_bc_add_alu(ctx->bc, &alu);
821 if (r)
822 return r;
823 }
824 r600_src[i].sel = treg;
825 r600_src[i].rel =0;
826 j--;
827 }
828 }
829 return 0;
830 }
831
832 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
833 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
834 {
835 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
836 struct r600_bc_alu alu;
837 int i, j, k, nliteral, r;
838
839 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
840 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
841 nliteral++;
842 }
843 }
844 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
845 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
846 int treg = r600_get_temp(ctx);
847 for (k = 0; k < 4; k++) {
848 memset(&alu, 0, sizeof(struct r600_bc_alu));
849 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
850 alu.src[0].sel = r600_src[i].sel;
851 alu.src[0].chan = k;
852 alu.dst.sel = treg;
853 alu.dst.chan = k;
854 alu.dst.write = 1;
855 if (k == 3)
856 alu.last = 1;
857 r = r600_bc_add_alu(ctx->bc, &alu);
858 if (r)
859 return r;
860 }
861 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
862 if (r)
863 return r;
864 r600_src[i].sel = treg;
865 j--;
866 }
867 }
868 return 0;
869 }
870
871 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
872 {
873 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
874 struct r600_bc_alu_src r600_src[3];
875 struct r600_bc_alu alu;
876 int i, j, r;
877 int lasti = 0;
878
879 for (i = 0; i < 4; i++) {
880 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
881 lasti = i;
882 }
883 }
884
885 r = tgsi_split_constant(ctx, r600_src);
886 if (r)
887 return r;
888 r = tgsi_split_literal_constant(ctx, r600_src);
889 if (r)
890 return r;
891 for (i = 0; i < lasti + 1; i++) {
892 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
893 continue;
894
895 memset(&alu, 0, sizeof(struct r600_bc_alu));
896 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
897 if (r)
898 return r;
899
900 alu.inst = ctx->inst_info->r600_opcode;
901 if (!swap) {
902 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
903 alu.src[j] = r600_src[j];
904 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
905 }
906 } else {
907 alu.src[0] = r600_src[1];
908 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
909
910 alu.src[1] = r600_src[0];
911 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
912 }
913 /* handle some special cases */
914 switch (ctx->inst_info->tgsi_opcode) {
915 case TGSI_OPCODE_SUB:
916 alu.src[1].neg = 1;
917 break;
918 case TGSI_OPCODE_ABS:
919 alu.src[0].abs = 1;
920 break;
921 default:
922 break;
923 }
924 if (i == lasti) {
925 alu.last = 1;
926 }
927 r = r600_bc_add_alu(ctx->bc, &alu);
928 if (r)
929 return r;
930 }
931 return 0;
932 }
933
934 static int tgsi_op2(struct r600_shader_ctx *ctx)
935 {
936 return tgsi_op2_s(ctx, 0);
937 }
938
939 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
940 {
941 return tgsi_op2_s(ctx, 1);
942 }
943
944 /*
945 * r600 - trunc to -PI..PI range
946 * r700 - normalize by dividing by 2PI
947 * see fdo bug 27901
948 */
949 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
950 struct r600_bc_alu_src r600_src[3])
951 {
952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
953 int r;
954 uint32_t lit_vals[4];
955 struct r600_bc_alu alu;
956
957 memset(lit_vals, 0, 4*4);
958 r = tgsi_split_constant(ctx, r600_src);
959 if (r)
960 return r;
961 r = tgsi_split_literal_constant(ctx, r600_src);
962 if (r)
963 return r;
964
965 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
966 lit_vals[1] = fui(0.5f);
967
968 memset(&alu, 0, sizeof(struct r600_bc_alu));
969 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
970 alu.is_op3 = 1;
971
972 alu.dst.chan = 0;
973 alu.dst.sel = ctx->temp_reg;
974 alu.dst.write = 1;
975
976 alu.src[0] = r600_src[0];
977 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
978
979 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
980 alu.src[1].chan = 0;
981 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
982 alu.src[2].chan = 1;
983 alu.last = 1;
984 r = r600_bc_add_alu(ctx->bc, &alu);
985 if (r)
986 return r;
987 r = r600_bc_add_literal(ctx->bc, lit_vals);
988 if (r)
989 return r;
990
991 memset(&alu, 0, sizeof(struct r600_bc_alu));
992 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
993
994 alu.dst.chan = 0;
995 alu.dst.sel = ctx->temp_reg;
996 alu.dst.write = 1;
997
998 alu.src[0].sel = ctx->temp_reg;
999 alu.src[0].chan = 0;
1000 alu.last = 1;
1001 r = r600_bc_add_alu(ctx->bc, &alu);
1002 if (r)
1003 return r;
1004
1005 if (ctx->bc->chiprev == CHIPREV_R600) {
1006 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1007 lit_vals[1] = fui(-3.1415926535897f);
1008 } else {
1009 lit_vals[0] = fui(1.0f);
1010 lit_vals[1] = fui(-0.5f);
1011 }
1012
1013 memset(&alu, 0, sizeof(struct r600_bc_alu));
1014 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1015 alu.is_op3 = 1;
1016
1017 alu.dst.chan = 0;
1018 alu.dst.sel = ctx->temp_reg;
1019 alu.dst.write = 1;
1020
1021 alu.src[0].sel = ctx->temp_reg;
1022 alu.src[0].chan = 0;
1023
1024 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1025 alu.src[1].chan = 0;
1026 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1027 alu.src[2].chan = 1;
1028 alu.last = 1;
1029 r = r600_bc_add_alu(ctx->bc, &alu);
1030 if (r)
1031 return r;
1032 r = r600_bc_add_literal(ctx->bc, lit_vals);
1033 if (r)
1034 return r;
1035 return 0;
1036 }
1037
1038 static int tgsi_trig(struct r600_shader_ctx *ctx)
1039 {
1040 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1041 struct r600_bc_alu_src r600_src[3];
1042 struct r600_bc_alu alu;
1043 int i, r;
1044 int lasti = 0;
1045
1046 r = tgsi_setup_trig(ctx, r600_src);
1047 if (r)
1048 return r;
1049
1050 memset(&alu, 0, sizeof(struct r600_bc_alu));
1051 alu.inst = ctx->inst_info->r600_opcode;
1052 alu.dst.chan = 0;
1053 alu.dst.sel = ctx->temp_reg;
1054 alu.dst.write = 1;
1055
1056 alu.src[0].sel = ctx->temp_reg;
1057 alu.src[0].chan = 0;
1058 alu.last = 1;
1059 r = r600_bc_add_alu(ctx->bc, &alu);
1060 if (r)
1061 return r;
1062
1063 /* replicate result */
1064 for (i = 0; i < 4; i++) {
1065 if (inst->Dst[0].Register.WriteMask & (1 << i))
1066 lasti = i;
1067 }
1068 for (i = 0; i < lasti + 1; i++) {
1069 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1070 continue;
1071
1072 memset(&alu, 0, sizeof(struct r600_bc_alu));
1073 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1074
1075 alu.src[0].sel = ctx->temp_reg;
1076 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1077 if (r)
1078 return r;
1079 if (i == lasti)
1080 alu.last = 1;
1081 r = r600_bc_add_alu(ctx->bc, &alu);
1082 if (r)
1083 return r;
1084 }
1085 return 0;
1086 }
1087
1088 static int tgsi_scs(struct r600_shader_ctx *ctx)
1089 {
1090 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1091 struct r600_bc_alu_src r600_src[3];
1092 struct r600_bc_alu alu;
1093 int r;
1094
1095 /* We'll only need the trig stuff if we are going to write to the
1096 * X or Y components of the destination vector.
1097 */
1098 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1099 r = tgsi_setup_trig(ctx, r600_src);
1100 if (r)
1101 return r;
1102 }
1103
1104 /* dst.x = COS */
1105 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1106 memset(&alu, 0, sizeof(struct r600_bc_alu));
1107 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1108 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1109 if (r)
1110 return r;
1111
1112 alu.src[0].sel = ctx->temp_reg;
1113 alu.src[0].chan = 0;
1114 alu.last = 1;
1115 r = r600_bc_add_alu(ctx->bc, &alu);
1116 if (r)
1117 return r;
1118 }
1119
1120 /* dst.y = SIN */
1121 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1122 memset(&alu, 0, sizeof(struct r600_bc_alu));
1123 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1124 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1125 if (r)
1126 return r;
1127
1128 alu.src[0].sel = ctx->temp_reg;
1129 alu.src[0].chan = 0;
1130 alu.last = 1;
1131 r = r600_bc_add_alu(ctx->bc, &alu);
1132 if (r)
1133 return r;
1134 }
1135
1136 /* dst.z = 0.0; */
1137 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1138 memset(&alu, 0, sizeof(struct r600_bc_alu));
1139
1140 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1141
1142 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1143 if (r)
1144 return r;
1145
1146 alu.src[0].sel = V_SQ_ALU_SRC_0;
1147 alu.src[0].chan = 0;
1148
1149 alu.last = 1;
1150
1151 r = r600_bc_add_alu(ctx->bc, &alu);
1152 if (r)
1153 return r;
1154
1155 r = r600_bc_add_literal(ctx->bc, ctx->value);
1156 if (r)
1157 return r;
1158 }
1159
1160 /* dst.w = 1.0; */
1161 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1162 memset(&alu, 0, sizeof(struct r600_bc_alu));
1163
1164 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1165
1166 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1167 if (r)
1168 return r;
1169
1170 alu.src[0].sel = V_SQ_ALU_SRC_1;
1171 alu.src[0].chan = 0;
1172
1173 alu.last = 1;
1174
1175 r = r600_bc_add_alu(ctx->bc, &alu);
1176 if (r)
1177 return r;
1178
1179 r = r600_bc_add_literal(ctx->bc, ctx->value);
1180 if (r)
1181 return r;
1182 }
1183
1184 return 0;
1185 }
1186
1187 static int tgsi_kill(struct r600_shader_ctx *ctx)
1188 {
1189 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1190 struct r600_bc_alu alu;
1191 int i, r;
1192
1193 for (i = 0; i < 4; i++) {
1194 memset(&alu, 0, sizeof(struct r600_bc_alu));
1195 alu.inst = ctx->inst_info->r600_opcode;
1196
1197 alu.dst.chan = i;
1198
1199 alu.src[0].sel = V_SQ_ALU_SRC_0;
1200
1201 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1202 alu.src[1].sel = V_SQ_ALU_SRC_1;
1203 alu.src[1].neg = 1;
1204 } else {
1205 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1206 if (r)
1207 return r;
1208 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1209 }
1210 if (i == 3) {
1211 alu.last = 1;
1212 }
1213 r = r600_bc_add_alu(ctx->bc, &alu);
1214 if (r)
1215 return r;
1216 }
1217 r = r600_bc_add_literal(ctx->bc, ctx->value);
1218 if (r)
1219 return r;
1220
1221 /* kill must be last in ALU */
1222 ctx->bc->force_add_cf = 1;
1223 ctx->shader->uses_kill = TRUE;
1224 return 0;
1225 }
1226
1227 static int tgsi_lit(struct r600_shader_ctx *ctx)
1228 {
1229 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1230 struct r600_bc_alu alu;
1231 struct r600_bc_alu_src r600_src[3];
1232 int r;
1233
1234 r = tgsi_split_constant(ctx, r600_src);
1235 if (r)
1236 return r;
1237 r = tgsi_split_literal_constant(ctx, r600_src);
1238 if (r)
1239 return r;
1240
1241 /* dst.x, <- 1.0 */
1242 memset(&alu, 0, sizeof(struct r600_bc_alu));
1243 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1244 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1245 alu.src[0].chan = 0;
1246 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1247 if (r)
1248 return r;
1249 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1250 r = r600_bc_add_alu(ctx->bc, &alu);
1251 if (r)
1252 return r;
1253
1254 /* dst.y = max(src.x, 0.0) */
1255 memset(&alu, 0, sizeof(struct r600_bc_alu));
1256 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1257 alu.src[0] = r600_src[0];
1258 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1259 alu.src[1].chan = 0;
1260 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1261 if (r)
1262 return r;
1263 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1264 r = r600_bc_add_alu(ctx->bc, &alu);
1265 if (r)
1266 return r;
1267
1268 /* dst.w, <- 1.0 */
1269 memset(&alu, 0, sizeof(struct r600_bc_alu));
1270 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1271 alu.src[0].sel = V_SQ_ALU_SRC_1;
1272 alu.src[0].chan = 0;
1273 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1274 if (r)
1275 return r;
1276 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1277 alu.last = 1;
1278 r = r600_bc_add_alu(ctx->bc, &alu);
1279 if (r)
1280 return r;
1281
1282 r = r600_bc_add_literal(ctx->bc, ctx->value);
1283 if (r)
1284 return r;
1285
1286 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1287 {
1288 int chan;
1289 int sel;
1290
1291 /* dst.z = log(src.y) */
1292 memset(&alu, 0, sizeof(struct r600_bc_alu));
1293 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1294 alu.src[0] = r600_src[0];
1295 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1296 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1297 if (r)
1298 return r;
1299 alu.last = 1;
1300 r = r600_bc_add_alu(ctx->bc, &alu);
1301 if (r)
1302 return r;
1303
1304 r = r600_bc_add_literal(ctx->bc, ctx->value);
1305 if (r)
1306 return r;
1307
1308 chan = alu.dst.chan;
1309 sel = alu.dst.sel;
1310
1311 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1312 memset(&alu, 0, sizeof(struct r600_bc_alu));
1313 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1314 alu.src[0] = r600_src[0];
1315 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1316 alu.src[1].sel = sel;
1317 alu.src[1].chan = chan;
1318
1319 alu.src[2] = r600_src[0];
1320 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1321 alu.dst.sel = ctx->temp_reg;
1322 alu.dst.chan = 0;
1323 alu.dst.write = 1;
1324 alu.is_op3 = 1;
1325 alu.last = 1;
1326 r = r600_bc_add_alu(ctx->bc, &alu);
1327 if (r)
1328 return r;
1329
1330 r = r600_bc_add_literal(ctx->bc, ctx->value);
1331 if (r)
1332 return r;
1333 /* dst.z = exp(tmp.x) */
1334 memset(&alu, 0, sizeof(struct r600_bc_alu));
1335 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1336 alu.src[0].sel = ctx->temp_reg;
1337 alu.src[0].chan = 0;
1338 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1339 if (r)
1340 return r;
1341 alu.last = 1;
1342 r = r600_bc_add_alu(ctx->bc, &alu);
1343 if (r)
1344 return r;
1345 }
1346 return 0;
1347 }
1348
1349 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1350 {
1351 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1352 struct r600_bc_alu alu;
1353 int i, r;
1354
1355 memset(&alu, 0, sizeof(struct r600_bc_alu));
1356
1357 /* FIXME:
1358 * For state trackers other than OpenGL, we'll want to use
1359 * _RECIPSQRT_IEEE instead.
1360 */
1361 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1362
1363 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1364 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1365 if (r)
1366 return r;
1367 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1368 alu.src[i].abs = 1;
1369 }
1370 alu.dst.sel = ctx->temp_reg;
1371 alu.dst.write = 1;
1372 alu.last = 1;
1373 r = r600_bc_add_alu(ctx->bc, &alu);
1374 if (r)
1375 return r;
1376 r = r600_bc_add_literal(ctx->bc, ctx->value);
1377 if (r)
1378 return r;
1379 /* replicate result */
1380 return tgsi_helper_tempx_replicate(ctx);
1381 }
1382
1383 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1384 {
1385 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1386 struct r600_bc_alu alu;
1387 int i, r;
1388
1389 for (i = 0; i < 4; i++) {
1390 memset(&alu, 0, sizeof(struct r600_bc_alu));
1391 alu.src[0].sel = ctx->temp_reg;
1392 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1393 alu.dst.chan = i;
1394 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1395 if (r)
1396 return r;
1397 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1398 if (i == 3)
1399 alu.last = 1;
1400 r = r600_bc_add_alu(ctx->bc, &alu);
1401 if (r)
1402 return r;
1403 }
1404 return 0;
1405 }
1406
1407 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1408 {
1409 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1410 struct r600_bc_alu alu;
1411 int i, r;
1412
1413 memset(&alu, 0, sizeof(struct r600_bc_alu));
1414 alu.inst = ctx->inst_info->r600_opcode;
1415 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1416 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1417 if (r)
1418 return r;
1419 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1420 }
1421 alu.dst.sel = ctx->temp_reg;
1422 alu.dst.write = 1;
1423 alu.last = 1;
1424 r = r600_bc_add_alu(ctx->bc, &alu);
1425 if (r)
1426 return r;
1427 r = r600_bc_add_literal(ctx->bc, ctx->value);
1428 if (r)
1429 return r;
1430 /* replicate result */
1431 return tgsi_helper_tempx_replicate(ctx);
1432 }
1433
1434 static int tgsi_pow(struct r600_shader_ctx *ctx)
1435 {
1436 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1437 struct r600_bc_alu alu;
1438 int r;
1439
1440 /* LOG2(a) */
1441 memset(&alu, 0, sizeof(struct r600_bc_alu));
1442 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1443 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1444 if (r)
1445 return r;
1446 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1447 alu.dst.sel = ctx->temp_reg;
1448 alu.dst.write = 1;
1449 alu.last = 1;
1450 r = r600_bc_add_alu(ctx->bc, &alu);
1451 if (r)
1452 return r;
1453 r = r600_bc_add_literal(ctx->bc,ctx->value);
1454 if (r)
1455 return r;
1456 /* b * LOG2(a) */
1457 memset(&alu, 0, sizeof(struct r600_bc_alu));
1458 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1459 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1460 if (r)
1461 return r;
1462 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1463 alu.src[1].sel = ctx->temp_reg;
1464 alu.dst.sel = ctx->temp_reg;
1465 alu.dst.write = 1;
1466 alu.last = 1;
1467 r = r600_bc_add_alu(ctx->bc, &alu);
1468 if (r)
1469 return r;
1470 r = r600_bc_add_literal(ctx->bc,ctx->value);
1471 if (r)
1472 return r;
1473 /* POW(a,b) = EXP2(b * LOG2(a))*/
1474 memset(&alu, 0, sizeof(struct r600_bc_alu));
1475 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1476 alu.src[0].sel = ctx->temp_reg;
1477 alu.dst.sel = ctx->temp_reg;
1478 alu.dst.write = 1;
1479 alu.last = 1;
1480 r = r600_bc_add_alu(ctx->bc, &alu);
1481 if (r)
1482 return r;
1483 r = r600_bc_add_literal(ctx->bc,ctx->value);
1484 if (r)
1485 return r;
1486 return tgsi_helper_tempx_replicate(ctx);
1487 }
1488
1489 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1490 {
1491 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1492 struct r600_bc_alu alu;
1493 struct r600_bc_alu_src r600_src[3];
1494 int i, r;
1495
1496 r = tgsi_split_constant(ctx, r600_src);
1497 if (r)
1498 return r;
1499 r = tgsi_split_literal_constant(ctx, r600_src);
1500 if (r)
1501 return r;
1502
1503 /* tmp = (src > 0 ? 1 : src) */
1504 for (i = 0; i < 4; i++) {
1505 memset(&alu, 0, sizeof(struct r600_bc_alu));
1506 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1507 alu.is_op3 = 1;
1508
1509 alu.dst.sel = ctx->temp_reg;
1510 alu.dst.chan = i;
1511
1512 alu.src[0] = r600_src[0];
1513 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1514
1515 alu.src[1].sel = V_SQ_ALU_SRC_1;
1516
1517 alu.src[2] = r600_src[0];
1518 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1519 if (i == 3)
1520 alu.last = 1;
1521 r = r600_bc_add_alu(ctx->bc, &alu);
1522 if (r)
1523 return r;
1524 }
1525 r = r600_bc_add_literal(ctx->bc, ctx->value);
1526 if (r)
1527 return r;
1528
1529 /* dst = (-tmp > 0 ? -1 : tmp) */
1530 for (i = 0; i < 4; i++) {
1531 memset(&alu, 0, sizeof(struct r600_bc_alu));
1532 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1533 alu.is_op3 = 1;
1534 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1535 if (r)
1536 return r;
1537
1538 alu.src[0].sel = ctx->temp_reg;
1539 alu.src[0].chan = i;
1540 alu.src[0].neg = 1;
1541
1542 alu.src[1].sel = V_SQ_ALU_SRC_1;
1543 alu.src[1].neg = 1;
1544
1545 alu.src[2].sel = ctx->temp_reg;
1546 alu.src[2].chan = i;
1547
1548 if (i == 3)
1549 alu.last = 1;
1550 r = r600_bc_add_alu(ctx->bc, &alu);
1551 if (r)
1552 return r;
1553 }
1554 return 0;
1555 }
1556
1557 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1558 {
1559 struct r600_bc_alu alu;
1560 int i, r;
1561
1562 r = r600_bc_add_literal(ctx->bc, ctx->value);
1563 if (r)
1564 return r;
1565 for (i = 0; i < 4; i++) {
1566 memset(&alu, 0, sizeof(struct r600_bc_alu));
1567 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1568 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1569 alu.dst.chan = i;
1570 } else {
1571 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1572 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1573 if (r)
1574 return r;
1575 alu.src[0].sel = ctx->temp_reg;
1576 alu.src[0].chan = i;
1577 }
1578 if (i == 3) {
1579 alu.last = 1;
1580 }
1581 r = r600_bc_add_alu(ctx->bc, &alu);
1582 if (r)
1583 return r;
1584 }
1585 return 0;
1586 }
1587
1588 static int tgsi_op3(struct r600_shader_ctx *ctx)
1589 {
1590 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1591 struct r600_bc_alu_src r600_src[3];
1592 struct r600_bc_alu alu;
1593 int i, j, r;
1594
1595 r = tgsi_split_constant(ctx, r600_src);
1596 if (r)
1597 return r;
1598 r = tgsi_split_literal_constant(ctx, r600_src);
1599 if (r)
1600 return r;
1601 /* do it in 2 step as op3 doesn't support writemask */
1602 for (i = 0; i < 4; i++) {
1603 memset(&alu, 0, sizeof(struct r600_bc_alu));
1604 alu.inst = ctx->inst_info->r600_opcode;
1605 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1606 alu.src[j] = r600_src[j];
1607 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1608 }
1609 alu.dst.sel = ctx->temp_reg;
1610 alu.dst.chan = i;
1611 alu.dst.write = 1;
1612 alu.is_op3 = 1;
1613 if (i == 3) {
1614 alu.last = 1;
1615 }
1616 r = r600_bc_add_alu(ctx->bc, &alu);
1617 if (r)
1618 return r;
1619 }
1620 return tgsi_helper_copy(ctx, inst);
1621 }
1622
1623 static int tgsi_dp(struct r600_shader_ctx *ctx)
1624 {
1625 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1626 struct r600_bc_alu_src r600_src[3];
1627 struct r600_bc_alu alu;
1628 int i, j, r;
1629
1630 r = tgsi_split_constant(ctx, r600_src);
1631 if (r)
1632 return r;
1633 r = tgsi_split_literal_constant(ctx, r600_src);
1634 if (r)
1635 return r;
1636 for (i = 0; i < 4; i++) {
1637 memset(&alu, 0, sizeof(struct r600_bc_alu));
1638 alu.inst = ctx->inst_info->r600_opcode;
1639 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1640 alu.src[j] = r600_src[j];
1641 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1642 }
1643 alu.dst.sel = ctx->temp_reg;
1644 alu.dst.chan = i;
1645 alu.dst.write = 1;
1646 /* handle some special cases */
1647 switch (ctx->inst_info->tgsi_opcode) {
1648 case TGSI_OPCODE_DP2:
1649 if (i > 1) {
1650 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1651 alu.src[0].chan = alu.src[1].chan = 0;
1652 }
1653 break;
1654 case TGSI_OPCODE_DP3:
1655 if (i > 2) {
1656 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1657 alu.src[0].chan = alu.src[1].chan = 0;
1658 }
1659 break;
1660 case TGSI_OPCODE_DPH:
1661 if (i == 3) {
1662 alu.src[0].sel = V_SQ_ALU_SRC_1;
1663 alu.src[0].chan = 0;
1664 alu.src[0].neg = 0;
1665 }
1666 break;
1667 default:
1668 break;
1669 }
1670 if (i == 3) {
1671 alu.last = 1;
1672 }
1673 r = r600_bc_add_alu(ctx->bc, &alu);
1674 if (r)
1675 return r;
1676 }
1677 return tgsi_helper_copy(ctx, inst);
1678 }
1679
1680 static int tgsi_tex(struct r600_shader_ctx *ctx)
1681 {
1682 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1683 struct r600_bc_tex tex;
1684 struct r600_bc_alu alu;
1685 unsigned src_gpr;
1686 int r, i;
1687 int opcode;
1688 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1689 uint32_t lit_vals[4];
1690
1691 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1692
1693 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1694 /* Add perspective divide */
1695 memset(&alu, 0, sizeof(struct r600_bc_alu));
1696 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1697 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1698 if (r)
1699 return r;
1700
1701 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1702 alu.dst.sel = ctx->temp_reg;
1703 alu.dst.chan = 3;
1704 alu.last = 1;
1705 alu.dst.write = 1;
1706 r = r600_bc_add_alu(ctx->bc, &alu);
1707 if (r)
1708 return r;
1709
1710 for (i = 0; i < 3; i++) {
1711 memset(&alu, 0, sizeof(struct r600_bc_alu));
1712 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1713 alu.src[0].sel = ctx->temp_reg;
1714 alu.src[0].chan = 3;
1715 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1716 if (r)
1717 return r;
1718 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1719 alu.dst.sel = ctx->temp_reg;
1720 alu.dst.chan = i;
1721 alu.dst.write = 1;
1722 r = r600_bc_add_alu(ctx->bc, &alu);
1723 if (r)
1724 return r;
1725 }
1726 memset(&alu, 0, sizeof(struct r600_bc_alu));
1727 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1728 alu.src[0].sel = V_SQ_ALU_SRC_1;
1729 alu.src[0].chan = 0;
1730 alu.dst.sel = ctx->temp_reg;
1731 alu.dst.chan = 3;
1732 alu.last = 1;
1733 alu.dst.write = 1;
1734 r = r600_bc_add_alu(ctx->bc, &alu);
1735 if (r)
1736 return r;
1737 src_not_temp = FALSE;
1738 src_gpr = ctx->temp_reg;
1739 }
1740
1741 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1742 int src_chan, src2_chan;
1743
1744 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1745 for (i = 0; i < 4; i++) {
1746 memset(&alu, 0, sizeof(struct r600_bc_alu));
1747 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1748 switch (i) {
1749 case 0:
1750 src_chan = 2;
1751 src2_chan = 1;
1752 break;
1753 case 1:
1754 src_chan = 2;
1755 src2_chan = 0;
1756 break;
1757 case 2:
1758 src_chan = 0;
1759 src2_chan = 2;
1760 break;
1761 case 3:
1762 src_chan = 1;
1763 src2_chan = 2;
1764 break;
1765 default:
1766 assert(0);
1767 src_chan = 0;
1768 src2_chan = 0;
1769 break;
1770 }
1771 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1772 if (r)
1773 return r;
1774 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1775 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1776 if (r)
1777 return r;
1778 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1779 alu.dst.sel = ctx->temp_reg;
1780 alu.dst.chan = i;
1781 if (i == 3)
1782 alu.last = 1;
1783 alu.dst.write = 1;
1784 r = r600_bc_add_alu(ctx->bc, &alu);
1785 if (r)
1786 return r;
1787 }
1788
1789 /* tmp1.z = RCP_e(|tmp1.z|) */
1790 memset(&alu, 0, sizeof(struct r600_bc_alu));
1791 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1792 alu.src[0].sel = ctx->temp_reg;
1793 alu.src[0].chan = 2;
1794 alu.src[0].abs = 1;
1795 alu.dst.sel = ctx->temp_reg;
1796 alu.dst.chan = 2;
1797 alu.dst.write = 1;
1798 alu.last = 1;
1799 r = r600_bc_add_alu(ctx->bc, &alu);
1800 if (r)
1801 return r;
1802
1803 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1804 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1805 * muladd has no writemask, have to use another temp
1806 */
1807 memset(&alu, 0, sizeof(struct r600_bc_alu));
1808 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1809 alu.is_op3 = 1;
1810
1811 alu.src[0].sel = ctx->temp_reg;
1812 alu.src[0].chan = 0;
1813 alu.src[1].sel = ctx->temp_reg;
1814 alu.src[1].chan = 2;
1815
1816 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1817 alu.src[2].chan = 0;
1818
1819 alu.dst.sel = ctx->temp_reg;
1820 alu.dst.chan = 0;
1821 alu.dst.write = 1;
1822
1823 r = r600_bc_add_alu(ctx->bc, &alu);
1824 if (r)
1825 return r;
1826
1827 memset(&alu, 0, sizeof(struct r600_bc_alu));
1828 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1829 alu.is_op3 = 1;
1830
1831 alu.src[0].sel = ctx->temp_reg;
1832 alu.src[0].chan = 1;
1833 alu.src[1].sel = ctx->temp_reg;
1834 alu.src[1].chan = 2;
1835
1836 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1837 alu.src[2].chan = 0;
1838
1839 alu.dst.sel = ctx->temp_reg;
1840 alu.dst.chan = 1;
1841 alu.dst.write = 1;
1842
1843 alu.last = 1;
1844 r = r600_bc_add_alu(ctx->bc, &alu);
1845 if (r)
1846 return r;
1847
1848 lit_vals[0] = fui(1.5f);
1849
1850 r = r600_bc_add_literal(ctx->bc, lit_vals);
1851 if (r)
1852 return r;
1853 src_not_temp = FALSE;
1854 src_gpr = ctx->temp_reg;
1855 }
1856
1857 if (src_not_temp) {
1858 for (i = 0; i < 4; i++) {
1859 memset(&alu, 0, sizeof(struct r600_bc_alu));
1860 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1861 alu.src[0].sel = src_gpr;
1862 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1863 alu.dst.sel = ctx->temp_reg;
1864 alu.dst.chan = i;
1865 if (i == 3)
1866 alu.last = 1;
1867 alu.dst.write = 1;
1868 r = r600_bc_add_alu(ctx->bc, &alu);
1869 if (r)
1870 return r;
1871 }
1872 src_gpr = ctx->temp_reg;
1873 }
1874
1875 opcode = ctx->inst_info->r600_opcode;
1876 if (opcode == SQ_TEX_INST_SAMPLE &&
1877 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1878 opcode = SQ_TEX_INST_SAMPLE_C;
1879
1880 memset(&tex, 0, sizeof(struct r600_bc_tex));
1881 tex.inst = opcode;
1882 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1883 tex.resource_id = tex.sampler_id;
1884 tex.src_gpr = src_gpr;
1885 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1886 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1887 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1888 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1889 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1890 tex.src_sel_x = 0;
1891 tex.src_sel_y = 1;
1892 tex.src_sel_z = 2;
1893 tex.src_sel_w = 3;
1894
1895 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1896 tex.src_sel_x = 1;
1897 tex.src_sel_y = 0;
1898 tex.src_sel_z = 3;
1899 tex.src_sel_w = 1;
1900 }
1901
1902 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1903 tex.coord_type_x = 1;
1904 tex.coord_type_y = 1;
1905 tex.coord_type_z = 1;
1906 tex.coord_type_w = 1;
1907 }
1908
1909 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1910 tex.src_sel_w = 2;
1911
1912 r = r600_bc_add_tex(ctx->bc, &tex);
1913 if (r)
1914 return r;
1915
1916 /* add shadow ambient support - gallium doesn't do it yet */
1917 return 0;
1918 }
1919
1920 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1921 {
1922 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1923 struct r600_bc_alu_src r600_src[3];
1924 struct r600_bc_alu alu;
1925 unsigned i;
1926 int r;
1927
1928 r = tgsi_split_constant(ctx, r600_src);
1929 if (r)
1930 return r;
1931 r = tgsi_split_literal_constant(ctx, r600_src);
1932 if (r)
1933 return r;
1934 /* 1 - src0 */
1935 for (i = 0; i < 4; i++) {
1936 memset(&alu, 0, sizeof(struct r600_bc_alu));
1937 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1938 alu.src[0].sel = V_SQ_ALU_SRC_1;
1939 alu.src[0].chan = 0;
1940 alu.src[1] = r600_src[0];
1941 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1942 alu.src[1].neg = 1;
1943 alu.dst.sel = ctx->temp_reg;
1944 alu.dst.chan = i;
1945 if (i == 3) {
1946 alu.last = 1;
1947 }
1948 alu.dst.write = 1;
1949 r = r600_bc_add_alu(ctx->bc, &alu);
1950 if (r)
1951 return r;
1952 }
1953 r = r600_bc_add_literal(ctx->bc, ctx->value);
1954 if (r)
1955 return r;
1956
1957 /* (1 - src0) * src2 */
1958 for (i = 0; i < 4; i++) {
1959 memset(&alu, 0, sizeof(struct r600_bc_alu));
1960 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1961 alu.src[0].sel = ctx->temp_reg;
1962 alu.src[0].chan = i;
1963 alu.src[1] = r600_src[2];
1964 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1965 alu.dst.sel = ctx->temp_reg;
1966 alu.dst.chan = i;
1967 if (i == 3) {
1968 alu.last = 1;
1969 }
1970 alu.dst.write = 1;
1971 r = r600_bc_add_alu(ctx->bc, &alu);
1972 if (r)
1973 return r;
1974 }
1975 r = r600_bc_add_literal(ctx->bc, ctx->value);
1976 if (r)
1977 return r;
1978
1979 /* src0 * src1 + (1 - src0) * src2 */
1980 for (i = 0; i < 4; i++) {
1981 memset(&alu, 0, sizeof(struct r600_bc_alu));
1982 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1983 alu.is_op3 = 1;
1984 alu.src[0] = r600_src[0];
1985 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1986 alu.src[1] = r600_src[1];
1987 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1988 alu.src[2].sel = ctx->temp_reg;
1989 alu.src[2].chan = i;
1990 alu.dst.sel = ctx->temp_reg;
1991 alu.dst.chan = i;
1992 if (i == 3) {
1993 alu.last = 1;
1994 }
1995 r = r600_bc_add_alu(ctx->bc, &alu);
1996 if (r)
1997 return r;
1998 }
1999 return tgsi_helper_copy(ctx, inst);
2000 }
2001
2002 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2003 {
2004 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2005 struct r600_bc_alu_src r600_src[3];
2006 struct r600_bc_alu alu;
2007 int use_temp = 0;
2008 int i, r;
2009
2010 r = tgsi_split_constant(ctx, r600_src);
2011 if (r)
2012 return r;
2013 r = tgsi_split_literal_constant(ctx, r600_src);
2014 if (r)
2015 return r;
2016
2017 if (inst->Dst[0].Register.WriteMask != 0xf)
2018 use_temp = 1;
2019
2020 for (i = 0; i < 4; i++) {
2021 memset(&alu, 0, sizeof(struct r600_bc_alu));
2022 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2023 alu.src[0] = r600_src[0];
2024 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2025
2026 alu.src[1] = r600_src[2];
2027 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2028
2029 alu.src[2] = r600_src[1];
2030 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2031
2032 if (use_temp)
2033 alu.dst.sel = ctx->temp_reg;
2034 else {
2035 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2036 if (r)
2037 return r;
2038 }
2039 alu.dst.chan = i;
2040 alu.dst.write = 1;
2041 alu.is_op3 = 1;
2042 if (i == 3)
2043 alu.last = 1;
2044 r = r600_bc_add_alu(ctx->bc, &alu);
2045 if (r)
2046 return r;
2047 }
2048 if (use_temp)
2049 return tgsi_helper_copy(ctx, inst);
2050 return 0;
2051 }
2052
2053 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2054 {
2055 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2056 struct r600_bc_alu_src r600_src[3];
2057 struct r600_bc_alu alu;
2058 uint32_t use_temp = 0;
2059 int i, r;
2060
2061 if (inst->Dst[0].Register.WriteMask != 0xf)
2062 use_temp = 1;
2063
2064 r = tgsi_split_constant(ctx, r600_src);
2065 if (r)
2066 return r;
2067 r = tgsi_split_literal_constant(ctx, r600_src);
2068 if (r)
2069 return r;
2070
2071 for (i = 0; i < 4; i++) {
2072 memset(&alu, 0, sizeof(struct r600_bc_alu));
2073 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2074
2075 alu.src[0] = r600_src[0];
2076 switch (i) {
2077 case 0:
2078 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2079 break;
2080 case 1:
2081 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2082 break;
2083 case 2:
2084 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2085 break;
2086 case 3:
2087 alu.src[0].sel = V_SQ_ALU_SRC_0;
2088 alu.src[0].chan = i;
2089 }
2090
2091 alu.src[1] = r600_src[1];
2092 switch (i) {
2093 case 0:
2094 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2095 break;
2096 case 1:
2097 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2098 break;
2099 case 2:
2100 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2101 break;
2102 case 3:
2103 alu.src[1].sel = V_SQ_ALU_SRC_0;
2104 alu.src[1].chan = i;
2105 }
2106
2107 alu.dst.sel = ctx->temp_reg;
2108 alu.dst.chan = i;
2109 alu.dst.write = 1;
2110
2111 if (i == 3)
2112 alu.last = 1;
2113 r = r600_bc_add_alu(ctx->bc, &alu);
2114 if (r)
2115 return r;
2116
2117 r = r600_bc_add_literal(ctx->bc, ctx->value);
2118 if (r)
2119 return r;
2120 }
2121
2122 for (i = 0; i < 4; i++) {
2123 memset(&alu, 0, sizeof(struct r600_bc_alu));
2124 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2125
2126 alu.src[0] = r600_src[0];
2127 switch (i) {
2128 case 0:
2129 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2130 break;
2131 case 1:
2132 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2133 break;
2134 case 2:
2135 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2136 break;
2137 case 3:
2138 alu.src[0].sel = V_SQ_ALU_SRC_0;
2139 alu.src[0].chan = i;
2140 }
2141
2142 alu.src[1] = r600_src[1];
2143 switch (i) {
2144 case 0:
2145 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2146 break;
2147 case 1:
2148 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2149 break;
2150 case 2:
2151 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2152 break;
2153 case 3:
2154 alu.src[1].sel = V_SQ_ALU_SRC_0;
2155 alu.src[1].chan = i;
2156 }
2157
2158 alu.src[2].sel = ctx->temp_reg;
2159 alu.src[2].neg = 1;
2160 alu.src[2].chan = i;
2161
2162 if (use_temp)
2163 alu.dst.sel = ctx->temp_reg;
2164 else {
2165 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2166 if (r)
2167 return r;
2168 }
2169 alu.dst.chan = i;
2170 alu.dst.write = 1;
2171 alu.is_op3 = 1;
2172 if (i == 3)
2173 alu.last = 1;
2174 r = r600_bc_add_alu(ctx->bc, &alu);
2175 if (r)
2176 return r;
2177
2178 r = r600_bc_add_literal(ctx->bc, ctx->value);
2179 if (r)
2180 return r;
2181 }
2182 if (use_temp)
2183 return tgsi_helper_copy(ctx, inst);
2184 return 0;
2185 }
2186
2187 static int tgsi_exp(struct r600_shader_ctx *ctx)
2188 {
2189 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2190 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2191 struct r600_bc_alu alu;
2192 int r;
2193
2194 /* result.x = 2^floor(src); */
2195 if (inst->Dst[0].Register.WriteMask & 1) {
2196 memset(&alu, 0, sizeof(struct r600_bc_alu));
2197
2198 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2199 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2200 if (r)
2201 return r;
2202
2203 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2204
2205 alu.dst.sel = ctx->temp_reg;
2206 alu.dst.chan = 0;
2207 alu.dst.write = 1;
2208 alu.last = 1;
2209 r = r600_bc_add_alu(ctx->bc, &alu);
2210 if (r)
2211 return r;
2212
2213 r = r600_bc_add_literal(ctx->bc, ctx->value);
2214 if (r)
2215 return r;
2216
2217 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2218 alu.src[0].sel = ctx->temp_reg;
2219 alu.src[0].chan = 0;
2220
2221 alu.dst.sel = ctx->temp_reg;
2222 alu.dst.chan = 0;
2223 alu.dst.write = 1;
2224 alu.last = 1;
2225 r = r600_bc_add_alu(ctx->bc, &alu);
2226 if (r)
2227 return r;
2228
2229 r = r600_bc_add_literal(ctx->bc, ctx->value);
2230 if (r)
2231 return r;
2232 }
2233
2234 /* result.y = tmp - floor(tmp); */
2235 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2236 memset(&alu, 0, sizeof(struct r600_bc_alu));
2237
2238 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2239 alu.src[0] = r600_src[0];
2240 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2241 if (r)
2242 return r;
2243 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2244
2245 alu.dst.sel = ctx->temp_reg;
2246 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2247 // if (r)
2248 // return r;
2249 alu.dst.write = 1;
2250 alu.dst.chan = 1;
2251
2252 alu.last = 1;
2253
2254 r = r600_bc_add_alu(ctx->bc, &alu);
2255 if (r)
2256 return r;
2257 r = r600_bc_add_literal(ctx->bc, ctx->value);
2258 if (r)
2259 return r;
2260 }
2261
2262 /* result.z = RoughApprox2ToX(tmp);*/
2263 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2264 memset(&alu, 0, sizeof(struct r600_bc_alu));
2265 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2266 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2267 if (r)
2268 return r;
2269 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2270
2271 alu.dst.sel = ctx->temp_reg;
2272 alu.dst.write = 1;
2273 alu.dst.chan = 2;
2274
2275 alu.last = 1;
2276
2277 r = r600_bc_add_alu(ctx->bc, &alu);
2278 if (r)
2279 return r;
2280 r = r600_bc_add_literal(ctx->bc, ctx->value);
2281 if (r)
2282 return r;
2283 }
2284
2285 /* result.w = 1.0;*/
2286 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2287 memset(&alu, 0, sizeof(struct r600_bc_alu));
2288
2289 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2290 alu.src[0].sel = V_SQ_ALU_SRC_1;
2291 alu.src[0].chan = 0;
2292
2293 alu.dst.sel = ctx->temp_reg;
2294 alu.dst.chan = 3;
2295 alu.dst.write = 1;
2296 alu.last = 1;
2297 r = r600_bc_add_alu(ctx->bc, &alu);
2298 if (r)
2299 return r;
2300 r = r600_bc_add_literal(ctx->bc, ctx->value);
2301 if (r)
2302 return r;
2303 }
2304 return tgsi_helper_copy(ctx, inst);
2305 }
2306
2307 static int tgsi_log(struct r600_shader_ctx *ctx)
2308 {
2309 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2310 struct r600_bc_alu alu;
2311 int r;
2312
2313 /* result.x = floor(log2(src)); */
2314 if (inst->Dst[0].Register.WriteMask & 1) {
2315 memset(&alu, 0, sizeof(struct r600_bc_alu));
2316
2317 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2318 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2319 if (r)
2320 return r;
2321
2322 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2323
2324 alu.dst.sel = ctx->temp_reg;
2325 alu.dst.chan = 0;
2326 alu.dst.write = 1;
2327 alu.last = 1;
2328 r = r600_bc_add_alu(ctx->bc, &alu);
2329 if (r)
2330 return r;
2331
2332 r = r600_bc_add_literal(ctx->bc, ctx->value);
2333 if (r)
2334 return r;
2335
2336 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2337 alu.src[0].sel = ctx->temp_reg;
2338 alu.src[0].chan = 0;
2339
2340 alu.dst.sel = ctx->temp_reg;
2341 alu.dst.chan = 0;
2342 alu.dst.write = 1;
2343 alu.last = 1;
2344
2345 r = r600_bc_add_alu(ctx->bc, &alu);
2346 if (r)
2347 return r;
2348
2349 r = r600_bc_add_literal(ctx->bc, ctx->value);
2350 if (r)
2351 return r;
2352 }
2353
2354 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2355 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2356 memset(&alu, 0, sizeof(struct r600_bc_alu));
2357
2358 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2359 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2360 if (r)
2361 return r;
2362
2363 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2364
2365 alu.dst.sel = ctx->temp_reg;
2366 alu.dst.chan = 1;
2367 alu.dst.write = 1;
2368 alu.last = 1;
2369
2370 r = r600_bc_add_alu(ctx->bc, &alu);
2371 if (r)
2372 return r;
2373
2374 r = r600_bc_add_literal(ctx->bc, ctx->value);
2375 if (r)
2376 return r;
2377
2378 memset(&alu, 0, sizeof(struct r600_bc_alu));
2379
2380 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2381 alu.src[0].sel = ctx->temp_reg;
2382 alu.src[0].chan = 1;
2383
2384 alu.dst.sel = ctx->temp_reg;
2385 alu.dst.chan = 1;
2386 alu.dst.write = 1;
2387 alu.last = 1;
2388
2389 r = r600_bc_add_alu(ctx->bc, &alu);
2390 if (r)
2391 return r;
2392
2393 r = r600_bc_add_literal(ctx->bc, ctx->value);
2394 if (r)
2395 return r;
2396
2397 memset(&alu, 0, sizeof(struct r600_bc_alu));
2398
2399 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2400 alu.src[0].sel = ctx->temp_reg;
2401 alu.src[0].chan = 1;
2402
2403 alu.dst.sel = ctx->temp_reg;
2404 alu.dst.chan = 1;
2405 alu.dst.write = 1;
2406 alu.last = 1;
2407
2408 r = r600_bc_add_alu(ctx->bc, &alu);
2409 if (r)
2410 return r;
2411
2412 r = r600_bc_add_literal(ctx->bc, ctx->value);
2413 if (r)
2414 return r;
2415
2416 memset(&alu, 0, sizeof(struct r600_bc_alu));
2417
2418 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2419 alu.src[0].sel = ctx->temp_reg;
2420 alu.src[0].chan = 1;
2421
2422 alu.dst.sel = ctx->temp_reg;
2423 alu.dst.chan = 1;
2424 alu.dst.write = 1;
2425 alu.last = 1;
2426
2427 r = r600_bc_add_alu(ctx->bc, &alu);
2428 if (r)
2429 return r;
2430
2431 r = r600_bc_add_literal(ctx->bc, ctx->value);
2432 if (r)
2433 return r;
2434
2435 memset(&alu, 0, sizeof(struct r600_bc_alu));
2436
2437 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2438
2439 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2440 if (r)
2441 return r;
2442
2443 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2444
2445 alu.src[1].sel = ctx->temp_reg;
2446 alu.src[1].chan = 1;
2447
2448 alu.dst.sel = ctx->temp_reg;
2449 alu.dst.chan = 1;
2450 alu.dst.write = 1;
2451 alu.last = 1;
2452
2453 r = r600_bc_add_alu(ctx->bc, &alu);
2454 if (r)
2455 return r;
2456
2457 r = r600_bc_add_literal(ctx->bc, ctx->value);
2458 if (r)
2459 return r;
2460 }
2461
2462 /* result.z = log2(src);*/
2463 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2464 memset(&alu, 0, sizeof(struct r600_bc_alu));
2465
2466 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2467 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2468 if (r)
2469 return r;
2470
2471 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2472
2473 alu.dst.sel = ctx->temp_reg;
2474 alu.dst.write = 1;
2475 alu.dst.chan = 2;
2476 alu.last = 1;
2477
2478 r = r600_bc_add_alu(ctx->bc, &alu);
2479 if (r)
2480 return r;
2481
2482 r = r600_bc_add_literal(ctx->bc, ctx->value);
2483 if (r)
2484 return r;
2485 }
2486
2487 /* result.w = 1.0; */
2488 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2489 memset(&alu, 0, sizeof(struct r600_bc_alu));
2490
2491 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2492 alu.src[0].sel = V_SQ_ALU_SRC_1;
2493 alu.src[0].chan = 0;
2494
2495 alu.dst.sel = ctx->temp_reg;
2496 alu.dst.chan = 3;
2497 alu.dst.write = 1;
2498 alu.last = 1;
2499
2500 r = r600_bc_add_alu(ctx->bc, &alu);
2501 if (r)
2502 return r;
2503
2504 r = r600_bc_add_literal(ctx->bc, ctx->value);
2505 if (r)
2506 return r;
2507 }
2508
2509 return tgsi_helper_copy(ctx, inst);
2510 }
2511
2512 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2513 {
2514 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2515 struct r600_bc_alu alu;
2516 int r;
2517 memset(&alu, 0, sizeof(struct r600_bc_alu));
2518
2519 switch (inst->Instruction.Opcode) {
2520 case TGSI_OPCODE_ARL:
2521 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2522 break;
2523 case TGSI_OPCODE_ARR:
2524 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2525 break;
2526 default:
2527 assert(0);
2528 return -1;
2529 }
2530
2531 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2532 if (r)
2533 return r;
2534 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2535 alu.last = 1;
2536 alu.dst.chan = 0;
2537 alu.dst.sel = ctx->temp_reg;
2538 alu.dst.write = 1;
2539 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2540 if (r)
2541 return r;
2542 memset(&alu, 0, sizeof(struct r600_bc_alu));
2543 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2544 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2545 if (r)
2546 return r;
2547 alu.src[0].sel = ctx->temp_reg;
2548 alu.src[0].chan = 0;
2549 alu.last = 1;
2550 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2551 if (r)
2552 return r;
2553 return 0;
2554 }
2555 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2556 {
2557 /* TODO from r600c, ar values don't persist between clauses */
2558 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2559 struct r600_bc_alu alu;
2560 int r;
2561 memset(&alu, 0, sizeof(struct r600_bc_alu));
2562
2563 switch (inst->Instruction.Opcode) {
2564 case TGSI_OPCODE_ARL:
2565 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2566 break;
2567 case TGSI_OPCODE_ARR:
2568 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2569 break;
2570 default:
2571 assert(0);
2572 return -1;
2573 }
2574
2575
2576 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2577 if (r)
2578 return r;
2579 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2580
2581 alu.last = 1;
2582
2583 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2584 if (r)
2585 return r;
2586 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2587 return 0;
2588 }
2589
2590 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2591 {
2592 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2593 struct r600_bc_alu alu;
2594 int i, r = 0;
2595
2596 for (i = 0; i < 4; i++) {
2597 memset(&alu, 0, sizeof(struct r600_bc_alu));
2598
2599 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2600 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2601 if (r)
2602 return r;
2603
2604 if (i == 0 || i == 3) {
2605 alu.src[0].sel = V_SQ_ALU_SRC_1;
2606 } else {
2607 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2608 if (r)
2609 return r;
2610 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2611 }
2612
2613 if (i == 0 || i == 2) {
2614 alu.src[1].sel = V_SQ_ALU_SRC_1;
2615 } else {
2616 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2617 if (r)
2618 return r;
2619 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2620 }
2621 if (i == 3)
2622 alu.last = 1;
2623 r = r600_bc_add_alu(ctx->bc, &alu);
2624 if (r)
2625 return r;
2626 }
2627 return 0;
2628 }
2629
2630 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2631 {
2632 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2633 struct r600_bc_alu alu;
2634 int r;
2635
2636 memset(&alu, 0, sizeof(struct r600_bc_alu));
2637 alu.inst = opcode;
2638 alu.predicate = 1;
2639
2640 alu.dst.sel = ctx->temp_reg;
2641 alu.dst.write = 1;
2642 alu.dst.chan = 0;
2643
2644 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2645 if (r)
2646 return r;
2647 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2648 alu.src[1].sel = V_SQ_ALU_SRC_0;
2649 alu.src[1].chan = 0;
2650
2651 alu.last = 1;
2652
2653 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2654 if (r)
2655 return r;
2656 return 0;
2657 }
2658
2659 static int pops(struct r600_shader_ctx *ctx, int pops)
2660 {
2661 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2662 ctx->bc->cf_last->pop_count = pops;
2663 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2664 return 0;
2665 }
2666
2667 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2668 {
2669 switch(reason) {
2670 case FC_PUSH_VPM:
2671 ctx->bc->callstack[ctx->bc->call_sp].current--;
2672 break;
2673 case FC_PUSH_WQM:
2674 case FC_LOOP:
2675 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2676 break;
2677 case FC_REP:
2678 /* TOODO : for 16 vp asic should -= 2; */
2679 ctx->bc->callstack[ctx->bc->call_sp].current --;
2680 break;
2681 }
2682 }
2683
2684 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2685 {
2686 if (check_max_only) {
2687 int diff;
2688 switch (reason) {
2689 case FC_PUSH_VPM:
2690 diff = 1;
2691 break;
2692 case FC_PUSH_WQM:
2693 diff = 4;
2694 break;
2695 default:
2696 assert(0);
2697 diff = 0;
2698 }
2699 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2700 ctx->bc->callstack[ctx->bc->call_sp].max) {
2701 ctx->bc->callstack[ctx->bc->call_sp].max =
2702 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2703 }
2704 return;
2705 }
2706 switch (reason) {
2707 case FC_PUSH_VPM:
2708 ctx->bc->callstack[ctx->bc->call_sp].current++;
2709 break;
2710 case FC_PUSH_WQM:
2711 case FC_LOOP:
2712 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2713 break;
2714 case FC_REP:
2715 ctx->bc->callstack[ctx->bc->call_sp].current++;
2716 break;
2717 }
2718
2719 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2720 ctx->bc->callstack[ctx->bc->call_sp].max) {
2721 ctx->bc->callstack[ctx->bc->call_sp].max =
2722 ctx->bc->callstack[ctx->bc->call_sp].current;
2723 }
2724 }
2725
2726 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2727 {
2728 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2729
2730 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2731 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2732 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2733 sp->num_mid++;
2734 }
2735
2736 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2737 {
2738 ctx->bc->fc_sp++;
2739 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2740 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2741 }
2742
2743 static void fc_poplevel(struct r600_shader_ctx *ctx)
2744 {
2745 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2746 if (sp->mid) {
2747 free(sp->mid);
2748 sp->mid = NULL;
2749 }
2750 sp->num_mid = 0;
2751 sp->start = NULL;
2752 sp->type = 0;
2753 ctx->bc->fc_sp--;
2754 }
2755
2756 #if 0
2757 static int emit_return(struct r600_shader_ctx *ctx)
2758 {
2759 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2760 return 0;
2761 }
2762
2763 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2764 {
2765
2766 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2767 ctx->bc->cf_last->pop_count = pops;
2768 /* TODO work out offset */
2769 return 0;
2770 }
2771
2772 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2773 {
2774 return 0;
2775 }
2776
2777 static void emit_testflag(struct r600_shader_ctx *ctx)
2778 {
2779
2780 }
2781
2782 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2783 {
2784 emit_testflag(ctx);
2785 emit_jump_to_offset(ctx, 1, 4);
2786 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2787 pops(ctx, ifidx + 1);
2788 emit_return(ctx);
2789 }
2790
2791 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2792 {
2793 emit_testflag(ctx);
2794
2795 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2796 ctx->bc->cf_last->pop_count = 1;
2797
2798 fc_set_mid(ctx, fc_sp);
2799
2800 pops(ctx, 1);
2801 }
2802 #endif
2803
2804 static int tgsi_if(struct r600_shader_ctx *ctx)
2805 {
2806 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2807
2808 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2809
2810 fc_pushlevel(ctx, FC_IF);
2811
2812 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2813 return 0;
2814 }
2815
2816 static int tgsi_else(struct r600_shader_ctx *ctx)
2817 {
2818 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2819 ctx->bc->cf_last->pop_count = 1;
2820
2821 fc_set_mid(ctx, ctx->bc->fc_sp);
2822 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2823 return 0;
2824 }
2825
2826 static int tgsi_endif(struct r600_shader_ctx *ctx)
2827 {
2828 pops(ctx, 1);
2829 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2830 R600_ERR("if/endif unbalanced in shader\n");
2831 return -1;
2832 }
2833
2834 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2835 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2836 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2837 } else {
2838 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2839 }
2840 fc_poplevel(ctx);
2841
2842 callstack_decrease_current(ctx, FC_PUSH_VPM);
2843 return 0;
2844 }
2845
2846 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2847 {
2848 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2849
2850 fc_pushlevel(ctx, FC_LOOP);
2851
2852 /* check stack depth */
2853 callstack_check_depth(ctx, FC_LOOP, 0);
2854 return 0;
2855 }
2856
2857 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2858 {
2859 int i;
2860
2861 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2862
2863 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2864 R600_ERR("loop/endloop in shader code are not paired.\n");
2865 return -EINVAL;
2866 }
2867
2868 /* fixup loop pointers - from r600isa
2869 LOOP END points to CF after LOOP START,
2870 LOOP START point to CF after LOOP END
2871 BRK/CONT point to LOOP END CF
2872 */
2873 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2874
2875 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2876
2877 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2878 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2879 }
2880 /* TODO add LOOPRET support */
2881 fc_poplevel(ctx);
2882 callstack_decrease_current(ctx, FC_LOOP);
2883 return 0;
2884 }
2885
2886 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2887 {
2888 unsigned int fscp;
2889
2890 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2891 {
2892 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2893 break;
2894 }
2895
2896 if (fscp == 0) {
2897 R600_ERR("Break not inside loop/endloop pair\n");
2898 return -EINVAL;
2899 }
2900
2901 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2902 ctx->bc->cf_last->pop_count = 1;
2903
2904 fc_set_mid(ctx, fscp);
2905
2906 pops(ctx, 1);
2907 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2908 return 0;
2909 }
2910
2911 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2912 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2913 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2914 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2915
2916 /* FIXME:
2917 * For state trackers other than OpenGL, we'll want to use
2918 * _RECIP_IEEE instead.
2919 */
2920 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2921
2922 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2923 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2924 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2925 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2926 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2927 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2928 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2929 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2930 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2931 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2932 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2933 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2934 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2935 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2936 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2937 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 /* gap */
2939 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 /* gap */
2942 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2945 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2947 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2949 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2950 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2951 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2952 /* gap */
2953 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2955 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2957 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2958 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2959 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2960 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2961 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2967 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2969 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2970 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2971 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2972 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2974 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2976 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2983 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2987 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2988 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2989 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2990 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2993 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2994 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2995 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2996 /* gap */
2997 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3000 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3001 /* gap */
3002 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3010 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 /* gap */
3012 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3021 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3024 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3026 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 /* gap */
3028 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 /* gap */
3034 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3041 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3042 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3043 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3044 /* gap */
3045 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3051 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3056 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 };
3074
3075 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3076 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3077 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3078 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3079 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3080 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3081 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3082 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3084 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3085 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3086 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3087 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3088 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3089 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3090 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3091 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3092 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3093 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3094 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3095 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 /* gap */
3097 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 /* gap */
3100 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3103 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3105 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3107 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3108 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3109 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3110 /* gap */
3111 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3113 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3115 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3116 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3117 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3118 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3119 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3125 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3127 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3128 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3129 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3130 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3132 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3134 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3141 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3145 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3146 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3147 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3148 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3151 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3152 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3153 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3154 /* gap */
3155 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3158 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3159 /* gap */
3160 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3168 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 /* gap */
3170 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3179 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3180 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3182 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3183 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3184 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3185 /* gap */
3186 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3187 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3188 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3189 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3190 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3191 /* gap */
3192 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3193 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3194 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3195 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3196 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3197 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3198 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3199 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3200 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3201 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3202 /* gap */
3203 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3204 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3205 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3206 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3207 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3208 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3209 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3210 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3211 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3212 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3213 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3214 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3215 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3216 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3217 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3218 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3219 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3220 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3221 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3222 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3223 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3224 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3225 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3226 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3227 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3228 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3229 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3230 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3231 };