projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: add support for geom shaders to r600/r700 chipsets (v2)
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_context *rctx,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static void r600_dump_streamout(struct pipe_stream_output_info *so)
88 {
89 unsigned i;
90
91 fprintf(stderr, "STREAMOUT\n");
92 for (i = 0; i < so->num_outputs; i++) {
93 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
94 so->output[i].start_component;
95 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
96 i, so->output[i].output_buffer,
97 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
98 so->output[i].register_index,
99 mask & 1 ? "x" : "",
100 mask & 2 ? "y" : "",
101 mask & 4 ? "z" : "",
102 mask & 8 ? "w" : "",
103 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
104 }
105 }
106
107 static int store_shader(struct pipe_context *ctx,
108 struct r600_pipe_shader *shader)
109 {
110 struct r600_context *rctx = (struct r600_context *)ctx;
111 uint32_t *ptr, i;
112
113 if (shader->bo == NULL) {
114 shader->bo = (struct r600_resource*)
115 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
116 if (shader->bo == NULL) {
117 return -ENOMEM;
118 }
119 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
120 if (R600_BIG_ENDIAN) {
121 for (i = 0; i < shader->shader.bc.ndw; ++i) {
122 ptr[i] = util_bswap32(shader->shader.bc.bytecode[i]);
123 }
124 } else {
125 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
126 }
127 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
128 }
129
130 return 0;
131 }
132
133 int r600_pipe_shader_create(struct pipe_context *ctx,
134 struct r600_pipe_shader *shader,
135 struct r600_shader_key key)
136 {
137 struct r600_context *rctx = (struct r600_context *)ctx;
138 struct r600_pipe_shader_selector *sel = shader->selector;
139 int r;
140 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
141 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
142 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
143 unsigned export_shader = key.vs_as_es;
144
145 shader->shader.bc.isa = rctx->isa;
146
147 if (dump) {
148 fprintf(stderr, "--------------------------------------------------------------\n");
149 tgsi_dump(sel->tokens, 0);
150
151 if (sel->so.num_outputs) {
152 r600_dump_streamout(&sel->so);
153 }
154 }
155 r = r600_shader_from_tgsi(rctx, shader, key);
156 if (r) {
157 R600_ERR("translation from TGSI failed !\n");
158 return r;
159 }
160
161 /* disable SB for geom shaders - it can't handle the CF_EMIT instructions */
162 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_GEOMETRY);
163
164 /* Check if the bytecode has already been built. When using the llvm
165 * backend, r600_shader_from_tgsi() will take care of building the
166 * bytecode.
167 */
168 if (!shader->shader.bc.bytecode) {
169 r = r600_bytecode_build(&shader->shader.bc);
170 if (r) {
171 R600_ERR("building bytecode failed !\n");
172 return r;
173 }
174 }
175
176 if (dump && !sb_disasm) {
177 fprintf(stderr, "--------------------------------------------------------------\n");
178 r600_bytecode_disasm(&shader->shader.bc);
179 fprintf(stderr, "______________________________________________________________\n");
180 } else if ((dump && sb_disasm) || use_sb) {
181 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
182 dump, use_sb);
183 if (r) {
184 R600_ERR("r600_sb_bytecode_process failed !\n");
185 return r;
186 }
187 }
188
189 if (shader->gs_copy_shader) {
190 if (dump) {
191 // dump copy shader
192 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
193 &shader->gs_copy_shader->shader, dump, 0);
194 if (r)
195 return r;
196 }
197
198 if ((r = store_shader(ctx, shader->gs_copy_shader)))
199 return r;
200 }
201
202 /* Store the shader in a buffer. */
203 if ((r = store_shader(ctx, shader)))
204 return r;
205
206 /* Build state. */
207 switch (shader->shader.processor_type) {
208 case TGSI_PROCESSOR_GEOMETRY:
209 if (rctx->b.chip_class >= EVERGREEN) {
210 evergreen_update_gs_state(ctx, shader);
211 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
212 } else {
213 r600_update_gs_state(ctx, shader);
214 r600_update_vs_state(ctx, shader->gs_copy_shader);
215 }
216 break;
217 case TGSI_PROCESSOR_VERTEX:
218 if (rctx->b.chip_class >= EVERGREEN) {
219 if (export_shader)
220 evergreen_update_es_state(ctx, shader);
221 else
222 evergreen_update_vs_state(ctx, shader);
223 } else {
224 if (export_shader)
225 r600_update_es_state(ctx, shader);
226 else
227 r600_update_vs_state(ctx, shader);
228 }
229 break;
230 case TGSI_PROCESSOR_FRAGMENT:
231 if (rctx->b.chip_class >= EVERGREEN) {
232 evergreen_update_ps_state(ctx, shader);
233 } else {
234 r600_update_ps_state(ctx, shader);
235 }
236 break;
237 default:
238 return -EINVAL;
239 }
240 return 0;
241 }
242
243 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
244 {
245 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
246 r600_bytecode_clear(&shader->shader.bc);
247 r600_release_command_buffer(&shader->command_buffer);
248 }
249
250 /*
251 * tgsi -> r600 shader
252 */
253 struct r600_shader_tgsi_instruction;
254
255 struct r600_shader_src {
256 unsigned sel;
257 unsigned swizzle[4];
258 unsigned neg;
259 unsigned abs;
260 unsigned rel;
261 unsigned kc_bank;
262 uint32_t value[4];
263 };
264
265 struct r600_shader_ctx {
266 struct tgsi_shader_info info;
267 struct tgsi_parse_context parse;
268 const struct tgsi_token *tokens;
269 unsigned type;
270 unsigned file_offset[TGSI_FILE_COUNT];
271 unsigned temp_reg;
272 struct r600_shader_tgsi_instruction *inst_info;
273 struct r600_bytecode *bc;
274 struct r600_shader *shader;
275 struct r600_shader_src src[4];
276 uint32_t *literals;
277 uint32_t nliterals;
278 uint32_t max_driver_temp_used;
279 boolean use_llvm;
280 /* needed for evergreen interpolation */
281 boolean input_centroid;
282 boolean input_linear;
283 boolean input_perspective;
284 int num_interp_gpr;
285 int face_gpr;
286 int colors_used;
287 boolean clip_vertex_write;
288 unsigned cv_output;
289 int fragcoord_input;
290 int native_integers;
291 int next_ring_offset;
292 int gs_out_ring_offset;
293 int gs_next_vertex;
294 struct r600_shader *gs_for_vs;
295 int gs_export_gpr_treg;
296 };
297
298 struct r600_shader_tgsi_instruction {
299 unsigned tgsi_opcode;
300 unsigned is_op3;
301 unsigned op;
302 int (*process)(struct r600_shader_ctx *ctx);
303 };
304
305 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind);
306 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
307 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
308 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
309 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
310 static int tgsi_else(struct r600_shader_ctx *ctx);
311 static int tgsi_endif(struct r600_shader_ctx *ctx);
312 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
313 static int tgsi_endloop(struct r600_shader_ctx *ctx);
314 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
315
316 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
317 {
318 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
319 int j;
320
321 if (i->Instruction.NumDstRegs > 1) {
322 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
323 return -EINVAL;
324 }
325 if (i->Instruction.Predicate) {
326 R600_ERR("predicate unsupported\n");
327 return -EINVAL;
328 }
329 #if 0
330 if (i->Instruction.Label) {
331 R600_ERR("label unsupported\n");
332 return -EINVAL;
333 }
334 #endif
335 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
336 if (i->Src[j].Register.Dimension) {
337 switch (i->Src[j].Register.File) {
338 case TGSI_FILE_CONSTANT:
339 break;
340 case TGSI_FILE_INPUT:
341 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
342 break;
343 default:
344 R600_ERR("unsupported src %d (dimension %d)\n", j,
345 i->Src[j].Register.Dimension);
346 return -EINVAL;
347 }
348 }
349 }
350 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
351 if (i->Dst[j].Register.Dimension) {
352 R600_ERR("unsupported dst (dimension)\n");
353 return -EINVAL;
354 }
355 }
356 return 0;
357 }
358
359 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
360 int input)
361 {
362 int ij_index = 0;
363
364 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
365 if (ctx->shader->input[input].centroid)
366 ij_index++;
367 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
368 /* if we have perspective add one */
369 if (ctx->input_perspective) {
370 ij_index++;
371 /* if we have perspective centroid */
372 if (ctx->input_centroid)
373 ij_index++;
374 }
375 if (ctx->shader->input[input].centroid)
376 ij_index++;
377 }
378
379 ctx->shader->input[input].ij_index = ij_index;
380 }
381
382 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
383 {
384 int i, r;
385 struct r600_bytecode_alu alu;
386 int gpr = 0, base_chan = 0;
387 int ij_index = ctx->shader->input[input].ij_index;
388
389 /* work out gpr and base_chan from index */
390 gpr = ij_index / 2;
391 base_chan = (2 * (ij_index % 2)) + 1;
392
393 for (i = 0; i < 8; i++) {
394 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
395
396 if (i < 4)
397 alu.op = ALU_OP2_INTERP_ZW;
398 else
399 alu.op = ALU_OP2_INTERP_XY;
400
401 if ((i > 1) && (i < 6)) {
402 alu.dst.sel = ctx->shader->input[input].gpr;
403 alu.dst.write = 1;
404 }
405
406 alu.dst.chan = i % 4;
407
408 alu.src[0].sel = gpr;
409 alu.src[0].chan = (base_chan - (i % 2));
410
411 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
412
413 alu.bank_swizzle_force = SQ_ALU_VEC_210;
414 if ((i % 4) == 3)
415 alu.last = 1;
416 r = r600_bytecode_add_alu(ctx->bc, &alu);
417 if (r)
418 return r;
419 }
420 return 0;
421 }
422
423 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
424 {
425 int i, r;
426 struct r600_bytecode_alu alu;
427
428 for (i = 0; i < 4; i++) {
429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
430
431 alu.op = ALU_OP1_INTERP_LOAD_P0;
432
433 alu.dst.sel = ctx->shader->input[input].gpr;
434 alu.dst.write = 1;
435
436 alu.dst.chan = i;
437
438 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
439 alu.src[0].chan = i;
440
441 if (i == 3)
442 alu.last = 1;
443 r = r600_bytecode_add_alu(ctx->bc, &alu);
444 if (r)
445 return r;
446 }
447 return 0;
448 }
449
450 /*
451 * Special export handling in shaders
452 *
453 * shader export ARRAY_BASE for EXPORT_POS:
454 * 60 is position
455 * 61 is misc vector
456 * 62, 63 are clip distance vectors
457 *
458 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
459 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
460 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
461 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
462 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
463 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
464 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
465 * exclusive from render target index)
466 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
467 *
468 *
469 * shader export ARRAY_BASE for EXPORT_PIXEL:
470 * 0-7 CB targets
471 * 61 computed Z vector
472 *
473 * The use of the values exported in the computed Z vector are controlled
474 * by DB_SHADER_CONTROL:
475 * Z_EXPORT_ENABLE - Z as a float in RED
476 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
477 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
478 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
479 * DB_SOURCE_FORMAT - export control restrictions
480 *
481 */
482
483
484 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
485 static int r600_spi_sid(struct r600_shader_io * io)
486 {
487 int index, name = io->name;
488
489 /* These params are handled differently, they don't need
490 * semantic indices, so we'll use 0 for them.
491 */
492 if (name == TGSI_SEMANTIC_POSITION ||
493 name == TGSI_SEMANTIC_PSIZE ||
494 name == TGSI_SEMANTIC_LAYER ||
495 name == TGSI_SEMANTIC_FACE)
496 index = 0;
497 else {
498 if (name == TGSI_SEMANTIC_GENERIC) {
499 /* For generic params simply use sid from tgsi */
500 index = io->sid;
501 } else {
502 /* For non-generic params - pack name and sid into 8 bits */
503 index = 0x80 | (name<<3) | (io->sid);
504 }
505
506 /* Make sure that all really used indices have nonzero value, so
507 * we can just compare it to 0 later instead of comparing the name
508 * with different values to detect special cases. */
509 index++;
510 }
511
512 return index;
513 };
514
515 /* turn input into interpolate on EG */
516 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
517 {
518 int r = 0;
519
520 if (ctx->shader->input[index].spi_sid) {
521 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
522 if (ctx->shader->input[index].interpolate > 0) {
523 evergreen_interp_assign_ij_index(ctx, index);
524 if (!ctx->use_llvm)
525 r = evergreen_interp_alu(ctx, index);
526 } else {
527 if (!ctx->use_llvm)
528 r = evergreen_interp_flat(ctx, index);
529 }
530 }
531 return r;
532 }
533
534 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
535 {
536 struct r600_bytecode_alu alu;
537 int i, r;
538 int gpr_front = ctx->shader->input[front].gpr;
539 int gpr_back = ctx->shader->input[back].gpr;
540
541 for (i = 0; i < 4; i++) {
542 memset(&alu, 0, sizeof(alu));
543 alu.op = ALU_OP3_CNDGT;
544 alu.is_op3 = 1;
545 alu.dst.write = 1;
546 alu.dst.sel = gpr_front;
547 alu.src[0].sel = ctx->face_gpr;
548 alu.src[1].sel = gpr_front;
549 alu.src[2].sel = gpr_back;
550
551 alu.dst.chan = i;
552 alu.src[1].chan = i;
553 alu.src[2].chan = i;
554 alu.last = (i==3);
555
556 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
557 return r;
558 }
559
560 return 0;
561 }
562
563 static int tgsi_declaration(struct r600_shader_ctx *ctx)
564 {
565 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
566 int r, i, j, count = d->Range.Last - d->Range.First + 1;
567
568 switch (d->Declaration.File) {
569 case TGSI_FILE_INPUT:
570 i = ctx->shader->ninput;
571 assert(i < Elements(ctx->shader->input));
572 ctx->shader->ninput += count;
573 ctx->shader->input[i].name = d->Semantic.Name;
574 ctx->shader->input[i].sid = d->Semantic.Index;
575 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
576 ctx->shader->input[i].centroid = d->Interp.Centroid;
577 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
578 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
579 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
580 switch (ctx->shader->input[i].name) {
581 case TGSI_SEMANTIC_FACE:
582 ctx->face_gpr = ctx->shader->input[i].gpr;
583 break;
584 case TGSI_SEMANTIC_COLOR:
585 ctx->colors_used++;
586 break;
587 case TGSI_SEMANTIC_POSITION:
588 ctx->fragcoord_input = i;
589 break;
590 }
591 if (ctx->bc->chip_class >= EVERGREEN) {
592 if ((r = evergreen_interp_input(ctx, i)))
593 return r;
594 }
595 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
596 /* FIXME probably skip inputs if they aren't passed in the ring */
597 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
598 ctx->next_ring_offset += 16;
599 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
600 ctx->shader->gs_prim_id_input = true;
601 }
602 for (j = 1; j < count; ++j) {
603 ctx->shader->input[i + j] = ctx->shader->input[i];
604 ctx->shader->input[i + j].gpr += j;
605 }
606 break;
607 case TGSI_FILE_OUTPUT:
608 i = ctx->shader->noutput++;
609 assert(i < Elements(ctx->shader->output));
610 ctx->shader->output[i].name = d->Semantic.Name;
611 ctx->shader->output[i].sid = d->Semantic.Index;
612 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
613 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
614 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
615 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
616 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
617 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
618 switch (d->Semantic.Name) {
619 case TGSI_SEMANTIC_CLIPDIST:
620 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
621 break;
622 case TGSI_SEMANTIC_PSIZE:
623 ctx->shader->vs_out_misc_write = 1;
624 ctx->shader->vs_out_point_size = 1;
625 break;
626 case TGSI_SEMANTIC_LAYER:
627 ctx->shader->vs_out_misc_write = 1;
628 ctx->shader->vs_out_layer = 1;
629 break;
630 case TGSI_SEMANTIC_CLIPVERTEX:
631 ctx->clip_vertex_write = TRUE;
632 ctx->cv_output = i;
633 break;
634 }
635 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
636 ctx->gs_out_ring_offset += 16;
637 }
638 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
639 switch (d->Semantic.Name) {
640 case TGSI_SEMANTIC_COLOR:
641 ctx->shader->nr_ps_max_color_exports++;
642 break;
643 }
644 }
645 break;
646 case TGSI_FILE_TEMPORARY:
647 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
648 if (d->Array.ArrayID) {
649 r600_add_gpr_array(ctx->shader,
650 ctx->file_offset[TGSI_FILE_TEMPORARY] +
651 d->Range.First,
652 d->Range.Last - d->Range.First + 1, 0x0F);
653 }
654 }
655 break;
656
657 case TGSI_FILE_CONSTANT:
658 case TGSI_FILE_SAMPLER:
659 case TGSI_FILE_ADDRESS:
660 break;
661
662 case TGSI_FILE_SYSTEM_VALUE:
663 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
664 if (!ctx->native_integers) {
665 struct r600_bytecode_alu alu;
666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
667
668 alu.op = ALU_OP1_INT_TO_FLT;
669 alu.src[0].sel = 0;
670 alu.src[0].chan = 3;
671
672 alu.dst.sel = 0;
673 alu.dst.chan = 3;
674 alu.dst.write = 1;
675 alu.last = 1;
676
677 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
678 return r;
679 }
680 break;
681 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
682 break;
683 default:
684 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
685 return -EINVAL;
686 }
687 return 0;
688 }
689
690 static int r600_get_temp(struct r600_shader_ctx *ctx)
691 {
692 return ctx->temp_reg + ctx->max_driver_temp_used++;
693 }
694
695 /*
696 * for evergreen we need to scan the shader to find the number of GPRs we need to
697 * reserve for interpolation.
698 *
699 * we need to know if we are going to emit
700 * any centroid inputs
701 * if perspective and linear are required
702 */
703 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
704 {
705 int i;
706 int num_baryc;
707
708 ctx->input_linear = FALSE;
709 ctx->input_perspective = FALSE;
710 ctx->input_centroid = FALSE;
711 ctx->num_interp_gpr = 1;
712
713 /* any centroid inputs */
714 for (i = 0; i < ctx->info.num_inputs; i++) {
715 /* skip position/face */
716 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
717 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
718 continue;
719 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
720 ctx->input_linear = TRUE;
721 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
722 ctx->input_perspective = TRUE;
723 if (ctx->info.input_centroid[i])
724 ctx->input_centroid = TRUE;
725 }
726
727 num_baryc = 0;
728 /* ignoring sample for now */
729 if (ctx->input_perspective)
730 num_baryc++;
731 if (ctx->input_linear)
732 num_baryc++;
733 if (ctx->input_centroid)
734 num_baryc *= 2;
735
736 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
737
738 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
739 return ctx->num_interp_gpr;
740 }
741
742 static void tgsi_src(struct r600_shader_ctx *ctx,
743 const struct tgsi_full_src_register *tgsi_src,
744 struct r600_shader_src *r600_src)
745 {
746 memset(r600_src, 0, sizeof(*r600_src));
747 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
748 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
749 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
750 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
751 r600_src->neg = tgsi_src->Register.Negate;
752 r600_src->abs = tgsi_src->Register.Absolute;
753
754 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
755 int index;
756 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
757 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
758 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
759
760 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
761 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
762 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
763 return;
764 }
765 index = tgsi_src->Register.Index;
766 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
767 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
768 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
769 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
770 r600_src->swizzle[0] = 3;
771 r600_src->swizzle[1] = 3;
772 r600_src->swizzle[2] = 3;
773 r600_src->swizzle[3] = 3;
774 r600_src->sel = 0;
775 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
776 r600_src->swizzle[0] = 0;
777 r600_src->swizzle[1] = 0;
778 r600_src->swizzle[2] = 0;
779 r600_src->swizzle[3] = 0;
780 r600_src->sel = 0;
781 }
782 } else {
783 if (tgsi_src->Register.Indirect)
784 r600_src->rel = V_SQ_REL_RELATIVE;
785 r600_src->sel = tgsi_src->Register.Index;
786 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
787 }
788 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
789 if (tgsi_src->Register.Dimension) {
790 r600_src->kc_bank = tgsi_src->Dimension.Index;
791 }
792 }
793 }
794
795 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
796 {
797 struct r600_bytecode_vtx vtx;
798 unsigned int ar_reg;
799 int r;
800
801 if (offset) {
802 struct r600_bytecode_alu alu;
803
804 memset(&alu, 0, sizeof(alu));
805
806 alu.op = ALU_OP2_ADD_INT;
807 alu.src[0].sel = ctx->bc->ar_reg;
808
809 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
810 alu.src[1].value = offset;
811
812 alu.dst.sel = dst_reg;
813 alu.dst.write = 1;
814 alu.last = 1;
815
816 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
817 return r;
818
819 ar_reg = dst_reg;
820 } else {
821 ar_reg = ctx->bc->ar_reg;
822 }
823
824 memset(&vtx, 0, sizeof(vtx));
825 vtx.buffer_id = cb_idx;
826 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
827 vtx.src_gpr = ar_reg;
828 vtx.mega_fetch_count = 16;
829 vtx.dst_gpr = dst_reg;
830 vtx.dst_sel_x = 0; /* SEL_X */
831 vtx.dst_sel_y = 1; /* SEL_Y */
832 vtx.dst_sel_z = 2; /* SEL_Z */
833 vtx.dst_sel_w = 3; /* SEL_W */
834 vtx.data_format = FMT_32_32_32_32_FLOAT;
835 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
836 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
837 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
838 vtx.endian = r600_endian_swap(32);
839
840 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
841 return r;
842
843 return 0;
844 }
845
846 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
847 {
848 struct r600_bytecode_vtx vtx;
849 int r;
850 unsigned index = src->Register.Index;
851 unsigned vtx_id = src->Dimension.Index;
852 int offset_reg = vtx_id / 3;
853 int offset_chan = vtx_id % 3;
854
855 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
856 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
857
858 if (offset_reg == 0 && offset_chan == 2)
859 offset_chan = 3;
860
861 if (src->Dimension.Indirect) {
862 int treg[3];
863 int t2;
864 struct r600_bytecode_alu alu;
865 int r, i;
866
867 /* you have got to be shitting me -
868 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
869 at least this is what fglrx seems to do. */
870 for (i = 0; i < 3; i++) {
871 treg[i] = r600_get_temp(ctx);
872 }
873 t2 = r600_get_temp(ctx);
874 for (i = 0; i < 3; i++) {
875 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
876 alu.op = ALU_OP1_MOV;
877 alu.src[0].sel = 0;
878 alu.src[0].chan = i == 2 ? 3 : i;
879 alu.dst.sel = treg[i];
880 alu.dst.chan = 0;
881 alu.dst.write = 1;
882 alu.last = 1;
883 r = r600_bytecode_add_alu(ctx->bc, &alu);
884 if (r)
885 return r;
886 }
887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
888 alu.op = ALU_OP1_MOV;
889 alu.src[0].sel = treg[0];
890 alu.src[0].rel = 1;
891 alu.dst.sel = t2;
892 alu.dst.write = 1;
893 alu.last = 1;
894 r = r600_bytecode_add_alu(ctx->bc, &alu);
895 if (r)
896 return r;
897 offset_reg = t2;
898 }
899
900
901 memset(&vtx, 0, sizeof(vtx));
902 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
903 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
904 vtx.src_gpr = offset_reg;
905 vtx.src_sel_x = offset_chan;
906 vtx.offset = index * 16; /*bytes*/
907 vtx.mega_fetch_count = 16;
908 vtx.dst_gpr = dst_reg;
909 vtx.dst_sel_x = 0; /* SEL_X */
910 vtx.dst_sel_y = 1; /* SEL_Y */
911 vtx.dst_sel_z = 2; /* SEL_Z */
912 vtx.dst_sel_w = 3; /* SEL_W */
913 if (ctx->bc->chip_class >= EVERGREEN) {
914 vtx.use_const_fields = 1;
915 } else {
916 vtx.data_format = FMT_32_32_32_32_FLOAT;
917 }
918
919 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
920 return r;
921
922 return 0;
923 }
924
925 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
926 {
927 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
928 int i;
929
930 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
931 struct tgsi_full_src_register *src = &inst->Src[i];
932
933 if (src->Register.File == TGSI_FILE_INPUT) {
934 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
935 /* primitive id is in R0.z */
936 ctx->src[i].sel = 0;
937 ctx->src[i].swizzle[0] = 2;
938 }
939 }
940 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
941 int treg = r600_get_temp(ctx);
942
943 fetch_gs_input(ctx, src, treg);
944 ctx->src[i].sel = treg;
945 }
946 }
947 return 0;
948 }
949
950 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
951 {
952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
953 struct r600_bytecode_alu alu;
954 int i, j, k, nconst, r;
955
956 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
957 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
958 nconst++;
959 }
960 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
961 }
962 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
963 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
964 continue;
965 }
966
967 if (ctx->src[i].rel) {
968 int treg = r600_get_temp(ctx);
969 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
970 return r;
971
972 ctx->src[i].kc_bank = 0;
973 ctx->src[i].sel = treg;
974 ctx->src[i].rel = 0;
975 j--;
976 } else if (j > 0) {
977 int treg = r600_get_temp(ctx);
978 for (k = 0; k < 4; k++) {
979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
980 alu.op = ALU_OP1_MOV;
981 alu.src[0].sel = ctx->src[i].sel;
982 alu.src[0].chan = k;
983 alu.src[0].rel = ctx->src[i].rel;
984 alu.dst.sel = treg;
985 alu.dst.chan = k;
986 alu.dst.write = 1;
987 if (k == 3)
988 alu.last = 1;
989 r = r600_bytecode_add_alu(ctx->bc, &alu);
990 if (r)
991 return r;
992 }
993 ctx->src[i].sel = treg;
994 ctx->src[i].rel =0;
995 j--;
996 }
997 }
998 return 0;
999 }
1000
1001 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1002 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1003 {
1004 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1005 struct r600_bytecode_alu alu;
1006 int i, j, k, nliteral, r;
1007
1008 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1009 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1010 nliteral++;
1011 }
1012 }
1013 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1014 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1015 int treg = r600_get_temp(ctx);
1016 for (k = 0; k < 4; k++) {
1017 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1018 alu.op = ALU_OP1_MOV;
1019 alu.src[0].sel = ctx->src[i].sel;
1020 alu.src[0].chan = k;
1021 alu.src[0].value = ctx->src[i].value[k];
1022 alu.dst.sel = treg;
1023 alu.dst.chan = k;
1024 alu.dst.write = 1;
1025 if (k == 3)
1026 alu.last = 1;
1027 r = r600_bytecode_add_alu(ctx->bc, &alu);
1028 if (r)
1029 return r;
1030 }
1031 ctx->src[i].sel = treg;
1032 j--;
1033 }
1034 }
1035 return 0;
1036 }
1037
1038 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1039 {
1040 int i, r, count = ctx->shader->ninput;
1041
1042 for (i = 0; i < count; i++) {
1043 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1044 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1045 if (r)
1046 return r;
1047 }
1048 }
1049 return 0;
1050 }
1051
1052 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so)
1053 {
1054 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1055 int i, j, r;
1056
1057 /* Sanity checking. */
1058 if (so->num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1059 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1060 r = -EINVAL;
1061 goto out_err;
1062 }
1063 for (i = 0; i < so->num_outputs; i++) {
1064 if (so->output[i].output_buffer >= 4) {
1065 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1066 so->output[i].output_buffer);
1067 r = -EINVAL;
1068 goto out_err;
1069 }
1070 }
1071
1072 /* Initialize locations where the outputs are stored. */
1073 for (i = 0; i < so->num_outputs; i++) {
1074 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1075
1076 /* Lower outputs with dst_offset < start_component.
1077 *
1078 * We can only output 4D vectors with a write mask, e.g. we can
1079 * only output the W component at offset 3, etc. If we want
1080 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1081 * to move it to X and output X. */
1082 if (so->output[i].dst_offset < so->output[i].start_component) {
1083 unsigned tmp = r600_get_temp(ctx);
1084
1085 for (j = 0; j < so->output[i].num_components; j++) {
1086 struct r600_bytecode_alu alu;
1087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1088 alu.op = ALU_OP1_MOV;
1089 alu.src[0].sel = so_gpr[i];
1090 alu.src[0].chan = so->output[i].start_component + j;
1091
1092 alu.dst.sel = tmp;
1093 alu.dst.chan = j;
1094 alu.dst.write = 1;
1095 if (j == so->output[i].num_components - 1)
1096 alu.last = 1;
1097 r = r600_bytecode_add_alu(ctx->bc, &alu);
1098 if (r)
1099 return r;
1100 }
1101 so->output[i].start_component = 0;
1102 so_gpr[i] = tmp;
1103 }
1104 }
1105
1106 /* Write outputs to buffers. */
1107 for (i = 0; i < so->num_outputs; i++) {
1108 struct r600_bytecode_output output;
1109
1110 memset(&output, 0, sizeof(struct r600_bytecode_output));
1111 output.gpr = so_gpr[i];
1112 output.elem_size = so->output[i].num_components;
1113 output.array_base = so->output[i].dst_offset - so->output[i].start_component;
1114 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1115 output.burst_count = 1;
1116 /* array_size is an upper limit for the burst_count
1117 * with MEM_STREAM instructions */
1118 output.array_size = 0xFFF;
1119 output.comp_mask = ((1 << so->output[i].num_components) - 1) << so->output[i].start_component;
1120 if (ctx->bc->chip_class >= EVERGREEN) {
1121 switch (so->output[i].output_buffer) {
1122 case 0:
1123 output.op = CF_OP_MEM_STREAM0_BUF0;
1124 break;
1125 case 1:
1126 output.op = CF_OP_MEM_STREAM0_BUF1;
1127 break;
1128 case 2:
1129 output.op = CF_OP_MEM_STREAM0_BUF2;
1130 break;
1131 case 3:
1132 output.op = CF_OP_MEM_STREAM0_BUF3;
1133 break;
1134 }
1135 } else {
1136 switch (so->output[i].output_buffer) {
1137 case 0:
1138 output.op = CF_OP_MEM_STREAM0;
1139 break;
1140 case 1:
1141 output.op = CF_OP_MEM_STREAM1;
1142 break;
1143 case 2:
1144 output.op = CF_OP_MEM_STREAM2;
1145 break;
1146 case 3:
1147 output.op = CF_OP_MEM_STREAM3;
1148 break;
1149 }
1150 }
1151 r = r600_bytecode_add_output(ctx->bc, &output);
1152 if (r)
1153 goto out_err;
1154 }
1155 return 0;
1156 out_err:
1157 return r;
1158 }
1159
1160 static int generate_gs_copy_shader(struct r600_context *rctx,
1161 struct r600_pipe_shader *gs,
1162 struct pipe_stream_output_info *so)
1163 {
1164 struct r600_shader_ctx ctx = {};
1165 struct r600_shader *gs_shader = &gs->shader;
1166 struct r600_pipe_shader *cshader;
1167 int ocnt = gs_shader->noutput;
1168 struct r600_bytecode_alu alu;
1169 struct r600_bytecode_vtx vtx;
1170 struct r600_bytecode_output output;
1171 struct r600_bytecode_cf *cf_jump, *cf_pop,
1172 *last_exp_pos = NULL, *last_exp_param = NULL;
1173 int i, next_clip_pos = 61, next_param = 0;
1174
1175 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1176 if (!cshader)
1177 return 0;
1178
1179 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1180 sizeof(struct r600_shader_io));
1181
1182 cshader->shader.noutput = ocnt;
1183
1184 ctx.shader = &cshader->shader;
1185 ctx.bc = &ctx.shader->bc;
1186 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1187
1188 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1189 rctx->screen->has_compressed_msaa_texturing);
1190
1191 ctx.bc->isa = rctx->isa;
1192
1193 /* R0.x = R0.x & 0x3fffffff */
1194 memset(&alu, 0, sizeof(alu));
1195 alu.op = ALU_OP2_AND_INT;
1196 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1197 alu.src[1].value = 0x3fffffff;
1198 alu.dst.write = 1;
1199 r600_bytecode_add_alu(ctx.bc, &alu);
1200
1201 /* R0.y = R0.x >> 30 */
1202 memset(&alu, 0, sizeof(alu));
1203 alu.op = ALU_OP2_LSHR_INT;
1204 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1205 alu.src[1].value = 0x1e;
1206 alu.dst.chan = 1;
1207 alu.dst.write = 1;
1208 alu.last = 1;
1209 r600_bytecode_add_alu(ctx.bc, &alu);
1210
1211 /* PRED_SETE_INT __, R0.y, 0 */
1212 memset(&alu, 0, sizeof(alu));
1213 alu.op = ALU_OP2_PRED_SETE_INT;
1214 alu.src[0].chan = 1;
1215 alu.src[1].sel = V_SQ_ALU_SRC_0;
1216 alu.execute_mask = 1;
1217 alu.update_pred = 1;
1218 alu.last = 1;
1219 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1220
1221 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1222 cf_jump = ctx.bc->cf_last;
1223
1224 /* fetch vertex data from GSVS ring */
1225 for (i = 0; i < ocnt; ++i) {
1226 struct r600_shader_io *out = &ctx.shader->output[i];
1227 out->gpr = i + 1;
1228 out->ring_offset = i * 16;
1229
1230 memset(&vtx, 0, sizeof(vtx));
1231 vtx.op = FETCH_OP_VFETCH;
1232 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1233 vtx.fetch_type = 2;
1234 vtx.offset = out->ring_offset;
1235 vtx.dst_gpr = out->gpr;
1236 vtx.dst_sel_x = 0;
1237 vtx.dst_sel_y = 1;
1238 vtx.dst_sel_z = 2;
1239 vtx.dst_sel_w = 3;
1240 if (rctx->b.chip_class >= EVERGREEN) {
1241 vtx.use_const_fields = 1;
1242 } else {
1243 vtx.data_format = FMT_32_32_32_32_FLOAT;
1244 }
1245
1246 r600_bytecode_add_vtx(ctx.bc, &vtx);
1247 }
1248
1249 /* XXX handle clipvertex, streamout? */
1250 emit_streamout(&ctx, so);
1251
1252 /* export vertex data */
1253 /* XXX factor out common code with r600_shader_from_tgsi ? */
1254 for (i = 0; i < ocnt; ++i) {
1255 struct r600_shader_io *out = &ctx.shader->output[i];
1256
1257 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1258 continue;
1259
1260 memset(&output, 0, sizeof(output));
1261 output.gpr = out->gpr;
1262 output.elem_size = 3;
1263 output.swizzle_x = 0;
1264 output.swizzle_y = 1;
1265 output.swizzle_z = 2;
1266 output.swizzle_w = 3;
1267 output.burst_count = 1;
1268 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1269 output.op = CF_OP_EXPORT;
1270 switch (out->name) {
1271 case TGSI_SEMANTIC_POSITION:
1272 output.array_base = 60;
1273 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1274 break;
1275
1276 case TGSI_SEMANTIC_PSIZE:
1277 output.array_base = 61;
1278 if (next_clip_pos == 61)
1279 next_clip_pos = 62;
1280 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1281 output.swizzle_y = 7;
1282 output.swizzle_z = 7;
1283 output.swizzle_w = 7;
1284 ctx.shader->vs_out_misc_write = 1;
1285 ctx.shader->vs_out_point_size = 1;
1286 break;
1287 case TGSI_SEMANTIC_LAYER:
1288 output.array_base = 61;
1289 if (next_clip_pos == 61)
1290 next_clip_pos = 62;
1291 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1292 output.swizzle_x = 7;
1293 output.swizzle_y = 7;
1294 output.swizzle_z = 0;
1295 output.swizzle_w = 7;
1296 ctx.shader->vs_out_misc_write = 1;
1297 ctx.shader->vs_out_layer = 1;
1298 break;
1299 case TGSI_SEMANTIC_CLIPDIST:
1300 /* spi_sid is 0 for clipdistance outputs that were generated
1301 * for clipvertex - we don't need to pass them to PS */
1302 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1303 if (out->spi_sid) {
1304 /* duplicate it as PARAM to pass to the pixel shader */
1305 output.array_base = next_param++;
1306 r600_bytecode_add_output(ctx.bc, &output);
1307 last_exp_param = ctx.bc->cf_last;
1308 }
1309 output.array_base = next_clip_pos++;
1310 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1311 break;
1312 case TGSI_SEMANTIC_FOG:
1313 output.swizzle_y = 4; /* 0 */
1314 output.swizzle_z = 4; /* 0 */
1315 output.swizzle_w = 5; /* 1 */
1316 break;
1317 default:
1318 output.array_base = next_param++;
1319 break;
1320 }
1321 r600_bytecode_add_output(ctx.bc, &output);
1322 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1323 last_exp_param = ctx.bc->cf_last;
1324 else
1325 last_exp_pos = ctx.bc->cf_last;
1326 }
1327
1328 if (!last_exp_pos) {
1329 memset(&output, 0, sizeof(output));
1330 output.gpr = 0;
1331 output.elem_size = 3;
1332 output.swizzle_x = 7;
1333 output.swizzle_y = 7;
1334 output.swizzle_z = 7;
1335 output.swizzle_w = 7;
1336 output.burst_count = 1;
1337 output.type = 2;
1338 output.op = CF_OP_EXPORT;
1339 output.array_base = 60;
1340 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1341 r600_bytecode_add_output(ctx.bc, &output);
1342 last_exp_pos = ctx.bc->cf_last;
1343 }
1344
1345 if (!last_exp_param) {
1346 memset(&output, 0, sizeof(output));
1347 output.gpr = 0;
1348 output.elem_size = 3;
1349 output.swizzle_x = 7;
1350 output.swizzle_y = 7;
1351 output.swizzle_z = 7;
1352 output.swizzle_w = 7;
1353 output.burst_count = 1;
1354 output.type = 2;
1355 output.op = CF_OP_EXPORT;
1356 output.array_base = next_param++;
1357 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1358 r600_bytecode_add_output(ctx.bc, &output);
1359 last_exp_param = ctx.bc->cf_last;
1360 }
1361
1362 last_exp_pos->op = CF_OP_EXPORT_DONE;
1363 last_exp_param->op = CF_OP_EXPORT_DONE;
1364
1365 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1366 cf_pop = ctx.bc->cf_last;
1367
1368 cf_jump->cf_addr = cf_pop->id + 2;
1369 cf_jump->pop_count = 1;
1370 cf_pop->cf_addr = cf_pop->id + 2;
1371 cf_pop->pop_count = 1;
1372
1373 if (ctx.bc->chip_class == CAYMAN)
1374 cm_bytecode_add_cf_end(ctx.bc);
1375 else {
1376 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1377 ctx.bc->cf_last->end_of_program = 1;
1378 }
1379
1380 gs->gs_copy_shader = cshader;
1381
1382 ctx.bc->nstack = 1;
1383 cshader->shader.ring_item_size = ocnt * 16;
1384
1385 return r600_bytecode_build(ctx.bc);
1386 }
1387
1388 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind)
1389 {
1390 struct r600_bytecode_output output;
1391 int i, k, ring_offset;
1392
1393 for (i = 0; i < ctx->shader->noutput; i++) {
1394 if (ctx->gs_for_vs) {
1395 /* for ES we need to lookup corresponding ring offset expected by GS
1396 * (map this output to GS input by name and sid) */
1397 /* FIXME precompute offsets */
1398 ring_offset = -1;
1399 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1400 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1401 struct r600_shader_io *out = &ctx->shader->output[i];
1402 if (in->name == out->name && in->sid == out->sid)
1403 ring_offset = in->ring_offset;
1404 }
1405
1406 if (ring_offset == -1)
1407 continue;
1408 } else
1409 ring_offset = i * 16;
1410
1411 /* next_ring_offset after parsing input decls contains total size of
1412 * single vertex data, gs_next_vertex - current vertex index */
1413 if (!ind)
1414 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1415
1416 /* get a temp and add the ring offset to the next vertex base in the shader */
1417 memset(&output, 0, sizeof(struct r600_bytecode_output));
1418 output.gpr = ctx->shader->output[i].gpr;
1419 output.elem_size = 3;
1420 output.comp_mask = 0xF;
1421 output.burst_count = 1;
1422
1423 if (ind)
1424 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1425 else
1426 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1427 output.op = CF_OP_MEM_RING;
1428
1429
1430 if (ind) {
1431 output.array_base = ring_offset >> 2; /* in dwords */
1432 output.array_size = 0xfff;
1433 output.index_gpr = ctx->gs_export_gpr_treg;
1434 } else
1435 output.array_base = ring_offset >> 2; /* in dwords */
1436 r600_bytecode_add_output(ctx->bc, &output);
1437 }
1438
1439 if (ind) {
1440 struct r600_bytecode_alu alu;
1441 int r;
1442
1443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1444 alu.op = ALU_OP2_ADD_INT;
1445 alu.src[0].sel = ctx->gs_export_gpr_treg;
1446 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1447 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1448 alu.dst.sel = ctx->gs_export_gpr_treg;
1449 alu.dst.write = 1;
1450 alu.last = 1;
1451 r = r600_bytecode_add_alu(ctx->bc, &alu);
1452 if (r)
1453 return r;
1454 }
1455 ++ctx->gs_next_vertex;
1456 return 0;
1457 }
1458
1459 static int r600_shader_from_tgsi(struct r600_context *rctx,
1460 struct r600_pipe_shader *pipeshader,
1461 struct r600_shader_key key)
1462 {
1463 struct r600_screen *rscreen = rctx->screen;
1464 struct r600_shader *shader = &pipeshader->shader;
1465 struct tgsi_token *tokens = pipeshader->selector->tokens;
1466 struct pipe_stream_output_info so = pipeshader->selector->so;
1467 struct tgsi_full_immediate *immediate;
1468 struct tgsi_full_property *property;
1469 struct r600_shader_ctx ctx;
1470 struct r600_bytecode_output output[32];
1471 unsigned output_done, noutput;
1472 unsigned opcode;
1473 int i, j, k, r = 0;
1474 int next_param_base = 0, next_clip_base;
1475 int max_color_exports = MAX2(key.nr_cbufs, 1);
1476 /* Declarations used by llvm code */
1477 bool use_llvm = false;
1478 bool indirect_gprs;
1479 bool ring_outputs = false;
1480 bool pos_emitted = false;
1481
1482 #ifdef R600_USE_LLVM
1483 use_llvm = !(rscreen->b.debug_flags & DBG_NO_LLVM);
1484 #endif
1485 ctx.bc = &shader->bc;
1486 ctx.shader = shader;
1487 ctx.native_integers = true;
1488
1489 shader->vs_as_es = key.vs_as_es;
1490
1491 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1492 rscreen->has_compressed_msaa_texturing);
1493 ctx.tokens = tokens;
1494 tgsi_scan_shader(tokens, &ctx.info);
1495 shader->indirect_files = ctx.info.indirect_files;
1496 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
1497 tgsi_parse_init(&ctx.parse, tokens);
1498 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1499 shader->processor_type = ctx.type;
1500 ctx.bc->type = shader->processor_type;
1501
1502 ring_outputs = key.vs_as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
1503
1504 if (key.vs_as_es) {
1505 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1506 } else {
1507 ctx.gs_for_vs = NULL;
1508 }
1509
1510 ctx.next_ring_offset = 0;
1511 ctx.gs_out_ring_offset = 0;
1512 ctx.gs_next_vertex = 0;
1513
1514 ctx.face_gpr = -1;
1515 ctx.fragcoord_input = -1;
1516 ctx.colors_used = 0;
1517 ctx.clip_vertex_write = 0;
1518
1519 shader->nr_ps_color_exports = 0;
1520 shader->nr_ps_max_color_exports = 0;
1521
1522 shader->two_side = key.color_two_side;
1523
1524 /* register allocations */
1525 /* Values [0,127] correspond to GPR[0..127].
1526 * Values [128,159] correspond to constant buffer bank 0
1527 * Values [160,191] correspond to constant buffer bank 1
1528 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1529 * Values [256,287] correspond to constant buffer bank 2 (EG)
1530 * Values [288,319] correspond to constant buffer bank 3 (EG)
1531 * Other special values are shown in the list below.
1532 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1533 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1534 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1535 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1536 * 248 SQ_ALU_SRC_0: special constant 0.0.
1537 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1538 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1539 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1540 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1541 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1542 * 254 SQ_ALU_SRC_PV: previous vector result.
1543 * 255 SQ_ALU_SRC_PS: previous scalar result.
1544 */
1545 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1546 ctx.file_offset[i] = 0;
1547 }
1548
1549 #ifdef R600_USE_LLVM
1550 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1551 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1552 "indirect adressing. Falling back to TGSI "
1553 "backend.\n");
1554 use_llvm = 0;
1555 }
1556 #endif
1557 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1558 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1559 if (!use_llvm) {
1560 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1561 }
1562 }
1563 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1564 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1565 }
1566 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1567 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1568 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1569 }
1570 ctx.use_llvm = use_llvm;
1571
1572 if (use_llvm) {
1573 ctx.file_offset[TGSI_FILE_OUTPUT] =
1574 ctx.file_offset[TGSI_FILE_INPUT];
1575 } else {
1576 ctx.file_offset[TGSI_FILE_OUTPUT] =
1577 ctx.file_offset[TGSI_FILE_INPUT] +
1578 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1579 }
1580 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1581 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1582
1583 /* Outside the GPR range. This will be translated to one of the
1584 * kcache banks later. */
1585 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1586
1587 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1588 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1589 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1590 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1591 ctx.gs_export_gpr_treg = ctx.bc->ar_reg + 1;
1592 ctx.temp_reg = ctx.bc->ar_reg + 2;
1593 } else
1594 ctx.temp_reg = ctx.bc->ar_reg + 1;
1595
1596 if (indirect_gprs) {
1597 shader->max_arrays = 0;
1598 shader->num_arrays = 0;
1599
1600 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1601 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1602 ctx.file_offset[TGSI_FILE_OUTPUT] -
1603 ctx.file_offset[TGSI_FILE_INPUT],
1604 0x0F);
1605 }
1606 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1607 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1608 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1609 ctx.file_offset[TGSI_FILE_OUTPUT],
1610 0x0F);
1611 }
1612 }
1613
1614 ctx.nliterals = 0;
1615 ctx.literals = NULL;
1616 shader->fs_write_all = FALSE;
1617 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1618 tgsi_parse_token(&ctx.parse);
1619 switch (ctx.parse.FullToken.Token.Type) {
1620 case TGSI_TOKEN_TYPE_IMMEDIATE:
1621 immediate = &ctx.parse.FullToken.FullImmediate;
1622 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1623 if(ctx.literals == NULL) {
1624 r = -ENOMEM;
1625 goto out_err;
1626 }
1627 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1628 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1629 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1630 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1631 ctx.nliterals++;
1632 break;
1633 case TGSI_TOKEN_TYPE_DECLARATION:
1634 r = tgsi_declaration(&ctx);
1635 if (r)
1636 goto out_err;
1637 break;
1638 case TGSI_TOKEN_TYPE_INSTRUCTION:
1639 break;
1640 case TGSI_TOKEN_TYPE_PROPERTY:
1641 property = &ctx.parse.FullToken.FullProperty;
1642 switch (property->Property.PropertyName) {
1643 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1644 if (property->u[0].Data == 1)
1645 shader->fs_write_all = TRUE;
1646 break;
1647 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1648 /* we don't need this one */
1649 break;
1650 case TGSI_PROPERTY_GS_INPUT_PRIM:
1651 shader->gs_input_prim = property->u[0].Data;
1652 break;
1653 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1654 shader->gs_output_prim = property->u[0].Data;
1655 break;
1656 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1657 shader->gs_max_out_vertices = property->u[0].Data;
1658 break;
1659 }
1660 break;
1661 default:
1662 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1663 r = -EINVAL;
1664 goto out_err;
1665 }
1666 }
1667
1668 shader->ring_item_size = ctx.next_ring_offset;
1669
1670 /* Process two side if needed */
1671 if (shader->two_side && ctx.colors_used) {
1672 int i, count = ctx.shader->ninput;
1673 unsigned next_lds_loc = ctx.shader->nlds;
1674
1675 /* additional inputs will be allocated right after the existing inputs,
1676 * we won't need them after the color selection, so we don't need to
1677 * reserve these gprs for the rest of the shader code and to adjust
1678 * output offsets etc. */
1679 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1680 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1681
1682 if (ctx.face_gpr == -1) {
1683 i = ctx.shader->ninput++;
1684 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1685 ctx.shader->input[i].spi_sid = 0;
1686 ctx.shader->input[i].gpr = gpr++;
1687 ctx.face_gpr = ctx.shader->input[i].gpr;
1688 }
1689
1690 for (i = 0; i < count; i++) {
1691 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1692 int ni = ctx.shader->ninput++;
1693 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1694 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1695 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1696 ctx.shader->input[ni].gpr = gpr++;
1697 // TGSI to LLVM needs to know the lds position of inputs.
1698 // Non LLVM path computes it later (in process_twoside_color)
1699 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1700 ctx.shader->input[i].back_color_input = ni;
1701 if (ctx.bc->chip_class >= EVERGREEN) {
1702 if ((r = evergreen_interp_input(&ctx, ni)))
1703 return r;
1704 }
1705 }
1706 }
1707 }
1708
1709 /* LLVM backend setup */
1710 #ifdef R600_USE_LLVM
1711 if (use_llvm) {
1712 struct radeon_llvm_context radeon_llvm_ctx;
1713 LLVMModuleRef mod;
1714 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
1715 boolean use_kill = false;
1716
1717 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1718 radeon_llvm_ctx.type = ctx.type;
1719 radeon_llvm_ctx.two_side = shader->two_side;
1720 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1721 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
1722 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1723 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1724 radeon_llvm_ctx.color_buffer_count = max_color_exports;
1725 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1726 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
1727 radeon_llvm_ctx.stream_outputs = &so;
1728 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1729 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1730 radeon_llvm_ctx.has_compressed_msaa_texturing =
1731 ctx.bc->has_compressed_msaa_texturing;
1732 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1733 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1734 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
1735
1736 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
1737 radeon_llvm_dispose(&radeon_llvm_ctx);
1738 use_llvm = 0;
1739 fprintf(stderr, "R600 LLVM backend failed to compile "
1740 "shader. Falling back to TGSI\n");
1741 } else {
1742 ctx.file_offset[TGSI_FILE_OUTPUT] =
1743 ctx.file_offset[TGSI_FILE_INPUT];
1744 }
1745 if (use_kill)
1746 ctx.shader->uses_kill = use_kill;
1747 radeon_llvm_dispose(&radeon_llvm_ctx);
1748 }
1749 #endif
1750 /* End of LLVM backend setup */
1751
1752 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
1753 shader->nr_ps_max_color_exports = 8;
1754
1755 if (!use_llvm) {
1756 if (ctx.fragcoord_input >= 0) {
1757 if (ctx.bc->chip_class == CAYMAN) {
1758 for (j = 0 ; j < 4; j++) {
1759 struct r600_bytecode_alu alu;
1760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1761 alu.op = ALU_OP1_RECIP_IEEE;
1762 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1763 alu.src[0].chan = 3;
1764
1765 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1766 alu.dst.chan = j;
1767 alu.dst.write = (j == 3);
1768 alu.last = 1;
1769 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1770 return r;
1771 }
1772 } else {
1773 struct r600_bytecode_alu alu;
1774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1775 alu.op = ALU_OP1_RECIP_IEEE;
1776 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1777 alu.src[0].chan = 3;
1778
1779 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1780 alu.dst.chan = 3;
1781 alu.dst.write = 1;
1782 alu.last = 1;
1783 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1784 return r;
1785 }
1786 }
1787
1788 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1789 struct r600_bytecode_alu alu;
1790 int r;
1791
1792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1793 alu.op = ALU_OP1_MOV;
1794 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1795 alu.src[0].value = 0;
1796 alu.dst.sel = ctx.gs_export_gpr_treg;
1797 alu.dst.write = 1;
1798 alu.last = 1;
1799 r = r600_bytecode_add_alu(ctx.bc, &alu);
1800 if (r)
1801 return r;
1802 }
1803 if (shader->two_side && ctx.colors_used) {
1804 if ((r = process_twoside_color_inputs(&ctx)))
1805 return r;
1806 }
1807
1808 tgsi_parse_init(&ctx.parse, tokens);
1809 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1810 tgsi_parse_token(&ctx.parse);
1811 switch (ctx.parse.FullToken.Token.Type) {
1812 case TGSI_TOKEN_TYPE_INSTRUCTION:
1813 r = tgsi_is_supported(&ctx);
1814 if (r)
1815 goto out_err;
1816 ctx.max_driver_temp_used = 0;
1817 /* reserve first tmp for everyone */
1818 r600_get_temp(&ctx);
1819
1820 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1821 if ((r = tgsi_split_constant(&ctx)))
1822 goto out_err;
1823 if ((r = tgsi_split_literal_constant(&ctx)))
1824 goto out_err;
1825 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
1826 if ((r = tgsi_split_gs_inputs(&ctx)))
1827 goto out_err;
1828 if (ctx.bc->chip_class == CAYMAN)
1829 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1830 else if (ctx.bc->chip_class >= EVERGREEN)
1831 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1832 else
1833 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1834 r = ctx.inst_info->process(&ctx);
1835 if (r)
1836 goto out_err;
1837 break;
1838 default:
1839 break;
1840 }
1841 }
1842 }
1843
1844 /* Reset the temporary register counter. */
1845 ctx.max_driver_temp_used = 0;
1846
1847 noutput = shader->noutput;
1848
1849 if (!ring_outputs && ctx.clip_vertex_write) {
1850 unsigned clipdist_temp[2];
1851
1852 clipdist_temp[0] = r600_get_temp(&ctx);
1853 clipdist_temp[1] = r600_get_temp(&ctx);
1854
1855 /* need to convert a clipvertex write into clipdistance writes and not export
1856 the clip vertex anymore */
1857
1858 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1859 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1860 shader->output[noutput].gpr = clipdist_temp[0];
1861 noutput++;
1862 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1863 shader->output[noutput].gpr = clipdist_temp[1];
1864 noutput++;
1865
1866 /* reset spi_sid for clipvertex output to avoid confusing spi */
1867 shader->output[ctx.cv_output].spi_sid = 0;
1868
1869 shader->clip_dist_write = 0xFF;
1870
1871 for (i = 0; i < 8; i++) {
1872 int oreg = i >> 2;
1873 int ochan = i & 3;
1874
1875 for (j = 0; j < 4; j++) {
1876 struct r600_bytecode_alu alu;
1877 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1878 alu.op = ALU_OP2_DOT4;
1879 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1880 alu.src[0].chan = j;
1881
1882 alu.src[1].sel = 512 + i;
1883 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1884 alu.src[1].chan = j;
1885
1886 alu.dst.sel = clipdist_temp[oreg];
1887 alu.dst.chan = j;
1888 alu.dst.write = (j == ochan);
1889 if (j == 3)
1890 alu.last = 1;
1891 if (!use_llvm)
1892 r = r600_bytecode_add_alu(ctx.bc, &alu);
1893 if (r)
1894 return r;
1895 }
1896 }
1897 }
1898
1899 /* Add stream outputs. */
1900 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
1901 so.num_outputs && !use_llvm)
1902 emit_streamout(&ctx, &so);
1903
1904 if (ring_outputs) {
1905 if (key.vs_as_es)
1906 emit_gs_ring_writes(&ctx, FALSE);
1907 } else {
1908 /* Export output */
1909 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
1910
1911 for (i = 0, j = 0; i < noutput; i++, j++) {
1912 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1913 output[j].gpr = shader->output[i].gpr;
1914 output[j].elem_size = 3;
1915 output[j].swizzle_x = 0;
1916 output[j].swizzle_y = 1;
1917 output[j].swizzle_z = 2;
1918 output[j].swizzle_w = 3;
1919 output[j].burst_count = 1;
1920 output[j].type = -1;
1921 output[j].op = CF_OP_EXPORT;
1922 switch (ctx.type) {
1923 case TGSI_PROCESSOR_VERTEX:
1924 switch (shader->output[i].name) {
1925 case TGSI_SEMANTIC_POSITION:
1926 output[j].array_base = 60;
1927 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1928 pos_emitted = true;
1929 break;
1930
1931 case TGSI_SEMANTIC_PSIZE:
1932 output[j].array_base = 61;
1933 output[j].swizzle_y = 7;
1934 output[j].swizzle_z = 7;
1935 output[j].swizzle_w = 7;
1936 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1937 pos_emitted = true;
1938 break;
1939 case TGSI_SEMANTIC_LAYER:
1940 output[j].array_base = 61;
1941 output[j].swizzle_x = 7;
1942 output[j].swizzle_y = 7;
1943 output[j].swizzle_z = 0;
1944 output[j].swizzle_w = 7;
1945 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1946 pos_emitted = true;
1947 break;
1948 case TGSI_SEMANTIC_CLIPVERTEX:
1949 j--;
1950 break;
1951 case TGSI_SEMANTIC_CLIPDIST:
1952 output[j].array_base = next_clip_base++;
1953 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1954 pos_emitted = true;
1955 /* spi_sid is 0 for clipdistance outputs that were generated
1956 * for clipvertex - we don't need to pass them to PS */
1957 if (shader->output[i].spi_sid) {
1958 j++;
1959 /* duplicate it as PARAM to pass to the pixel shader */
1960 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1961 output[j].array_base = next_param_base++;
1962 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1963 }
1964 break;
1965 case TGSI_SEMANTIC_FOG:
1966 output[j].swizzle_y = 4; /* 0 */
1967 output[j].swizzle_z = 4; /* 0 */
1968 output[j].swizzle_w = 5; /* 1 */
1969 break;
1970 }
1971 break;
1972 case TGSI_PROCESSOR_FRAGMENT:
1973 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1974 /* never export more colors than the number of CBs */
1975 if (shader->output[i].sid >= max_color_exports) {
1976 /* skip export */
1977 j--;
1978 continue;
1979 }
1980 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1981 output[j].array_base = shader->output[i].sid;
1982 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1983 shader->nr_ps_color_exports++;
1984 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
1985 for (k = 1; k < max_color_exports; k++) {
1986 j++;
1987 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1988 output[j].gpr = shader->output[i].gpr;
1989 output[j].elem_size = 3;
1990 output[j].swizzle_x = 0;
1991 output[j].swizzle_y = 1;
1992 output[j].swizzle_z = 2;
1993 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1994 output[j].burst_count = 1;
1995 output[j].array_base = k;
1996 output[j].op = CF_OP_EXPORT;
1997 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1998 shader->nr_ps_color_exports++;
1999 }
2000 }
2001 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2002 output[j].array_base = 61;
2003 output[j].swizzle_x = 2;
2004 output[j].swizzle_y = 7;
2005 output[j].swizzle_z = output[j].swizzle_w = 7;
2006 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2007 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2008 output[j].array_base = 61;
2009 output[j].swizzle_x = 7;
2010 output[j].swizzle_y = 1;
2011 output[j].swizzle_z = output[j].swizzle_w = 7;
2012 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2013 } else {
2014 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2015 r = -EINVAL;
2016 goto out_err;
2017 }
2018 break;
2019 default:
2020 R600_ERR("unsupported processor type %d\n", ctx.type);
2021 r = -EINVAL;
2022 goto out_err;
2023 }
2024
2025 if (output[j].type==-1) {
2026 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2027 output[j].array_base = next_param_base++;
2028 }
2029 }
2030
2031 /* add fake position export */
2032 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2033 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2034 output[j].gpr = 0;
2035 output[j].elem_size = 3;
2036 output[j].swizzle_x = 7;
2037 output[j].swizzle_y = 7;
2038 output[j].swizzle_z = 7;
2039 output[j].swizzle_w = 7;
2040 output[j].burst_count = 1;
2041 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2042 output[j].array_base = 60;
2043 output[j].op = CF_OP_EXPORT;
2044 j++;
2045 }
2046
2047 /* add fake param output for vertex shader if no param is exported */
2048 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2049 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2050 output[j].gpr = 0;
2051 output[j].elem_size = 3;
2052 output[j].swizzle_x = 7;
2053 output[j].swizzle_y = 7;
2054 output[j].swizzle_z = 7;
2055 output[j].swizzle_w = 7;
2056 output[j].burst_count = 1;
2057 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2058 output[j].array_base = 0;
2059 output[j].op = CF_OP_EXPORT;
2060 j++;
2061 }
2062
2063 /* add fake pixel export */
2064 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2065 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2066 output[j].gpr = 0;
2067 output[j].elem_size = 3;
2068 output[j].swizzle_x = 7;
2069 output[j].swizzle_y = 7;
2070 output[j].swizzle_z = 7;
2071 output[j].swizzle_w = 7;
2072 output[j].burst_count = 1;
2073 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2074 output[j].array_base = 0;
2075 output[j].op = CF_OP_EXPORT;
2076 j++;
2077 }
2078
2079 noutput = j;
2080
2081 /* set export done on last export of each type */
2082 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2083 if (!(output_done & (1 << output[i].type))) {
2084 output_done |= (1 << output[i].type);
2085 output[i].op = CF_OP_EXPORT_DONE;
2086 }
2087 }
2088 /* add output to bytecode */
2089 if (!use_llvm) {
2090 for (i = 0; i < noutput; i++) {
2091 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2092 if (r)
2093 goto out_err;
2094 }
2095 }
2096 }
2097
2098 /* add program end */
2099 if (!use_llvm) {
2100 if (ctx.bc->chip_class == CAYMAN)
2101 cm_bytecode_add_cf_end(ctx.bc);
2102 else {
2103 const struct cf_op_info *last = NULL;
2104
2105 if (ctx.bc->cf_last)
2106 last = r600_isa_cf(ctx.bc->cf_last->op);
2107
2108 /* alu clause instructions don't have EOP bit, so add NOP */
2109 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2110 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2111
2112 ctx.bc->cf_last->end_of_program = 1;
2113 }
2114 }
2115
2116 /* check GPR limit - we have 124 = 128 - 4
2117 * (4 are reserved as alu clause temporary registers) */
2118 if (ctx.bc->ngpr > 124) {
2119 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2120 r = -ENOMEM;
2121 goto out_err;
2122 }
2123
2124 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2125 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2126 return r;
2127 }
2128
2129 free(ctx.literals);
2130 tgsi_parse_free(&ctx.parse);
2131 return 0;
2132 out_err:
2133 free(ctx.literals);
2134 tgsi_parse_free(&ctx.parse);
2135 return r;
2136 }
2137
2138 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2139 {
2140 R600_ERR("%s tgsi opcode unsupported\n",
2141 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
2142 return -EINVAL;
2143 }
2144
2145 static int tgsi_end(struct r600_shader_ctx *ctx)
2146 {
2147 return 0;
2148 }
2149
2150 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2151 const struct r600_shader_src *shader_src,
2152 unsigned chan)
2153 {
2154 bc_src->sel = shader_src->sel;
2155 bc_src->chan = shader_src->swizzle[chan];
2156 bc_src->neg = shader_src->neg;
2157 bc_src->abs = shader_src->abs;
2158 bc_src->rel = shader_src->rel;
2159 bc_src->value = shader_src->value[bc_src->chan];
2160 bc_src->kc_bank = shader_src->kc_bank;
2161 }
2162
2163 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2164 {
2165 bc_src->abs = 1;
2166 bc_src->neg = 0;
2167 }
2168
2169 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2170 {
2171 bc_src->neg = !bc_src->neg;
2172 }
2173
2174 static void tgsi_dst(struct r600_shader_ctx *ctx,
2175 const struct tgsi_full_dst_register *tgsi_dst,
2176 unsigned swizzle,
2177 struct r600_bytecode_alu_dst *r600_dst)
2178 {
2179 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2180
2181 r600_dst->sel = tgsi_dst->Register.Index;
2182 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2183 r600_dst->chan = swizzle;
2184 r600_dst->write = 1;
2185 if (tgsi_dst->Register.Indirect)
2186 r600_dst->rel = V_SQ_REL_RELATIVE;
2187 if (inst->Instruction.Saturate) {
2188 r600_dst->clamp = 1;
2189 }
2190 }
2191
2192 static int tgsi_last_instruction(unsigned writemask)
2193 {
2194 int i, lasti = 0;
2195
2196 for (i = 0; i < 4; i++) {
2197 if (writemask & (1 << i)) {
2198 lasti = i;
2199 }
2200 }
2201 return lasti;
2202 }
2203
2204 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2205 {
2206 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2207 struct r600_bytecode_alu alu;
2208 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2209 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2210 /* use temp register if trans_only and more than one dst component */
2211 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2212
2213 for (i = 0; i <= lasti; i++) {
2214 if (!(write_mask & (1 << i)))
2215 continue;
2216
2217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2218 if (use_tmp) {
2219 alu.dst.sel = ctx->temp_reg;
2220 alu.dst.chan = i;
2221 alu.dst.write = 1;
2222 } else
2223 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2224
2225 alu.op = ctx->inst_info->op;
2226 if (!swap) {
2227 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2228 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2229 }
2230 } else {
2231 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2232 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2233 }
2234 /* handle some special cases */
2235 switch (ctx->inst_info->tgsi_opcode) {
2236 case TGSI_OPCODE_SUB:
2237 r600_bytecode_src_toggle_neg(&alu.src[1]);
2238 break;
2239 case TGSI_OPCODE_ABS:
2240 r600_bytecode_src_set_abs(&alu.src[0]);
2241 break;
2242 default:
2243 break;
2244 }
2245 if (i == lasti || trans_only) {
2246 alu.last = 1;
2247 }
2248 r = r600_bytecode_add_alu(ctx->bc, &alu);
2249 if (r)
2250 return r;
2251 }
2252
2253 if (use_tmp) {
2254 /* move result from temp to dst */
2255 for (i = 0; i <= lasti; i++) {
2256 if (!(write_mask & (1 << i)))
2257 continue;
2258
2259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2260 alu.op = ALU_OP1_MOV;
2261 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2262 alu.src[0].sel = ctx->temp_reg;
2263 alu.src[0].chan = i;
2264 alu.last = (i == lasti);
2265
2266 r = r600_bytecode_add_alu(ctx->bc, &alu);
2267 if (r)
2268 return r;
2269 }
2270 }
2271 return 0;
2272 }
2273
2274 static int tgsi_op2(struct r600_shader_ctx *ctx)
2275 {
2276 return tgsi_op2_s(ctx, 0, 0);
2277 }
2278
2279 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2280 {
2281 return tgsi_op2_s(ctx, 1, 0);
2282 }
2283
2284 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2285 {
2286 return tgsi_op2_s(ctx, 0, 1);
2287 }
2288
2289 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2290 {
2291 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2292 struct r600_bytecode_alu alu;
2293 int i, r;
2294 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2295
2296 for (i = 0; i < lasti + 1; i++) {
2297
2298 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2299 continue;
2300 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2301 alu.op = ctx->inst_info->op;
2302
2303 alu.src[0].sel = V_SQ_ALU_SRC_0;
2304
2305 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2306
2307 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2308
2309 if (i == lasti) {
2310 alu.last = 1;
2311 }
2312 r = r600_bytecode_add_alu(ctx->bc, &alu);
2313 if (r)
2314 return r;
2315 }
2316 return 0;
2317
2318 }
2319
2320 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2321 {
2322 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2323 int i, j, r;
2324 struct r600_bytecode_alu alu;
2325 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2326
2327 for (i = 0 ; i < last_slot; i++) {
2328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2329 alu.op = ctx->inst_info->op;
2330 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2331 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2332
2333 /* RSQ should take the absolute value of src */
2334 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
2335 r600_bytecode_src_set_abs(&alu.src[j]);
2336 }
2337 }
2338 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2339 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2340
2341 if (i == last_slot - 1)
2342 alu.last = 1;
2343 r = r600_bytecode_add_alu(ctx->bc, &alu);
2344 if (r)
2345 return r;
2346 }
2347 return 0;
2348 }
2349
2350 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2351 {
2352 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2353 int i, j, k, r;
2354 struct r600_bytecode_alu alu;
2355 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2356 for (k = 0; k < last_slot; k++) {
2357 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2358 continue;
2359
2360 for (i = 0 ; i < 4; i++) {
2361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2362 alu.op = ctx->inst_info->op;
2363 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2364 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2365 }
2366 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2367 alu.dst.write = (i == k);
2368 if (i == 3)
2369 alu.last = 1;
2370 r = r600_bytecode_add_alu(ctx->bc, &alu);
2371 if (r)
2372 return r;
2373 }
2374 }
2375 return 0;
2376 }
2377
2378 /*
2379 * r600 - trunc to -PI..PI range
2380 * r700 - normalize by dividing by 2PI
2381 * see fdo bug 27901
2382 */
2383 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2384 {
2385 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2386 static float double_pi = 3.1415926535 * 2;
2387 static float neg_pi = -3.1415926535;
2388
2389 int r;
2390 struct r600_bytecode_alu alu;
2391
2392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2393 alu.op = ALU_OP3_MULADD;
2394 alu.is_op3 = 1;
2395
2396 alu.dst.chan = 0;
2397 alu.dst.sel = ctx->temp_reg;
2398 alu.dst.write = 1;
2399
2400 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2401
2402 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2403 alu.src[1].chan = 0;
2404 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2405 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2406 alu.src[2].chan = 0;
2407 alu.last = 1;
2408 r = r600_bytecode_add_alu(ctx->bc, &alu);
2409 if (r)
2410 return r;
2411
2412 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2413 alu.op = ALU_OP1_FRACT;
2414
2415 alu.dst.chan = 0;
2416 alu.dst.sel = ctx->temp_reg;
2417 alu.dst.write = 1;
2418
2419 alu.src[0].sel = ctx->temp_reg;
2420 alu.src[0].chan = 0;
2421 alu.last = 1;
2422 r = r600_bytecode_add_alu(ctx->bc, &alu);
2423 if (r)
2424 return r;
2425
2426 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2427 alu.op = ALU_OP3_MULADD;
2428 alu.is_op3 = 1;
2429
2430 alu.dst.chan = 0;
2431 alu.dst.sel = ctx->temp_reg;
2432 alu.dst.write = 1;
2433
2434 alu.src[0].sel = ctx->temp_reg;
2435 alu.src[0].chan = 0;
2436
2437 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2438 alu.src[1].chan = 0;
2439 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2440 alu.src[2].chan = 0;
2441
2442 if (ctx->bc->chip_class == R600) {
2443 alu.src[1].value = *(uint32_t *)&double_pi;
2444 alu.src[2].value = *(uint32_t *)&neg_pi;
2445 } else {
2446 alu.src[1].sel = V_SQ_ALU_SRC_1;
2447 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2448 alu.src[2].neg = 1;
2449 }
2450
2451 alu.last = 1;
2452 r = r600_bytecode_add_alu(ctx->bc, &alu);
2453 if (r)
2454 return r;
2455 return 0;
2456 }
2457
2458 static int cayman_trig(struct r600_shader_ctx *ctx)
2459 {
2460 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2461 struct r600_bytecode_alu alu;
2462 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2463 int i, r;
2464
2465 r = tgsi_setup_trig(ctx);
2466 if (r)
2467 return r;
2468
2469
2470 for (i = 0; i < last_slot; i++) {
2471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2472 alu.op = ctx->inst_info->op;
2473 alu.dst.chan = i;
2474
2475 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2476 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2477
2478 alu.src[0].sel = ctx->temp_reg;
2479 alu.src[0].chan = 0;
2480 if (i == last_slot - 1)
2481 alu.last = 1;
2482 r = r600_bytecode_add_alu(ctx->bc, &alu);
2483 if (r)
2484 return r;
2485 }
2486 return 0;
2487 }
2488
2489 static int tgsi_trig(struct r600_shader_ctx *ctx)
2490 {
2491 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2492 struct r600_bytecode_alu alu;
2493 int i, r;
2494 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2495
2496 r = tgsi_setup_trig(ctx);
2497 if (r)
2498 return r;
2499
2500 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2501 alu.op = ctx->inst_info->op;
2502 alu.dst.chan = 0;
2503 alu.dst.sel = ctx->temp_reg;
2504 alu.dst.write = 1;
2505
2506 alu.src[0].sel = ctx->temp_reg;
2507 alu.src[0].chan = 0;
2508 alu.last = 1;
2509 r = r600_bytecode_add_alu(ctx->bc, &alu);
2510 if (r)
2511 return r;
2512
2513 /* replicate result */
2514 for (i = 0; i < lasti + 1; i++) {
2515 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2516 continue;
2517
2518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2519 alu.op = ALU_OP1_MOV;
2520
2521 alu.src[0].sel = ctx->temp_reg;
2522 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2523 if (i == lasti)
2524 alu.last = 1;
2525 r = r600_bytecode_add_alu(ctx->bc, &alu);
2526 if (r)
2527 return r;
2528 }
2529 return 0;
2530 }
2531
2532 static int tgsi_scs(struct r600_shader_ctx *ctx)
2533 {
2534 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2535 struct r600_bytecode_alu alu;
2536 int i, r;
2537
2538 /* We'll only need the trig stuff if we are going to write to the
2539 * X or Y components of the destination vector.
2540 */
2541 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2542 r = tgsi_setup_trig(ctx);
2543 if (r)
2544 return r;
2545 }
2546
2547 /* dst.x = COS */
2548 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2549 if (ctx->bc->chip_class == CAYMAN) {
2550 for (i = 0 ; i < 3; i++) {
2551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2552 alu.op = ALU_OP1_COS;
2553 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2554
2555 if (i == 0)
2556 alu.dst.write = 1;
2557 else
2558 alu.dst.write = 0;
2559 alu.src[0].sel = ctx->temp_reg;
2560 alu.src[0].chan = 0;
2561 if (i == 2)
2562 alu.last = 1;
2563 r = r600_bytecode_add_alu(ctx->bc, &alu);
2564 if (r)
2565 return r;
2566 }
2567 } else {
2568 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2569 alu.op = ALU_OP1_COS;
2570 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2571
2572 alu.src[0].sel = ctx->temp_reg;
2573 alu.src[0].chan = 0;
2574 alu.last = 1;
2575 r = r600_bytecode_add_alu(ctx->bc, &alu);
2576 if (r)
2577 return r;
2578 }
2579 }
2580
2581 /* dst.y = SIN */
2582 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2583 if (ctx->bc->chip_class == CAYMAN) {
2584 for (i = 0 ; i < 3; i++) {
2585 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2586 alu.op = ALU_OP1_SIN;
2587 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2588 if (i == 1)
2589 alu.dst.write = 1;
2590 else
2591 alu.dst.write = 0;
2592 alu.src[0].sel = ctx->temp_reg;
2593 alu.src[0].chan = 0;
2594 if (i == 2)
2595 alu.last = 1;
2596 r = r600_bytecode_add_alu(ctx->bc, &alu);
2597 if (r)
2598 return r;
2599 }
2600 } else {
2601 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2602 alu.op = ALU_OP1_SIN;
2603 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2604
2605 alu.src[0].sel = ctx->temp_reg;
2606 alu.src[0].chan = 0;
2607 alu.last = 1;
2608 r = r600_bytecode_add_alu(ctx->bc, &alu);
2609 if (r)
2610 return r;
2611 }
2612 }
2613
2614 /* dst.z = 0.0; */
2615 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2616 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2617
2618 alu.op = ALU_OP1_MOV;
2619
2620 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2621
2622 alu.src[0].sel = V_SQ_ALU_SRC_0;
2623 alu.src[0].chan = 0;
2624
2625 alu.last = 1;
2626
2627 r = r600_bytecode_add_alu(ctx->bc, &alu);
2628 if (r)
2629 return r;
2630 }
2631
2632 /* dst.w = 1.0; */
2633 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2635
2636 alu.op = ALU_OP1_MOV;
2637
2638 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2639
2640 alu.src[0].sel = V_SQ_ALU_SRC_1;
2641 alu.src[0].chan = 0;
2642
2643 alu.last = 1;
2644
2645 r = r600_bytecode_add_alu(ctx->bc, &alu);
2646 if (r)
2647 return r;
2648 }
2649
2650 return 0;
2651 }
2652
2653 static int tgsi_kill(struct r600_shader_ctx *ctx)
2654 {
2655 struct r600_bytecode_alu alu;
2656 int i, r;
2657
2658 for (i = 0; i < 4; i++) {
2659 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2660 alu.op = ctx->inst_info->op;
2661
2662 alu.dst.chan = i;
2663
2664 alu.src[0].sel = V_SQ_ALU_SRC_0;
2665
2666 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILL) {
2667 alu.src[1].sel = V_SQ_ALU_SRC_1;
2668 alu.src[1].neg = 1;
2669 } else {
2670 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2671 }
2672 if (i == 3) {
2673 alu.last = 1;
2674 }
2675 r = r600_bytecode_add_alu(ctx->bc, &alu);
2676 if (r)
2677 return r;
2678 }
2679
2680 /* kill must be last in ALU */
2681 ctx->bc->force_add_cf = 1;
2682 ctx->shader->uses_kill = TRUE;
2683 return 0;
2684 }
2685
2686 static int tgsi_lit(struct r600_shader_ctx *ctx)
2687 {
2688 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2689 struct r600_bytecode_alu alu;
2690 int r;
2691
2692 /* tmp.x = max(src.y, 0.0) */
2693 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2694 alu.op = ALU_OP2_MAX;
2695 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2696 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2697 alu.src[1].chan = 1;
2698
2699 alu.dst.sel = ctx->temp_reg;
2700 alu.dst.chan = 0;
2701 alu.dst.write = 1;
2702
2703 alu.last = 1;
2704 r = r600_bytecode_add_alu(ctx->bc, &alu);
2705 if (r)
2706 return r;
2707
2708 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2709 {
2710 int chan;
2711 int sel;
2712 int i;
2713
2714 if (ctx->bc->chip_class == CAYMAN) {
2715 for (i = 0; i < 3; i++) {
2716 /* tmp.z = log(tmp.x) */
2717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2718 alu.op = ALU_OP1_LOG_CLAMPED;
2719 alu.src[0].sel = ctx->temp_reg;
2720 alu.src[0].chan = 0;
2721 alu.dst.sel = ctx->temp_reg;
2722 alu.dst.chan = i;
2723 if (i == 2) {
2724 alu.dst.write = 1;
2725 alu.last = 1;
2726 } else
2727 alu.dst.write = 0;
2728
2729 r = r600_bytecode_add_alu(ctx->bc, &alu);
2730 if (r)
2731 return r;
2732 }
2733 } else {
2734 /* tmp.z = log(tmp.x) */
2735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2736 alu.op = ALU_OP1_LOG_CLAMPED;
2737 alu.src[0].sel = ctx->temp_reg;
2738 alu.src[0].chan = 0;
2739 alu.dst.sel = ctx->temp_reg;
2740 alu.dst.chan = 2;
2741 alu.dst.write = 1;
2742 alu.last = 1;
2743 r = r600_bytecode_add_alu(ctx->bc, &alu);
2744 if (r)
2745 return r;
2746 }
2747
2748 chan = alu.dst.chan;
2749 sel = alu.dst.sel;
2750
2751 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2753 alu.op = ALU_OP3_MUL_LIT;
2754 alu.src[0].sel = sel;
2755 alu.src[0].chan = chan;
2756 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2757 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2758 alu.dst.sel = ctx->temp_reg;
2759 alu.dst.chan = 0;
2760 alu.dst.write = 1;
2761 alu.is_op3 = 1;
2762 alu.last = 1;
2763 r = r600_bytecode_add_alu(ctx->bc, &alu);
2764 if (r)
2765 return r;
2766
2767 if (ctx->bc->chip_class == CAYMAN) {
2768 for (i = 0; i < 3; i++) {
2769 /* dst.z = exp(tmp.x) */
2770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2771 alu.op = ALU_OP1_EXP_IEEE;
2772 alu.src[0].sel = ctx->temp_reg;
2773 alu.src[0].chan = 0;
2774 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2775 if (i == 2) {
2776 alu.dst.write = 1;
2777 alu.last = 1;
2778 } else
2779 alu.dst.write = 0;
2780 r = r600_bytecode_add_alu(ctx->bc, &alu);
2781 if (r)
2782 return r;
2783 }
2784 } else {
2785 /* dst.z = exp(tmp.x) */
2786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2787 alu.op = ALU_OP1_EXP_IEEE;
2788 alu.src[0].sel = ctx->temp_reg;
2789 alu.src[0].chan = 0;
2790 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2791 alu.last = 1;
2792 r = r600_bytecode_add_alu(ctx->bc, &alu);
2793 if (r)
2794 return r;
2795 }
2796 }
2797
2798 /* dst.x, <- 1.0 */
2799 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2800 alu.op = ALU_OP1_MOV;
2801 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2802 alu.src[0].chan = 0;
2803 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2804 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2805 r = r600_bytecode_add_alu(ctx->bc, &alu);
2806 if (r)
2807 return r;
2808
2809 /* dst.y = max(src.x, 0.0) */
2810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2811 alu.op = ALU_OP2_MAX;
2812 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2813 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2814 alu.src[1].chan = 0;
2815 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2816 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2817 r = r600_bytecode_add_alu(ctx->bc, &alu);
2818 if (r)
2819 return r;
2820
2821 /* dst.w, <- 1.0 */
2822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2823 alu.op = ALU_OP1_MOV;
2824 alu.src[0].sel = V_SQ_ALU_SRC_1;
2825 alu.src[0].chan = 0;
2826 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2827 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2828 alu.last = 1;
2829 r = r600_bytecode_add_alu(ctx->bc, &alu);
2830 if (r)
2831 return r;
2832
2833 return 0;
2834 }
2835
2836 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2837 {
2838 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2839 struct r600_bytecode_alu alu;
2840 int i, r;
2841
2842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2843
2844 /* XXX:
2845 * For state trackers other than OpenGL, we'll want to use
2846 * _RECIPSQRT_IEEE instead.
2847 */
2848 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2849
2850 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2851 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2852 r600_bytecode_src_set_abs(&alu.src[i]);
2853 }
2854 alu.dst.sel = ctx->temp_reg;
2855 alu.dst.write = 1;
2856 alu.last = 1;
2857 r = r600_bytecode_add_alu(ctx->bc, &alu);
2858 if (r)
2859 return r;
2860 /* replicate result */
2861 return tgsi_helper_tempx_replicate(ctx);
2862 }
2863
2864 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2865 {
2866 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2867 struct r600_bytecode_alu alu;
2868 int i, r;
2869
2870 for (i = 0; i < 4; i++) {
2871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2872 alu.src[0].sel = ctx->temp_reg;
2873 alu.op = ALU_OP1_MOV;
2874 alu.dst.chan = i;
2875 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2876 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2877 if (i == 3)
2878 alu.last = 1;
2879 r = r600_bytecode_add_alu(ctx->bc, &alu);
2880 if (r)
2881 return r;
2882 }
2883 return 0;
2884 }
2885
2886 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2887 {
2888 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2889 struct r600_bytecode_alu alu;
2890 int i, r;
2891
2892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2893 alu.op = ctx->inst_info->op;
2894 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2895 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2896 }
2897 alu.dst.sel = ctx->temp_reg;
2898 alu.dst.write = 1;
2899 alu.last = 1;
2900 r = r600_bytecode_add_alu(ctx->bc, &alu);
2901 if (r)
2902 return r;
2903 /* replicate result */
2904 return tgsi_helper_tempx_replicate(ctx);
2905 }
2906
2907 static int cayman_pow(struct r600_shader_ctx *ctx)
2908 {
2909 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2910 int i, r;
2911 struct r600_bytecode_alu alu;
2912 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2913
2914 for (i = 0; i < 3; i++) {
2915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2916 alu.op = ALU_OP1_LOG_IEEE;
2917 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2918 alu.dst.sel = ctx->temp_reg;
2919 alu.dst.chan = i;
2920 alu.dst.write = 1;
2921 if (i == 2)
2922 alu.last = 1;
2923 r = r600_bytecode_add_alu(ctx->bc, &alu);
2924 if (r)
2925 return r;
2926 }
2927
2928 /* b * LOG2(a) */
2929 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2930 alu.op = ALU_OP2_MUL;
2931 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2932 alu.src[1].sel = ctx->temp_reg;
2933 alu.dst.sel = ctx->temp_reg;
2934 alu.dst.write = 1;
2935 alu.last = 1;
2936 r = r600_bytecode_add_alu(ctx->bc, &alu);
2937 if (r)
2938 return r;
2939
2940 for (i = 0; i < last_slot; i++) {
2941 /* POW(a,b) = EXP2(b * LOG2(a))*/
2942 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2943 alu.op = ALU_OP1_EXP_IEEE;
2944 alu.src[0].sel = ctx->temp_reg;
2945
2946 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2947 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2948 if (i == last_slot - 1)
2949 alu.last = 1;
2950 r = r600_bytecode_add_alu(ctx->bc, &alu);
2951 if (r)
2952 return r;
2953 }
2954 return 0;
2955 }
2956
2957 static int tgsi_pow(struct r600_shader_ctx *ctx)
2958 {
2959 struct r600_bytecode_alu alu;
2960 int r;
2961
2962 /* LOG2(a) */
2963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2964 alu.op = ALU_OP1_LOG_IEEE;
2965 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2966 alu.dst.sel = ctx->temp_reg;
2967 alu.dst.write = 1;
2968 alu.last = 1;
2969 r = r600_bytecode_add_alu(ctx->bc, &alu);
2970 if (r)
2971 return r;
2972 /* b * LOG2(a) */
2973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2974 alu.op = ALU_OP2_MUL;
2975 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2976 alu.src[1].sel = ctx->temp_reg;
2977 alu.dst.sel = ctx->temp_reg;
2978 alu.dst.write = 1;
2979 alu.last = 1;
2980 r = r600_bytecode_add_alu(ctx->bc, &alu);
2981 if (r)
2982 return r;
2983 /* POW(a,b) = EXP2(b * LOG2(a))*/
2984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2985 alu.op = ALU_OP1_EXP_IEEE;
2986 alu.src[0].sel = ctx->temp_reg;
2987 alu.dst.sel = ctx->temp_reg;
2988 alu.dst.write = 1;
2989 alu.last = 1;
2990 r = r600_bytecode_add_alu(ctx->bc, &alu);
2991 if (r)
2992 return r;
2993 return tgsi_helper_tempx_replicate(ctx);
2994 }
2995
2996 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2997 {
2998 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2999 struct r600_bytecode_alu alu;
3000 int i, r, j;
3001 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3002 int tmp0 = ctx->temp_reg;
3003 int tmp1 = r600_get_temp(ctx);
3004 int tmp2 = r600_get_temp(ctx);
3005 int tmp3 = r600_get_temp(ctx);
3006 /* Unsigned path:
3007 *
3008 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3009 *
3010 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3011 * 2. tmp0.z = lo (tmp0.x * src2)
3012 * 3. tmp0.w = -tmp0.z
3013 * 4. tmp0.y = hi (tmp0.x * src2)
3014 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3015 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3016 * 7. tmp1.x = tmp0.x - tmp0.w
3017 * 8. tmp1.y = tmp0.x + tmp0.w
3018 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3019 * 10. tmp0.z = hi(tmp0.x * src1) = q
3020 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3021 *
3022 * 12. tmp0.w = src1 - tmp0.y = r
3023 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3024 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3025 *
3026 * if DIV
3027 *
3028 * 15. tmp1.z = tmp0.z + 1 = q + 1
3029 * 16. tmp1.w = tmp0.z - 1 = q - 1
3030 *
3031 * else MOD
3032 *
3033 * 15. tmp1.z = tmp0.w - src2 = r - src2
3034 * 16. tmp1.w = tmp0.w + src2 = r + src2
3035 *
3036 * endif
3037 *
3038 * 17. tmp1.x = tmp1.x & tmp1.y
3039 *
3040 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3041 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3042 *
3043 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3044 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
3045 *
3046 * Signed path:
3047 *
3048 * Same as unsigned, using abs values of the operands,
3049 * and fixing the sign of the result in the end.
3050 */
3051
3052 for (i = 0; i < 4; i++) {
3053 if (!(write_mask & (1<<i)))
3054 continue;
3055
3056 if (signed_op) {
3057
3058 /* tmp2.x = -src0 */
3059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3060 alu.op = ALU_OP2_SUB_INT;
3061
3062 alu.dst.sel = tmp2;
3063 alu.dst.chan = 0;
3064 alu.dst.write = 1;
3065
3066 alu.src[0].sel = V_SQ_ALU_SRC_0;
3067
3068 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3069
3070 alu.last = 1;
3071 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3072 return r;
3073
3074 /* tmp2.y = -src1 */
3075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3076 alu.op = ALU_OP2_SUB_INT;
3077
3078 alu.dst.sel = tmp2;
3079 alu.dst.chan = 1;
3080 alu.dst.write = 1;
3081
3082 alu.src[0].sel = V_SQ_ALU_SRC_0;
3083
3084 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3085
3086 alu.last = 1;
3087 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3088 return r;
3089
3090 /* tmp2.z sign bit is set if src0 and src2 signs are different */
3091 /* it will be a sign of the quotient */
3092 if (!mod) {
3093
3094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3095 alu.op = ALU_OP2_XOR_INT;
3096
3097 alu.dst.sel = tmp2;
3098 alu.dst.chan = 2;
3099 alu.dst.write = 1;
3100
3101 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3102 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3103
3104 alu.last = 1;
3105 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3106 return r;
3107 }
3108
3109 /* tmp2.x = |src0| */
3110 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3111 alu.op = ALU_OP3_CNDGE_INT;
3112 alu.is_op3 = 1;
3113
3114 alu.dst.sel = tmp2;
3115 alu.dst.chan = 0;
3116 alu.dst.write = 1;
3117
3118 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3119 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3120 alu.src[2].sel = tmp2;
3121 alu.src[2].chan = 0;
3122
3123 alu.last = 1;
3124 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3125 return r;
3126
3127 /* tmp2.y = |src1| */
3128 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3129 alu.op = ALU_OP3_CNDGE_INT;
3130 alu.is_op3 = 1;
3131
3132 alu.dst.sel = tmp2;
3133 alu.dst.chan = 1;
3134 alu.dst.write = 1;
3135
3136 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3137 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3138 alu.src[2].sel = tmp2;
3139 alu.src[2].chan = 1;
3140
3141 alu.last = 1;
3142 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3143 return r;
3144
3145 }
3146
3147 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
3148 if (ctx->bc->chip_class == CAYMAN) {
3149 /* tmp3.x = u2f(src2) */
3150 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3151 alu.op = ALU_OP1_UINT_TO_FLT;
3152
3153 alu.dst.sel = tmp3;
3154 alu.dst.chan = 0;
3155 alu.dst.write = 1;
3156
3157 if (signed_op) {
3158 alu.src[0].sel = tmp2;
3159 alu.src[0].chan = 1;
3160 } else {
3161 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3162 }
3163
3164 alu.last = 1;
3165 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3166 return r;
3167
3168 /* tmp0.x = recip(tmp3.x) */
3169 for (j = 0 ; j < 3; j++) {
3170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3171 alu.op = ALU_OP1_RECIP_IEEE;
3172
3173 alu.dst.sel = tmp0;
3174 alu.dst.chan = j;
3175 alu.dst.write = (j == 0);
3176
3177 alu.src[0].sel = tmp3;
3178 alu.src[0].chan = 0;
3179
3180 if (j == 2)
3181 alu.last = 1;
3182 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3183 return r;
3184 }
3185
3186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3187 alu.op = ALU_OP2_MUL;
3188
3189 alu.src[0].sel = tmp0;
3190 alu.src[0].chan = 0;
3191
3192 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3193 alu.src[1].value = 0x4f800000;
3194
3195 alu.dst.sel = tmp3;
3196 alu.dst.write = 1;
3197 alu.last = 1;
3198 r = r600_bytecode_add_alu(ctx->bc, &alu);
3199 if (r)
3200 return r;
3201
3202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3203 alu.op = ALU_OP1_FLT_TO_UINT;
3204
3205 alu.dst.sel = tmp0;
3206 alu.dst.chan = 0;
3207 alu.dst.write = 1;
3208
3209 alu.src[0].sel = tmp3;
3210 alu.src[0].chan = 0;
3211
3212 alu.last = 1;
3213 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3214 return r;
3215
3216 } else {
3217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3218 alu.op = ALU_OP1_RECIP_UINT;
3219
3220 alu.dst.sel = tmp0;
3221 alu.dst.chan = 0;
3222 alu.dst.write = 1;
3223
3224 if (signed_op) {
3225 alu.src[0].sel = tmp2;
3226 alu.src[0].chan = 1;
3227 } else {
3228 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3229 }
3230
3231 alu.last = 1;
3232 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3233 return r;
3234 }
3235
3236 /* 2. tmp0.z = lo (tmp0.x * src2) */
3237 if (ctx->bc->chip_class == CAYMAN) {
3238 for (j = 0 ; j < 4; j++) {
3239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3240 alu.op = ALU_OP2_MULLO_UINT;
3241
3242 alu.dst.sel = tmp0;
3243 alu.dst.chan = j;
3244 alu.dst.write = (j == 2);
3245
3246 alu.src[0].sel = tmp0;
3247 alu.src[0].chan = 0;
3248 if (signed_op) {
3249 alu.src[1].sel = tmp2;
3250 alu.src[1].chan = 1;
3251 } else {
3252 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3253 }
3254
3255 alu.last = (j == 3);
3256 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3257 return r;
3258 }
3259 } else {
3260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3261 alu.op = ALU_OP2_MULLO_UINT;
3262
3263 alu.dst.sel = tmp0;
3264 alu.dst.chan = 2;
3265 alu.dst.write = 1;
3266
3267 alu.src[0].sel = tmp0;
3268 alu.src[0].chan = 0;
3269 if (signed_op) {
3270 alu.src[1].sel = tmp2;
3271 alu.src[1].chan = 1;
3272 } else {
3273 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3274 }
3275
3276 alu.last = 1;
3277 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3278 return r;
3279 }
3280
3281 /* 3. tmp0.w = -tmp0.z */
3282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3283 alu.op = ALU_OP2_SUB_INT;
3284
3285 alu.dst.sel = tmp0;
3286 alu.dst.chan = 3;
3287 alu.dst.write = 1;
3288
3289 alu.src[0].sel = V_SQ_ALU_SRC_0;
3290 alu.src[1].sel = tmp0;
3291 alu.src[1].chan = 2;
3292
3293 alu.last = 1;
3294 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3295 return r;
3296
3297 /* 4. tmp0.y = hi (tmp0.x * src2) */
3298 if (ctx->bc->chip_class == CAYMAN) {
3299 for (j = 0 ; j < 4; j++) {
3300 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3301 alu.op = ALU_OP2_MULHI_UINT;
3302
3303 alu.dst.sel = tmp0;
3304 alu.dst.chan = j;
3305 alu.dst.write = (j == 1);
3306
3307 alu.src[0].sel = tmp0;
3308 alu.src[0].chan = 0;
3309
3310 if (signed_op) {
3311 alu.src[1].sel = tmp2;
3312 alu.src[1].chan = 1;
3313 } else {
3314 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3315 }
3316 alu.last = (j == 3);
3317 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3318 return r;
3319 }
3320 } else {
3321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3322 alu.op = ALU_OP2_MULHI_UINT;
3323
3324 alu.dst.sel = tmp0;
3325 alu.dst.chan = 1;
3326 alu.dst.write = 1;
3327
3328 alu.src[0].sel = tmp0;
3329 alu.src[0].chan = 0;
3330
3331 if (signed_op) {
3332 alu.src[1].sel = tmp2;
3333 alu.src[1].chan = 1;
3334 } else {
3335 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3336 }
3337
3338 alu.last = 1;
3339 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3340 return r;
3341 }
3342
3343 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3345 alu.op = ALU_OP3_CNDE_INT;
3346 alu.is_op3 = 1;
3347
3348 alu.dst.sel = tmp0;
3349 alu.dst.chan = 2;
3350 alu.dst.write = 1;
3351
3352 alu.src[0].sel = tmp0;
3353 alu.src[0].chan = 1;
3354 alu.src[1].sel = tmp0;
3355 alu.src[1].chan = 3;
3356 alu.src[2].sel = tmp0;
3357 alu.src[2].chan = 2;
3358
3359 alu.last = 1;
3360 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3361 return r;
3362
3363 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3364 if (ctx->bc->chip_class == CAYMAN) {
3365 for (j = 0 ; j < 4; j++) {
3366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3367 alu.op = ALU_OP2_MULHI_UINT;
3368
3369 alu.dst.sel = tmp0;
3370 alu.dst.chan = j;
3371 alu.dst.write = (j == 3);
3372
3373 alu.src[0].sel = tmp0;
3374 alu.src[0].chan = 2;
3375
3376 alu.src[1].sel = tmp0;
3377 alu.src[1].chan = 0;
3378
3379 alu.last = (j == 3);
3380 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3381 return r;
3382 }
3383 } else {
3384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3385 alu.op = ALU_OP2_MULHI_UINT;
3386
3387 alu.dst.sel = tmp0;
3388 alu.dst.chan = 3;
3389 alu.dst.write = 1;
3390
3391 alu.src[0].sel = tmp0;
3392 alu.src[0].chan = 2;
3393
3394 alu.src[1].sel = tmp0;
3395 alu.src[1].chan = 0;
3396
3397 alu.last = 1;
3398 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3399 return r;
3400 }
3401
3402 /* 7. tmp1.x = tmp0.x - tmp0.w */
3403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3404 alu.op = ALU_OP2_SUB_INT;
3405
3406 alu.dst.sel = tmp1;
3407 alu.dst.chan = 0;
3408 alu.dst.write = 1;
3409
3410 alu.src[0].sel = tmp0;
3411 alu.src[0].chan = 0;
3412 alu.src[1].sel = tmp0;
3413 alu.src[1].chan = 3;
3414
3415 alu.last = 1;
3416 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3417 return r;
3418
3419 /* 8. tmp1.y = tmp0.x + tmp0.w */
3420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3421 alu.op = ALU_OP2_ADD_INT;
3422
3423 alu.dst.sel = tmp1;
3424 alu.dst.chan = 1;
3425 alu.dst.write = 1;
3426
3427 alu.src[0].sel = tmp0;
3428 alu.src[0].chan = 0;
3429 alu.src[1].sel = tmp0;
3430 alu.src[1].chan = 3;
3431
3432 alu.last = 1;
3433 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3434 return r;
3435
3436 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3437 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3438 alu.op = ALU_OP3_CNDE_INT;
3439 alu.is_op3 = 1;
3440
3441 alu.dst.sel = tmp0;
3442 alu.dst.chan = 0;
3443 alu.dst.write = 1;
3444
3445 alu.src[0].sel = tmp0;
3446 alu.src[0].chan = 1;
3447 alu.src[1].sel = tmp1;
3448 alu.src[1].chan = 1;
3449 alu.src[2].sel = tmp1;
3450 alu.src[2].chan = 0;
3451
3452 alu.last = 1;
3453 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3454 return r;
3455
3456 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3457 if (ctx->bc->chip_class == CAYMAN) {
3458 for (j = 0 ; j < 4; j++) {
3459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3460 alu.op = ALU_OP2_MULHI_UINT;
3461
3462 alu.dst.sel = tmp0;
3463 alu.dst.chan = j;
3464 alu.dst.write = (j == 2);
3465
3466 alu.src[0].sel = tmp0;
3467 alu.src[0].chan = 0;
3468
3469 if (signed_op) {
3470 alu.src[1].sel = tmp2;
3471 alu.src[1].chan = 0;
3472 } else {
3473 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3474 }
3475
3476 alu.last = (j == 3);
3477 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3478 return r;
3479 }
3480 } else {
3481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3482 alu.op = ALU_OP2_MULHI_UINT;
3483
3484 alu.dst.sel = tmp0;
3485 alu.dst.chan = 2;
3486 alu.dst.write = 1;
3487
3488 alu.src[0].sel = tmp0;
3489 alu.src[0].chan = 0;
3490
3491 if (signed_op) {
3492 alu.src[1].sel = tmp2;
3493 alu.src[1].chan = 0;
3494 } else {
3495 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3496 }
3497
3498 alu.last = 1;
3499 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3500 return r;
3501 }
3502
3503 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3504 if (ctx->bc->chip_class == CAYMAN) {
3505 for (j = 0 ; j < 4; j++) {
3506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3507 alu.op = ALU_OP2_MULLO_UINT;
3508
3509 alu.dst.sel = tmp0;
3510 alu.dst.chan = j;
3511 alu.dst.write = (j == 1);
3512
3513 if (signed_op) {
3514 alu.src[0].sel = tmp2;
3515 alu.src[0].chan = 1;
3516 } else {
3517 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3518 }
3519
3520 alu.src[1].sel = tmp0;
3521 alu.src[1].chan = 2;
3522
3523 alu.last = (j == 3);
3524 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3525 return r;
3526 }
3527 } else {
3528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3529 alu.op = ALU_OP2_MULLO_UINT;
3530
3531 alu.dst.sel = tmp0;
3532 alu.dst.chan = 1;
3533 alu.dst.write = 1;
3534
3535 if (signed_op) {
3536 alu.src[0].sel = tmp2;
3537 alu.src[0].chan = 1;
3538 } else {
3539 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3540 }
3541
3542 alu.src[1].sel = tmp0;
3543 alu.src[1].chan = 2;
3544
3545 alu.last = 1;
3546 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3547 return r;
3548 }
3549
3550 /* 12. tmp0.w = src1 - tmp0.y = r */
3551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3552 alu.op = ALU_OP2_SUB_INT;
3553
3554 alu.dst.sel = tmp0;
3555 alu.dst.chan = 3;
3556 alu.dst.write = 1;
3557
3558 if (signed_op) {
3559 alu.src[0].sel = tmp2;
3560 alu.src[0].chan = 0;
3561 } else {
3562 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3563 }
3564
3565 alu.src[1].sel = tmp0;
3566 alu.src[1].chan = 1;
3567
3568 alu.last = 1;
3569 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3570 return r;
3571
3572 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3574 alu.op = ALU_OP2_SETGE_UINT;
3575
3576 alu.dst.sel = tmp1;
3577 alu.dst.chan = 0;
3578 alu.dst.write = 1;
3579
3580 alu.src[0].sel = tmp0;
3581 alu.src[0].chan = 3;
3582 if (signed_op) {
3583 alu.src[1].sel = tmp2;
3584 alu.src[1].chan = 1;
3585 } else {
3586 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3587 }
3588
3589 alu.last = 1;
3590 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3591 return r;
3592
3593 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3594 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3595 alu.op = ALU_OP2_SETGE_UINT;
3596
3597 alu.dst.sel = tmp1;
3598 alu.dst.chan = 1;
3599 alu.dst.write = 1;
3600
3601 if (signed_op) {
3602 alu.src[0].sel = tmp2;
3603 alu.src[0].chan = 0;
3604 } else {
3605 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3606 }
3607
3608 alu.src[1].sel = tmp0;
3609 alu.src[1].chan = 1;
3610
3611 alu.last = 1;
3612 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3613 return r;
3614
3615 if (mod) { /* UMOD */
3616
3617 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3619 alu.op = ALU_OP2_SUB_INT;
3620
3621 alu.dst.sel = tmp1;
3622 alu.dst.chan = 2;
3623 alu.dst.write = 1;
3624
3625 alu.src[0].sel = tmp0;
3626 alu.src[0].chan = 3;
3627
3628 if (signed_op) {
3629 alu.src[1].sel = tmp2;
3630 alu.src[1].chan = 1;
3631 } else {
3632 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3633 }
3634
3635 alu.last = 1;
3636 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3637 return r;
3638
3639 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3640 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3641 alu.op = ALU_OP2_ADD_INT;
3642
3643 alu.dst.sel = tmp1;
3644 alu.dst.chan = 3;
3645 alu.dst.write = 1;
3646
3647 alu.src[0].sel = tmp0;
3648 alu.src[0].chan = 3;
3649 if (signed_op) {
3650 alu.src[1].sel = tmp2;
3651 alu.src[1].chan = 1;
3652 } else {
3653 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3654 }
3655
3656 alu.last = 1;
3657 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3658 return r;
3659
3660 } else { /* UDIV */
3661
3662 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3664 alu.op = ALU_OP2_ADD_INT;
3665
3666 alu.dst.sel = tmp1;
3667 alu.dst.chan = 2;
3668 alu.dst.write = 1;
3669
3670 alu.src[0].sel = tmp0;
3671 alu.src[0].chan = 2;
3672 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3673
3674 alu.last = 1;
3675 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3676 return r;
3677
3678 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3679 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3680 alu.op = ALU_OP2_ADD_INT;
3681
3682 alu.dst.sel = tmp1;
3683 alu.dst.chan = 3;
3684 alu.dst.write = 1;
3685
3686 alu.src[0].sel = tmp0;
3687 alu.src[0].chan = 2;
3688 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3689
3690 alu.last = 1;
3691 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3692 return r;
3693
3694 }
3695
3696 /* 17. tmp1.x = tmp1.x & tmp1.y */
3697 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3698 alu.op = ALU_OP2_AND_INT;
3699
3700 alu.dst.sel = tmp1;
3701 alu.dst.chan = 0;
3702 alu.dst.write = 1;
3703
3704 alu.src[0].sel = tmp1;
3705 alu.src[0].chan = 0;
3706 alu.src[1].sel = tmp1;
3707 alu.src[1].chan = 1;
3708
3709 alu.last = 1;
3710 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3711 return r;
3712
3713 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3714 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3715 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3716 alu.op = ALU_OP3_CNDE_INT;
3717 alu.is_op3 = 1;
3718
3719 alu.dst.sel = tmp0;
3720 alu.dst.chan = 2;
3721 alu.dst.write = 1;
3722
3723 alu.src[0].sel = tmp1;
3724 alu.src[0].chan = 0;
3725 alu.src[1].sel = tmp0;
3726 alu.src[1].chan = mod ? 3 : 2;
3727 alu.src[2].sel = tmp1;
3728 alu.src[2].chan = 2;
3729
3730 alu.last = 1;
3731 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3732 return r;
3733
3734 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3736 alu.op = ALU_OP3_CNDE_INT;
3737 alu.is_op3 = 1;
3738
3739 if (signed_op) {
3740 alu.dst.sel = tmp0;
3741 alu.dst.chan = 2;
3742 alu.dst.write = 1;
3743 } else {
3744 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3745 }
3746
3747 alu.src[0].sel = tmp1;
3748 alu.src[0].chan = 1;
3749 alu.src[1].sel = tmp1;
3750 alu.src[1].chan = 3;
3751 alu.src[2].sel = tmp0;
3752 alu.src[2].chan = 2;
3753
3754 alu.last = 1;
3755 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3756 return r;
3757
3758 if (signed_op) {
3759
3760 /* fix the sign of the result */
3761
3762 if (mod) {
3763
3764 /* tmp0.x = -tmp0.z */
3765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3766 alu.op = ALU_OP2_SUB_INT;
3767
3768 alu.dst.sel = tmp0;
3769 alu.dst.chan = 0;
3770 alu.dst.write = 1;
3771
3772 alu.src[0].sel = V_SQ_ALU_SRC_0;
3773 alu.src[1].sel = tmp0;
3774 alu.src[1].chan = 2;
3775
3776 alu.last = 1;
3777 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3778 return r;
3779
3780 /* sign of the remainder is the same as the sign of src0 */
3781 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3783 alu.op = ALU_OP3_CNDGE_INT;
3784 alu.is_op3 = 1;
3785
3786 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3787
3788 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3789 alu.src[1].sel = tmp0;
3790 alu.src[1].chan = 2;
3791 alu.src[2].sel = tmp0;
3792 alu.src[2].chan = 0;
3793
3794 alu.last = 1;
3795 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3796 return r;
3797
3798 } else {
3799
3800 /* tmp0.x = -tmp0.z */
3801 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3802 alu.op = ALU_OP2_SUB_INT;
3803
3804 alu.dst.sel = tmp0;
3805 alu.dst.chan = 0;
3806 alu.dst.write = 1;
3807
3808 alu.src[0].sel = V_SQ_ALU_SRC_0;
3809 alu.src[1].sel = tmp0;
3810 alu.src[1].chan = 2;
3811
3812 alu.last = 1;
3813 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3814 return r;
3815
3816 /* fix the quotient sign (same as the sign of src0*src1) */
3817 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3819 alu.op = ALU_OP3_CNDGE_INT;
3820 alu.is_op3 = 1;
3821
3822 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3823
3824 alu.src[0].sel = tmp2;
3825 alu.src[0].chan = 2;
3826 alu.src[1].sel = tmp0;
3827 alu.src[1].chan = 2;
3828 alu.src[2].sel = tmp0;
3829 alu.src[2].chan = 0;
3830
3831 alu.last = 1;
3832 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3833 return r;
3834 }
3835 }
3836 }
3837 return 0;
3838 }
3839
3840 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3841 {
3842 return tgsi_divmod(ctx, 0, 0);
3843 }
3844
3845 static int tgsi_umod(struct r600_shader_ctx *ctx)
3846 {
3847 return tgsi_divmod(ctx, 1, 0);
3848 }
3849
3850 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3851 {
3852 return tgsi_divmod(ctx, 0, 1);
3853 }
3854
3855 static int tgsi_imod(struct r600_shader_ctx *ctx)
3856 {
3857 return tgsi_divmod(ctx, 1, 1);
3858 }
3859
3860
3861 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3862 {
3863 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3864 struct r600_bytecode_alu alu;
3865 int i, r;
3866 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3867 int last_inst = tgsi_last_instruction(write_mask);
3868
3869 for (i = 0; i < 4; i++) {
3870 if (!(write_mask & (1<<i)))
3871 continue;
3872
3873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3874 alu.op = ALU_OP1_TRUNC;
3875
3876 alu.dst.sel = ctx->temp_reg;
3877 alu.dst.chan = i;
3878 alu.dst.write = 1;
3879
3880 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3881 if (i == last_inst)
3882 alu.last = 1;
3883 r = r600_bytecode_add_alu(ctx->bc, &alu);
3884 if (r)
3885 return r;
3886 }
3887
3888 for (i = 0; i < 4; i++) {
3889 if (!(write_mask & (1<<i)))
3890 continue;
3891
3892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3893 alu.op = ctx->inst_info->op;
3894
3895 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3896
3897 alu.src[0].sel = ctx->temp_reg;
3898 alu.src[0].chan = i;
3899
3900 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3901 alu.last = 1;
3902 r = r600_bytecode_add_alu(ctx->bc, &alu);
3903 if (r)
3904 return r;
3905 }
3906
3907 return 0;
3908 }
3909
3910 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3911 {
3912 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3913 struct r600_bytecode_alu alu;
3914 int i, r;
3915 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3916 int last_inst = tgsi_last_instruction(write_mask);
3917
3918 /* tmp = -src */
3919 for (i = 0; i < 4; i++) {
3920 if (!(write_mask & (1<<i)))
3921 continue;
3922
3923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3924 alu.op = ALU_OP2_SUB_INT;
3925
3926 alu.dst.sel = ctx->temp_reg;
3927 alu.dst.chan = i;
3928 alu.dst.write = 1;
3929
3930 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3931 alu.src[0].sel = V_SQ_ALU_SRC_0;
3932
3933 if (i == last_inst)
3934 alu.last = 1;
3935 r = r600_bytecode_add_alu(ctx->bc, &alu);
3936 if (r)
3937 return r;
3938 }
3939
3940 /* dst = (src >= 0 ? src : tmp) */
3941 for (i = 0; i < 4; i++) {
3942 if (!(write_mask & (1<<i)))
3943 continue;
3944
3945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3946 alu.op = ALU_OP3_CNDGE_INT;
3947 alu.is_op3 = 1;
3948 alu.dst.write = 1;
3949
3950 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3951
3952 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3953 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3954 alu.src[2].sel = ctx->temp_reg;
3955 alu.src[2].chan = i;
3956
3957 if (i == last_inst)
3958 alu.last = 1;
3959 r = r600_bytecode_add_alu(ctx->bc, &alu);
3960 if (r)
3961 return r;
3962 }
3963 return 0;
3964 }
3965
3966 static int tgsi_issg(struct r600_shader_ctx *ctx)
3967 {
3968 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3969 struct r600_bytecode_alu alu;
3970 int i, r;
3971 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3972 int last_inst = tgsi_last_instruction(write_mask);
3973
3974 /* tmp = (src >= 0 ? src : -1) */
3975 for (i = 0; i < 4; i++) {
3976 if (!(write_mask & (1<<i)))
3977 continue;
3978
3979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3980 alu.op = ALU_OP3_CNDGE_INT;
3981 alu.is_op3 = 1;
3982
3983 alu.dst.sel = ctx->temp_reg;
3984 alu.dst.chan = i;
3985 alu.dst.write = 1;
3986
3987 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3988 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3989 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3990
3991 if (i == last_inst)
3992 alu.last = 1;
3993 r = r600_bytecode_add_alu(ctx->bc, &alu);
3994 if (r)
3995 return r;
3996 }
3997
3998 /* dst = (tmp > 0 ? 1 : tmp) */
3999 for (i = 0; i < 4; i++) {
4000 if (!(write_mask & (1<<i)))
4001 continue;
4002
4003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4004 alu.op = ALU_OP3_CNDGT_INT;
4005 alu.is_op3 = 1;
4006 alu.dst.write = 1;
4007
4008 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4009
4010 alu.src[0].sel = ctx->temp_reg;
4011 alu.src[0].chan = i;
4012
4013 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4014
4015 alu.src[2].sel = ctx->temp_reg;
4016 alu.src[2].chan = i;
4017
4018 if (i == last_inst)
4019 alu.last = 1;
4020 r = r600_bytecode_add_alu(ctx->bc, &alu);
4021 if (r)
4022 return r;
4023 }
4024 return 0;
4025 }
4026
4027
4028
4029 static int tgsi_ssg(struct r600_shader_ctx *ctx)
4030 {
4031 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4032 struct r600_bytecode_alu alu;
4033 int i, r;
4034
4035 /* tmp = (src > 0 ? 1 : src) */
4036 for (i = 0; i < 4; i++) {
4037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4038 alu.op = ALU_OP3_CNDGT;
4039 alu.is_op3 = 1;
4040
4041 alu.dst.sel = ctx->temp_reg;
4042 alu.dst.chan = i;
4043
4044 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4045 alu.src[1].sel = V_SQ_ALU_SRC_1;
4046 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4047
4048 if (i == 3)
4049 alu.last = 1;
4050 r = r600_bytecode_add_alu(ctx->bc, &alu);
4051 if (r)
4052 return r;
4053 }
4054
4055 /* dst = (-tmp > 0 ? -1 : tmp) */
4056 for (i = 0; i < 4; i++) {
4057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4058 alu.op = ALU_OP3_CNDGT;
4059 alu.is_op3 = 1;
4060 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4061
4062 alu.src[0].sel = ctx->temp_reg;
4063 alu.src[0].chan = i;
4064 alu.src[0].neg = 1;
4065
4066 alu.src[1].sel = V_SQ_ALU_SRC_1;
4067 alu.src[1].neg = 1;
4068
4069 alu.src[2].sel = ctx->temp_reg;
4070 alu.src[2].chan = i;
4071
4072 if (i == 3)
4073 alu.last = 1;
4074 r = r600_bytecode_add_alu(ctx->bc, &alu);
4075 if (r)
4076 return r;
4077 }
4078 return 0;
4079 }
4080
4081 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
4082 {
4083 struct r600_bytecode_alu alu;
4084 int i, r;
4085
4086 for (i = 0; i < 4; i++) {
4087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4088 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
4089 alu.op = ALU_OP0_NOP;
4090 alu.dst.chan = i;
4091 } else {
4092 alu.op = ALU_OP1_MOV;
4093 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4094 alu.src[0].sel = ctx->temp_reg;
4095 alu.src[0].chan = i;
4096 }
4097 if (i == 3) {
4098 alu.last = 1;
4099 }
4100 r = r600_bytecode_add_alu(ctx->bc, &alu);
4101 if (r)
4102 return r;
4103 }
4104 return 0;
4105 }
4106
4107 static int tgsi_op3(struct r600_shader_ctx *ctx)
4108 {
4109 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4110 struct r600_bytecode_alu alu;
4111 int i, j, r;
4112 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4113
4114 for (i = 0; i < lasti + 1; i++) {
4115 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4116 continue;
4117
4118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4119 alu.op = ctx->inst_info->op;
4120 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4121 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4122 }
4123
4124 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4125 alu.dst.chan = i;
4126 alu.dst.write = 1;
4127 alu.is_op3 = 1;
4128 if (i == lasti) {
4129 alu.last = 1;
4130 }
4131 r = r600_bytecode_add_alu(ctx->bc, &alu);
4132 if (r)
4133 return r;
4134 }
4135 return 0;
4136 }
4137
4138 static int tgsi_dp(struct r600_shader_ctx *ctx)
4139 {
4140 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4141 struct r600_bytecode_alu alu;
4142 int i, j, r;
4143
4144 for (i = 0; i < 4; i++) {
4145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4146 alu.op = ctx->inst_info->op;
4147 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4148 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4149 }
4150
4151 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4152 alu.dst.chan = i;
4153 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4154 /* handle some special cases */
4155 switch (ctx->inst_info->tgsi_opcode) {
4156 case TGSI_OPCODE_DP2:
4157 if (i > 1) {
4158 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4159 alu.src[0].chan = alu.src[1].chan = 0;
4160 }
4161 break;
4162 case TGSI_OPCODE_DP3:
4163 if (i > 2) {
4164 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4165 alu.src[0].chan = alu.src[1].chan = 0;
4166 }
4167 break;
4168 case TGSI_OPCODE_DPH:
4169 if (i == 3) {
4170 alu.src[0].sel = V_SQ_ALU_SRC_1;
4171 alu.src[0].chan = 0;
4172 alu.src[0].neg = 0;
4173 }
4174 break;
4175 default:
4176 break;
4177 }
4178 if (i == 3) {
4179 alu.last = 1;
4180 }
4181 r = r600_bytecode_add_alu(ctx->bc, &alu);
4182 if (r)
4183 return r;
4184 }
4185 return 0;
4186 }
4187
4188 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
4189 unsigned index)
4190 {
4191 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4192 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
4193 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
4194 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
4195 ctx->src[index].neg || ctx->src[index].abs;
4196 }
4197
4198 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
4199 unsigned index)
4200 {
4201 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4202 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
4203 }
4204
4205 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
4206 {
4207 struct r600_bytecode_vtx vtx;
4208 struct r600_bytecode_alu alu;
4209 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4210 int src_gpr, r, i;
4211 int id = tgsi_tex_get_src_gpr(ctx, 1);
4212
4213 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4214 if (src_requires_loading) {
4215 for (i = 0; i < 4; i++) {
4216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4217 alu.op = ALU_OP1_MOV;
4218 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4219 alu.dst.sel = ctx->temp_reg;
4220 alu.dst.chan = i;
4221 if (i == 3)
4222 alu.last = 1;
4223 alu.dst.write = 1;
4224 r = r600_bytecode_add_alu(ctx->bc, &alu);
4225 if (r)
4226 return r;
4227 }
4228 src_gpr = ctx->temp_reg;
4229 }
4230
4231 memset(&vtx, 0, sizeof(vtx));
4232 vtx.op = FETCH_OP_VFETCH;
4233 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
4234 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
4235 vtx.src_gpr = src_gpr;
4236 vtx.mega_fetch_count = 16;
4237 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4238 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
4239 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
4240 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
4241 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
4242 vtx.use_const_fields = 1;
4243 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
4244
4245 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
4246 return r;
4247
4248 if (ctx->bc->chip_class >= EVERGREEN)
4249 return 0;
4250
4251 for (i = 0; i < 4; i++) {
4252 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4253 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4254 continue;
4255
4256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4257 alu.op = ALU_OP2_AND_INT;
4258
4259 alu.dst.chan = i;
4260 alu.dst.sel = vtx.dst_gpr;
4261 alu.dst.write = 1;
4262
4263 alu.src[0].sel = vtx.dst_gpr;
4264 alu.src[0].chan = i;
4265
4266 alu.src[1].sel = 512 + (id * 2);
4267 alu.src[1].chan = i % 4;
4268 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4269
4270 if (i == lasti)
4271 alu.last = 1;
4272 r = r600_bytecode_add_alu(ctx->bc, &alu);
4273 if (r)
4274 return r;
4275 }
4276
4277 if (inst->Dst[0].Register.WriteMask & 3) {
4278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4279 alu.op = ALU_OP2_OR_INT;
4280
4281 alu.dst.chan = 3;
4282 alu.dst.sel = vtx.dst_gpr;
4283 alu.dst.write = 1;
4284
4285 alu.src[0].sel = vtx.dst_gpr;
4286 alu.src[0].chan = 3;
4287
4288 alu.src[1].sel = 512 + (id * 2) + 1;
4289 alu.src[1].chan = 0;
4290 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4291
4292 alu.last = 1;
4293 r = r600_bytecode_add_alu(ctx->bc, &alu);
4294 if (r)
4295 return r;
4296 }
4297 return 0;
4298 }
4299
4300 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
4301 {
4302 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4303 struct r600_bytecode_alu alu;
4304 int r;
4305 int id = tgsi_tex_get_src_gpr(ctx, 1);
4306
4307 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4308 alu.op = ALU_OP1_MOV;
4309
4310 if (ctx->bc->chip_class >= EVERGREEN) {
4311 alu.src[0].sel = 512 + (id / 4);
4312 alu.src[0].chan = id % 4;
4313 } else {
4314 /* r600 we have them at channel 2 of the second dword */
4315 alu.src[0].sel = 512 + (id * 2) + 1;
4316 alu.src[0].chan = 1;
4317 }
4318 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4319 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4320 alu.last = 1;
4321 r = r600_bytecode_add_alu(ctx->bc, &alu);
4322 if (r)
4323 return r;
4324 return 0;
4325 }
4326
4327 static int tgsi_tex(struct r600_shader_ctx *ctx)
4328 {
4329 static float one_point_five = 1.5f;
4330 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4331 struct r600_bytecode_tex tex;
4332 struct r600_bytecode_alu alu;
4333 unsigned src_gpr;
4334 int r, i, j;
4335 int opcode;
4336 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
4337 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4338 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
4339 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
4340
4341 /* Texture fetch instructions can only use gprs as source.
4342 * Also they cannot negate the source or take the absolute value */
4343 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
4344 tgsi_tex_src_requires_loading(ctx, 0)) ||
4345 read_compressed_msaa;
4346 boolean src_loaded = FALSE;
4347 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
4348 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
4349 boolean has_txq_cube_array_z = false;
4350
4351 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
4352 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4353 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
4354 if (inst->Dst[0].Register.WriteMask & 4) {
4355 ctx->shader->has_txq_cube_array_z_comp = true;
4356 has_txq_cube_array_z = true;
4357 }
4358
4359 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
4360 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4361 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4362 sampler_src_reg = 2;
4363
4364 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4365
4366 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
4367 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
4368 ctx->shader->uses_tex_buffers = true;
4369 return r600_do_buffer_txq(ctx);
4370 }
4371 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4372 if (ctx->bc->chip_class < EVERGREEN)
4373 ctx->shader->uses_tex_buffers = true;
4374 return do_vtx_fetch_inst(ctx, src_requires_loading);
4375 }
4376 }
4377
4378 /* get offset values */
4379 if (inst->Texture.NumOffsets) {
4380 assert(inst->Texture.NumOffsets == 1);
4381
4382 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
4383 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
4384 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
4385 }
4386
4387 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
4388 /* TGSI moves the sampler to src reg 3 for TXD */
4389 sampler_src_reg = 3;
4390
4391 for (i = 1; i < 3; i++) {
4392 /* set gradients h/v */
4393 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4394 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
4395 FETCH_OP_SET_GRADIENTS_V;
4396 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4397 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4398
4399 if (tgsi_tex_src_requires_loading(ctx, i)) {
4400 tex.src_gpr = r600_get_temp(ctx);
4401 tex.src_sel_x = 0;
4402 tex.src_sel_y = 1;
4403 tex.src_sel_z = 2;
4404 tex.src_sel_w = 3;
4405
4406 for (j = 0; j < 4; j++) {
4407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4408 alu.op = ALU_OP1_MOV;
4409 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
4410 alu.dst.sel = tex.src_gpr;
4411 alu.dst.chan = j;
4412 if (j == 3)
4413 alu.last = 1;
4414 alu.dst.write = 1;
4415 r = r600_bytecode_add_alu(ctx->bc, &alu);
4416 if (r)
4417 return r;
4418 }
4419
4420 } else {
4421 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
4422 tex.src_sel_x = ctx->src[i].swizzle[0];
4423 tex.src_sel_y = ctx->src[i].swizzle[1];
4424 tex.src_sel_z = ctx->src[i].swizzle[2];
4425 tex.src_sel_w = ctx->src[i].swizzle[3];
4426 tex.src_rel = ctx->src[i].rel;
4427 }
4428 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
4429 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4430 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
4431 tex.coord_type_x = 1;
4432 tex.coord_type_y = 1;
4433 tex.coord_type_z = 1;
4434 tex.coord_type_w = 1;
4435 }
4436 r = r600_bytecode_add_tex(ctx->bc, &tex);
4437 if (r)
4438 return r;
4439 }
4440 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
4441 int out_chan;
4442 /* Add perspective divide */
4443 if (ctx->bc->chip_class == CAYMAN) {
4444 out_chan = 2;
4445 for (i = 0; i < 3; i++) {
4446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4447 alu.op = ALU_OP1_RECIP_IEEE;
4448 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4449
4450 alu.dst.sel = ctx->temp_reg;
4451 alu.dst.chan = i;
4452 if (i == 2)
4453 alu.last = 1;
4454 if (out_chan == i)
4455 alu.dst.write = 1;
4456 r = r600_bytecode_add_alu(ctx->bc, &alu);
4457 if (r)
4458 return r;
4459 }
4460
4461 } else {
4462 out_chan = 3;
4463 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4464 alu.op = ALU_OP1_RECIP_IEEE;
4465 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4466
4467 alu.dst.sel = ctx->temp_reg;
4468 alu.dst.chan = out_chan;
4469 alu.last = 1;
4470 alu.dst.write = 1;
4471 r = r600_bytecode_add_alu(ctx->bc, &alu);
4472 if (r)
4473 return r;
4474 }
4475
4476 for (i = 0; i < 3; i++) {
4477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4478 alu.op = ALU_OP2_MUL;
4479 alu.src[0].sel = ctx->temp_reg;
4480 alu.src[0].chan = out_chan;
4481 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4482 alu.dst.sel = ctx->temp_reg;
4483 alu.dst.chan = i;
4484 alu.dst.write = 1;
4485 r = r600_bytecode_add_alu(ctx->bc, &alu);
4486 if (r)
4487 return r;
4488 }
4489 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4490 alu.op = ALU_OP1_MOV;
4491 alu.src[0].sel = V_SQ_ALU_SRC_1;
4492 alu.src[0].chan = 0;
4493 alu.dst.sel = ctx->temp_reg;
4494 alu.dst.chan = 3;
4495 alu.last = 1;
4496 alu.dst.write = 1;
4497 r = r600_bytecode_add_alu(ctx->bc, &alu);
4498 if (r)
4499 return r;
4500 src_loaded = TRUE;
4501 src_gpr = ctx->temp_reg;
4502 }
4503
4504 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4505 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4506 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4507 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4508 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
4509 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4510
4511 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
4512 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
4513
4514 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
4515 for (i = 0; i < 4; i++) {
4516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4517 alu.op = ALU_OP2_CUBE;
4518 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4519 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4520 alu.dst.sel = ctx->temp_reg;
4521 alu.dst.chan = i;
4522 if (i == 3)
4523 alu.last = 1;
4524 alu.dst.write = 1;
4525 r = r600_bytecode_add_alu(ctx->bc, &alu);
4526 if (r)
4527 return r;
4528 }
4529
4530 /* tmp1.z = RCP_e(|tmp1.z|) */
4531 if (ctx->bc->chip_class == CAYMAN) {
4532 for (i = 0; i < 3; i++) {
4533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4534 alu.op = ALU_OP1_RECIP_IEEE;
4535 alu.src[0].sel = ctx->temp_reg;
4536 alu.src[0].chan = 2;
4537 alu.src[0].abs = 1;
4538 alu.dst.sel = ctx->temp_reg;
4539 alu.dst.chan = i;
4540 if (i == 2)
4541 alu.dst.write = 1;
4542 if (i == 2)
4543 alu.last = 1;
4544 r = r600_bytecode_add_alu(ctx->bc, &alu);
4545 if (r)
4546 return r;
4547 }
4548 } else {
4549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4550 alu.op = ALU_OP1_RECIP_IEEE;
4551 alu.src[0].sel = ctx->temp_reg;
4552 alu.src[0].chan = 2;
4553 alu.src[0].abs = 1;
4554 alu.dst.sel = ctx->temp_reg;
4555 alu.dst.chan = 2;
4556 alu.dst.write = 1;
4557 alu.last = 1;
4558 r = r600_bytecode_add_alu(ctx->bc, &alu);
4559 if (r)
4560 return r;
4561 }
4562
4563 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4564 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4565 * muladd has no writemask, have to use another temp
4566 */
4567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4568 alu.op = ALU_OP3_MULADD;
4569 alu.is_op3 = 1;
4570
4571 alu.src[0].sel = ctx->temp_reg;
4572 alu.src[0].chan = 0;
4573 alu.src[1].sel = ctx->temp_reg;
4574 alu.src[1].chan = 2;
4575
4576 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4577 alu.src[2].chan = 0;
4578 alu.src[2].value = *(uint32_t *)&one_point_five;
4579
4580 alu.dst.sel = ctx->temp_reg;
4581 alu.dst.chan = 0;
4582 alu.dst.write = 1;
4583
4584 r = r600_bytecode_add_alu(ctx->bc, &alu);
4585 if (r)
4586 return r;
4587
4588 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4589 alu.op = ALU_OP3_MULADD;
4590 alu.is_op3 = 1;
4591
4592 alu.src[0].sel = ctx->temp_reg;
4593 alu.src[0].chan = 1;
4594 alu.src[1].sel = ctx->temp_reg;
4595 alu.src[1].chan = 2;
4596
4597 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4598 alu.src[2].chan = 0;
4599 alu.src[2].value = *(uint32_t *)&one_point_five;
4600
4601 alu.dst.sel = ctx->temp_reg;
4602 alu.dst.chan = 1;
4603 alu.dst.write = 1;
4604
4605 alu.last = 1;
4606 r = r600_bytecode_add_alu(ctx->bc, &alu);
4607 if (r)
4608 return r;
4609 /* write initial compare value into Z component
4610 - W src 0 for shadow cube
4611 - X src 1 for shadow cube array */
4612 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4613 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4615 alu.op = ALU_OP1_MOV;
4616 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4617 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4618 else
4619 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4620 alu.dst.sel = ctx->temp_reg;
4621 alu.dst.chan = 2;
4622 alu.dst.write = 1;
4623 alu.last = 1;
4624 r = r600_bytecode_add_alu(ctx->bc, &alu);
4625 if (r)
4626 return r;
4627 }
4628
4629 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4630 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4631 if (ctx->bc->chip_class >= EVERGREEN) {
4632 int mytmp = r600_get_temp(ctx);
4633 static const float eight = 8.0f;
4634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4635 alu.op = ALU_OP1_MOV;
4636 alu.src[0].sel = ctx->temp_reg;
4637 alu.src[0].chan = 3;
4638 alu.dst.sel = mytmp;
4639 alu.dst.chan = 0;
4640 alu.dst.write = 1;
4641 alu.last = 1;
4642 r = r600_bytecode_add_alu(ctx->bc, &alu);
4643 if (r)
4644 return r;
4645
4646 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4648 alu.op = ALU_OP3_MULADD;
4649 alu.is_op3 = 1;
4650 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4651 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4652 alu.src[1].chan = 0;
4653 alu.src[1].value = *(uint32_t *)&eight;
4654 alu.src[2].sel = mytmp;
4655 alu.src[2].chan = 0;
4656 alu.dst.sel = ctx->temp_reg;
4657 alu.dst.chan = 3;
4658 alu.dst.write = 1;
4659 alu.last = 1;
4660 r = r600_bytecode_add_alu(ctx->bc, &alu);
4661 if (r)
4662 return r;
4663 } else if (ctx->bc->chip_class < EVERGREEN) {
4664 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4665 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4666 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4667 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4668 tex.src_gpr = r600_get_temp(ctx);
4669 tex.src_sel_x = 0;
4670 tex.src_sel_y = 0;
4671 tex.src_sel_z = 0;
4672 tex.src_sel_w = 0;
4673 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4674 tex.coord_type_x = 1;
4675 tex.coord_type_y = 1;
4676 tex.coord_type_z = 1;
4677 tex.coord_type_w = 1;
4678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4679 alu.op = ALU_OP1_MOV;
4680 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4681 alu.dst.sel = tex.src_gpr;
4682 alu.dst.chan = 0;
4683 alu.last = 1;
4684 alu.dst.write = 1;
4685 r = r600_bytecode_add_alu(ctx->bc, &alu);
4686 if (r)
4687 return r;
4688
4689 r = r600_bytecode_add_tex(ctx->bc, &tex);
4690 if (r)
4691 return r;
4692 }
4693
4694 }
4695
4696 /* for cube forms of lod and bias we need to route things */
4697 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4698 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4699 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4700 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4702 alu.op = ALU_OP1_MOV;
4703 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4704 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4705 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4706 else
4707 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4708 alu.dst.sel = ctx->temp_reg;
4709 alu.dst.chan = 2;
4710 alu.last = 1;
4711 alu.dst.write = 1;
4712 r = r600_bytecode_add_alu(ctx->bc, &alu);
4713 if (r)
4714 return r;
4715 }
4716
4717 src_loaded = TRUE;
4718 src_gpr = ctx->temp_reg;
4719 }
4720
4721 if (src_requires_loading && !src_loaded) {
4722 for (i = 0; i < 4; i++) {
4723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4724 alu.op = ALU_OP1_MOV;
4725 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4726 alu.dst.sel = ctx->temp_reg;
4727 alu.dst.chan = i;
4728 if (i == 3)
4729 alu.last = 1;
4730 alu.dst.write = 1;
4731 r = r600_bytecode_add_alu(ctx->bc, &alu);
4732 if (r)
4733 return r;
4734 }
4735 src_loaded = TRUE;
4736 src_gpr = ctx->temp_reg;
4737 }
4738
4739 /* Obtain the sample index for reading a compressed MSAA color texture.
4740 * To read the FMASK, we use the ldfptr instruction, which tells us
4741 * where the samples are stored.
4742 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4743 * which is the identity mapping. Each nibble says which physical sample
4744 * should be fetched to get that sample.
4745 *
4746 * Assume src.z contains the sample index. It should be modified like this:
4747 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4748 * Then fetch the texel with src.
4749 */
4750 if (read_compressed_msaa) {
4751 unsigned sample_chan = 3;
4752 unsigned temp = r600_get_temp(ctx);
4753 assert(src_loaded);
4754
4755 /* temp.w = ldfptr() */
4756 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4757 tex.op = FETCH_OP_LD;
4758 tex.inst_mod = 1; /* to indicate this is ldfptr */
4759 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4760 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4761 tex.src_gpr = src_gpr;
4762 tex.dst_gpr = temp;
4763 tex.dst_sel_x = 7; /* mask out these components */
4764 tex.dst_sel_y = 7;
4765 tex.dst_sel_z = 7;
4766 tex.dst_sel_w = 0; /* store X */
4767 tex.src_sel_x = 0;
4768 tex.src_sel_y = 1;
4769 tex.src_sel_z = 2;
4770 tex.src_sel_w = 3;
4771 tex.offset_x = offset_x;
4772 tex.offset_y = offset_y;
4773 tex.offset_z = offset_z;
4774 r = r600_bytecode_add_tex(ctx->bc, &tex);
4775 if (r)
4776 return r;
4777
4778 /* temp.x = sample_index*4 */
4779 if (ctx->bc->chip_class == CAYMAN) {
4780 for (i = 0 ; i < 4; i++) {
4781 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4782 alu.op = ALU_OP2_MULLO_INT;
4783 alu.src[0].sel = src_gpr;
4784 alu.src[0].chan = sample_chan;
4785 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4786 alu.src[1].value = 4;
4787 alu.dst.sel = temp;
4788 alu.dst.chan = i;
4789 alu.dst.write = i == 0;
4790 if (i == 3)
4791 alu.last = 1;
4792 r = r600_bytecode_add_alu(ctx->bc, &alu);
4793 if (r)
4794 return r;
4795 }
4796 } else {
4797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4798 alu.op = ALU_OP2_MULLO_INT;
4799 alu.src[0].sel = src_gpr;
4800 alu.src[0].chan = sample_chan;
4801 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4802 alu.src[1].value = 4;
4803 alu.dst.sel = temp;
4804 alu.dst.chan = 0;
4805 alu.dst.write = 1;
4806 alu.last = 1;
4807 r = r600_bytecode_add_alu(ctx->bc, &alu);
4808 if (r)
4809 return r;
4810 }
4811
4812 /* sample_index = temp.w >> temp.x */
4813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4814 alu.op = ALU_OP2_LSHR_INT;
4815 alu.src[0].sel = temp;
4816 alu.src[0].chan = 3;
4817 alu.src[1].sel = temp;
4818 alu.src[1].chan = 0;
4819 alu.dst.sel = src_gpr;
4820 alu.dst.chan = sample_chan;
4821 alu.dst.write = 1;
4822 alu.last = 1;
4823 r = r600_bytecode_add_alu(ctx->bc, &alu);
4824 if (r)
4825 return r;
4826
4827 /* sample_index & 0xF */
4828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4829 alu.op = ALU_OP2_AND_INT;
4830 alu.src[0].sel = src_gpr;
4831 alu.src[0].chan = sample_chan;
4832 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4833 alu.src[1].value = 0xF;
4834 alu.dst.sel = src_gpr;
4835 alu.dst.chan = sample_chan;
4836 alu.dst.write = 1;
4837 alu.last = 1;
4838 r = r600_bytecode_add_alu(ctx->bc, &alu);
4839 if (r)
4840 return r;
4841 #if 0
4842 /* visualize the FMASK */
4843 for (i = 0; i < 4; i++) {
4844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4845 alu.op = ALU_OP1_INT_TO_FLT;
4846 alu.src[0].sel = src_gpr;
4847 alu.src[0].chan = sample_chan;
4848 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4849 alu.dst.chan = i;
4850 alu.dst.write = 1;
4851 alu.last = 1;
4852 r = r600_bytecode_add_alu(ctx->bc, &alu);
4853 if (r)
4854 return r;
4855 }
4856 return 0;
4857 #endif
4858 }
4859
4860 /* does this shader want a num layers from TXQ for a cube array? */
4861 if (has_txq_cube_array_z) {
4862 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4863
4864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4865 alu.op = ALU_OP1_MOV;
4866
4867 alu.src[0].sel = 512 + (id / 4);
4868 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4869 alu.src[0].chan = id % 4;
4870 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4871 alu.last = 1;
4872 r = r600_bytecode_add_alu(ctx->bc, &alu);
4873 if (r)
4874 return r;
4875 /* disable writemask from texture instruction */
4876 inst->Dst[0].Register.WriteMask &= ~4;
4877 }
4878
4879 opcode = ctx->inst_info->op;
4880 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4881 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4882 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4883 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4884 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4885 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4886 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4887 switch (opcode) {
4888 case FETCH_OP_SAMPLE:
4889 opcode = FETCH_OP_SAMPLE_C;
4890 break;
4891 case FETCH_OP_SAMPLE_L:
4892 opcode = FETCH_OP_SAMPLE_C_L;
4893 break;
4894 case FETCH_OP_SAMPLE_LB:
4895 opcode = FETCH_OP_SAMPLE_C_LB;
4896 break;
4897 case FETCH_OP_SAMPLE_G:
4898 opcode = FETCH_OP_SAMPLE_C_G;
4899 break;
4900 }
4901 }
4902
4903 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4904 tex.op = opcode;
4905
4906 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4907 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4908 tex.src_gpr = src_gpr;
4909 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4910 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4911 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4912 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4913 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4914
4915 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4916 tex.src_sel_x = 4;
4917 tex.src_sel_y = 4;
4918 tex.src_sel_z = 4;
4919 tex.src_sel_w = 4;
4920 } else if (src_loaded) {
4921 tex.src_sel_x = 0;
4922 tex.src_sel_y = 1;
4923 tex.src_sel_z = 2;
4924 tex.src_sel_w = 3;
4925 } else {
4926 tex.src_sel_x = ctx->src[0].swizzle[0];
4927 tex.src_sel_y = ctx->src[0].swizzle[1];
4928 tex.src_sel_z = ctx->src[0].swizzle[2];
4929 tex.src_sel_w = ctx->src[0].swizzle[3];
4930 tex.src_rel = ctx->src[0].rel;
4931 }
4932
4933 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4934 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4935 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4936 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4937 tex.src_sel_x = 1;
4938 tex.src_sel_y = 0;
4939 tex.src_sel_z = 3;
4940 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4941 }
4942
4943 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4944 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4945 tex.coord_type_x = 1;
4946 tex.coord_type_y = 1;
4947 }
4948 tex.coord_type_z = 1;
4949 tex.coord_type_w = 1;
4950
4951 tex.offset_x = offset_x;
4952 tex.offset_y = offset_y;
4953 tex.offset_z = offset_z;
4954
4955 /* Put the depth for comparison in W.
4956 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4957 * Some instructions expect the depth in Z. */
4958 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4959 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4960 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4961 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4962 opcode != FETCH_OP_SAMPLE_C_L &&
4963 opcode != FETCH_OP_SAMPLE_C_LB) {
4964 tex.src_sel_w = tex.src_sel_z;
4965 }
4966
4967 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4968 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4969 if (opcode == FETCH_OP_SAMPLE_C_L ||
4970 opcode == FETCH_OP_SAMPLE_C_LB) {
4971 /* the array index is read from Y */
4972 tex.coord_type_y = 0;
4973 } else {
4974 /* the array index is read from Z */
4975 tex.coord_type_z = 0;
4976 tex.src_sel_z = tex.src_sel_y;
4977 }
4978 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4979 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4980 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4981 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4982 (ctx->bc->chip_class >= EVERGREEN)))
4983 /* the array index is read from Z */
4984 tex.coord_type_z = 0;
4985
4986 /* mask unused source components */
4987 if (opcode == FETCH_OP_SAMPLE) {
4988 switch (inst->Texture.Texture) {
4989 case TGSI_TEXTURE_2D:
4990 case TGSI_TEXTURE_RECT:
4991 tex.src_sel_z = 7;
4992 tex.src_sel_w = 7;
4993 break;
4994 case TGSI_TEXTURE_1D_ARRAY:
4995 tex.src_sel_y = 7;
4996 tex.src_sel_w = 7;
4997 break;
4998 case TGSI_TEXTURE_1D:
4999 tex.src_sel_y = 7;
5000 tex.src_sel_z = 7;
5001 tex.src_sel_w = 7;
5002 break;
5003 }
5004 }
5005
5006 r = r600_bytecode_add_tex(ctx->bc, &tex);
5007 if (r)
5008 return r;
5009
5010 /* add shadow ambient support - gallium doesn't do it yet */
5011 return 0;
5012 }
5013
5014 static int tgsi_lrp(struct r600_shader_ctx *ctx)
5015 {
5016 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5017 struct r600_bytecode_alu alu;
5018 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5019 unsigned i;
5020 int r;
5021
5022 /* optimize if it's just an equal balance */
5023 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
5024 for (i = 0; i < lasti + 1; i++) {
5025 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5026 continue;
5027
5028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5029 alu.op = ALU_OP2_ADD;
5030 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5031 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5032 alu.omod = 3;
5033 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5034 alu.dst.chan = i;
5035 if (i == lasti) {
5036 alu.last = 1;
5037 }
5038 r = r600_bytecode_add_alu(ctx->bc, &alu);
5039 if (r)
5040 return r;
5041 }
5042 return 0;
5043 }
5044
5045 /* 1 - src0 */
5046 for (i = 0; i < lasti + 1; i++) {
5047 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5048 continue;
5049
5050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5051 alu.op = ALU_OP2_ADD;
5052 alu.src[0].sel = V_SQ_ALU_SRC_1;
5053 alu.src[0].chan = 0;
5054 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5055 r600_bytecode_src_toggle_neg(&alu.src[1]);
5056 alu.dst.sel = ctx->temp_reg;
5057 alu.dst.chan = i;
5058 if (i == lasti) {
5059 alu.last = 1;
5060 }
5061 alu.dst.write = 1;
5062 r = r600_bytecode_add_alu(ctx->bc, &alu);
5063 if (r)
5064 return r;
5065 }
5066
5067 /* (1 - src0) * src2 */
5068 for (i = 0; i < lasti + 1; i++) {
5069 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5070 continue;
5071
5072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5073 alu.op = ALU_OP2_MUL;
5074 alu.src[0].sel = ctx->temp_reg;
5075 alu.src[0].chan = i;
5076 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5077 alu.dst.sel = ctx->temp_reg;
5078 alu.dst.chan = i;
5079 if (i == lasti) {
5080 alu.last = 1;
5081 }
5082 alu.dst.write = 1;
5083 r = r600_bytecode_add_alu(ctx->bc, &alu);
5084 if (r)
5085 return r;
5086 }
5087
5088 /* src0 * src1 + (1 - src0) * src2 */
5089 for (i = 0; i < lasti + 1; i++) {
5090 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5091 continue;
5092
5093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5094 alu.op = ALU_OP3_MULADD;
5095 alu.is_op3 = 1;
5096 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5097 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5098 alu.src[2].sel = ctx->temp_reg;
5099 alu.src[2].chan = i;
5100
5101 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5102 alu.dst.chan = i;
5103 if (i == lasti) {
5104 alu.last = 1;
5105 }
5106 r = r600_bytecode_add_alu(ctx->bc, &alu);
5107 if (r)
5108 return r;
5109 }
5110 return 0;
5111 }
5112
5113 static int tgsi_cmp(struct r600_shader_ctx *ctx)
5114 {
5115 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5116 struct r600_bytecode_alu alu;
5117 int i, r;
5118 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5119
5120 for (i = 0; i < lasti + 1; i++) {
5121 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5122 continue;
5123
5124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5125 alu.op = ALU_OP3_CNDGE;
5126 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5127 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5128 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
5129 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5130 alu.dst.chan = i;
5131 alu.dst.write = 1;
5132 alu.is_op3 = 1;
5133 if (i == lasti)
5134 alu.last = 1;
5135 r = r600_bytecode_add_alu(ctx->bc, &alu);
5136 if (r)
5137 return r;
5138 }
5139 return 0;
5140 }
5141
5142 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
5143 {
5144 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5145 struct r600_bytecode_alu alu;
5146 int i, r;
5147 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5148
5149 for (i = 0; i < lasti + 1; i++) {
5150 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5151 continue;
5152
5153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5154 alu.op = ALU_OP3_CNDGE_INT;
5155 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5156 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5157 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
5158 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5159 alu.dst.chan = i;
5160 alu.dst.write = 1;
5161 alu.is_op3 = 1;
5162 if (i == lasti)
5163 alu.last = 1;
5164 r = r600_bytecode_add_alu(ctx->bc, &alu);
5165 if (r)
5166 return r;
5167 }
5168 return 0;
5169 }
5170
5171 static int tgsi_xpd(struct r600_shader_ctx *ctx)
5172 {
5173 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5174 static const unsigned int src0_swizzle[] = {2, 0, 1};
5175 static const unsigned int src1_swizzle[] = {1, 2, 0};
5176 struct r600_bytecode_alu alu;
5177 uint32_t use_temp = 0;
5178 int i, r;
5179
5180 if (inst->Dst[0].Register.WriteMask != 0xf)
5181 use_temp = 1;
5182
5183 for (i = 0; i < 4; i++) {
5184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5185 alu.op = ALU_OP2_MUL;
5186 if (i < 3) {
5187 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5188 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
5189 } else {
5190 alu.src[0].sel = V_SQ_ALU_SRC_0;
5191 alu.src[0].chan = i;
5192 alu.src[1].sel = V_SQ_ALU_SRC_0;
5193 alu.src[1].chan = i;
5194 }
5195
5196 alu.dst.sel = ctx->temp_reg;
5197 alu.dst.chan = i;
5198 alu.dst.write = 1;
5199
5200 if (i == 3)
5201 alu.last = 1;
5202 r = r600_bytecode_add_alu(ctx->bc, &alu);
5203 if (r)
5204 return r;
5205 }
5206
5207 for (i = 0; i < 4; i++) {
5208 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5209 alu.op = ALU_OP3_MULADD;
5210
5211 if (i < 3) {
5212 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
5213 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
5214 } else {
5215 alu.src[0].sel = V_SQ_ALU_SRC_0;
5216 alu.src[0].chan = i;
5217 alu.src[1].sel = V_SQ_ALU_SRC_0;
5218 alu.src[1].chan = i;
5219 }
5220
5221 alu.src[2].sel = ctx->temp_reg;
5222 alu.src[2].neg = 1;
5223 alu.src[2].chan = i;
5224
5225 if (use_temp)
5226 alu.dst.sel = ctx->temp_reg;
5227 else
5228 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5229 alu.dst.chan = i;
5230 alu.dst.write = 1;
5231 alu.is_op3 = 1;
5232 if (i == 3)
5233 alu.last = 1;
5234 r = r600_bytecode_add_alu(ctx->bc, &alu);
5235 if (r)
5236 return r;
5237 }
5238 if (use_temp)
5239 return tgsi_helper_copy(ctx, inst);
5240 return 0;
5241 }
5242
5243 static int tgsi_exp(struct r600_shader_ctx *ctx)
5244 {
5245 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5246 struct r600_bytecode_alu alu;
5247 int r;
5248 int i;
5249
5250 /* result.x = 2^floor(src); */
5251 if (inst->Dst[0].Register.WriteMask & 1) {
5252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5253
5254 alu.op = ALU_OP1_FLOOR;
5255 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5256
5257 alu.dst.sel = ctx->temp_reg;
5258 alu.dst.chan = 0;
5259 alu.dst.write = 1;
5260 alu.last = 1;
5261 r = r600_bytecode_add_alu(ctx->bc, &alu);
5262 if (r)
5263 return r;
5264
5265 if (ctx->bc->chip_class == CAYMAN) {
5266 for (i = 0; i < 3; i++) {
5267 alu.op = ALU_OP1_EXP_IEEE;
5268 alu.src[0].sel = ctx->temp_reg;
5269 alu.src[0].chan = 0;
5270
5271 alu.dst.sel = ctx->temp_reg;
5272 alu.dst.chan = i;
5273 alu.dst.write = i == 0;
5274 alu.last = i == 2;
5275 r = r600_bytecode_add_alu(ctx->bc, &alu);
5276 if (r)
5277 return r;
5278 }
5279 } else {
5280 alu.op = ALU_OP1_EXP_IEEE;
5281 alu.src[0].sel = ctx->temp_reg;
5282 alu.src[0].chan = 0;
5283
5284 alu.dst.sel = ctx->temp_reg;
5285 alu.dst.chan = 0;
5286 alu.dst.write = 1;
5287 alu.last = 1;
5288 r = r600_bytecode_add_alu(ctx->bc, &alu);
5289 if (r)
5290 return r;
5291 }
5292 }
5293
5294 /* result.y = tmp - floor(tmp); */
5295 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5297
5298 alu.op = ALU_OP1_FRACT;
5299 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5300
5301 alu.dst.sel = ctx->temp_reg;
5302 #if 0
5303 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5304 if (r)
5305 return r;
5306 #endif
5307 alu.dst.write = 1;
5308 alu.dst.chan = 1;
5309
5310 alu.last = 1;
5311
5312 r = r600_bytecode_add_alu(ctx->bc, &alu);
5313 if (r)
5314 return r;
5315 }
5316
5317 /* result.z = RoughApprox2ToX(tmp);*/
5318 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
5319 if (ctx->bc->chip_class == CAYMAN) {
5320 for (i = 0; i < 3; i++) {
5321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5322 alu.op = ALU_OP1_EXP_IEEE;
5323 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5324
5325 alu.dst.sel = ctx->temp_reg;
5326 alu.dst.chan = i;
5327 if (i == 2) {
5328 alu.dst.write = 1;
5329 alu.last = 1;
5330 }
5331
5332 r = r600_bytecode_add_alu(ctx->bc, &alu);
5333 if (r)
5334 return r;
5335 }
5336 } else {
5337 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5338 alu.op = ALU_OP1_EXP_IEEE;
5339 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5340
5341 alu.dst.sel = ctx->temp_reg;
5342 alu.dst.write = 1;
5343 alu.dst.chan = 2;
5344
5345 alu.last = 1;
5346
5347 r = r600_bytecode_add_alu(ctx->bc, &alu);
5348 if (r)
5349 return r;
5350 }
5351 }
5352
5353 /* result.w = 1.0;*/
5354 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
5355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5356
5357 alu.op = ALU_OP1_MOV;
5358 alu.src[0].sel = V_SQ_ALU_SRC_1;
5359 alu.src[0].chan = 0;
5360
5361 alu.dst.sel = ctx->temp_reg;
5362 alu.dst.chan = 3;
5363 alu.dst.write = 1;
5364 alu.last = 1;
5365 r = r600_bytecode_add_alu(ctx->bc, &alu);
5366 if (r)
5367 return r;
5368 }
5369 return tgsi_helper_copy(ctx, inst);
5370 }
5371
5372 static int tgsi_log(struct r600_shader_ctx *ctx)
5373 {
5374 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5375 struct r600_bytecode_alu alu;
5376 int r;
5377 int i;
5378
5379 /* result.x = floor(log2(|src|)); */
5380 if (inst->Dst[0].Register.WriteMask & 1) {
5381 if (ctx->bc->chip_class == CAYMAN) {
5382 for (i = 0; i < 3; i++) {
5383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5384
5385 alu.op = ALU_OP1_LOG_IEEE;
5386 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5387 r600_bytecode_src_set_abs(&alu.src[0]);
5388
5389 alu.dst.sel = ctx->temp_reg;
5390 alu.dst.chan = i;
5391 if (i == 0)
5392 alu.dst.write = 1;
5393 if (i == 2)
5394 alu.last = 1;
5395 r = r600_bytecode_add_alu(ctx->bc, &alu);
5396 if (r)
5397 return r;
5398 }
5399
5400 } else {
5401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5402
5403 alu.op = ALU_OP1_LOG_IEEE;
5404 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5405 r600_bytecode_src_set_abs(&alu.src[0]);
5406
5407 alu.dst.sel = ctx->temp_reg;
5408 alu.dst.chan = 0;
5409 alu.dst.write = 1;
5410 alu.last = 1;
5411 r = r600_bytecode_add_alu(ctx->bc, &alu);
5412 if (r)
5413 return r;
5414 }
5415
5416 alu.op = ALU_OP1_FLOOR;
5417 alu.src[0].sel = ctx->temp_reg;
5418 alu.src[0].chan = 0;
5419
5420 alu.dst.sel = ctx->temp_reg;
5421 alu.dst.chan = 0;
5422 alu.dst.write = 1;
5423 alu.last = 1;
5424
5425 r = r600_bytecode_add_alu(ctx->bc, &alu);
5426 if (r)
5427 return r;
5428 }
5429
5430 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
5431 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5432
5433 if (ctx->bc->chip_class == CAYMAN) {
5434 for (i = 0; i < 3; i++) {
5435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5436
5437 alu.op = ALU_OP1_LOG_IEEE;
5438 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5439 r600_bytecode_src_set_abs(&alu.src[0]);
5440
5441 alu.dst.sel = ctx->temp_reg;
5442 alu.dst.chan = i;
5443 if (i == 1)
5444 alu.dst.write = 1;
5445 if (i == 2)
5446 alu.last = 1;
5447
5448 r = r600_bytecode_add_alu(ctx->bc, &alu);
5449 if (r)
5450 return r;
5451 }
5452 } else {
5453 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5454
5455 alu.op = ALU_OP1_LOG_IEEE;
5456 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5457 r600_bytecode_src_set_abs(&alu.src[0]);
5458
5459 alu.dst.sel = ctx->temp_reg;
5460 alu.dst.chan = 1;
5461 alu.dst.write = 1;
5462 alu.last = 1;
5463
5464 r = r600_bytecode_add_alu(ctx->bc, &alu);
5465 if (r)
5466 return r;
5467 }
5468
5469 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5470
5471 alu.op = ALU_OP1_FLOOR;
5472 alu.src[0].sel = ctx->temp_reg;
5473 alu.src[0].chan = 1;
5474
5475 alu.dst.sel = ctx->temp_reg;
5476 alu.dst.chan = 1;
5477 alu.dst.write = 1;
5478 alu.last = 1;
5479
5480 r = r600_bytecode_add_alu(ctx->bc, &alu);
5481 if (r)
5482 return r;
5483
5484 if (ctx->bc->chip_class == CAYMAN) {
5485 for (i = 0; i < 3; i++) {
5486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5487 alu.op = ALU_OP1_EXP_IEEE;
5488 alu.src[0].sel = ctx->temp_reg;
5489 alu.src[0].chan = 1;
5490
5491 alu.dst.sel = ctx->temp_reg;
5492 alu.dst.chan = i;
5493 if (i == 1)
5494 alu.dst.write = 1;
5495 if (i == 2)
5496 alu.last = 1;
5497
5498 r = r600_bytecode_add_alu(ctx->bc, &alu);
5499 if (r)
5500 return r;
5501 }
5502 } else {
5503 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5504 alu.op = ALU_OP1_EXP_IEEE;
5505 alu.src[0].sel = ctx->temp_reg;
5506 alu.src[0].chan = 1;
5507
5508 alu.dst.sel = ctx->temp_reg;
5509 alu.dst.chan = 1;
5510 alu.dst.write = 1;
5511 alu.last = 1;
5512
5513 r = r600_bytecode_add_alu(ctx->bc, &alu);
5514 if (r)
5515 return r;
5516 }
5517
5518 if (ctx->bc->chip_class == CAYMAN) {
5519 for (i = 0; i < 3; i++) {
5520 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5521 alu.op = ALU_OP1_RECIP_IEEE;
5522 alu.src[0].sel = ctx->temp_reg;
5523 alu.src[0].chan = 1;
5524
5525 alu.dst.sel = ctx->temp_reg;
5526 alu.dst.chan = i;
5527 if (i == 1)
5528 alu.dst.write = 1;
5529 if (i == 2)
5530 alu.last = 1;
5531
5532 r = r600_bytecode_add_alu(ctx->bc, &alu);
5533 if (r)
5534 return r;
5535 }
5536 } else {
5537 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5538 alu.op = ALU_OP1_RECIP_IEEE;
5539 alu.src[0].sel = ctx->temp_reg;
5540 alu.src[0].chan = 1;
5541
5542 alu.dst.sel = ctx->temp_reg;
5543 alu.dst.chan = 1;
5544 alu.dst.write = 1;
5545 alu.last = 1;
5546
5547 r = r600_bytecode_add_alu(ctx->bc, &alu);
5548 if (r)
5549 return r;
5550 }
5551
5552 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5553
5554 alu.op = ALU_OP2_MUL;
5555
5556 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5557 r600_bytecode_src_set_abs(&alu.src[0]);
5558
5559 alu.src[1].sel = ctx->temp_reg;
5560 alu.src[1].chan = 1;
5561
5562 alu.dst.sel = ctx->temp_reg;
5563 alu.dst.chan = 1;
5564 alu.dst.write = 1;
5565 alu.last = 1;
5566
5567 r = r600_bytecode_add_alu(ctx->bc, &alu);
5568 if (r)
5569 return r;
5570 }
5571
5572 /* result.z = log2(|src|);*/
5573 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5574 if (ctx->bc->chip_class == CAYMAN) {
5575 for (i = 0; i < 3; i++) {
5576 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5577
5578 alu.op = ALU_OP1_LOG_IEEE;
5579 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5580 r600_bytecode_src_set_abs(&alu.src[0]);
5581
5582 alu.dst.sel = ctx->temp_reg;
5583 if (i == 2)
5584 alu.dst.write = 1;
5585 alu.dst.chan = i;
5586 if (i == 2)
5587 alu.last = 1;
5588
5589 r = r600_bytecode_add_alu(ctx->bc, &alu);
5590 if (r)
5591 return r;
5592 }
5593 } else {
5594 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5595
5596 alu.op = ALU_OP1_LOG_IEEE;
5597 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5598 r600_bytecode_src_set_abs(&alu.src[0]);
5599
5600 alu.dst.sel = ctx->temp_reg;
5601 alu.dst.write = 1;
5602 alu.dst.chan = 2;
5603 alu.last = 1;
5604
5605 r = r600_bytecode_add_alu(ctx->bc, &alu);
5606 if (r)
5607 return r;
5608 }
5609 }
5610
5611 /* result.w = 1.0; */
5612 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5614
5615 alu.op = ALU_OP1_MOV;
5616 alu.src[0].sel = V_SQ_ALU_SRC_1;
5617 alu.src[0].chan = 0;
5618
5619 alu.dst.sel = ctx->temp_reg;
5620 alu.dst.chan = 3;
5621 alu.dst.write = 1;
5622 alu.last = 1;
5623
5624 r = r600_bytecode_add_alu(ctx->bc, &alu);
5625 if (r)
5626 return r;
5627 }
5628
5629 return tgsi_helper_copy(ctx, inst);
5630 }
5631
5632 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5633 {
5634 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5635 struct r600_bytecode_alu alu;
5636 int r;
5637
5638 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5639
5640 switch (inst->Instruction.Opcode) {
5641 case TGSI_OPCODE_ARL:
5642 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5643 break;
5644 case TGSI_OPCODE_ARR:
5645 alu.op = ALU_OP1_FLT_TO_INT;
5646 break;
5647 case TGSI_OPCODE_UARL:
5648 alu.op = ALU_OP1_MOV;
5649 break;
5650 default:
5651 assert(0);
5652 return -1;
5653 }
5654
5655 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5656 alu.last = 1;
5657 alu.dst.sel = ctx->bc->ar_reg;
5658 alu.dst.write = 1;
5659 r = r600_bytecode_add_alu(ctx->bc, &alu);
5660 if (r)
5661 return r;
5662
5663 ctx->bc->ar_loaded = 0;
5664 return 0;
5665 }
5666 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5667 {
5668 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5669 struct r600_bytecode_alu alu;
5670 int r;
5671
5672 switch (inst->Instruction.Opcode) {
5673 case TGSI_OPCODE_ARL:
5674 memset(&alu, 0, sizeof(alu));
5675 alu.op = ALU_OP1_FLOOR;
5676 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5677 alu.dst.sel = ctx->bc->ar_reg;
5678 alu.dst.write = 1;
5679 alu.last = 1;
5680
5681 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5682 return r;
5683
5684 memset(&alu, 0, sizeof(alu));
5685 alu.op = ALU_OP1_FLT_TO_INT;
5686 alu.src[0].sel = ctx->bc->ar_reg;
5687 alu.dst.sel = ctx->bc->ar_reg;
5688 alu.dst.write = 1;
5689 alu.last = 1;
5690
5691 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5692 return r;
5693 break;
5694 case TGSI_OPCODE_ARR:
5695 memset(&alu, 0, sizeof(alu));
5696 alu.op = ALU_OP1_FLT_TO_INT;
5697 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5698 alu.dst.sel = ctx->bc->ar_reg;
5699 alu.dst.write = 1;
5700 alu.last = 1;
5701
5702 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5703 return r;
5704 break;
5705 case TGSI_OPCODE_UARL:
5706 memset(&alu, 0, sizeof(alu));
5707 alu.op = ALU_OP1_MOV;
5708 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5709 alu.dst.sel = ctx->bc->ar_reg;
5710 alu.dst.write = 1;
5711 alu.last = 1;
5712
5713 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5714 return r;
5715 break;
5716 default:
5717 assert(0);
5718 return -1;
5719 }
5720
5721 ctx->bc->ar_loaded = 0;
5722 return 0;
5723 }
5724
5725 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5726 {
5727 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5728 struct r600_bytecode_alu alu;
5729 int i, r = 0;
5730
5731 for (i = 0; i < 4; i++) {
5732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5733
5734 alu.op = ALU_OP2_MUL;
5735 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5736
5737 if (i == 0 || i == 3) {
5738 alu.src[0].sel = V_SQ_ALU_SRC_1;
5739 } else {
5740 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5741 }
5742
5743 if (i == 0 || i == 2) {
5744 alu.src[1].sel = V_SQ_ALU_SRC_1;
5745 } else {
5746 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5747 }
5748 if (i == 3)
5749 alu.last = 1;
5750 r = r600_bytecode_add_alu(ctx->bc, &alu);
5751 if (r)
5752 return r;
5753 }
5754 return 0;
5755 }
5756
5757 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5758 {
5759 struct r600_bytecode_alu alu;
5760 int r;
5761
5762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5763 alu.op = opcode;
5764 alu.execute_mask = 1;
5765 alu.update_pred = 1;
5766
5767 alu.dst.sel = ctx->temp_reg;
5768 alu.dst.write = 1;
5769 alu.dst.chan = 0;
5770
5771 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5772 alu.src[1].sel = V_SQ_ALU_SRC_0;
5773 alu.src[1].chan = 0;
5774
5775 alu.last = 1;
5776
5777 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5778 if (r)
5779 return r;
5780 return 0;
5781 }
5782
5783 static int pops(struct r600_shader_ctx *ctx, int pops)
5784 {
5785 unsigned force_pop = ctx->bc->force_add_cf;
5786
5787 if (!force_pop) {
5788 int alu_pop = 3;
5789 if (ctx->bc->cf_last) {
5790 if (ctx->bc->cf_last->op == CF_OP_ALU)
5791 alu_pop = 0;
5792 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5793 alu_pop = 1;
5794 }
5795 alu_pop += pops;
5796 if (alu_pop == 1) {
5797 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5798 ctx->bc->force_add_cf = 1;
5799 } else if (alu_pop == 2) {
5800 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5801 ctx->bc->force_add_cf = 1;
5802 } else {
5803 force_pop = 1;
5804 }
5805 }
5806
5807 if (force_pop) {
5808 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5809 ctx->bc->cf_last->pop_count = pops;
5810 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5811 }
5812
5813 return 0;
5814 }
5815
5816 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5817 unsigned reason)
5818 {
5819 struct r600_stack_info *stack = &ctx->bc->stack;
5820 unsigned elements, entries;
5821
5822 unsigned entry_size = stack->entry_size;
5823
5824 elements = (stack->loop + stack->push_wqm ) * entry_size;
5825 elements += stack->push;
5826
5827 switch (ctx->bc->chip_class) {
5828 case R600:
5829 case R700:
5830 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5831 * the stack must be reserved to hold the current active/continue
5832 * masks */
5833 if (reason == FC_PUSH_VPM) {
5834 elements += 2;
5835 }
5836 break;
5837
5838 case CAYMAN:
5839 /* r9xx: any stack operation on empty stack consumes 2 additional
5840 * elements */
5841 elements += 2;
5842
5843 /* fallthrough */
5844 /* FIXME: do the two elements added above cover the cases for the
5845 * r8xx+ below? */
5846
5847 case EVERGREEN:
5848 /* r8xx+: 2 extra elements are not always required, but one extra
5849 * element must be added for each of the following cases:
5850 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5851 * stack usage.
5852 * (Currently we don't use ALU_ELSE_AFTER.)
5853 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5854 * PUSH instruction executed.
5855 *
5856 * NOTE: it seems we also need to reserve additional element in some
5857 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5858 * then STACK_SIZE should be 2 instead of 1 */
5859 if (reason == FC_PUSH_VPM) {
5860 elements += 1;
5861 }
5862 break;
5863
5864 default:
5865 assert(0);
5866 break;
5867 }
5868
5869 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5870 * for all chips, so we use 4 in the final formula, not the real entry_size
5871 * for the chip */
5872 entry_size = 4;
5873
5874 entries = (elements + (entry_size - 1)) / entry_size;
5875
5876 if (entries > stack->max_entries)
5877 stack->max_entries = entries;
5878 }
5879
5880 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5881 {
5882 switch(reason) {
5883 case FC_PUSH_VPM:
5884 --ctx->bc->stack.push;
5885 assert(ctx->bc->stack.push >= 0);
5886 break;
5887 case FC_PUSH_WQM:
5888 --ctx->bc->stack.push_wqm;
5889 assert(ctx->bc->stack.push_wqm >= 0);
5890 break;
5891 case FC_LOOP:
5892 --ctx->bc->stack.loop;
5893 assert(ctx->bc->stack.loop >= 0);
5894 break;
5895 default:
5896 assert(0);
5897 break;
5898 }
5899 }
5900
5901 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5902 {
5903 switch (reason) {
5904 case FC_PUSH_VPM:
5905 ++ctx->bc->stack.push;
5906 break;
5907 case FC_PUSH_WQM:
5908 ++ctx->bc->stack.push_wqm;
5909 case FC_LOOP:
5910 ++ctx->bc->stack.loop;
5911 break;
5912 default:
5913 assert(0);
5914 }
5915
5916 callstack_update_max_depth(ctx, reason);
5917 }
5918
5919 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5920 {
5921 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5922
5923 sp->mid = realloc((void *)sp->mid,
5924 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5925 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5926 sp->num_mid++;
5927 }
5928
5929 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5930 {
5931 ctx->bc->fc_sp++;
5932 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5933 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5934 }
5935
5936 static void fc_poplevel(struct r600_shader_ctx *ctx)
5937 {
5938 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5939 free(sp->mid);
5940 sp->mid = NULL;
5941 sp->num_mid = 0;
5942 sp->start = NULL;
5943 sp->type = 0;
5944 ctx->bc->fc_sp--;
5945 }
5946
5947 #if 0
5948 static int emit_return(struct r600_shader_ctx *ctx)
5949 {
5950 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5951 return 0;
5952 }
5953
5954 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5955 {
5956
5957 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5958 ctx->bc->cf_last->pop_count = pops;
5959 /* XXX work out offset */
5960 return 0;
5961 }
5962
5963 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5964 {
5965 return 0;
5966 }
5967
5968 static void emit_testflag(struct r600_shader_ctx *ctx)
5969 {
5970
5971 }
5972
5973 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5974 {
5975 emit_testflag(ctx);
5976 emit_jump_to_offset(ctx, 1, 4);
5977 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5978 pops(ctx, ifidx + 1);
5979 emit_return(ctx);
5980 }
5981
5982 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5983 {
5984 emit_testflag(ctx);
5985
5986 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5987 ctx->bc->cf_last->pop_count = 1;
5988
5989 fc_set_mid(ctx, fc_sp);
5990
5991 pops(ctx, 1);
5992 }
5993 #endif
5994
5995 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5996 {
5997 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5998
5999 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
6000 * LOOP_STARTxxx for nested loops may put the branch stack into a state
6001 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
6002 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
6003 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
6004 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
6005 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
6006 alu_type = CF_OP_ALU;
6007 }
6008
6009 emit_logic_pred(ctx, opcode, alu_type);
6010
6011 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
6012
6013 fc_pushlevel(ctx, FC_IF);
6014
6015 callstack_push(ctx, FC_PUSH_VPM);
6016 return 0;
6017 }
6018
6019 static int tgsi_if(struct r600_shader_ctx *ctx)
6020 {
6021 return emit_if(ctx, ALU_OP2_PRED_SETNE);
6022 }
6023
6024 static int tgsi_uif(struct r600_shader_ctx *ctx)
6025 {
6026 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
6027 }
6028
6029 static int tgsi_else(struct r600_shader_ctx *ctx)
6030 {
6031 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
6032 ctx->bc->cf_last->pop_count = 1;
6033
6034 fc_set_mid(ctx, ctx->bc->fc_sp);
6035 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
6036 return 0;
6037 }
6038
6039 static int tgsi_endif(struct r600_shader_ctx *ctx)
6040 {
6041 pops(ctx, 1);
6042 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
6043 R600_ERR("if/endif unbalanced in shader\n");
6044 return -1;
6045 }
6046
6047 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
6048 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
6049 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
6050 } else {
6051 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
6052 }
6053 fc_poplevel(ctx);
6054
6055 callstack_pop(ctx, FC_PUSH_VPM);
6056 return 0;
6057 }
6058
6059 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
6060 {
6061 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
6062 * limited to 4096 iterations, like the other LOOP_* instructions. */
6063 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
6064
6065 fc_pushlevel(ctx, FC_LOOP);
6066
6067 /* check stack depth */
6068 callstack_push(ctx, FC_LOOP);
6069 return 0;
6070 }
6071
6072 static int tgsi_endloop(struct r600_shader_ctx *ctx)
6073 {
6074 int i;
6075
6076 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
6077
6078 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
6079 R600_ERR("loop/endloop in shader code are not paired.\n");
6080 return -EINVAL;
6081 }
6082
6083 /* fixup loop pointers - from r600isa
6084 LOOP END points to CF after LOOP START,
6085 LOOP START point to CF after LOOP END
6086 BRK/CONT point to LOOP END CF
6087 */
6088 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
6089
6090 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
6091
6092 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
6093 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
6094 }
6095 /* XXX add LOOPRET support */
6096 fc_poplevel(ctx);
6097 callstack_pop(ctx, FC_LOOP);
6098 return 0;
6099 }
6100
6101 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
6102 {
6103 unsigned int fscp;
6104
6105 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
6106 {
6107 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
6108 break;
6109 }
6110
6111 if (fscp == 0) {
6112 R600_ERR("Break not inside loop/endloop pair\n");
6113 return -EINVAL;
6114 }
6115
6116 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6117
6118 fc_set_mid(ctx, fscp);
6119
6120 return 0;
6121 }
6122
6123 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
6124 {
6125 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
6126 emit_gs_ring_writes(ctx, TRUE);
6127
6128 return r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6129 }
6130
6131 static int tgsi_umad(struct r600_shader_ctx *ctx)
6132 {
6133 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6134 struct r600_bytecode_alu alu;
6135 int i, j, k, r;
6136 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6137
6138 /* src0 * src1 */
6139 for (i = 0; i < lasti + 1; i++) {
6140 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6141 continue;
6142
6143 if (ctx->bc->chip_class == CAYMAN) {
6144 for (j = 0 ; j < 4; j++) {
6145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6146
6147 alu.op = ALU_OP2_MULLO_UINT;
6148 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
6149 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
6150 }
6151 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
6152 alu.dst.sel = ctx->temp_reg;
6153 alu.dst.write = (j == i);
6154 if (j == 3)
6155 alu.last = 1;
6156 r = r600_bytecode_add_alu(ctx->bc, &alu);
6157 if (r)
6158 return r;
6159 }
6160 } else {
6161 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6162
6163 alu.dst.chan = i;
6164 alu.dst.sel = ctx->temp_reg;
6165 alu.dst.write = 1;
6166
6167 alu.op = ALU_OP2_MULLO_UINT;
6168 for (j = 0; j < 2; j++) {
6169 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6170 }
6171
6172 alu.last = 1;
6173 r = r600_bytecode_add_alu(ctx->bc, &alu);
6174 if (r)
6175 return r;
6176 }
6177 }
6178
6179
6180 for (i = 0; i < lasti + 1; i++) {
6181 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6182 continue;
6183
6184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6185 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6186
6187 alu.op = ALU_OP2_ADD_INT;
6188
6189 alu.src[0].sel = ctx->temp_reg;
6190 alu.src[0].chan = i;
6191
6192 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6193 if (i == lasti) {
6194 alu.last = 1;
6195 }
6196 r = r600_bytecode_add_alu(ctx->bc, &alu);
6197 if (r)
6198 return r;
6199 }
6200 return 0;
6201 }
6202
6203 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
6204 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
6205 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6206 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6207
6208 /* XXX:
6209 * For state trackers other than OpenGL, we'll want to use
6210 * _RECIP_IEEE instead.
6211 */
6212 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
6213
6214 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
6215 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6216 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6217 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6218 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6219 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6220 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6221 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6222 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6223 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6224 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6225 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6226 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6227 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6228 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6229 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6230 /* gap */
6231 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6232 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6233 /* gap */
6234 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6235 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6236 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6237 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6238 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6239 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6240 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6241 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6242 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6243 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6244 /* gap */
6245 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6246 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6247 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6248 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6249 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6250 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6251 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6252 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6253 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6254 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6255 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6256 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6257 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6258 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6259 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6260 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6261 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6262 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6263 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6264 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6265 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6266 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6267 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6268 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6269 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6270 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6271 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6272 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6273 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6274 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
6275 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6276 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6277 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6278 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6279 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6280 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6281 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6282 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6283 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6284 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6285 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6286 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6287 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6288 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6289 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6290 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6291 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6292 /* gap */
6293 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6294 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6295 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6296 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6297 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6298 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6299 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6300 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6301 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
6302 /* gap */
6303 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6304 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6305 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6306 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6307 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6308 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6309 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6310 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6311 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6312 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6313 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6314 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6315 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6316 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6317 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6318 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6319 /* gap */
6320 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6321 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6322 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6323 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6324 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6325 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6326 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6327 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6328 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6329 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6330 /* gap */
6331 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6332 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6333 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6334 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6335 /* gap */
6336 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6337 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
6338 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6339 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6340 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6341 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6342 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6343 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
6344 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6345 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
6346 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6347 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6348 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6349 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6350 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6351 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6352 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6353 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6354 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6355 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6356 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
6357 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6358 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
6359 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6360 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6361 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6362 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6363 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6364 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6365 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6366 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6367 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6368 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6369 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6370 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6371 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6372 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6373 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6374 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6375 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
6376 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6377 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6378 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6379 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6380 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6381 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6382 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6383 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6384 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6385 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6386 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6387 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6388 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6389 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6390 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6391 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6392 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6393 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6394 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6395 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6396 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6397 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6398 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6399 };
6400
6401 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
6402 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6403 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6404 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6405 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
6406 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
6407 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6408 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6409 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6410 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6411 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6412 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6413 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6414 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6415 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6416 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6417 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6418 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6419 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6420 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6421 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6422 /* gap */
6423 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6424 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6425 /* gap */
6426 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6427 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6428 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6429 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6430 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6431 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6432 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6433 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6434 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6435 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6436 /* gap */
6437 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6438 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6439 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6440 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6441 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6442 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6443 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6444 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6445 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6446 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6447 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6448 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6449 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6450 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6451 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6452 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6453 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6454 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6455 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6456 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6457 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6458 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6459 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6460 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6461 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6462 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6463 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6464 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6465 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6466 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6467 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6468 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6469 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6470 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6471 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6472 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6473 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6474 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6475 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6476 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6477 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6478 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6479 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6480 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6481 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6482 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6483 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6484 /* gap */
6485 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6486 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6487 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6488 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6489 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6490 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6491 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6492 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6493 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6494 /* gap */
6495 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6496 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6497 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6498 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6499 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6500 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6501 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6502 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6503 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6504 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6505 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6506 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6507 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6508 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6509 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6510 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6511 /* gap */
6512 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6513 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6514 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6515 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6516 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6517 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6518 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6519 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6520 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6521 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6522 /* gap */
6523 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6524 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6525 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6526 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6527 /* gap */
6528 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6529 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
6530 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6531 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6532 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6533 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6534 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6535 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6536 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6537 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
6538 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6539 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6540 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6541 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6542 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6543 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6544 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6545 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6546 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6547 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6548 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6549 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6550 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6551 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6552 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6553 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6554 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6555 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6556 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6557 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6558 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6559 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6560 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6561 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6562 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6563 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6564 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6565 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6566 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6567 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6568 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6569 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6570 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6571 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6572 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6573 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6574 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6575 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6576 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6577 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6578 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6579 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6580 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6581 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6582 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6583 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6584 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6585 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6586 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6587 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6588 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6589 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6590 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6591 };
6592
6593 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6594 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6595 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6596 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6597 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6598 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6599 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6600 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6601 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6602 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6603 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6604 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6605 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6606 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6607 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6608 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6609 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6610 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6611 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6612 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6613 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6614 /* gap */
6615 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6616 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6617 /* gap */
6618 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6619 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6620 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6621 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6622 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6623 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6624 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6625 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6626 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6627 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6628 /* gap */
6629 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6630 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6631 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6632 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6633 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6634 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6635 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6636 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6637 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6638 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6639 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6640 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6641 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6642 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6643 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6644 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6645 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6646 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6647 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6648 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6649 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6650 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6651 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6652 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6653 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6654 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6655 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6656 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6657 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6658 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6659 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6660 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6661 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6662 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6663 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6664 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6665 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6666 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6667 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6668 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6669 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6670 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6671 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6672 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6673 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6674 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6675 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6676 /* gap */
6677 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6678 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6679 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6680 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6681 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6682 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6683 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6684 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6685 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6686 /* gap */
6687 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6688 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6689 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6690 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6691 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6692 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6693 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6694 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6695 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6696 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6697 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6698 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6699 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6700 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6701 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6702 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6703 /* gap */
6704 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6705 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6706 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6707 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6708 /* gap */
6709 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6710 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6711 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6712 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6713 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6714 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6715 /* gap */
6716 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6717 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6718 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6719 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6720 /* gap */
6721 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6722 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6723 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6724 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6725 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6726 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6727 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6728 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6729 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6730 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6731 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6732 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6733 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6734 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6735 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6736 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6737 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6738 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6739 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6740 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6741 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6742 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6743 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6744 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6745 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6746 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6747 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6748 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6749 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6750 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6751 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6752 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6753 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6754 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6755 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6756 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6757 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6758 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6759 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6760 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6761 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6762 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6763 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6764 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6765 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6766 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6767 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6768 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6769 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6770 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6771 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6772 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6773 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6774 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6775 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6776 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6777 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6778 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6779 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6780 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6781 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6782 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6783 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6784 };