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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "pipe/p_shader_tokens.h"
31 #include "tgsi/tgsi_info.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "util/u_memory.h"
36 #include <stdio.h>
37 #include <errno.h>
38 #include <byteswap.h>
39
40 /* CAYMAN notes
41 Why CAYMAN got loops for lots of instructions is explained here.
42
43 -These 8xx t-slot only ops are implemented in all vector slots.
44 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
45 These 8xx t-slot only opcodes become vector ops, with all four
46 slots expecting the arguments on sources a and b. Result is
47 broadcast to all channels.
48 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
49 These 8xx t-slot only opcodes become vector ops in the z, y, and
50 x slots.
51 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
52 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
53 SQRT_IEEE/_64
54 SIN/COS
55 The w slot may have an independent co-issued operation, or if the
56 result is required to be in the w slot, the opcode above may be
57 issued in the w slot as well.
58 The compiler must issue the source argument to slots z, y, and x
59 */
60
61 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
62 struct r600_pipe_shader *pipeshader,
63 struct r600_shader_key key);
64
65 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
66 {
67 struct tgsi_parse_context parse;
68
69 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
70 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
71 return ~0;
72 }
73 return parse.FullHeader.Processor.Processor;
74 }
75
76 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
77 {
78 switch (processor_type) {
79 case TGSI_PROCESSOR_VERTEX:
80 return (rscreen->debug_flags & DBG_VS) != 0;
81 case TGSI_PROCESSOR_GEOMETRY:
82 return (rscreen->debug_flags & DBG_GS) != 0;
83 case TGSI_PROCESSOR_FRAGMENT:
84 return (rscreen->debug_flags & DBG_PS) != 0;
85 case TGSI_PROCESSOR_COMPUTE:
86 return (rscreen->debug_flags & DBG_CS) != 0;
87 default:
88 return false;
89 }
90 }
91
92 static void r600_dump_streamout(struct pipe_stream_output_info *so)
93 {
94 unsigned i;
95
96 fprintf(stderr, "STREAMOUT\n");
97 for (i = 0; i < so->num_outputs; i++) {
98 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
99 so->output[i].start_component;
100 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
101 i, so->output[i].output_buffer,
102 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
103 so->output[i].register_index,
104 mask & 1 ? "x" : "",
105 mask & 2 ? "y" : "",
106 mask & 4 ? "z" : "",
107 mask & 8 ? "w" : "",
108 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
109 }
110 }
111
112 int r600_pipe_shader_create(struct pipe_context *ctx,
113 struct r600_pipe_shader *shader,
114 struct r600_shader_key key)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117 struct r600_pipe_shader_selector *sel = shader->selector;
118 int r, i;
119 uint32_t *ptr;
120 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
121
122 shader->shader.bc.isa = rctx->isa;
123
124 if (dump) {
125 fprintf(stderr, "--------------------------------------------------------------\n");
126 tgsi_dump(sel->tokens, 0);
127
128 if (sel->so.num_outputs) {
129 r600_dump_streamout(&sel->so);
130 }
131 }
132 r = r600_shader_from_tgsi(rctx->screen, shader, key);
133 if (r) {
134 R600_ERR("translation from TGSI failed !\n");
135 return r;
136 }
137 r = r600_bytecode_build(&shader->shader.bc);
138 if (r) {
139 R600_ERR("building bytecode failed !\n");
140 return r;
141 }
142 if (dump) {
143 fprintf(stderr, "--------------------------------------------------------------\n");
144 r600_bytecode_disasm(&shader->shader.bc);
145 fprintf(stderr, "______________________________________________________________\n");
146 }
147
148
149 /* Store the shader in a buffer. */
150 if (shader->bo == NULL) {
151 shader->bo = (struct r600_resource*)
152 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
153 if (shader->bo == NULL) {
154 return -ENOMEM;
155 }
156 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
157 if (R600_BIG_ENDIAN) {
158 for (i = 0; i < shader->shader.bc.ndw; ++i) {
159 ptr[i] = bswap_32(shader->shader.bc.bytecode[i]);
160 }
161 } else {
162 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
163 }
164 rctx->ws->buffer_unmap(shader->bo->cs_buf);
165 }
166
167 /* Build state. */
168 switch (shader->shader.processor_type) {
169 case TGSI_PROCESSOR_VERTEX:
170 if (rctx->chip_class >= EVERGREEN) {
171 evergreen_update_vs_state(ctx, shader);
172 } else {
173 r600_update_vs_state(ctx, shader);
174 }
175 break;
176 case TGSI_PROCESSOR_FRAGMENT:
177 if (rctx->chip_class >= EVERGREEN) {
178 evergreen_update_ps_state(ctx, shader);
179 } else {
180 r600_update_ps_state(ctx, shader);
181 }
182 break;
183 default:
184 return -EINVAL;
185 }
186 return 0;
187 }
188
189 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
190 {
191 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
192 r600_bytecode_clear(&shader->shader.bc);
193 r600_release_command_buffer(&shader->command_buffer);
194 }
195
196 /*
197 * tgsi -> r600 shader
198 */
199 struct r600_shader_tgsi_instruction;
200
201 struct r600_shader_src {
202 unsigned sel;
203 unsigned swizzle[4];
204 unsigned neg;
205 unsigned abs;
206 unsigned rel;
207 unsigned kc_bank;
208 uint32_t value[4];
209 };
210
211 struct r600_shader_ctx {
212 struct tgsi_shader_info info;
213 struct tgsi_parse_context parse;
214 const struct tgsi_token *tokens;
215 unsigned type;
216 unsigned file_offset[TGSI_FILE_COUNT];
217 unsigned temp_reg;
218 struct r600_shader_tgsi_instruction *inst_info;
219 struct r600_bytecode *bc;
220 struct r600_shader *shader;
221 struct r600_shader_src src[4];
222 uint32_t *literals;
223 uint32_t nliterals;
224 uint32_t max_driver_temp_used;
225 boolean use_llvm;
226 /* needed for evergreen interpolation */
227 boolean input_centroid;
228 boolean input_linear;
229 boolean input_perspective;
230 int num_interp_gpr;
231 int face_gpr;
232 int colors_used;
233 boolean clip_vertex_write;
234 unsigned cv_output;
235 int fragcoord_input;
236 int native_integers;
237 };
238
239 struct r600_shader_tgsi_instruction {
240 unsigned tgsi_opcode;
241 unsigned is_op3;
242 unsigned op;
243 int (*process)(struct r600_shader_ctx *ctx);
244 };
245
246 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
247 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
248 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
249 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
250 static int tgsi_else(struct r600_shader_ctx *ctx);
251 static int tgsi_endif(struct r600_shader_ctx *ctx);
252 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
253 static int tgsi_endloop(struct r600_shader_ctx *ctx);
254 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
255
256 /*
257 * bytestream -> r600 shader
258 *
259 * These functions are used to transform the output of the LLVM backend into
260 * struct r600_bytecode.
261 */
262
263 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
264 unsigned char * bytes, unsigned num_bytes);
265
266 #ifdef HAVE_OPENCL
267 int r600_compute_shader_create(struct pipe_context * ctx,
268 LLVMModuleRef mod, struct r600_bytecode * bytecode)
269 {
270 struct r600_context *r600_ctx = (struct r600_context *)ctx;
271 unsigned char * bytes;
272 unsigned byte_count;
273 struct r600_shader_ctx shader_ctx;
274 bool dump = (r600_ctx->screen->debug_flags & DBG_CS) != 0;
275
276 r600_llvm_compile(mod, &bytes, &byte_count, r600_ctx->family , dump);
277 shader_ctx.bc = bytecode;
278 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family,
279 r600_ctx->screen->msaa_texture_support);
280 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
281 shader_ctx.bc->isa = r600_ctx->isa;
282 r600_bytecode_from_byte_stream(&shader_ctx, bytes, byte_count);
283 if (shader_ctx.bc->chip_class == CAYMAN) {
284 cm_bytecode_add_cf_end(shader_ctx.bc);
285 }
286 r600_bytecode_build(shader_ctx.bc);
287 if (dump) {
288 r600_bytecode_disasm(shader_ctx.bc);
289 }
290 free(bytes);
291 return 1;
292 }
293
294 #endif /* HAVE_OPENCL */
295
296 static uint32_t i32_from_byte_stream(unsigned char * bytes,
297 unsigned * bytes_read)
298 {
299 unsigned i;
300 uint32_t out = 0;
301 for (i = 0; i < 4; i++) {
302 out |= bytes[(*bytes_read)++] << (8 * i);
303 }
304 return out;
305 }
306
307 static unsigned r600_src_from_byte_stream(unsigned char * bytes,
308 unsigned bytes_read, struct r600_bytecode_alu * alu, unsigned src_idx)
309 {
310 unsigned i;
311 unsigned sel0, sel1;
312 sel0 = bytes[bytes_read++];
313 sel1 = bytes[bytes_read++];
314 alu->src[src_idx].sel = sel0 | (sel1 << 8);
315 alu->src[src_idx].chan = bytes[bytes_read++];
316 alu->src[src_idx].neg = bytes[bytes_read++];
317 alu->src[src_idx].abs = bytes[bytes_read++];
318 alu->src[src_idx].rel = bytes[bytes_read++];
319 alu->src[src_idx].kc_bank = bytes[bytes_read++];
320 for (i = 0; i < 4; i++) {
321 alu->src[src_idx].value |= bytes[bytes_read++] << (i * 8);
322 }
323 return bytes_read;
324 }
325
326 static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
327 unsigned char * bytes, unsigned bytes_read)
328 {
329 unsigned src_idx, src_num;
330 struct r600_bytecode_alu alu;
331 unsigned src_use_sel[3];
332 const struct alu_op_info *alu_op;
333 unsigned src_sel[3] = {};
334 uint32_t word0, word1;
335
336 src_num = bytes[bytes_read++];
337
338 memset(&alu, 0, sizeof(alu));
339 for(src_idx = 0; src_idx < src_num; src_idx++) {
340 unsigned i;
341 src_use_sel[src_idx] = bytes[bytes_read++];
342 for (i = 0; i < 4; i++) {
343 src_sel[src_idx] |= bytes[bytes_read++] << (i * 8);
344 }
345 for (i = 0; i < 4; i++) {
346 alu.src[src_idx].value |= bytes[bytes_read++] << (i * 8);
347 }
348 }
349
350 word0 = i32_from_byte_stream(bytes, &bytes_read);
351 word1 = i32_from_byte_stream(bytes, &bytes_read);
352
353 switch(ctx->bc->chip_class) {
354 default:
355 case R600:
356 r600_bytecode_alu_read(ctx->bc, &alu, word0, word1);
357 break;
358 case R700:
359 case EVERGREEN:
360 case CAYMAN:
361 r700_bytecode_alu_read(ctx->bc, &alu, word0, word1);
362 break;
363 }
364
365 for(src_idx = 0; src_idx < src_num; src_idx++) {
366 if (src_use_sel[src_idx]) {
367 unsigned sel = src_sel[src_idx];
368
369 alu.src[src_idx].chan = sel & 3;
370 sel >>= 2;
371
372 if (sel>=512) { /* constant */
373 sel -= 512;
374 alu.src[src_idx].kc_bank = sel >> 12;
375 alu.src[src_idx].sel = (sel & 4095) + 512;
376 }
377 else {
378 alu.src[src_idx].sel = sel;
379 }
380 }
381 }
382
383 alu_op = r600_isa_alu(alu.op);
384
385 #if HAVE_LLVM < 0x0302
386 if ((alu_op->flags & AF_PRED) && alu_op->src_count == 2) {
387 alu.update_pred = 1;
388 alu.dst.write = 0;
389 alu.src[1].sel = V_SQ_ALU_SRC_0;
390 alu.src[1].chan = 0;
391 alu.last = 1;
392 }
393 #endif
394
395 if (alu_op->flags & AF_MOVA) {
396 ctx->bc->ar_reg = alu.src[0].sel;
397 ctx->bc->ar_chan = alu.src[0].chan;
398 ctx->bc->ar_loaded = 0;
399 return bytes_read;
400 }
401
402 r600_bytecode_add_alu_type(ctx->bc, &alu, ctx->bc->cf_last->op);
403
404 /* XXX: Handle other KILL instructions */
405 if (alu_op->flags & AF_KILL) {
406 ctx->shader->uses_kill = 1;
407 /* XXX: This should be enforced in the LLVM backend. */
408 ctx->bc->force_add_cf = 1;
409 }
410 return bytes_read;
411 }
412
413 static void llvm_if(struct r600_shader_ctx *ctx)
414 {
415 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
416 fc_pushlevel(ctx, FC_IF);
417 callstack_push(ctx, FC_PUSH_VPM);
418 }
419
420 static void r600_break_from_byte_stream(struct r600_shader_ctx *ctx)
421 {
422 unsigned opcode = TGSI_OPCODE_BRK;
423 if (ctx->bc->chip_class == CAYMAN)
424 ctx->inst_info = &cm_shader_tgsi_instruction[opcode];
425 else if (ctx->bc->chip_class >= EVERGREEN)
426 ctx->inst_info = &eg_shader_tgsi_instruction[opcode];
427 else
428 ctx->inst_info = &r600_shader_tgsi_instruction[opcode];
429 llvm_if(ctx);
430 tgsi_loop_brk_cont(ctx);
431 tgsi_endif(ctx);
432 }
433
434 static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx *ctx,
435 unsigned char * bytes, unsigned bytes_read)
436 {
437 struct r600_bytecode_alu alu;
438 unsigned inst;
439 memset(&alu, 0, sizeof(alu));
440 bytes_read = r600_src_from_byte_stream(bytes, bytes_read, &alu, 0);
441 inst = bytes[bytes_read++];
442 switch (inst) {
443 case 0: /* IF_PREDICATED */
444 llvm_if(ctx);
445 break;
446 case 1: /* ELSE */
447 tgsi_else(ctx);
448 break;
449 case 2: /* ENDIF */
450 tgsi_endif(ctx);
451 break;
452 case 3: /* BGNLOOP */
453 tgsi_bgnloop(ctx);
454 break;
455 case 4: /* ENDLOOP */
456 tgsi_endloop(ctx);
457 break;
458 case 5: /* PREDICATED_BREAK */
459 r600_break_from_byte_stream(ctx);
460 break;
461 case 6: /* CONTINUE */
462 {
463 unsigned opcode = TGSI_OPCODE_CONT;
464 if (ctx->bc->chip_class == CAYMAN) {
465 ctx->inst_info =
466 &cm_shader_tgsi_instruction[opcode];
467 } else if (ctx->bc->chip_class >= EVERGREEN) {
468 ctx->inst_info =
469 &eg_shader_tgsi_instruction[opcode];
470 } else {
471 ctx->inst_info =
472 &r600_shader_tgsi_instruction[opcode];
473 }
474 tgsi_loop_brk_cont(ctx);
475 }
476 break;
477 }
478
479 return bytes_read;
480 }
481
482 static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx *ctx,
483 unsigned char * bytes, unsigned bytes_read)
484 {
485 struct r600_bytecode_tex tex;
486
487 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
488 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
489 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
490
491 tex.op = r600_isa_fetch_by_opcode(ctx->bc->isa, G_SQ_TEX_WORD0_TEX_INST(word0));
492 tex.resource_id = G_SQ_TEX_WORD0_RESOURCE_ID(word0);
493 tex.src_gpr = G_SQ_TEX_WORD0_SRC_GPR(word0);
494 tex.src_rel = G_SQ_TEX_WORD0_SRC_REL(word0);
495 tex.dst_gpr = G_SQ_TEX_WORD1_DST_GPR(word1);
496 tex.dst_rel = G_SQ_TEX_WORD1_DST_REL(word1);
497 tex.dst_sel_x = G_SQ_TEX_WORD1_DST_SEL_X(word1);
498 tex.dst_sel_y = G_SQ_TEX_WORD1_DST_SEL_Y(word1);
499 tex.dst_sel_z = G_SQ_TEX_WORD1_DST_SEL_Z(word1);
500 tex.dst_sel_w = G_SQ_TEX_WORD1_DST_SEL_W(word1);
501 tex.lod_bias = G_SQ_TEX_WORD1_LOD_BIAS(word1);
502 tex.coord_type_x = G_SQ_TEX_WORD1_COORD_TYPE_X(word1);
503 tex.coord_type_y = G_SQ_TEX_WORD1_COORD_TYPE_Y(word1);
504 tex.coord_type_z = G_SQ_TEX_WORD1_COORD_TYPE_Z(word1);
505 tex.coord_type_w = G_SQ_TEX_WORD1_COORD_TYPE_W(word1);
506 tex.offset_x = G_SQ_TEX_WORD2_OFFSET_X(word2);
507 tex.offset_y = G_SQ_TEX_WORD2_OFFSET_Y(word2);
508 tex.offset_z = G_SQ_TEX_WORD2_OFFSET_Z(word2);
509 tex.sampler_id = G_SQ_TEX_WORD2_SAMPLER_ID(word2);
510 tex.src_sel_x = G_SQ_TEX_WORD2_SRC_SEL_X(word2);
511 tex.src_sel_y = G_SQ_TEX_WORD2_SRC_SEL_Y(word2);
512 tex.src_sel_z = G_SQ_TEX_WORD2_SRC_SEL_Z(word2);
513 tex.src_sel_w = G_SQ_TEX_WORD2_SRC_SEL_W(word2);
514 tex.offset_x <<= 1;
515 tex.offset_y <<= 1;
516 tex.offset_z <<= 1;
517
518 tex.inst_mod = 0;
519
520 r600_bytecode_add_tex(ctx->bc, &tex);
521
522 return bytes_read;
523 }
524
525 static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
526 unsigned char * bytes, unsigned bytes_read)
527 {
528 struct r600_bytecode_vtx vtx;
529
530 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
531 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
532 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
533
534 memset(&vtx, 0, sizeof(vtx));
535
536 /* WORD0 */
537 vtx.op = r600_isa_fetch_by_opcode(ctx->bc->isa,
538 G_SQ_VTX_WORD0_VTX_INST(word0));
539 vtx.fetch_type = G_SQ_VTX_WORD0_FETCH_TYPE(word0);
540 vtx.buffer_id = G_SQ_VTX_WORD0_BUFFER_ID(word0);
541 vtx.src_gpr = G_SQ_VTX_WORD0_SRC_GPR(word0);
542 vtx.src_sel_x = G_SQ_VTX_WORD0_SRC_SEL_X(word0);
543 vtx.mega_fetch_count = G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(word0);
544
545 /* WORD1 */
546 vtx.dst_gpr = G_SQ_VTX_WORD1_GPR_DST_GPR(word1);
547 vtx.dst_sel_x = G_SQ_VTX_WORD1_DST_SEL_X(word1);
548 vtx.dst_sel_y = G_SQ_VTX_WORD1_DST_SEL_Y(word1);
549 vtx.dst_sel_z = G_SQ_VTX_WORD1_DST_SEL_Z(word1);
550 vtx.dst_sel_w = G_SQ_VTX_WORD1_DST_SEL_W(word1);
551 vtx.use_const_fields = G_SQ_VTX_WORD1_USE_CONST_FIELDS(word1);
552 vtx.data_format = G_SQ_VTX_WORD1_DATA_FORMAT(word1);
553 vtx.num_format_all = G_SQ_VTX_WORD1_NUM_FORMAT_ALL(word1);
554 vtx.format_comp_all = G_SQ_VTX_WORD1_FORMAT_COMP_ALL(word1);
555 vtx.srf_mode_all = G_SQ_VTX_WORD1_SRF_MODE_ALL(word1);
556
557 /* WORD 2*/
558 vtx.offset = G_SQ_VTX_WORD2_OFFSET(word2);
559 vtx.endian = G_SQ_VTX_WORD2_ENDIAN_SWAP(word2);
560
561 if (r600_bytecode_add_vtx(ctx->bc, &vtx)) {
562 fprintf(stderr, "Error adding vtx\n");
563 }
564
565 /* Use the Texture Cache for compute shaders*/
566 if (ctx->bc->chip_class >= EVERGREEN &&
567 ctx->bc->type == TGSI_PROCESSOR_COMPUTE) {
568 ctx->bc->cf_last->op = CF_OP_TEX;
569 }
570 return bytes_read;
571 }
572
573 static int r600_export_from_byte_stream(struct r600_shader_ctx *ctx,
574 unsigned char * bytes, unsigned bytes_read)
575 {
576 uint32_t word0 = 0, word1 = 0;
577 struct r600_bytecode_output output;
578 memset(&output, 0, sizeof(struct r600_bytecode_output));
579 word0 = i32_from_byte_stream(bytes, &bytes_read);
580 word1 = i32_from_byte_stream(bytes, &bytes_read);
581 if (ctx->bc->chip_class >= EVERGREEN)
582 eg_bytecode_export_read(ctx->bc, &output, word0,word1);
583 else
584 r600_bytecode_export_read(ctx->bc, &output, word0,word1);
585 r600_bytecode_add_output(ctx->bc, &output);
586 return bytes_read;
587 }
588
589 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
590 unsigned char * bytes, unsigned num_bytes)
591 {
592 unsigned bytes_read = 0;
593 ctx->bc->nstack = bytes[bytes_read++];
594 unsigned i, byte;
595 while (bytes_read < num_bytes) {
596 char inst_type = bytes[bytes_read++];
597 switch (inst_type) {
598 case 0:
599 bytes_read = r600_alu_from_byte_stream(ctx, bytes,
600 bytes_read);
601 break;
602 case 1:
603 bytes_read = r600_tex_from_byte_stream(ctx, bytes,
604 bytes_read);
605 break;
606 case 2:
607 bytes_read = r600_fc_from_byte_stream(ctx, bytes,
608 bytes_read);
609 break;
610 case 3:
611 r600_bytecode_add_cfinst(ctx->bc, CF_NATIVE);
612 for (i = 0; i < 2; i++) {
613 for (byte = 0 ; byte < 4; byte++) {
614 ctx->bc->cf_last->isa[i] |=
615 (bytes[bytes_read++] << (byte * 8));
616 }
617 }
618 break;
619
620 case 4:
621 bytes_read = r600_vtx_from_byte_stream(ctx, bytes,
622 bytes_read);
623 break;
624 case 5:
625 bytes_read = r600_export_from_byte_stream(ctx, bytes,
626 bytes_read);
627 break;
628 case 6: {
629 int32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
630 int32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
631
632 r600_bytecode_add_cf(ctx->bc);
633 ctx->bc->cf_last->op = r600_isa_cf_by_opcode(ctx->bc->isa, G_SQ_CF_ALU_WORD1_CF_INST(word1), 1);
634 ctx->bc->cf_last->kcache[0].bank = G_SQ_CF_ALU_WORD0_KCACHE_BANK0(word0);
635 ctx->bc->cf_last->kcache[0].addr = G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(word1);
636 ctx->bc->cf_last->kcache[0].mode = G_SQ_CF_ALU_WORD0_KCACHE_MODE0(word0);
637 ctx->bc->cf_last->kcache[1].bank = G_SQ_CF_ALU_WORD0_KCACHE_BANK1(word0);
638 ctx->bc->cf_last->kcache[1].addr = G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(word1);
639 ctx->bc->cf_last->kcache[1].mode = G_SQ_CF_ALU_WORD1_KCACHE_MODE1(word1);
640 break;
641 }
642 default:
643 /* XXX: Error here */
644 break;
645 }
646 }
647 }
648
649 /* End bytestream -> r600 shader functions*/
650
651 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
652 {
653 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
654 int j;
655
656 if (i->Instruction.NumDstRegs > 1) {
657 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
658 return -EINVAL;
659 }
660 if (i->Instruction.Predicate) {
661 R600_ERR("predicate unsupported\n");
662 return -EINVAL;
663 }
664 #if 0
665 if (i->Instruction.Label) {
666 R600_ERR("label unsupported\n");
667 return -EINVAL;
668 }
669 #endif
670 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
671 if (i->Src[j].Register.Dimension) {
672 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
673 R600_ERR("unsupported src %d (dimension %d)\n", j,
674 i->Src[j].Register.Dimension);
675 return -EINVAL;
676 }
677 }
678 }
679 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
680 if (i->Dst[j].Register.Dimension) {
681 R600_ERR("unsupported dst (dimension)\n");
682 return -EINVAL;
683 }
684 }
685 return 0;
686 }
687
688 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
689 int input)
690 {
691 int ij_index = 0;
692
693 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
694 if (ctx->shader->input[input].centroid)
695 ij_index++;
696 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
697 /* if we have perspective add one */
698 if (ctx->input_perspective) {
699 ij_index++;
700 /* if we have perspective centroid */
701 if (ctx->input_centroid)
702 ij_index++;
703 }
704 if (ctx->shader->input[input].centroid)
705 ij_index++;
706 }
707
708 ctx->shader->input[input].ij_index = ij_index;
709 }
710
711 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
712 {
713 int i, r;
714 struct r600_bytecode_alu alu;
715 int gpr = 0, base_chan = 0;
716 int ij_index = ctx->shader->input[input].ij_index;
717
718 /* work out gpr and base_chan from index */
719 gpr = ij_index / 2;
720 base_chan = (2 * (ij_index % 2)) + 1;
721
722 for (i = 0; i < 8; i++) {
723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
724
725 if (i < 4)
726 alu.op = ALU_OP2_INTERP_ZW;
727 else
728 alu.op = ALU_OP2_INTERP_XY;
729
730 if ((i > 1) && (i < 6)) {
731 alu.dst.sel = ctx->shader->input[input].gpr;
732 alu.dst.write = 1;
733 }
734
735 alu.dst.chan = i % 4;
736
737 alu.src[0].sel = gpr;
738 alu.src[0].chan = (base_chan - (i % 2));
739
740 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
741
742 alu.bank_swizzle_force = SQ_ALU_VEC_210;
743 if ((i % 4) == 3)
744 alu.last = 1;
745 r = r600_bytecode_add_alu(ctx->bc, &alu);
746 if (r)
747 return r;
748 }
749 return 0;
750 }
751
752 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
753 {
754 int i, r;
755 struct r600_bytecode_alu alu;
756
757 for (i = 0; i < 4; i++) {
758 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
759
760 alu.op = ALU_OP1_INTERP_LOAD_P0;
761
762 alu.dst.sel = ctx->shader->input[input].gpr;
763 alu.dst.write = 1;
764
765 alu.dst.chan = i;
766
767 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
768 alu.src[0].chan = i;
769
770 if (i == 3)
771 alu.last = 1;
772 r = r600_bytecode_add_alu(ctx->bc, &alu);
773 if (r)
774 return r;
775 }
776 return 0;
777 }
778
779 /*
780 * Special export handling in shaders
781 *
782 * shader export ARRAY_BASE for EXPORT_POS:
783 * 60 is position
784 * 61 is misc vector
785 * 62, 63 are clip distance vectors
786 *
787 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
788 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
789 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
790 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
791 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
792 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
793 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
794 * exclusive from render target index)
795 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
796 *
797 *
798 * shader export ARRAY_BASE for EXPORT_PIXEL:
799 * 0-7 CB targets
800 * 61 computed Z vector
801 *
802 * The use of the values exported in the computed Z vector are controlled
803 * by DB_SHADER_CONTROL:
804 * Z_EXPORT_ENABLE - Z as a float in RED
805 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
806 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
807 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
808 * DB_SOURCE_FORMAT - export control restrictions
809 *
810 */
811
812
813 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
814 static int r600_spi_sid(struct r600_shader_io * io)
815 {
816 int index, name = io->name;
817
818 /* These params are handled differently, they don't need
819 * semantic indices, so we'll use 0 for them.
820 */
821 if (name == TGSI_SEMANTIC_POSITION ||
822 name == TGSI_SEMANTIC_PSIZE ||
823 name == TGSI_SEMANTIC_FACE)
824 index = 0;
825 else {
826 if (name == TGSI_SEMANTIC_GENERIC) {
827 /* For generic params simply use sid from tgsi */
828 index = io->sid;
829 } else {
830 /* For non-generic params - pack name and sid into 8 bits */
831 index = 0x80 | (name<<3) | (io->sid);
832 }
833
834 /* Make sure that all really used indices have nonzero value, so
835 * we can just compare it to 0 later instead of comparing the name
836 * with different values to detect special cases. */
837 index++;
838 }
839
840 return index;
841 };
842
843 /* turn input into interpolate on EG */
844 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
845 {
846 int r = 0;
847
848 if (ctx->shader->input[index].spi_sid) {
849 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
850 if (ctx->shader->input[index].interpolate > 0) {
851 evergreen_interp_assign_ij_index(ctx, index);
852 if (!ctx->use_llvm)
853 r = evergreen_interp_alu(ctx, index);
854 } else {
855 if (!ctx->use_llvm)
856 r = evergreen_interp_flat(ctx, index);
857 }
858 }
859 return r;
860 }
861
862 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
863 {
864 struct r600_bytecode_alu alu;
865 int i, r;
866 int gpr_front = ctx->shader->input[front].gpr;
867 int gpr_back = ctx->shader->input[back].gpr;
868
869 for (i = 0; i < 4; i++) {
870 memset(&alu, 0, sizeof(alu));
871 alu.op = ALU_OP3_CNDGT;
872 alu.is_op3 = 1;
873 alu.dst.write = 1;
874 alu.dst.sel = gpr_front;
875 alu.src[0].sel = ctx->face_gpr;
876 alu.src[1].sel = gpr_front;
877 alu.src[2].sel = gpr_back;
878
879 alu.dst.chan = i;
880 alu.src[1].chan = i;
881 alu.src[2].chan = i;
882 alu.last = (i==3);
883
884 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
885 return r;
886 }
887
888 return 0;
889 }
890
891 static int tgsi_declaration(struct r600_shader_ctx *ctx)
892 {
893 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
894 int r, i, j, count = d->Range.Last - d->Range.First + 1;
895
896 switch (d->Declaration.File) {
897 case TGSI_FILE_INPUT:
898 i = ctx->shader->ninput;
899 ctx->shader->ninput += count;
900 ctx->shader->input[i].name = d->Semantic.Name;
901 ctx->shader->input[i].sid = d->Semantic.Index;
902 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
903 ctx->shader->input[i].centroid = d->Interp.Centroid;
904 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
905 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
906 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
907 switch (ctx->shader->input[i].name) {
908 case TGSI_SEMANTIC_FACE:
909 ctx->face_gpr = ctx->shader->input[i].gpr;
910 break;
911 case TGSI_SEMANTIC_COLOR:
912 ctx->colors_used++;
913 break;
914 case TGSI_SEMANTIC_POSITION:
915 ctx->fragcoord_input = i;
916 break;
917 }
918 if (ctx->bc->chip_class >= EVERGREEN) {
919 if ((r = evergreen_interp_input(ctx, i)))
920 return r;
921 }
922 }
923 for (j = 1; j < count; ++j) {
924 ctx->shader->input[i + j] = ctx->shader->input[i];
925 ctx->shader->input[i + j].gpr += j;
926 }
927 break;
928 case TGSI_FILE_OUTPUT:
929 i = ctx->shader->noutput++;
930 ctx->shader->output[i].name = d->Semantic.Name;
931 ctx->shader->output[i].sid = d->Semantic.Index;
932 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
933 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
934 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
935 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
936 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
937 switch (d->Semantic.Name) {
938 case TGSI_SEMANTIC_CLIPDIST:
939 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
940 break;
941 case TGSI_SEMANTIC_PSIZE:
942 ctx->shader->vs_out_misc_write = 1;
943 ctx->shader->vs_out_point_size = 1;
944 break;
945 case TGSI_SEMANTIC_CLIPVERTEX:
946 ctx->clip_vertex_write = TRUE;
947 ctx->cv_output = i;
948 break;
949 }
950 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
951 switch (d->Semantic.Name) {
952 case TGSI_SEMANTIC_COLOR:
953 ctx->shader->nr_ps_max_color_exports++;
954 break;
955 }
956 }
957 break;
958 case TGSI_FILE_CONSTANT:
959 case TGSI_FILE_TEMPORARY:
960 case TGSI_FILE_SAMPLER:
961 case TGSI_FILE_ADDRESS:
962 break;
963
964 case TGSI_FILE_SYSTEM_VALUE:
965 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
966 if (!ctx->native_integers) {
967 struct r600_bytecode_alu alu;
968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
969
970 alu.op = ALU_OP1_INT_TO_FLT;
971 alu.src[0].sel = 0;
972 alu.src[0].chan = 3;
973
974 alu.dst.sel = 0;
975 alu.dst.chan = 3;
976 alu.dst.write = 1;
977 alu.last = 1;
978
979 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
980 return r;
981 }
982 break;
983 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
984 break;
985 default:
986 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
987 return -EINVAL;
988 }
989 return 0;
990 }
991
992 static int r600_get_temp(struct r600_shader_ctx *ctx)
993 {
994 return ctx->temp_reg + ctx->max_driver_temp_used++;
995 }
996
997 /*
998 * for evergreen we need to scan the shader to find the number of GPRs we need to
999 * reserve for interpolation.
1000 *
1001 * we need to know if we are going to emit
1002 * any centroid inputs
1003 * if perspective and linear are required
1004 */
1005 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1006 {
1007 int i;
1008 int num_baryc;
1009
1010 ctx->input_linear = FALSE;
1011 ctx->input_perspective = FALSE;
1012 ctx->input_centroid = FALSE;
1013 ctx->num_interp_gpr = 1;
1014
1015 /* any centroid inputs */
1016 for (i = 0; i < ctx->info.num_inputs; i++) {
1017 /* skip position/face */
1018 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1019 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
1020 continue;
1021 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
1022 ctx->input_linear = TRUE;
1023 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
1024 ctx->input_perspective = TRUE;
1025 if (ctx->info.input_centroid[i])
1026 ctx->input_centroid = TRUE;
1027 }
1028
1029 num_baryc = 0;
1030 /* ignoring sample for now */
1031 if (ctx->input_perspective)
1032 num_baryc++;
1033 if (ctx->input_linear)
1034 num_baryc++;
1035 if (ctx->input_centroid)
1036 num_baryc *= 2;
1037
1038 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
1039
1040 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
1041 return ctx->num_interp_gpr;
1042 }
1043
1044 static void tgsi_src(struct r600_shader_ctx *ctx,
1045 const struct tgsi_full_src_register *tgsi_src,
1046 struct r600_shader_src *r600_src)
1047 {
1048 memset(r600_src, 0, sizeof(*r600_src));
1049 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1050 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1051 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1052 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1053 r600_src->neg = tgsi_src->Register.Negate;
1054 r600_src->abs = tgsi_src->Register.Absolute;
1055
1056 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1057 int index;
1058 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1059 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1060 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1061
1062 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1063 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
1064 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1065 return;
1066 }
1067 index = tgsi_src->Register.Index;
1068 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1069 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1070 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1071 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1072 r600_src->swizzle[0] = 3;
1073 r600_src->swizzle[1] = 3;
1074 r600_src->swizzle[2] = 3;
1075 r600_src->swizzle[3] = 3;
1076 r600_src->sel = 0;
1077 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1078 r600_src->swizzle[0] = 0;
1079 r600_src->swizzle[1] = 0;
1080 r600_src->swizzle[2] = 0;
1081 r600_src->swizzle[3] = 0;
1082 r600_src->sel = 0;
1083 }
1084 } else {
1085 if (tgsi_src->Register.Indirect)
1086 r600_src->rel = V_SQ_REL_RELATIVE;
1087 r600_src->sel = tgsi_src->Register.Index;
1088 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1089 }
1090 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1091 if (tgsi_src->Register.Dimension) {
1092 r600_src->kc_bank = tgsi_src->Dimension.Index;
1093 }
1094 }
1095 }
1096
1097 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
1098 {
1099 struct r600_bytecode_vtx vtx;
1100 unsigned int ar_reg;
1101 int r;
1102
1103 if (offset) {
1104 struct r600_bytecode_alu alu;
1105
1106 memset(&alu, 0, sizeof(alu));
1107
1108 alu.op = ALU_OP2_ADD_INT;
1109 alu.src[0].sel = ctx->bc->ar_reg;
1110
1111 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1112 alu.src[1].value = offset;
1113
1114 alu.dst.sel = dst_reg;
1115 alu.dst.write = 1;
1116 alu.last = 1;
1117
1118 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1119 return r;
1120
1121 ar_reg = dst_reg;
1122 } else {
1123 ar_reg = ctx->bc->ar_reg;
1124 }
1125
1126 memset(&vtx, 0, sizeof(vtx));
1127 vtx.buffer_id = cb_idx;
1128 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
1129 vtx.src_gpr = ar_reg;
1130 vtx.mega_fetch_count = 16;
1131 vtx.dst_gpr = dst_reg;
1132 vtx.dst_sel_x = 0; /* SEL_X */
1133 vtx.dst_sel_y = 1; /* SEL_Y */
1134 vtx.dst_sel_z = 2; /* SEL_Z */
1135 vtx.dst_sel_w = 3; /* SEL_W */
1136 vtx.data_format = FMT_32_32_32_32_FLOAT;
1137 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1138 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1139 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1140 vtx.endian = r600_endian_swap(32);
1141
1142 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1143 return r;
1144
1145 return 0;
1146 }
1147
1148 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1149 {
1150 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1151 struct r600_bytecode_alu alu;
1152 int i, j, k, nconst, r;
1153
1154 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1155 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1156 nconst++;
1157 }
1158 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1159 }
1160 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1161 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1162 continue;
1163 }
1164
1165 if (ctx->src[i].rel) {
1166 int treg = r600_get_temp(ctx);
1167 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
1168 return r;
1169
1170 ctx->src[i].kc_bank = 0;
1171 ctx->src[i].sel = treg;
1172 ctx->src[i].rel = 0;
1173 j--;
1174 } else if (j > 0) {
1175 int treg = r600_get_temp(ctx);
1176 for (k = 0; k < 4; k++) {
1177 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1178 alu.op = ALU_OP1_MOV;
1179 alu.src[0].sel = ctx->src[i].sel;
1180 alu.src[0].chan = k;
1181 alu.src[0].rel = ctx->src[i].rel;
1182 alu.dst.sel = treg;
1183 alu.dst.chan = k;
1184 alu.dst.write = 1;
1185 if (k == 3)
1186 alu.last = 1;
1187 r = r600_bytecode_add_alu(ctx->bc, &alu);
1188 if (r)
1189 return r;
1190 }
1191 ctx->src[i].sel = treg;
1192 ctx->src[i].rel =0;
1193 j--;
1194 }
1195 }
1196 return 0;
1197 }
1198
1199 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1200 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1201 {
1202 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1203 struct r600_bytecode_alu alu;
1204 int i, j, k, nliteral, r;
1205
1206 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1207 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1208 nliteral++;
1209 }
1210 }
1211 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1212 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1213 int treg = r600_get_temp(ctx);
1214 for (k = 0; k < 4; k++) {
1215 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1216 alu.op = ALU_OP1_MOV;
1217 alu.src[0].sel = ctx->src[i].sel;
1218 alu.src[0].chan = k;
1219 alu.src[0].value = ctx->src[i].value[k];
1220 alu.dst.sel = treg;
1221 alu.dst.chan = k;
1222 alu.dst.write = 1;
1223 if (k == 3)
1224 alu.last = 1;
1225 r = r600_bytecode_add_alu(ctx->bc, &alu);
1226 if (r)
1227 return r;
1228 }
1229 ctx->src[i].sel = treg;
1230 j--;
1231 }
1232 }
1233 return 0;
1234 }
1235
1236 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1237 {
1238 int i, r, count = ctx->shader->ninput;
1239
1240 for (i = 0; i < count; i++) {
1241 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1242 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1243 if (r)
1244 return r;
1245 }
1246 }
1247 return 0;
1248 }
1249
1250 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
1251 struct r600_pipe_shader *pipeshader,
1252 struct r600_shader_key key)
1253 {
1254 struct r600_shader *shader = &pipeshader->shader;
1255 struct tgsi_token *tokens = pipeshader->selector->tokens;
1256 struct pipe_stream_output_info so = pipeshader->selector->so;
1257 struct tgsi_full_immediate *immediate;
1258 struct tgsi_full_property *property;
1259 struct r600_shader_ctx ctx;
1260 struct r600_bytecode_output output[32];
1261 unsigned output_done, noutput;
1262 unsigned opcode;
1263 int i, j, k, r = 0;
1264 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
1265 /* Declarations used by llvm code */
1266 bool use_llvm = false;
1267 unsigned char * inst_bytes = NULL;
1268 unsigned inst_byte_count = 0;
1269
1270 #ifdef R600_USE_LLVM
1271 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
1272 #endif
1273 ctx.bc = &shader->bc;
1274 ctx.shader = shader;
1275 ctx.native_integers = true;
1276
1277 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
1278 rscreen->msaa_texture_support);
1279 ctx.tokens = tokens;
1280 tgsi_scan_shader(tokens, &ctx.info);
1281 tgsi_parse_init(&ctx.parse, tokens);
1282 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1283 shader->processor_type = ctx.type;
1284 ctx.bc->type = shader->processor_type;
1285
1286 ctx.face_gpr = -1;
1287 ctx.fragcoord_input = -1;
1288 ctx.colors_used = 0;
1289 ctx.clip_vertex_write = 0;
1290
1291 shader->nr_ps_color_exports = 0;
1292 shader->nr_ps_max_color_exports = 0;
1293
1294 shader->two_side = key.color_two_side;
1295
1296 /* register allocations */
1297 /* Values [0,127] correspond to GPR[0..127].
1298 * Values [128,159] correspond to constant buffer bank 0
1299 * Values [160,191] correspond to constant buffer bank 1
1300 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1301 * Values [256,287] correspond to constant buffer bank 2 (EG)
1302 * Values [288,319] correspond to constant buffer bank 3 (EG)
1303 * Other special values are shown in the list below.
1304 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1305 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1306 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1307 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1308 * 248 SQ_ALU_SRC_0: special constant 0.0.
1309 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1310 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1311 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1312 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1313 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1314 * 254 SQ_ALU_SRC_PV: previous vector result.
1315 * 255 SQ_ALU_SRC_PS: previous scalar result.
1316 */
1317 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1318 ctx.file_offset[i] = 0;
1319 }
1320 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1321 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1322 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1323 }
1324 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1325 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1326 }
1327
1328 #ifdef R600_USE_LLVM
1329 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1330 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1331 "indirect adressing. Falling back to TGSI "
1332 "backend.\n");
1333 use_llvm = 0;
1334 }
1335 #endif
1336 ctx.use_llvm = use_llvm;
1337
1338 if (use_llvm) {
1339 ctx.file_offset[TGSI_FILE_OUTPUT] =
1340 ctx.file_offset[TGSI_FILE_INPUT];
1341 } else {
1342 ctx.file_offset[TGSI_FILE_OUTPUT] =
1343 ctx.file_offset[TGSI_FILE_INPUT] +
1344 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1345 }
1346 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1347 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1348
1349 /* Outside the GPR range. This will be translated to one of the
1350 * kcache banks later. */
1351 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1352
1353 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1354 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1355 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1356 ctx.temp_reg = ctx.bc->ar_reg + 1;
1357
1358 ctx.nliterals = 0;
1359 ctx.literals = NULL;
1360 shader->fs_write_all = FALSE;
1361 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1362 tgsi_parse_token(&ctx.parse);
1363 switch (ctx.parse.FullToken.Token.Type) {
1364 case TGSI_TOKEN_TYPE_IMMEDIATE:
1365 immediate = &ctx.parse.FullToken.FullImmediate;
1366 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1367 if(ctx.literals == NULL) {
1368 r = -ENOMEM;
1369 goto out_err;
1370 }
1371 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1372 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1373 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1374 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1375 ctx.nliterals++;
1376 break;
1377 case TGSI_TOKEN_TYPE_DECLARATION:
1378 r = tgsi_declaration(&ctx);
1379 if (r)
1380 goto out_err;
1381 break;
1382 case TGSI_TOKEN_TYPE_INSTRUCTION:
1383 break;
1384 case TGSI_TOKEN_TYPE_PROPERTY:
1385 property = &ctx.parse.FullToken.FullProperty;
1386 switch (property->Property.PropertyName) {
1387 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1388 if (property->u[0].Data == 1)
1389 shader->fs_write_all = TRUE;
1390 break;
1391 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1392 /* we don't need this one */
1393 break;
1394 }
1395 break;
1396 default:
1397 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1398 r = -EINVAL;
1399 goto out_err;
1400 }
1401 }
1402
1403 /* Process two side if needed */
1404 if (shader->two_side && ctx.colors_used) {
1405 int i, count = ctx.shader->ninput;
1406 unsigned next_lds_loc = ctx.shader->nlds;
1407
1408 /* additional inputs will be allocated right after the existing inputs,
1409 * we won't need them after the color selection, so we don't need to
1410 * reserve these gprs for the rest of the shader code and to adjust
1411 * output offsets etc. */
1412 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1413 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1414
1415 if (ctx.face_gpr == -1) {
1416 i = ctx.shader->ninput++;
1417 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1418 ctx.shader->input[i].spi_sid = 0;
1419 ctx.shader->input[i].gpr = gpr++;
1420 ctx.face_gpr = ctx.shader->input[i].gpr;
1421 }
1422
1423 for (i = 0; i < count; i++) {
1424 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1425 int ni = ctx.shader->ninput++;
1426 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1427 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1428 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1429 ctx.shader->input[ni].gpr = gpr++;
1430 // TGSI to LLVM needs to know the lds position of inputs.
1431 // Non LLVM path computes it later (in process_twoside_color)
1432 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1433 ctx.shader->input[i].back_color_input = ni;
1434 if (ctx.bc->chip_class >= EVERGREEN) {
1435 if ((r = evergreen_interp_input(&ctx, ni)))
1436 return r;
1437 }
1438 }
1439 }
1440 }
1441
1442 /* LLVM backend setup */
1443 #ifdef R600_USE_LLVM
1444 if (use_llvm) {
1445 struct radeon_llvm_context radeon_llvm_ctx;
1446 LLVMModuleRef mod;
1447 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1448
1449 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1450 radeon_llvm_ctx.type = ctx.type;
1451 radeon_llvm_ctx.two_side = shader->two_side;
1452 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1453 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1454 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1455 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1456 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1457 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1458 radeon_llvm_ctx.stream_outputs = &so;
1459 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1460 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1461 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1462
1463 if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
1464 rscreen->family, dump)) {
1465 FREE(inst_bytes);
1466 radeon_llvm_dispose(&radeon_llvm_ctx);
1467 use_llvm = 0;
1468 fprintf(stderr, "R600 LLVM backend failed to compile "
1469 "shader. Falling back to TGSI\n");
1470 } else {
1471 ctx.file_offset[TGSI_FILE_OUTPUT] =
1472 ctx.file_offset[TGSI_FILE_INPUT];
1473 }
1474 radeon_llvm_dispose(&radeon_llvm_ctx);
1475 }
1476 #endif
1477 /* End of LLVM backend setup */
1478
1479 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1480 shader->nr_ps_max_color_exports = 8;
1481
1482 if (!use_llvm) {
1483 if (ctx.fragcoord_input >= 0) {
1484 if (ctx.bc->chip_class == CAYMAN) {
1485 for (j = 0 ; j < 4; j++) {
1486 struct r600_bytecode_alu alu;
1487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1488 alu.op = ALU_OP1_RECIP_IEEE;
1489 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1490 alu.src[0].chan = 3;
1491
1492 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1493 alu.dst.chan = j;
1494 alu.dst.write = (j == 3);
1495 alu.last = 1;
1496 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1497 return r;
1498 }
1499 } else {
1500 struct r600_bytecode_alu alu;
1501 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1502 alu.op = ALU_OP1_RECIP_IEEE;
1503 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1504 alu.src[0].chan = 3;
1505
1506 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1507 alu.dst.chan = 3;
1508 alu.dst.write = 1;
1509 alu.last = 1;
1510 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1511 return r;
1512 }
1513 }
1514
1515 if (shader->two_side && ctx.colors_used) {
1516 if ((r = process_twoside_color_inputs(&ctx)))
1517 return r;
1518 }
1519
1520 tgsi_parse_init(&ctx.parse, tokens);
1521 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1522 tgsi_parse_token(&ctx.parse);
1523 switch (ctx.parse.FullToken.Token.Type) {
1524 case TGSI_TOKEN_TYPE_INSTRUCTION:
1525 r = tgsi_is_supported(&ctx);
1526 if (r)
1527 goto out_err;
1528 ctx.max_driver_temp_used = 0;
1529 /* reserve first tmp for everyone */
1530 r600_get_temp(&ctx);
1531
1532 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1533 if ((r = tgsi_split_constant(&ctx)))
1534 goto out_err;
1535 if ((r = tgsi_split_literal_constant(&ctx)))
1536 goto out_err;
1537 if (ctx.bc->chip_class == CAYMAN)
1538 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1539 else if (ctx.bc->chip_class >= EVERGREEN)
1540 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1541 else
1542 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1543 r = ctx.inst_info->process(&ctx);
1544 if (r)
1545 goto out_err;
1546 break;
1547 default:
1548 break;
1549 }
1550 }
1551 }
1552
1553 /* Reset the temporary register counter. */
1554 ctx.max_driver_temp_used = 0;
1555
1556 /* Get instructions if we are using the LLVM backend. */
1557 if (use_llvm) {
1558 r600_bytecode_from_byte_stream(&ctx, inst_bytes, inst_byte_count);
1559 FREE(inst_bytes);
1560 }
1561
1562 noutput = shader->noutput;
1563
1564 if (ctx.clip_vertex_write) {
1565 unsigned clipdist_temp[2];
1566
1567 clipdist_temp[0] = r600_get_temp(&ctx);
1568 clipdist_temp[1] = r600_get_temp(&ctx);
1569
1570 /* need to convert a clipvertex write into clipdistance writes and not export
1571 the clip vertex anymore */
1572
1573 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1574 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1575 shader->output[noutput].gpr = clipdist_temp[0];
1576 noutput++;
1577 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1578 shader->output[noutput].gpr = clipdist_temp[1];
1579 noutput++;
1580
1581 /* reset spi_sid for clipvertex output to avoid confusing spi */
1582 shader->output[ctx.cv_output].spi_sid = 0;
1583
1584 shader->clip_dist_write = 0xFF;
1585
1586 for (i = 0; i < 8; i++) {
1587 int oreg = i >> 2;
1588 int ochan = i & 3;
1589
1590 for (j = 0; j < 4; j++) {
1591 struct r600_bytecode_alu alu;
1592 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1593 alu.op = ALU_OP2_DOT4;
1594 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1595 alu.src[0].chan = j;
1596
1597 alu.src[1].sel = 512 + i;
1598 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1599 alu.src[1].chan = j;
1600
1601 alu.dst.sel = clipdist_temp[oreg];
1602 alu.dst.chan = j;
1603 alu.dst.write = (j == ochan);
1604 if (j == 3)
1605 alu.last = 1;
1606 if (!use_llvm)
1607 r = r600_bytecode_add_alu(ctx.bc, &alu);
1608 if (r)
1609 return r;
1610 }
1611 }
1612 }
1613
1614 /* Add stream outputs. */
1615 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1616 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1617
1618 /* Sanity checking. */
1619 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1620 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1621 r = -EINVAL;
1622 goto out_err;
1623 }
1624 for (i = 0; i < so.num_outputs; i++) {
1625 if (so.output[i].output_buffer >= 4) {
1626 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1627 so.output[i].output_buffer);
1628 r = -EINVAL;
1629 goto out_err;
1630 }
1631 }
1632
1633 /* Initialize locations where the outputs are stored. */
1634 for (i = 0; i < so.num_outputs; i++) {
1635 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1636
1637 /* Lower outputs with dst_offset < start_component.
1638 *
1639 * We can only output 4D vectors with a write mask, e.g. we can
1640 * only output the W component at offset 3, etc. If we want
1641 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1642 * to move it to X and output X. */
1643 if (so.output[i].dst_offset < so.output[i].start_component) {
1644 unsigned tmp = r600_get_temp(&ctx);
1645
1646 for (j = 0; j < so.output[i].num_components; j++) {
1647 struct r600_bytecode_alu alu;
1648 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1649 alu.op = ALU_OP1_MOV;
1650 alu.src[0].sel = so_gpr[i];
1651 alu.src[0].chan = so.output[i].start_component + j;
1652
1653 alu.dst.sel = tmp;
1654 alu.dst.chan = j;
1655 alu.dst.write = 1;
1656 if (j == so.output[i].num_components - 1)
1657 alu.last = 1;
1658 r = r600_bytecode_add_alu(ctx.bc, &alu);
1659 if (r)
1660 return r;
1661 }
1662 so.output[i].start_component = 0;
1663 so_gpr[i] = tmp;
1664 }
1665 }
1666
1667 /* Write outputs to buffers. */
1668 for (i = 0; i < so.num_outputs; i++) {
1669 struct r600_bytecode_output output;
1670
1671 memset(&output, 0, sizeof(struct r600_bytecode_output));
1672 output.gpr = so_gpr[i];
1673 output.elem_size = so.output[i].num_components;
1674 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1675 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1676 output.burst_count = 1;
1677 output.barrier = 1;
1678 /* array_size is an upper limit for the burst_count
1679 * with MEM_STREAM instructions */
1680 output.array_size = 0xFFF;
1681 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1682 if (ctx.bc->chip_class >= EVERGREEN) {
1683 switch (so.output[i].output_buffer) {
1684 case 0:
1685 output.op = CF_OP_MEM_STREAM0_BUF0;
1686 break;
1687 case 1:
1688 output.op = CF_OP_MEM_STREAM0_BUF1;
1689 break;
1690 case 2:
1691 output.op = CF_OP_MEM_STREAM0_BUF2;
1692 break;
1693 case 3:
1694 output.op = CF_OP_MEM_STREAM0_BUF3;
1695 break;
1696 }
1697 } else {
1698 switch (so.output[i].output_buffer) {
1699 case 0:
1700 output.op = CF_OP_MEM_STREAM0;
1701 break;
1702 case 1:
1703 output.op = CF_OP_MEM_STREAM1;
1704 break;
1705 case 2:
1706 output.op = CF_OP_MEM_STREAM2;
1707 break;
1708 case 3:
1709 output.op = CF_OP_MEM_STREAM3;
1710 break;
1711 }
1712 }
1713 r = r600_bytecode_add_output(ctx.bc, &output);
1714 if (r)
1715 goto out_err;
1716 }
1717 }
1718
1719 /* export output */
1720 for (i = 0, j = 0; i < noutput; i++, j++) {
1721 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1722 output[j].gpr = shader->output[i].gpr;
1723 output[j].elem_size = 3;
1724 output[j].swizzle_x = 0;
1725 output[j].swizzle_y = 1;
1726 output[j].swizzle_z = 2;
1727 output[j].swizzle_w = 3;
1728 output[j].burst_count = 1;
1729 output[j].barrier = 1;
1730 output[j].type = -1;
1731 output[j].op = CF_OP_EXPORT;
1732 switch (ctx.type) {
1733 case TGSI_PROCESSOR_VERTEX:
1734 switch (shader->output[i].name) {
1735 case TGSI_SEMANTIC_POSITION:
1736 output[j].array_base = next_pos_base++;
1737 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1738 break;
1739
1740 case TGSI_SEMANTIC_PSIZE:
1741 output[j].array_base = next_pos_base++;
1742 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1743 break;
1744 case TGSI_SEMANTIC_CLIPVERTEX:
1745 j--;
1746 break;
1747 case TGSI_SEMANTIC_CLIPDIST:
1748 output[j].array_base = next_pos_base++;
1749 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1750 /* spi_sid is 0 for clipdistance outputs that were generated
1751 * for clipvertex - we don't need to pass them to PS */
1752 if (shader->output[i].spi_sid) {
1753 j++;
1754 /* duplicate it as PARAM to pass to the pixel shader */
1755 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1756 output[j].array_base = next_param_base++;
1757 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1758 }
1759 break;
1760 case TGSI_SEMANTIC_FOG:
1761 output[j].swizzle_y = 4; /* 0 */
1762 output[j].swizzle_z = 4; /* 0 */
1763 output[j].swizzle_w = 5; /* 1 */
1764 break;
1765 }
1766 break;
1767 case TGSI_PROCESSOR_FRAGMENT:
1768 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1769 /* never export more colors than the number of CBs */
1770 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1771 /* skip export */
1772 j--;
1773 continue;
1774 }
1775 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1776 output[j].array_base = next_pixel_base++;
1777 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1778 shader->nr_ps_color_exports++;
1779 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1780 for (k = 1; k < key.nr_cbufs; k++) {
1781 j++;
1782 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1783 output[j].gpr = shader->output[i].gpr;
1784 output[j].elem_size = 3;
1785 output[j].swizzle_x = 0;
1786 output[j].swizzle_y = 1;
1787 output[j].swizzle_z = 2;
1788 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1789 output[j].burst_count = 1;
1790 output[j].barrier = 1;
1791 output[j].array_base = next_pixel_base++;
1792 output[j].op = CF_OP_EXPORT;
1793 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1794 shader->nr_ps_color_exports++;
1795 }
1796 }
1797 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1798 output[j].array_base = 61;
1799 output[j].swizzle_x = 2;
1800 output[j].swizzle_y = 7;
1801 output[j].swizzle_z = output[j].swizzle_w = 7;
1802 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1803 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1804 output[j].array_base = 61;
1805 output[j].swizzle_x = 7;
1806 output[j].swizzle_y = 1;
1807 output[j].swizzle_z = output[j].swizzle_w = 7;
1808 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1809 } else {
1810 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1811 r = -EINVAL;
1812 goto out_err;
1813 }
1814 break;
1815 default:
1816 R600_ERR("unsupported processor type %d\n", ctx.type);
1817 r = -EINVAL;
1818 goto out_err;
1819 }
1820
1821 if (output[j].type==-1) {
1822 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1823 output[j].array_base = next_param_base++;
1824 }
1825 }
1826
1827 /* add fake position export */
1828 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1829 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1830 output[j].gpr = 0;
1831 output[j].elem_size = 3;
1832 output[j].swizzle_x = 7;
1833 output[j].swizzle_y = 7;
1834 output[j].swizzle_z = 7;
1835 output[j].swizzle_w = 7;
1836 output[j].burst_count = 1;
1837 output[j].barrier = 1;
1838 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1839 output[j].array_base = next_pos_base;
1840 output[j].op = CF_OP_EXPORT;
1841 j++;
1842 }
1843
1844 /* add fake param output for vertex shader if no param is exported */
1845 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1846 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1847 output[j].gpr = 0;
1848 output[j].elem_size = 3;
1849 output[j].swizzle_x = 7;
1850 output[j].swizzle_y = 7;
1851 output[j].swizzle_z = 7;
1852 output[j].swizzle_w = 7;
1853 output[j].burst_count = 1;
1854 output[j].barrier = 1;
1855 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1856 output[j].array_base = 0;
1857 output[j].op = CF_OP_EXPORT;
1858 j++;
1859 }
1860
1861 /* add fake pixel export */
1862 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1863 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1864 output[j].gpr = 0;
1865 output[j].elem_size = 3;
1866 output[j].swizzle_x = 7;
1867 output[j].swizzle_y = 7;
1868 output[j].swizzle_z = 7;
1869 output[j].swizzle_w = 7;
1870 output[j].burst_count = 1;
1871 output[j].barrier = 1;
1872 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1873 output[j].array_base = 0;
1874 output[j].op = CF_OP_EXPORT;
1875 j++;
1876 }
1877
1878 noutput = j;
1879
1880 /* set export done on last export of each type */
1881 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1882 if (ctx.bc->chip_class < CAYMAN) {
1883 if (i == (noutput - 1)) {
1884 output[i].end_of_program = 1;
1885 }
1886 }
1887 if (!(output_done & (1 << output[i].type))) {
1888 output_done |= (1 << output[i].type);
1889 output[i].op = CF_OP_EXPORT_DONE;
1890 }
1891 }
1892 /* add output to bytecode */
1893 if (!use_llvm) {
1894 for (i = 0; i < noutput; i++) {
1895 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1896 if (r)
1897 goto out_err;
1898 }
1899 }
1900 /* add program end */
1901 if (ctx.bc->chip_class == CAYMAN)
1902 cm_bytecode_add_cf_end(ctx.bc);
1903
1904 /* check GPR limit - we have 124 = 128 - 4
1905 * (4 are reserved as alu clause temporary registers) */
1906 if (ctx.bc->ngpr > 124) {
1907 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1908 r = -ENOMEM;
1909 goto out_err;
1910 }
1911
1912 free(ctx.literals);
1913 tgsi_parse_free(&ctx.parse);
1914 return 0;
1915 out_err:
1916 free(ctx.literals);
1917 tgsi_parse_free(&ctx.parse);
1918 return r;
1919 }
1920
1921 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1922 {
1923 R600_ERR("%s tgsi opcode unsupported\n",
1924 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1925 return -EINVAL;
1926 }
1927
1928 static int tgsi_end(struct r600_shader_ctx *ctx)
1929 {
1930 return 0;
1931 }
1932
1933 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1934 const struct r600_shader_src *shader_src,
1935 unsigned chan)
1936 {
1937 bc_src->sel = shader_src->sel;
1938 bc_src->chan = shader_src->swizzle[chan];
1939 bc_src->neg = shader_src->neg;
1940 bc_src->abs = shader_src->abs;
1941 bc_src->rel = shader_src->rel;
1942 bc_src->value = shader_src->value[bc_src->chan];
1943 bc_src->kc_bank = shader_src->kc_bank;
1944 }
1945
1946 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1947 {
1948 bc_src->abs = 1;
1949 bc_src->neg = 0;
1950 }
1951
1952 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1953 {
1954 bc_src->neg = !bc_src->neg;
1955 }
1956
1957 static void tgsi_dst(struct r600_shader_ctx *ctx,
1958 const struct tgsi_full_dst_register *tgsi_dst,
1959 unsigned swizzle,
1960 struct r600_bytecode_alu_dst *r600_dst)
1961 {
1962 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1963
1964 r600_dst->sel = tgsi_dst->Register.Index;
1965 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1966 r600_dst->chan = swizzle;
1967 r600_dst->write = 1;
1968 if (tgsi_dst->Register.Indirect)
1969 r600_dst->rel = V_SQ_REL_RELATIVE;
1970 if (inst->Instruction.Saturate) {
1971 r600_dst->clamp = 1;
1972 }
1973 }
1974
1975 static int tgsi_last_instruction(unsigned writemask)
1976 {
1977 int i, lasti = 0;
1978
1979 for (i = 0; i < 4; i++) {
1980 if (writemask & (1 << i)) {
1981 lasti = i;
1982 }
1983 }
1984 return lasti;
1985 }
1986
1987 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1988 {
1989 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1990 struct r600_bytecode_alu alu;
1991 int i, j, r;
1992 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1993
1994 for (i = 0; i < lasti + 1; i++) {
1995 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1996 continue;
1997
1998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1999 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2000
2001 alu.op = ctx->inst_info->op;
2002 if (!swap) {
2003 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2004 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2005 }
2006 } else {
2007 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2008 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2009 }
2010 /* handle some special cases */
2011 switch (ctx->inst_info->tgsi_opcode) {
2012 case TGSI_OPCODE_SUB:
2013 r600_bytecode_src_toggle_neg(&alu.src[1]);
2014 break;
2015 case TGSI_OPCODE_ABS:
2016 r600_bytecode_src_set_abs(&alu.src[0]);
2017 break;
2018 default:
2019 break;
2020 }
2021 if (i == lasti || trans_only) {
2022 alu.last = 1;
2023 }
2024 r = r600_bytecode_add_alu(ctx->bc, &alu);
2025 if (r)
2026 return r;
2027 }
2028 return 0;
2029 }
2030
2031 static int tgsi_op2(struct r600_shader_ctx *ctx)
2032 {
2033 return tgsi_op2_s(ctx, 0, 0);
2034 }
2035
2036 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2037 {
2038 return tgsi_op2_s(ctx, 1, 0);
2039 }
2040
2041 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2042 {
2043 return tgsi_op2_s(ctx, 0, 1);
2044 }
2045
2046 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2047 {
2048 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2049 struct r600_bytecode_alu alu;
2050 int i, r;
2051 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2052
2053 for (i = 0; i < lasti + 1; i++) {
2054
2055 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2056 continue;
2057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2058 alu.op = ctx->inst_info->op;
2059
2060 alu.src[0].sel = V_SQ_ALU_SRC_0;
2061
2062 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2063
2064 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2065
2066 if (i == lasti) {
2067 alu.last = 1;
2068 }
2069 r = r600_bytecode_add_alu(ctx->bc, &alu);
2070 if (r)
2071 return r;
2072 }
2073 return 0;
2074
2075 }
2076
2077 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2078 {
2079 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2080 int i, j, r;
2081 struct r600_bytecode_alu alu;
2082 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2083
2084 for (i = 0 ; i < last_slot; i++) {
2085 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2086 alu.op = ctx->inst_info->op;
2087 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2088 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2089
2090 /* RSQ should take the absolute value of src */
2091 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
2092 r600_bytecode_src_set_abs(&alu.src[j]);
2093 }
2094 }
2095 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2096 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2097
2098 if (i == last_slot - 1)
2099 alu.last = 1;
2100 r = r600_bytecode_add_alu(ctx->bc, &alu);
2101 if (r)
2102 return r;
2103 }
2104 return 0;
2105 }
2106
2107 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2108 {
2109 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2110 int i, j, k, r;
2111 struct r600_bytecode_alu alu;
2112 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2113 for (k = 0; k < last_slot; k++) {
2114 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2115 continue;
2116
2117 for (i = 0 ; i < 4; i++) {
2118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2119 alu.op = ctx->inst_info->op;
2120 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2121 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2122 }
2123 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2124 alu.dst.write = (i == k);
2125 if (i == 3)
2126 alu.last = 1;
2127 r = r600_bytecode_add_alu(ctx->bc, &alu);
2128 if (r)
2129 return r;
2130 }
2131 }
2132 return 0;
2133 }
2134
2135 /*
2136 * r600 - trunc to -PI..PI range
2137 * r700 - normalize by dividing by 2PI
2138 * see fdo bug 27901
2139 */
2140 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2141 {
2142 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2143 static float double_pi = 3.1415926535 * 2;
2144 static float neg_pi = -3.1415926535;
2145
2146 int r;
2147 struct r600_bytecode_alu alu;
2148
2149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2150 alu.op = ALU_OP3_MULADD;
2151 alu.is_op3 = 1;
2152
2153 alu.dst.chan = 0;
2154 alu.dst.sel = ctx->temp_reg;
2155 alu.dst.write = 1;
2156
2157 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2158
2159 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2160 alu.src[1].chan = 0;
2161 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2162 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2163 alu.src[2].chan = 0;
2164 alu.last = 1;
2165 r = r600_bytecode_add_alu(ctx->bc, &alu);
2166 if (r)
2167 return r;
2168
2169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2170 alu.op = ALU_OP1_FRACT;
2171
2172 alu.dst.chan = 0;
2173 alu.dst.sel = ctx->temp_reg;
2174 alu.dst.write = 1;
2175
2176 alu.src[0].sel = ctx->temp_reg;
2177 alu.src[0].chan = 0;
2178 alu.last = 1;
2179 r = r600_bytecode_add_alu(ctx->bc, &alu);
2180 if (r)
2181 return r;
2182
2183 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2184 alu.op = ALU_OP3_MULADD;
2185 alu.is_op3 = 1;
2186
2187 alu.dst.chan = 0;
2188 alu.dst.sel = ctx->temp_reg;
2189 alu.dst.write = 1;
2190
2191 alu.src[0].sel = ctx->temp_reg;
2192 alu.src[0].chan = 0;
2193
2194 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2195 alu.src[1].chan = 0;
2196 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2197 alu.src[2].chan = 0;
2198
2199 if (ctx->bc->chip_class == R600) {
2200 alu.src[1].value = *(uint32_t *)&double_pi;
2201 alu.src[2].value = *(uint32_t *)&neg_pi;
2202 } else {
2203 alu.src[1].sel = V_SQ_ALU_SRC_1;
2204 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2205 alu.src[2].neg = 1;
2206 }
2207
2208 alu.last = 1;
2209 r = r600_bytecode_add_alu(ctx->bc, &alu);
2210 if (r)
2211 return r;
2212 return 0;
2213 }
2214
2215 static int cayman_trig(struct r600_shader_ctx *ctx)
2216 {
2217 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2218 struct r600_bytecode_alu alu;
2219 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2220 int i, r;
2221
2222 r = tgsi_setup_trig(ctx);
2223 if (r)
2224 return r;
2225
2226
2227 for (i = 0; i < last_slot; i++) {
2228 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2229 alu.op = ctx->inst_info->op;
2230 alu.dst.chan = i;
2231
2232 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2233 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2234
2235 alu.src[0].sel = ctx->temp_reg;
2236 alu.src[0].chan = 0;
2237 if (i == last_slot - 1)
2238 alu.last = 1;
2239 r = r600_bytecode_add_alu(ctx->bc, &alu);
2240 if (r)
2241 return r;
2242 }
2243 return 0;
2244 }
2245
2246 static int tgsi_trig(struct r600_shader_ctx *ctx)
2247 {
2248 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2249 struct r600_bytecode_alu alu;
2250 int i, r;
2251 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2252
2253 r = tgsi_setup_trig(ctx);
2254 if (r)
2255 return r;
2256
2257 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2258 alu.op = ctx->inst_info->op;
2259 alu.dst.chan = 0;
2260 alu.dst.sel = ctx->temp_reg;
2261 alu.dst.write = 1;
2262
2263 alu.src[0].sel = ctx->temp_reg;
2264 alu.src[0].chan = 0;
2265 alu.last = 1;
2266 r = r600_bytecode_add_alu(ctx->bc, &alu);
2267 if (r)
2268 return r;
2269
2270 /* replicate result */
2271 for (i = 0; i < lasti + 1; i++) {
2272 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2273 continue;
2274
2275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2276 alu.op = ALU_OP1_MOV;
2277
2278 alu.src[0].sel = ctx->temp_reg;
2279 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2280 if (i == lasti)
2281 alu.last = 1;
2282 r = r600_bytecode_add_alu(ctx->bc, &alu);
2283 if (r)
2284 return r;
2285 }
2286 return 0;
2287 }
2288
2289 static int tgsi_scs(struct r600_shader_ctx *ctx)
2290 {
2291 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2292 struct r600_bytecode_alu alu;
2293 int i, r;
2294
2295 /* We'll only need the trig stuff if we are going to write to the
2296 * X or Y components of the destination vector.
2297 */
2298 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2299 r = tgsi_setup_trig(ctx);
2300 if (r)
2301 return r;
2302 }
2303
2304 /* dst.x = COS */
2305 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2306 if (ctx->bc->chip_class == CAYMAN) {
2307 for (i = 0 ; i < 3; i++) {
2308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2309 alu.op = ALU_OP1_COS;
2310 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2311
2312 if (i == 0)
2313 alu.dst.write = 1;
2314 else
2315 alu.dst.write = 0;
2316 alu.src[0].sel = ctx->temp_reg;
2317 alu.src[0].chan = 0;
2318 if (i == 2)
2319 alu.last = 1;
2320 r = r600_bytecode_add_alu(ctx->bc, &alu);
2321 if (r)
2322 return r;
2323 }
2324 } else {
2325 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2326 alu.op = ALU_OP1_COS;
2327 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2328
2329 alu.src[0].sel = ctx->temp_reg;
2330 alu.src[0].chan = 0;
2331 alu.last = 1;
2332 r = r600_bytecode_add_alu(ctx->bc, &alu);
2333 if (r)
2334 return r;
2335 }
2336 }
2337
2338 /* dst.y = SIN */
2339 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2340 if (ctx->bc->chip_class == CAYMAN) {
2341 for (i = 0 ; i < 3; i++) {
2342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2343 alu.op = ALU_OP1_SIN;
2344 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2345 if (i == 1)
2346 alu.dst.write = 1;
2347 else
2348 alu.dst.write = 0;
2349 alu.src[0].sel = ctx->temp_reg;
2350 alu.src[0].chan = 0;
2351 if (i == 2)
2352 alu.last = 1;
2353 r = r600_bytecode_add_alu(ctx->bc, &alu);
2354 if (r)
2355 return r;
2356 }
2357 } else {
2358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2359 alu.op = ALU_OP1_SIN;
2360 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2361
2362 alu.src[0].sel = ctx->temp_reg;
2363 alu.src[0].chan = 0;
2364 alu.last = 1;
2365 r = r600_bytecode_add_alu(ctx->bc, &alu);
2366 if (r)
2367 return r;
2368 }
2369 }
2370
2371 /* dst.z = 0.0; */
2372 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2374
2375 alu.op = ALU_OP1_MOV;
2376
2377 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2378
2379 alu.src[0].sel = V_SQ_ALU_SRC_0;
2380 alu.src[0].chan = 0;
2381
2382 alu.last = 1;
2383
2384 r = r600_bytecode_add_alu(ctx->bc, &alu);
2385 if (r)
2386 return r;
2387 }
2388
2389 /* dst.w = 1.0; */
2390 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2392
2393 alu.op = ALU_OP1_MOV;
2394
2395 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2396
2397 alu.src[0].sel = V_SQ_ALU_SRC_1;
2398 alu.src[0].chan = 0;
2399
2400 alu.last = 1;
2401
2402 r = r600_bytecode_add_alu(ctx->bc, &alu);
2403 if (r)
2404 return r;
2405 }
2406
2407 return 0;
2408 }
2409
2410 static int tgsi_kill(struct r600_shader_ctx *ctx)
2411 {
2412 struct r600_bytecode_alu alu;
2413 int i, r;
2414
2415 for (i = 0; i < 4; i++) {
2416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2417 alu.op = ctx->inst_info->op;
2418
2419 alu.dst.chan = i;
2420
2421 alu.src[0].sel = V_SQ_ALU_SRC_0;
2422
2423 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2424 alu.src[1].sel = V_SQ_ALU_SRC_1;
2425 alu.src[1].neg = 1;
2426 } else {
2427 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2428 }
2429 if (i == 3) {
2430 alu.last = 1;
2431 }
2432 r = r600_bytecode_add_alu(ctx->bc, &alu);
2433 if (r)
2434 return r;
2435 }
2436
2437 /* kill must be last in ALU */
2438 ctx->bc->force_add_cf = 1;
2439 ctx->shader->uses_kill = TRUE;
2440 return 0;
2441 }
2442
2443 static int tgsi_lit(struct r600_shader_ctx *ctx)
2444 {
2445 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2446 struct r600_bytecode_alu alu;
2447 int r;
2448
2449 /* tmp.x = max(src.y, 0.0) */
2450 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2451 alu.op = ALU_OP2_MAX;
2452 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2453 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2454 alu.src[1].chan = 1;
2455
2456 alu.dst.sel = ctx->temp_reg;
2457 alu.dst.chan = 0;
2458 alu.dst.write = 1;
2459
2460 alu.last = 1;
2461 r = r600_bytecode_add_alu(ctx->bc, &alu);
2462 if (r)
2463 return r;
2464
2465 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2466 {
2467 int chan;
2468 int sel;
2469 int i;
2470
2471 if (ctx->bc->chip_class == CAYMAN) {
2472 for (i = 0; i < 3; i++) {
2473 /* tmp.z = log(tmp.x) */
2474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2475 alu.op = ALU_OP1_LOG_CLAMPED;
2476 alu.src[0].sel = ctx->temp_reg;
2477 alu.src[0].chan = 0;
2478 alu.dst.sel = ctx->temp_reg;
2479 alu.dst.chan = i;
2480 if (i == 2) {
2481 alu.dst.write = 1;
2482 alu.last = 1;
2483 } else
2484 alu.dst.write = 0;
2485
2486 r = r600_bytecode_add_alu(ctx->bc, &alu);
2487 if (r)
2488 return r;
2489 }
2490 } else {
2491 /* tmp.z = log(tmp.x) */
2492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2493 alu.op = ALU_OP1_LOG_CLAMPED;
2494 alu.src[0].sel = ctx->temp_reg;
2495 alu.src[0].chan = 0;
2496 alu.dst.sel = ctx->temp_reg;
2497 alu.dst.chan = 2;
2498 alu.dst.write = 1;
2499 alu.last = 1;
2500 r = r600_bytecode_add_alu(ctx->bc, &alu);
2501 if (r)
2502 return r;
2503 }
2504
2505 chan = alu.dst.chan;
2506 sel = alu.dst.sel;
2507
2508 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2509 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2510 alu.op = ALU_OP3_MUL_LIT;
2511 alu.src[0].sel = sel;
2512 alu.src[0].chan = chan;
2513 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2514 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2515 alu.dst.sel = ctx->temp_reg;
2516 alu.dst.chan = 0;
2517 alu.dst.write = 1;
2518 alu.is_op3 = 1;
2519 alu.last = 1;
2520 r = r600_bytecode_add_alu(ctx->bc, &alu);
2521 if (r)
2522 return r;
2523
2524 if (ctx->bc->chip_class == CAYMAN) {
2525 for (i = 0; i < 3; i++) {
2526 /* dst.z = exp(tmp.x) */
2527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2528 alu.op = ALU_OP1_EXP_IEEE;
2529 alu.src[0].sel = ctx->temp_reg;
2530 alu.src[0].chan = 0;
2531 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2532 if (i == 2) {
2533 alu.dst.write = 1;
2534 alu.last = 1;
2535 } else
2536 alu.dst.write = 0;
2537 r = r600_bytecode_add_alu(ctx->bc, &alu);
2538 if (r)
2539 return r;
2540 }
2541 } else {
2542 /* dst.z = exp(tmp.x) */
2543 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2544 alu.op = ALU_OP1_EXP_IEEE;
2545 alu.src[0].sel = ctx->temp_reg;
2546 alu.src[0].chan = 0;
2547 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2548 alu.last = 1;
2549 r = r600_bytecode_add_alu(ctx->bc, &alu);
2550 if (r)
2551 return r;
2552 }
2553 }
2554
2555 /* dst.x, <- 1.0 */
2556 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2557 alu.op = ALU_OP1_MOV;
2558 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2559 alu.src[0].chan = 0;
2560 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2561 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2562 r = r600_bytecode_add_alu(ctx->bc, &alu);
2563 if (r)
2564 return r;
2565
2566 /* dst.y = max(src.x, 0.0) */
2567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2568 alu.op = ALU_OP2_MAX;
2569 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2570 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2571 alu.src[1].chan = 0;
2572 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2573 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2574 r = r600_bytecode_add_alu(ctx->bc, &alu);
2575 if (r)
2576 return r;
2577
2578 /* dst.w, <- 1.0 */
2579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2580 alu.op = ALU_OP1_MOV;
2581 alu.src[0].sel = V_SQ_ALU_SRC_1;
2582 alu.src[0].chan = 0;
2583 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2584 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2585 alu.last = 1;
2586 r = r600_bytecode_add_alu(ctx->bc, &alu);
2587 if (r)
2588 return r;
2589
2590 return 0;
2591 }
2592
2593 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2594 {
2595 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2596 struct r600_bytecode_alu alu;
2597 int i, r;
2598
2599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2600
2601 /* XXX:
2602 * For state trackers other than OpenGL, we'll want to use
2603 * _RECIPSQRT_IEEE instead.
2604 */
2605 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2606
2607 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2608 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2609 r600_bytecode_src_set_abs(&alu.src[i]);
2610 }
2611 alu.dst.sel = ctx->temp_reg;
2612 alu.dst.write = 1;
2613 alu.last = 1;
2614 r = r600_bytecode_add_alu(ctx->bc, &alu);
2615 if (r)
2616 return r;
2617 /* replicate result */
2618 return tgsi_helper_tempx_replicate(ctx);
2619 }
2620
2621 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2622 {
2623 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2624 struct r600_bytecode_alu alu;
2625 int i, r;
2626
2627 for (i = 0; i < 4; i++) {
2628 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2629 alu.src[0].sel = ctx->temp_reg;
2630 alu.op = ALU_OP1_MOV;
2631 alu.dst.chan = i;
2632 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2633 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2634 if (i == 3)
2635 alu.last = 1;
2636 r = r600_bytecode_add_alu(ctx->bc, &alu);
2637 if (r)
2638 return r;
2639 }
2640 return 0;
2641 }
2642
2643 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2644 {
2645 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2646 struct r600_bytecode_alu alu;
2647 int i, r;
2648
2649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2650 alu.op = ctx->inst_info->op;
2651 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2652 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2653 }
2654 alu.dst.sel = ctx->temp_reg;
2655 alu.dst.write = 1;
2656 alu.last = 1;
2657 r = r600_bytecode_add_alu(ctx->bc, &alu);
2658 if (r)
2659 return r;
2660 /* replicate result */
2661 return tgsi_helper_tempx_replicate(ctx);
2662 }
2663
2664 static int cayman_pow(struct r600_shader_ctx *ctx)
2665 {
2666 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2667 int i, r;
2668 struct r600_bytecode_alu alu;
2669 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2670
2671 for (i = 0; i < 3; i++) {
2672 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2673 alu.op = ALU_OP1_LOG_IEEE;
2674 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2675 alu.dst.sel = ctx->temp_reg;
2676 alu.dst.chan = i;
2677 alu.dst.write = 1;
2678 if (i == 2)
2679 alu.last = 1;
2680 r = r600_bytecode_add_alu(ctx->bc, &alu);
2681 if (r)
2682 return r;
2683 }
2684
2685 /* b * LOG2(a) */
2686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2687 alu.op = ALU_OP2_MUL;
2688 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2689 alu.src[1].sel = ctx->temp_reg;
2690 alu.dst.sel = ctx->temp_reg;
2691 alu.dst.write = 1;
2692 alu.last = 1;
2693 r = r600_bytecode_add_alu(ctx->bc, &alu);
2694 if (r)
2695 return r;
2696
2697 for (i = 0; i < last_slot; i++) {
2698 /* POW(a,b) = EXP2(b * LOG2(a))*/
2699 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2700 alu.op = ALU_OP1_EXP_IEEE;
2701 alu.src[0].sel = ctx->temp_reg;
2702
2703 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2704 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2705 if (i == last_slot - 1)
2706 alu.last = 1;
2707 r = r600_bytecode_add_alu(ctx->bc, &alu);
2708 if (r)
2709 return r;
2710 }
2711 return 0;
2712 }
2713
2714 static int tgsi_pow(struct r600_shader_ctx *ctx)
2715 {
2716 struct r600_bytecode_alu alu;
2717 int r;
2718
2719 /* LOG2(a) */
2720 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2721 alu.op = ALU_OP1_LOG_IEEE;
2722 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2723 alu.dst.sel = ctx->temp_reg;
2724 alu.dst.write = 1;
2725 alu.last = 1;
2726 r = r600_bytecode_add_alu(ctx->bc, &alu);
2727 if (r)
2728 return r;
2729 /* b * LOG2(a) */
2730 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2731 alu.op = ALU_OP2_MUL;
2732 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2733 alu.src[1].sel = ctx->temp_reg;
2734 alu.dst.sel = ctx->temp_reg;
2735 alu.dst.write = 1;
2736 alu.last = 1;
2737 r = r600_bytecode_add_alu(ctx->bc, &alu);
2738 if (r)
2739 return r;
2740 /* POW(a,b) = EXP2(b * LOG2(a))*/
2741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2742 alu.op = ALU_OP1_EXP_IEEE;
2743 alu.src[0].sel = ctx->temp_reg;
2744 alu.dst.sel = ctx->temp_reg;
2745 alu.dst.write = 1;
2746 alu.last = 1;
2747 r = r600_bytecode_add_alu(ctx->bc, &alu);
2748 if (r)
2749 return r;
2750 return tgsi_helper_tempx_replicate(ctx);
2751 }
2752
2753 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2754 {
2755 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2756 struct r600_bytecode_alu alu;
2757 int i, r, j;
2758 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2759 int tmp0 = ctx->temp_reg;
2760 int tmp1 = r600_get_temp(ctx);
2761 int tmp2 = r600_get_temp(ctx);
2762 int tmp3 = r600_get_temp(ctx);
2763 /* Unsigned path:
2764 *
2765 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2766 *
2767 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2768 * 2. tmp0.z = lo (tmp0.x * src2)
2769 * 3. tmp0.w = -tmp0.z
2770 * 4. tmp0.y = hi (tmp0.x * src2)
2771 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2772 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2773 * 7. tmp1.x = tmp0.x - tmp0.w
2774 * 8. tmp1.y = tmp0.x + tmp0.w
2775 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2776 * 10. tmp0.z = hi(tmp0.x * src1) = q
2777 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2778 *
2779 * 12. tmp0.w = src1 - tmp0.y = r
2780 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2781 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2782 *
2783 * if DIV
2784 *
2785 * 15. tmp1.z = tmp0.z + 1 = q + 1
2786 * 16. tmp1.w = tmp0.z - 1 = q - 1
2787 *
2788 * else MOD
2789 *
2790 * 15. tmp1.z = tmp0.w - src2 = r - src2
2791 * 16. tmp1.w = tmp0.w + src2 = r + src2
2792 *
2793 * endif
2794 *
2795 * 17. tmp1.x = tmp1.x & tmp1.y
2796 *
2797 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2798 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2799 *
2800 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2801 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2802 *
2803 * Signed path:
2804 *
2805 * Same as unsigned, using abs values of the operands,
2806 * and fixing the sign of the result in the end.
2807 */
2808
2809 for (i = 0; i < 4; i++) {
2810 if (!(write_mask & (1<<i)))
2811 continue;
2812
2813 if (signed_op) {
2814
2815 /* tmp2.x = -src0 */
2816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2817 alu.op = ALU_OP2_SUB_INT;
2818
2819 alu.dst.sel = tmp2;
2820 alu.dst.chan = 0;
2821 alu.dst.write = 1;
2822
2823 alu.src[0].sel = V_SQ_ALU_SRC_0;
2824
2825 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2826
2827 alu.last = 1;
2828 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2829 return r;
2830
2831 /* tmp2.y = -src1 */
2832 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2833 alu.op = ALU_OP2_SUB_INT;
2834
2835 alu.dst.sel = tmp2;
2836 alu.dst.chan = 1;
2837 alu.dst.write = 1;
2838
2839 alu.src[0].sel = V_SQ_ALU_SRC_0;
2840
2841 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2842
2843 alu.last = 1;
2844 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2845 return r;
2846
2847 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2848 /* it will be a sign of the quotient */
2849 if (!mod) {
2850
2851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2852 alu.op = ALU_OP2_XOR_INT;
2853
2854 alu.dst.sel = tmp2;
2855 alu.dst.chan = 2;
2856 alu.dst.write = 1;
2857
2858 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2859 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2860
2861 alu.last = 1;
2862 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2863 return r;
2864 }
2865
2866 /* tmp2.x = |src0| */
2867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2868 alu.op = ALU_OP3_CNDGE_INT;
2869 alu.is_op3 = 1;
2870
2871 alu.dst.sel = tmp2;
2872 alu.dst.chan = 0;
2873 alu.dst.write = 1;
2874
2875 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2876 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2877 alu.src[2].sel = tmp2;
2878 alu.src[2].chan = 0;
2879
2880 alu.last = 1;
2881 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2882 return r;
2883
2884 /* tmp2.y = |src1| */
2885 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2886 alu.op = ALU_OP3_CNDGE_INT;
2887 alu.is_op3 = 1;
2888
2889 alu.dst.sel = tmp2;
2890 alu.dst.chan = 1;
2891 alu.dst.write = 1;
2892
2893 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2894 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2895 alu.src[2].sel = tmp2;
2896 alu.src[2].chan = 1;
2897
2898 alu.last = 1;
2899 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2900 return r;
2901
2902 }
2903
2904 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2905 if (ctx->bc->chip_class == CAYMAN) {
2906 /* tmp3.x = u2f(src2) */
2907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2908 alu.op = ALU_OP1_UINT_TO_FLT;
2909
2910 alu.dst.sel = tmp3;
2911 alu.dst.chan = 0;
2912 alu.dst.write = 1;
2913
2914 if (signed_op) {
2915 alu.src[0].sel = tmp2;
2916 alu.src[0].chan = 1;
2917 } else {
2918 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2919 }
2920
2921 alu.last = 1;
2922 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2923 return r;
2924
2925 /* tmp0.x = recip(tmp3.x) */
2926 for (j = 0 ; j < 3; j++) {
2927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2928 alu.op = ALU_OP1_RECIP_IEEE;
2929
2930 alu.dst.sel = tmp0;
2931 alu.dst.chan = j;
2932 alu.dst.write = (j == 0);
2933
2934 alu.src[0].sel = tmp3;
2935 alu.src[0].chan = 0;
2936
2937 if (j == 2)
2938 alu.last = 1;
2939 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2940 return r;
2941 }
2942
2943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2944 alu.op = ALU_OP2_MUL;
2945
2946 alu.src[0].sel = tmp0;
2947 alu.src[0].chan = 0;
2948
2949 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2950 alu.src[1].value = 0x4f800000;
2951
2952 alu.dst.sel = tmp3;
2953 alu.dst.write = 1;
2954 alu.last = 1;
2955 r = r600_bytecode_add_alu(ctx->bc, &alu);
2956 if (r)
2957 return r;
2958
2959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2960 alu.op = ALU_OP1_FLT_TO_UINT;
2961
2962 alu.dst.sel = tmp0;
2963 alu.dst.chan = 0;
2964 alu.dst.write = 1;
2965
2966 alu.src[0].sel = tmp3;
2967 alu.src[0].chan = 0;
2968
2969 alu.last = 1;
2970 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2971 return r;
2972
2973 } else {
2974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2975 alu.op = ALU_OP1_RECIP_UINT;
2976
2977 alu.dst.sel = tmp0;
2978 alu.dst.chan = 0;
2979 alu.dst.write = 1;
2980
2981 if (signed_op) {
2982 alu.src[0].sel = tmp2;
2983 alu.src[0].chan = 1;
2984 } else {
2985 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2986 }
2987
2988 alu.last = 1;
2989 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2990 return r;
2991 }
2992
2993 /* 2. tmp0.z = lo (tmp0.x * src2) */
2994 if (ctx->bc->chip_class == CAYMAN) {
2995 for (j = 0 ; j < 4; j++) {
2996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2997 alu.op = ALU_OP2_MULLO_UINT;
2998
2999 alu.dst.sel = tmp0;
3000 alu.dst.chan = j;
3001 alu.dst.write = (j == 2);
3002
3003 alu.src[0].sel = tmp0;
3004 alu.src[0].chan = 0;
3005 if (signed_op) {
3006 alu.src[1].sel = tmp2;
3007 alu.src[1].chan = 1;
3008 } else {
3009 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3010 }
3011
3012 alu.last = (j == 3);
3013 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3014 return r;
3015 }
3016 } else {
3017 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3018 alu.op = ALU_OP2_MULLO_UINT;
3019
3020 alu.dst.sel = tmp0;
3021 alu.dst.chan = 2;
3022 alu.dst.write = 1;
3023
3024 alu.src[0].sel = tmp0;
3025 alu.src[0].chan = 0;
3026 if (signed_op) {
3027 alu.src[1].sel = tmp2;
3028 alu.src[1].chan = 1;
3029 } else {
3030 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3031 }
3032
3033 alu.last = 1;
3034 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3035 return r;
3036 }
3037
3038 /* 3. tmp0.w = -tmp0.z */
3039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3040 alu.op = ALU_OP2_SUB_INT;
3041
3042 alu.dst.sel = tmp0;
3043 alu.dst.chan = 3;
3044 alu.dst.write = 1;
3045
3046 alu.src[0].sel = V_SQ_ALU_SRC_0;
3047 alu.src[1].sel = tmp0;
3048 alu.src[1].chan = 2;
3049
3050 alu.last = 1;
3051 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3052 return r;
3053
3054 /* 4. tmp0.y = hi (tmp0.x * src2) */
3055 if (ctx->bc->chip_class == CAYMAN) {
3056 for (j = 0 ; j < 4; j++) {
3057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3058 alu.op = ALU_OP2_MULHI_UINT;
3059
3060 alu.dst.sel = tmp0;
3061 alu.dst.chan = j;
3062 alu.dst.write = (j == 1);
3063
3064 alu.src[0].sel = tmp0;
3065 alu.src[0].chan = 0;
3066
3067 if (signed_op) {
3068 alu.src[1].sel = tmp2;
3069 alu.src[1].chan = 1;
3070 } else {
3071 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3072 }
3073 alu.last = (j == 3);
3074 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3075 return r;
3076 }
3077 } else {
3078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3079 alu.op = ALU_OP2_MULHI_UINT;
3080
3081 alu.dst.sel = tmp0;
3082 alu.dst.chan = 1;
3083 alu.dst.write = 1;
3084
3085 alu.src[0].sel = tmp0;
3086 alu.src[0].chan = 0;
3087
3088 if (signed_op) {
3089 alu.src[1].sel = tmp2;
3090 alu.src[1].chan = 1;
3091 } else {
3092 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3093 }
3094
3095 alu.last = 1;
3096 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3097 return r;
3098 }
3099
3100 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3102 alu.op = ALU_OP3_CNDE_INT;
3103 alu.is_op3 = 1;
3104
3105 alu.dst.sel = tmp0;
3106 alu.dst.chan = 2;
3107 alu.dst.write = 1;
3108
3109 alu.src[0].sel = tmp0;
3110 alu.src[0].chan = 1;
3111 alu.src[1].sel = tmp0;
3112 alu.src[1].chan = 3;
3113 alu.src[2].sel = tmp0;
3114 alu.src[2].chan = 2;
3115
3116 alu.last = 1;
3117 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3118 return r;
3119
3120 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3121 if (ctx->bc->chip_class == CAYMAN) {
3122 for (j = 0 ; j < 4; j++) {
3123 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3124 alu.op = ALU_OP2_MULHI_UINT;
3125
3126 alu.dst.sel = tmp0;
3127 alu.dst.chan = j;
3128 alu.dst.write = (j == 3);
3129
3130 alu.src[0].sel = tmp0;
3131 alu.src[0].chan = 2;
3132
3133 alu.src[1].sel = tmp0;
3134 alu.src[1].chan = 0;
3135
3136 alu.last = (j == 3);
3137 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3138 return r;
3139 }
3140 } else {
3141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3142 alu.op = ALU_OP2_MULHI_UINT;
3143
3144 alu.dst.sel = tmp0;
3145 alu.dst.chan = 3;
3146 alu.dst.write = 1;
3147
3148 alu.src[0].sel = tmp0;
3149 alu.src[0].chan = 2;
3150
3151 alu.src[1].sel = tmp0;
3152 alu.src[1].chan = 0;
3153
3154 alu.last = 1;
3155 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3156 return r;
3157 }
3158
3159 /* 7. tmp1.x = tmp0.x - tmp0.w */
3160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3161 alu.op = ALU_OP2_SUB_INT;
3162
3163 alu.dst.sel = tmp1;
3164 alu.dst.chan = 0;
3165 alu.dst.write = 1;
3166
3167 alu.src[0].sel = tmp0;
3168 alu.src[0].chan = 0;
3169 alu.src[1].sel = tmp0;
3170 alu.src[1].chan = 3;
3171
3172 alu.last = 1;
3173 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3174 return r;
3175
3176 /* 8. tmp1.y = tmp0.x + tmp0.w */
3177 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3178 alu.op = ALU_OP2_ADD_INT;
3179
3180 alu.dst.sel = tmp1;
3181 alu.dst.chan = 1;
3182 alu.dst.write = 1;
3183
3184 alu.src[0].sel = tmp0;
3185 alu.src[0].chan = 0;
3186 alu.src[1].sel = tmp0;
3187 alu.src[1].chan = 3;
3188
3189 alu.last = 1;
3190 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3191 return r;
3192
3193 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3195 alu.op = ALU_OP3_CNDE_INT;
3196 alu.is_op3 = 1;
3197
3198 alu.dst.sel = tmp0;
3199 alu.dst.chan = 0;
3200 alu.dst.write = 1;
3201
3202 alu.src[0].sel = tmp0;
3203 alu.src[0].chan = 1;
3204 alu.src[1].sel = tmp1;
3205 alu.src[1].chan = 1;
3206 alu.src[2].sel = tmp1;
3207 alu.src[2].chan = 0;
3208
3209 alu.last = 1;
3210 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3211 return r;
3212
3213 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3214 if (ctx->bc->chip_class == CAYMAN) {
3215 for (j = 0 ; j < 4; j++) {
3216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3217 alu.op = ALU_OP2_MULHI_UINT;
3218
3219 alu.dst.sel = tmp0;
3220 alu.dst.chan = j;
3221 alu.dst.write = (j == 2);
3222
3223 alu.src[0].sel = tmp0;
3224 alu.src[0].chan = 0;
3225
3226 if (signed_op) {
3227 alu.src[1].sel = tmp2;
3228 alu.src[1].chan = 0;
3229 } else {
3230 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3231 }
3232
3233 alu.last = (j == 3);
3234 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3235 return r;
3236 }
3237 } else {
3238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3239 alu.op = ALU_OP2_MULHI_UINT;
3240
3241 alu.dst.sel = tmp0;
3242 alu.dst.chan = 2;
3243 alu.dst.write = 1;
3244
3245 alu.src[0].sel = tmp0;
3246 alu.src[0].chan = 0;
3247
3248 if (signed_op) {
3249 alu.src[1].sel = tmp2;
3250 alu.src[1].chan = 0;
3251 } else {
3252 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3253 }
3254
3255 alu.last = 1;
3256 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3257 return r;
3258 }
3259
3260 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3261 if (ctx->bc->chip_class == CAYMAN) {
3262 for (j = 0 ; j < 4; j++) {
3263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3264 alu.op = ALU_OP2_MULLO_UINT;
3265
3266 alu.dst.sel = tmp0;
3267 alu.dst.chan = j;
3268 alu.dst.write = (j == 1);
3269
3270 if (signed_op) {
3271 alu.src[0].sel = tmp2;
3272 alu.src[0].chan = 1;
3273 } else {
3274 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3275 }
3276
3277 alu.src[1].sel = tmp0;
3278 alu.src[1].chan = 2;
3279
3280 alu.last = (j == 3);
3281 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3282 return r;
3283 }
3284 } else {
3285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3286 alu.op = ALU_OP2_MULLO_UINT;
3287
3288 alu.dst.sel = tmp0;
3289 alu.dst.chan = 1;
3290 alu.dst.write = 1;
3291
3292 if (signed_op) {
3293 alu.src[0].sel = tmp2;
3294 alu.src[0].chan = 1;
3295 } else {
3296 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3297 }
3298
3299 alu.src[1].sel = tmp0;
3300 alu.src[1].chan = 2;
3301
3302 alu.last = 1;
3303 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3304 return r;
3305 }
3306
3307 /* 12. tmp0.w = src1 - tmp0.y = r */
3308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3309 alu.op = ALU_OP2_SUB_INT;
3310
3311 alu.dst.sel = tmp0;
3312 alu.dst.chan = 3;
3313 alu.dst.write = 1;
3314
3315 if (signed_op) {
3316 alu.src[0].sel = tmp2;
3317 alu.src[0].chan = 0;
3318 } else {
3319 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3320 }
3321
3322 alu.src[1].sel = tmp0;
3323 alu.src[1].chan = 1;
3324
3325 alu.last = 1;
3326 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3327 return r;
3328
3329 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3331 alu.op = ALU_OP2_SETGE_UINT;
3332
3333 alu.dst.sel = tmp1;
3334 alu.dst.chan = 0;
3335 alu.dst.write = 1;
3336
3337 alu.src[0].sel = tmp0;
3338 alu.src[0].chan = 3;
3339 if (signed_op) {
3340 alu.src[1].sel = tmp2;
3341 alu.src[1].chan = 1;
3342 } else {
3343 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3344 }
3345
3346 alu.last = 1;
3347 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3348 return r;
3349
3350 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3352 alu.op = ALU_OP2_SETGE_UINT;
3353
3354 alu.dst.sel = tmp1;
3355 alu.dst.chan = 1;
3356 alu.dst.write = 1;
3357
3358 if (signed_op) {
3359 alu.src[0].sel = tmp2;
3360 alu.src[0].chan = 0;
3361 } else {
3362 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3363 }
3364
3365 alu.src[1].sel = tmp0;
3366 alu.src[1].chan = 1;
3367
3368 alu.last = 1;
3369 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3370 return r;
3371
3372 if (mod) { /* UMOD */
3373
3374 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3376 alu.op = ALU_OP2_SUB_INT;
3377
3378 alu.dst.sel = tmp1;
3379 alu.dst.chan = 2;
3380 alu.dst.write = 1;
3381
3382 alu.src[0].sel = tmp0;
3383 alu.src[0].chan = 3;
3384
3385 if (signed_op) {
3386 alu.src[1].sel = tmp2;
3387 alu.src[1].chan = 1;
3388 } else {
3389 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3390 }
3391
3392 alu.last = 1;
3393 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3394 return r;
3395
3396 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3398 alu.op = ALU_OP2_ADD_INT;
3399
3400 alu.dst.sel = tmp1;
3401 alu.dst.chan = 3;
3402 alu.dst.write = 1;
3403
3404 alu.src[0].sel = tmp0;
3405 alu.src[0].chan = 3;
3406 if (signed_op) {
3407 alu.src[1].sel = tmp2;
3408 alu.src[1].chan = 1;
3409 } else {
3410 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3411 }
3412
3413 alu.last = 1;
3414 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3415 return r;
3416
3417 } else { /* UDIV */
3418
3419 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3421 alu.op = ALU_OP2_ADD_INT;
3422
3423 alu.dst.sel = tmp1;
3424 alu.dst.chan = 2;
3425 alu.dst.write = 1;
3426
3427 alu.src[0].sel = tmp0;
3428 alu.src[0].chan = 2;
3429 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3430
3431 alu.last = 1;
3432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3433 return r;
3434
3435 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3437 alu.op = ALU_OP2_ADD_INT;
3438
3439 alu.dst.sel = tmp1;
3440 alu.dst.chan = 3;
3441 alu.dst.write = 1;
3442
3443 alu.src[0].sel = tmp0;
3444 alu.src[0].chan = 2;
3445 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3446
3447 alu.last = 1;
3448 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3449 return r;
3450
3451 }
3452
3453 /* 17. tmp1.x = tmp1.x & tmp1.y */
3454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3455 alu.op = ALU_OP2_AND_INT;
3456
3457 alu.dst.sel = tmp1;
3458 alu.dst.chan = 0;
3459 alu.dst.write = 1;
3460
3461 alu.src[0].sel = tmp1;
3462 alu.src[0].chan = 0;
3463 alu.src[1].sel = tmp1;
3464 alu.src[1].chan = 1;
3465
3466 alu.last = 1;
3467 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3468 return r;
3469
3470 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3471 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3472 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3473 alu.op = ALU_OP3_CNDE_INT;
3474 alu.is_op3 = 1;
3475
3476 alu.dst.sel = tmp0;
3477 alu.dst.chan = 2;
3478 alu.dst.write = 1;
3479
3480 alu.src[0].sel = tmp1;
3481 alu.src[0].chan = 0;
3482 alu.src[1].sel = tmp0;
3483 alu.src[1].chan = mod ? 3 : 2;
3484 alu.src[2].sel = tmp1;
3485 alu.src[2].chan = 2;
3486
3487 alu.last = 1;
3488 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3489 return r;
3490
3491 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3493 alu.op = ALU_OP3_CNDE_INT;
3494 alu.is_op3 = 1;
3495
3496 if (signed_op) {
3497 alu.dst.sel = tmp0;
3498 alu.dst.chan = 2;
3499 alu.dst.write = 1;
3500 } else {
3501 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3502 }
3503
3504 alu.src[0].sel = tmp1;
3505 alu.src[0].chan = 1;
3506 alu.src[1].sel = tmp1;
3507 alu.src[1].chan = 3;
3508 alu.src[2].sel = tmp0;
3509 alu.src[2].chan = 2;
3510
3511 alu.last = 1;
3512 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3513 return r;
3514
3515 if (signed_op) {
3516
3517 /* fix the sign of the result */
3518
3519 if (mod) {
3520
3521 /* tmp0.x = -tmp0.z */
3522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3523 alu.op = ALU_OP2_SUB_INT;
3524
3525 alu.dst.sel = tmp0;
3526 alu.dst.chan = 0;
3527 alu.dst.write = 1;
3528
3529 alu.src[0].sel = V_SQ_ALU_SRC_0;
3530 alu.src[1].sel = tmp0;
3531 alu.src[1].chan = 2;
3532
3533 alu.last = 1;
3534 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3535 return r;
3536
3537 /* sign of the remainder is the same as the sign of src0 */
3538 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3540 alu.op = ALU_OP3_CNDGE_INT;
3541 alu.is_op3 = 1;
3542
3543 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3544
3545 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3546 alu.src[1].sel = tmp0;
3547 alu.src[1].chan = 2;
3548 alu.src[2].sel = tmp0;
3549 alu.src[2].chan = 0;
3550
3551 alu.last = 1;
3552 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3553 return r;
3554
3555 } else {
3556
3557 /* tmp0.x = -tmp0.z */
3558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3559 alu.op = ALU_OP2_SUB_INT;
3560
3561 alu.dst.sel = tmp0;
3562 alu.dst.chan = 0;
3563 alu.dst.write = 1;
3564
3565 alu.src[0].sel = V_SQ_ALU_SRC_0;
3566 alu.src[1].sel = tmp0;
3567 alu.src[1].chan = 2;
3568
3569 alu.last = 1;
3570 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3571 return r;
3572
3573 /* fix the quotient sign (same as the sign of src0*src1) */
3574 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3576 alu.op = ALU_OP3_CNDGE_INT;
3577 alu.is_op3 = 1;
3578
3579 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3580
3581 alu.src[0].sel = tmp2;
3582 alu.src[0].chan = 2;
3583 alu.src[1].sel = tmp0;
3584 alu.src[1].chan = 2;
3585 alu.src[2].sel = tmp0;
3586 alu.src[2].chan = 0;
3587
3588 alu.last = 1;
3589 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3590 return r;
3591 }
3592 }
3593 }
3594 return 0;
3595 }
3596
3597 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3598 {
3599 return tgsi_divmod(ctx, 0, 0);
3600 }
3601
3602 static int tgsi_umod(struct r600_shader_ctx *ctx)
3603 {
3604 return tgsi_divmod(ctx, 1, 0);
3605 }
3606
3607 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3608 {
3609 return tgsi_divmod(ctx, 0, 1);
3610 }
3611
3612 static int tgsi_imod(struct r600_shader_ctx *ctx)
3613 {
3614 return tgsi_divmod(ctx, 1, 1);
3615 }
3616
3617
3618 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3619 {
3620 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3621 struct r600_bytecode_alu alu;
3622 int i, r;
3623 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3624 int last_inst = tgsi_last_instruction(write_mask);
3625
3626 for (i = 0; i < 4; i++) {
3627 if (!(write_mask & (1<<i)))
3628 continue;
3629
3630 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3631 alu.op = ALU_OP1_TRUNC;
3632
3633 alu.dst.sel = ctx->temp_reg;
3634 alu.dst.chan = i;
3635 alu.dst.write = 1;
3636
3637 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3638 if (i == last_inst)
3639 alu.last = 1;
3640 r = r600_bytecode_add_alu(ctx->bc, &alu);
3641 if (r)
3642 return r;
3643 }
3644
3645 for (i = 0; i < 4; i++) {
3646 if (!(write_mask & (1<<i)))
3647 continue;
3648
3649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3650 alu.op = ctx->inst_info->op;
3651
3652 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3653
3654 alu.src[0].sel = ctx->temp_reg;
3655 alu.src[0].chan = i;
3656
3657 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3658 alu.last = 1;
3659 r = r600_bytecode_add_alu(ctx->bc, &alu);
3660 if (r)
3661 return r;
3662 }
3663
3664 return 0;
3665 }
3666
3667 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3668 {
3669 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3670 struct r600_bytecode_alu alu;
3671 int i, r;
3672 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3673 int last_inst = tgsi_last_instruction(write_mask);
3674
3675 /* tmp = -src */
3676 for (i = 0; i < 4; i++) {
3677 if (!(write_mask & (1<<i)))
3678 continue;
3679
3680 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3681 alu.op = ALU_OP2_SUB_INT;
3682
3683 alu.dst.sel = ctx->temp_reg;
3684 alu.dst.chan = i;
3685 alu.dst.write = 1;
3686
3687 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3688 alu.src[0].sel = V_SQ_ALU_SRC_0;
3689
3690 if (i == last_inst)
3691 alu.last = 1;
3692 r = r600_bytecode_add_alu(ctx->bc, &alu);
3693 if (r)
3694 return r;
3695 }
3696
3697 /* dst = (src >= 0 ? src : tmp) */
3698 for (i = 0; i < 4; i++) {
3699 if (!(write_mask & (1<<i)))
3700 continue;
3701
3702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3703 alu.op = ALU_OP3_CNDGE_INT;
3704 alu.is_op3 = 1;
3705 alu.dst.write = 1;
3706
3707 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3708
3709 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3710 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3711 alu.src[2].sel = ctx->temp_reg;
3712 alu.src[2].chan = i;
3713
3714 if (i == last_inst)
3715 alu.last = 1;
3716 r = r600_bytecode_add_alu(ctx->bc, &alu);
3717 if (r)
3718 return r;
3719 }
3720 return 0;
3721 }
3722
3723 static int tgsi_issg(struct r600_shader_ctx *ctx)
3724 {
3725 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3726 struct r600_bytecode_alu alu;
3727 int i, r;
3728 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3729 int last_inst = tgsi_last_instruction(write_mask);
3730
3731 /* tmp = (src >= 0 ? src : -1) */
3732 for (i = 0; i < 4; i++) {
3733 if (!(write_mask & (1<<i)))
3734 continue;
3735
3736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3737 alu.op = ALU_OP3_CNDGE_INT;
3738 alu.is_op3 = 1;
3739
3740 alu.dst.sel = ctx->temp_reg;
3741 alu.dst.chan = i;
3742 alu.dst.write = 1;
3743
3744 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3745 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3746 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3747
3748 if (i == last_inst)
3749 alu.last = 1;
3750 r = r600_bytecode_add_alu(ctx->bc, &alu);
3751 if (r)
3752 return r;
3753 }
3754
3755 /* dst = (tmp > 0 ? 1 : tmp) */
3756 for (i = 0; i < 4; i++) {
3757 if (!(write_mask & (1<<i)))
3758 continue;
3759
3760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3761 alu.op = ALU_OP3_CNDGT_INT;
3762 alu.is_op3 = 1;
3763 alu.dst.write = 1;
3764
3765 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3766
3767 alu.src[0].sel = ctx->temp_reg;
3768 alu.src[0].chan = i;
3769
3770 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3771
3772 alu.src[2].sel = ctx->temp_reg;
3773 alu.src[2].chan = i;
3774
3775 if (i == last_inst)
3776 alu.last = 1;
3777 r = r600_bytecode_add_alu(ctx->bc, &alu);
3778 if (r)
3779 return r;
3780 }
3781 return 0;
3782 }
3783
3784
3785
3786 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3787 {
3788 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3789 struct r600_bytecode_alu alu;
3790 int i, r;
3791
3792 /* tmp = (src > 0 ? 1 : src) */
3793 for (i = 0; i < 4; i++) {
3794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3795 alu.op = ALU_OP3_CNDGT;
3796 alu.is_op3 = 1;
3797
3798 alu.dst.sel = ctx->temp_reg;
3799 alu.dst.chan = i;
3800
3801 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3802 alu.src[1].sel = V_SQ_ALU_SRC_1;
3803 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3804
3805 if (i == 3)
3806 alu.last = 1;
3807 r = r600_bytecode_add_alu(ctx->bc, &alu);
3808 if (r)
3809 return r;
3810 }
3811
3812 /* dst = (-tmp > 0 ? -1 : tmp) */
3813 for (i = 0; i < 4; i++) {
3814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3815 alu.op = ALU_OP3_CNDGT;
3816 alu.is_op3 = 1;
3817 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3818
3819 alu.src[0].sel = ctx->temp_reg;
3820 alu.src[0].chan = i;
3821 alu.src[0].neg = 1;
3822
3823 alu.src[1].sel = V_SQ_ALU_SRC_1;
3824 alu.src[1].neg = 1;
3825
3826 alu.src[2].sel = ctx->temp_reg;
3827 alu.src[2].chan = i;
3828
3829 if (i == 3)
3830 alu.last = 1;
3831 r = r600_bytecode_add_alu(ctx->bc, &alu);
3832 if (r)
3833 return r;
3834 }
3835 return 0;
3836 }
3837
3838 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3839 {
3840 struct r600_bytecode_alu alu;
3841 int i, r;
3842
3843 for (i = 0; i < 4; i++) {
3844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3845 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3846 alu.op = ALU_OP0_NOP;
3847 alu.dst.chan = i;
3848 } else {
3849 alu.op = ALU_OP1_MOV;
3850 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3851 alu.src[0].sel = ctx->temp_reg;
3852 alu.src[0].chan = i;
3853 }
3854 if (i == 3) {
3855 alu.last = 1;
3856 }
3857 r = r600_bytecode_add_alu(ctx->bc, &alu);
3858 if (r)
3859 return r;
3860 }
3861 return 0;
3862 }
3863
3864 static int tgsi_op3(struct r600_shader_ctx *ctx)
3865 {
3866 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3867 struct r600_bytecode_alu alu;
3868 int i, j, r;
3869 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3870
3871 for (i = 0; i < lasti + 1; i++) {
3872 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3873 continue;
3874
3875 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3876 alu.op = ctx->inst_info->op;
3877 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3878 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3879 }
3880
3881 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3882 alu.dst.chan = i;
3883 alu.dst.write = 1;
3884 alu.is_op3 = 1;
3885 if (i == lasti) {
3886 alu.last = 1;
3887 }
3888 r = r600_bytecode_add_alu(ctx->bc, &alu);
3889 if (r)
3890 return r;
3891 }
3892 return 0;
3893 }
3894
3895 static int tgsi_dp(struct r600_shader_ctx *ctx)
3896 {
3897 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3898 struct r600_bytecode_alu alu;
3899 int i, j, r;
3900
3901 for (i = 0; i < 4; i++) {
3902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3903 alu.op = ctx->inst_info->op;
3904 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3905 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3906 }
3907
3908 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3909 alu.dst.chan = i;
3910 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3911 /* handle some special cases */
3912 switch (ctx->inst_info->tgsi_opcode) {
3913 case TGSI_OPCODE_DP2:
3914 if (i > 1) {
3915 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3916 alu.src[0].chan = alu.src[1].chan = 0;
3917 }
3918 break;
3919 case TGSI_OPCODE_DP3:
3920 if (i > 2) {
3921 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3922 alu.src[0].chan = alu.src[1].chan = 0;
3923 }
3924 break;
3925 case TGSI_OPCODE_DPH:
3926 if (i == 3) {
3927 alu.src[0].sel = V_SQ_ALU_SRC_1;
3928 alu.src[0].chan = 0;
3929 alu.src[0].neg = 0;
3930 }
3931 break;
3932 default:
3933 break;
3934 }
3935 if (i == 3) {
3936 alu.last = 1;
3937 }
3938 r = r600_bytecode_add_alu(ctx->bc, &alu);
3939 if (r)
3940 return r;
3941 }
3942 return 0;
3943 }
3944
3945 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3946 unsigned index)
3947 {
3948 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3949 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3950 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3951 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3952 ctx->src[index].neg || ctx->src[index].abs;
3953 }
3954
3955 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3956 unsigned index)
3957 {
3958 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3959 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3960 }
3961
3962 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3963 {
3964 struct r600_bytecode_vtx vtx;
3965 struct r600_bytecode_alu alu;
3966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3967 int src_gpr, r, i;
3968 int id = tgsi_tex_get_src_gpr(ctx, 1);
3969
3970 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3971 if (src_requires_loading) {
3972 for (i = 0; i < 4; i++) {
3973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3974 alu.op = ALU_OP1_MOV;
3975 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3976 alu.dst.sel = ctx->temp_reg;
3977 alu.dst.chan = i;
3978 if (i == 3)
3979 alu.last = 1;
3980 alu.dst.write = 1;
3981 r = r600_bytecode_add_alu(ctx->bc, &alu);
3982 if (r)
3983 return r;
3984 }
3985 src_gpr = ctx->temp_reg;
3986 }
3987
3988 memset(&vtx, 0, sizeof(vtx));
3989 vtx.op = FETCH_OP_VFETCH;
3990 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3991 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3992 vtx.src_gpr = src_gpr;
3993 vtx.mega_fetch_count = 16;
3994 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3995 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3996 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3997 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
3998 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
3999 vtx.use_const_fields = 1;
4000 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
4001
4002 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
4003 return r;
4004
4005 if (ctx->bc->chip_class >= EVERGREEN)
4006 return 0;
4007
4008 for (i = 0; i < 4; i++) {
4009 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4010 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4011 continue;
4012
4013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4014 alu.op = ALU_OP2_AND_INT;
4015
4016 alu.dst.chan = i;
4017 alu.dst.sel = vtx.dst_gpr;
4018 alu.dst.write = 1;
4019
4020 alu.src[0].sel = vtx.dst_gpr;
4021 alu.src[0].chan = i;
4022
4023 alu.src[1].sel = 512 + (id * 2);
4024 alu.src[1].chan = i % 4;
4025 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4026
4027 if (i == lasti)
4028 alu.last = 1;
4029 r = r600_bytecode_add_alu(ctx->bc, &alu);
4030 if (r)
4031 return r;
4032 }
4033
4034 if (inst->Dst[0].Register.WriteMask & 3) {
4035 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4036 alu.op = ALU_OP2_OR_INT;
4037
4038 alu.dst.chan = 3;
4039 alu.dst.sel = vtx.dst_gpr;
4040 alu.dst.write = 1;
4041
4042 alu.src[0].sel = vtx.dst_gpr;
4043 alu.src[0].chan = 3;
4044
4045 alu.src[1].sel = 512 + (id * 2) + 1;
4046 alu.src[1].chan = 0;
4047 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4048
4049 alu.last = 1;
4050 r = r600_bytecode_add_alu(ctx->bc, &alu);
4051 if (r)
4052 return r;
4053 }
4054 return 0;
4055 }
4056
4057 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
4058 {
4059 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4060 struct r600_bytecode_alu alu;
4061 int r;
4062 int id = tgsi_tex_get_src_gpr(ctx, 1);
4063
4064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4065 alu.op = ALU_OP1_MOV;
4066
4067 if (ctx->bc->chip_class >= EVERGREEN) {
4068 alu.src[0].sel = 512 + (id / 4);
4069 alu.src[0].chan = id % 4;
4070 } else {
4071 /* r600 we have them at channel 2 of the second dword */
4072 alu.src[0].sel = 512 + (id * 2) + 1;
4073 alu.src[0].chan = 1;
4074 }
4075 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4076 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4077 alu.last = 1;
4078 r = r600_bytecode_add_alu(ctx->bc, &alu);
4079 if (r)
4080 return r;
4081 return 0;
4082 }
4083
4084 static int tgsi_tex(struct r600_shader_ctx *ctx)
4085 {
4086 static float one_point_five = 1.5f;
4087 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4088 struct r600_bytecode_tex tex;
4089 struct r600_bytecode_alu alu;
4090 unsigned src_gpr;
4091 int r, i, j;
4092 int opcode;
4093 bool read_compressed_msaa = ctx->bc->msaa_texture_mode == MSAA_TEXTURE_COMPRESSED &&
4094 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4095 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
4096 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
4097 /* Texture fetch instructions can only use gprs as source.
4098 * Also they cannot negate the source or take the absolute value */
4099 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
4100 tgsi_tex_src_requires_loading(ctx, 0)) ||
4101 read_compressed_msaa;
4102 boolean src_loaded = FALSE;
4103 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
4104 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
4105 boolean has_txq_cube_array_z = false;
4106
4107 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
4108 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4109 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
4110 if (inst->Dst[0].Register.WriteMask & 4) {
4111 ctx->shader->has_txq_cube_array_z_comp = true;
4112 has_txq_cube_array_z = true;
4113 }
4114
4115 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
4116 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4117 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4118 sampler_src_reg = 2;
4119
4120 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4121
4122 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
4123 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
4124 ctx->shader->uses_tex_buffers = true;
4125 return r600_do_buffer_txq(ctx);
4126 }
4127 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4128 if (ctx->bc->chip_class < EVERGREEN)
4129 ctx->shader->uses_tex_buffers = true;
4130 return do_vtx_fetch_inst(ctx, src_requires_loading);
4131 }
4132 }
4133
4134 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4135 /* get offset values */
4136 if (inst->Texture.NumOffsets) {
4137 assert(inst->Texture.NumOffsets == 1);
4138
4139 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
4140 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
4141 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
4142 }
4143 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
4144 /* TGSI moves the sampler to src reg 3 for TXD */
4145 sampler_src_reg = 3;
4146
4147 for (i = 1; i < 3; i++) {
4148 /* set gradients h/v */
4149 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4150 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
4151 FETCH_OP_SET_GRADIENTS_V;
4152 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4153 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4154
4155 if (tgsi_tex_src_requires_loading(ctx, i)) {
4156 tex.src_gpr = r600_get_temp(ctx);
4157 tex.src_sel_x = 0;
4158 tex.src_sel_y = 1;
4159 tex.src_sel_z = 2;
4160 tex.src_sel_w = 3;
4161
4162 for (j = 0; j < 4; j++) {
4163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4164 alu.op = ALU_OP1_MOV;
4165 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
4166 alu.dst.sel = tex.src_gpr;
4167 alu.dst.chan = j;
4168 if (j == 3)
4169 alu.last = 1;
4170 alu.dst.write = 1;
4171 r = r600_bytecode_add_alu(ctx->bc, &alu);
4172 if (r)
4173 return r;
4174 }
4175
4176 } else {
4177 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
4178 tex.src_sel_x = ctx->src[i].swizzle[0];
4179 tex.src_sel_y = ctx->src[i].swizzle[1];
4180 tex.src_sel_z = ctx->src[i].swizzle[2];
4181 tex.src_sel_w = ctx->src[i].swizzle[3];
4182 tex.src_rel = ctx->src[i].rel;
4183 }
4184 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
4185 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4186 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
4187 tex.coord_type_x = 1;
4188 tex.coord_type_y = 1;
4189 tex.coord_type_z = 1;
4190 tex.coord_type_w = 1;
4191 }
4192 r = r600_bytecode_add_tex(ctx->bc, &tex);
4193 if (r)
4194 return r;
4195 }
4196 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
4197 int out_chan;
4198 /* Add perspective divide */
4199 if (ctx->bc->chip_class == CAYMAN) {
4200 out_chan = 2;
4201 for (i = 0; i < 3; i++) {
4202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4203 alu.op = ALU_OP1_RECIP_IEEE;
4204 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4205
4206 alu.dst.sel = ctx->temp_reg;
4207 alu.dst.chan = i;
4208 if (i == 2)
4209 alu.last = 1;
4210 if (out_chan == i)
4211 alu.dst.write = 1;
4212 r = r600_bytecode_add_alu(ctx->bc, &alu);
4213 if (r)
4214 return r;
4215 }
4216
4217 } else {
4218 out_chan = 3;
4219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4220 alu.op = ALU_OP1_RECIP_IEEE;
4221 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4222
4223 alu.dst.sel = ctx->temp_reg;
4224 alu.dst.chan = out_chan;
4225 alu.last = 1;
4226 alu.dst.write = 1;
4227 r = r600_bytecode_add_alu(ctx->bc, &alu);
4228 if (r)
4229 return r;
4230 }
4231
4232 for (i = 0; i < 3; i++) {
4233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4234 alu.op = ALU_OP2_MUL;
4235 alu.src[0].sel = ctx->temp_reg;
4236 alu.src[0].chan = out_chan;
4237 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4238 alu.dst.sel = ctx->temp_reg;
4239 alu.dst.chan = i;
4240 alu.dst.write = 1;
4241 r = r600_bytecode_add_alu(ctx->bc, &alu);
4242 if (r)
4243 return r;
4244 }
4245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4246 alu.op = ALU_OP1_MOV;
4247 alu.src[0].sel = V_SQ_ALU_SRC_1;
4248 alu.src[0].chan = 0;
4249 alu.dst.sel = ctx->temp_reg;
4250 alu.dst.chan = 3;
4251 alu.last = 1;
4252 alu.dst.write = 1;
4253 r = r600_bytecode_add_alu(ctx->bc, &alu);
4254 if (r)
4255 return r;
4256 src_loaded = TRUE;
4257 src_gpr = ctx->temp_reg;
4258 }
4259
4260 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4261 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4262 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4263 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4264 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
4265 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4266
4267 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
4268 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
4269
4270 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
4271 for (i = 0; i < 4; i++) {
4272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4273 alu.op = ALU_OP2_CUBE;
4274 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4275 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4276 alu.dst.sel = ctx->temp_reg;
4277 alu.dst.chan = i;
4278 if (i == 3)
4279 alu.last = 1;
4280 alu.dst.write = 1;
4281 r = r600_bytecode_add_alu(ctx->bc, &alu);
4282 if (r)
4283 return r;
4284 }
4285
4286 /* tmp1.z = RCP_e(|tmp1.z|) */
4287 if (ctx->bc->chip_class == CAYMAN) {
4288 for (i = 0; i < 3; i++) {
4289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4290 alu.op = ALU_OP1_RECIP_IEEE;
4291 alu.src[0].sel = ctx->temp_reg;
4292 alu.src[0].chan = 2;
4293 alu.src[0].abs = 1;
4294 alu.dst.sel = ctx->temp_reg;
4295 alu.dst.chan = i;
4296 if (i == 2)
4297 alu.dst.write = 1;
4298 if (i == 2)
4299 alu.last = 1;
4300 r = r600_bytecode_add_alu(ctx->bc, &alu);
4301 if (r)
4302 return r;
4303 }
4304 } else {
4305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4306 alu.op = ALU_OP1_RECIP_IEEE;
4307 alu.src[0].sel = ctx->temp_reg;
4308 alu.src[0].chan = 2;
4309 alu.src[0].abs = 1;
4310 alu.dst.sel = ctx->temp_reg;
4311 alu.dst.chan = 2;
4312 alu.dst.write = 1;
4313 alu.last = 1;
4314 r = r600_bytecode_add_alu(ctx->bc, &alu);
4315 if (r)
4316 return r;
4317 }
4318
4319 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4320 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4321 * muladd has no writemask, have to use another temp
4322 */
4323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4324 alu.op = ALU_OP3_MULADD;
4325 alu.is_op3 = 1;
4326
4327 alu.src[0].sel = ctx->temp_reg;
4328 alu.src[0].chan = 0;
4329 alu.src[1].sel = ctx->temp_reg;
4330 alu.src[1].chan = 2;
4331
4332 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4333 alu.src[2].chan = 0;
4334 alu.src[2].value = *(uint32_t *)&one_point_five;
4335
4336 alu.dst.sel = ctx->temp_reg;
4337 alu.dst.chan = 0;
4338 alu.dst.write = 1;
4339
4340 r = r600_bytecode_add_alu(ctx->bc, &alu);
4341 if (r)
4342 return r;
4343
4344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4345 alu.op = ALU_OP3_MULADD;
4346 alu.is_op3 = 1;
4347
4348 alu.src[0].sel = ctx->temp_reg;
4349 alu.src[0].chan = 1;
4350 alu.src[1].sel = ctx->temp_reg;
4351 alu.src[1].chan = 2;
4352
4353 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4354 alu.src[2].chan = 0;
4355 alu.src[2].value = *(uint32_t *)&one_point_five;
4356
4357 alu.dst.sel = ctx->temp_reg;
4358 alu.dst.chan = 1;
4359 alu.dst.write = 1;
4360
4361 alu.last = 1;
4362 r = r600_bytecode_add_alu(ctx->bc, &alu);
4363 if (r)
4364 return r;
4365 /* write initial compare value into Z component
4366 - W src 0 for shadow cube
4367 - X src 1 for shadow cube array */
4368 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4369 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4370 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4371 alu.op = ALU_OP1_MOV;
4372 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4373 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4374 else
4375 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4376 alu.dst.sel = ctx->temp_reg;
4377 alu.dst.chan = 2;
4378 alu.dst.write = 1;
4379 alu.last = 1;
4380 r = r600_bytecode_add_alu(ctx->bc, &alu);
4381 if (r)
4382 return r;
4383 }
4384
4385 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4386 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4387 if (ctx->bc->chip_class >= EVERGREEN) {
4388 int mytmp = r600_get_temp(ctx);
4389 static const float eight = 8.0f;
4390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4391 alu.op = ALU_OP1_MOV;
4392 alu.src[0].sel = ctx->temp_reg;
4393 alu.src[0].chan = 3;
4394 alu.dst.sel = mytmp;
4395 alu.dst.chan = 0;
4396 alu.dst.write = 1;
4397 alu.last = 1;
4398 r = r600_bytecode_add_alu(ctx->bc, &alu);
4399 if (r)
4400 return r;
4401
4402 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4404 alu.op = ALU_OP3_MULADD;
4405 alu.is_op3 = 1;
4406 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4407 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4408 alu.src[1].chan = 0;
4409 alu.src[1].value = *(uint32_t *)&eight;
4410 alu.src[2].sel = mytmp;
4411 alu.src[2].chan = 0;
4412 alu.dst.sel = ctx->temp_reg;
4413 alu.dst.chan = 3;
4414 alu.dst.write = 1;
4415 alu.last = 1;
4416 r = r600_bytecode_add_alu(ctx->bc, &alu);
4417 if (r)
4418 return r;
4419 } else if (ctx->bc->chip_class < EVERGREEN) {
4420 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4421 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4422 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4423 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4424 tex.src_gpr = r600_get_temp(ctx);
4425 tex.src_sel_x = 0;
4426 tex.src_sel_y = 0;
4427 tex.src_sel_z = 0;
4428 tex.src_sel_w = 0;
4429 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4430 tex.coord_type_x = 1;
4431 tex.coord_type_y = 1;
4432 tex.coord_type_z = 1;
4433 tex.coord_type_w = 1;
4434 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4435 alu.op = ALU_OP1_MOV;
4436 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4437 alu.dst.sel = tex.src_gpr;
4438 alu.dst.chan = 0;
4439 alu.last = 1;
4440 alu.dst.write = 1;
4441 r = r600_bytecode_add_alu(ctx->bc, &alu);
4442 if (r)
4443 return r;
4444
4445 r = r600_bytecode_add_tex(ctx->bc, &tex);
4446 if (r)
4447 return r;
4448 }
4449
4450 }
4451
4452 /* for cube forms of lod and bias we need to route things */
4453 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4454 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4455 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4456 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4457 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4458 alu.op = ALU_OP1_MOV;
4459 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4460 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4461 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4462 else
4463 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4464 alu.dst.sel = ctx->temp_reg;
4465 alu.dst.chan = 2;
4466 alu.last = 1;
4467 alu.dst.write = 1;
4468 r = r600_bytecode_add_alu(ctx->bc, &alu);
4469 if (r)
4470 return r;
4471 }
4472
4473 src_loaded = TRUE;
4474 src_gpr = ctx->temp_reg;
4475 }
4476
4477 if (src_requires_loading && !src_loaded) {
4478 for (i = 0; i < 4; i++) {
4479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4480 alu.op = ALU_OP1_MOV;
4481 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4482 alu.dst.sel = ctx->temp_reg;
4483 alu.dst.chan = i;
4484 if (i == 3)
4485 alu.last = 1;
4486 alu.dst.write = 1;
4487 r = r600_bytecode_add_alu(ctx->bc, &alu);
4488 if (r)
4489 return r;
4490 }
4491 src_loaded = TRUE;
4492 src_gpr = ctx->temp_reg;
4493 }
4494
4495 /* Obtain the sample index for reading a compressed MSAA color texture.
4496 * To read the FMASK, we use the ldfptr instruction, which tells us
4497 * where the samples are stored.
4498 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4499 * which is the identity mapping. Each nibble says which physical sample
4500 * should be fetched to get that sample.
4501 *
4502 * Assume src.z contains the sample index. It should be modified like this:
4503 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4504 * Then fetch the texel with src.
4505 */
4506 if (read_compressed_msaa) {
4507 unsigned sample_chan = 3;
4508 unsigned temp = r600_get_temp(ctx);
4509 assert(src_loaded);
4510
4511 /* temp.w = ldfptr() */
4512 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4513 tex.op = FETCH_OP_LD;
4514 tex.inst_mod = 1; /* to indicate this is ldfptr */
4515 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4516 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4517 tex.src_gpr = src_gpr;
4518 tex.dst_gpr = temp;
4519 tex.dst_sel_x = 7; /* mask out these components */
4520 tex.dst_sel_y = 7;
4521 tex.dst_sel_z = 7;
4522 tex.dst_sel_w = 0; /* store X */
4523 tex.src_sel_x = 0;
4524 tex.src_sel_y = 1;
4525 tex.src_sel_z = 2;
4526 tex.src_sel_w = 3;
4527 tex.offset_x = offset_x;
4528 tex.offset_y = offset_y;
4529 tex.offset_z = offset_z;
4530 r = r600_bytecode_add_tex(ctx->bc, &tex);
4531 if (r)
4532 return r;
4533
4534 /* temp.x = sample_index*4 */
4535 if (ctx->bc->chip_class == CAYMAN) {
4536 for (i = 0 ; i < 4; i++) {
4537 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4538 alu.op = ALU_OP2_MULLO_INT;
4539 alu.src[0].sel = src_gpr;
4540 alu.src[0].chan = sample_chan;
4541 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4542 alu.src[1].value = 4;
4543 alu.dst.sel = temp;
4544 alu.dst.chan = i;
4545 alu.dst.write = i == 0;
4546 if (i == 3)
4547 alu.last = 1;
4548 r = r600_bytecode_add_alu(ctx->bc, &alu);
4549 if (r)
4550 return r;
4551 }
4552 } else {
4553 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4554 alu.op = ALU_OP2_MULLO_INT;
4555 alu.src[0].sel = src_gpr;
4556 alu.src[0].chan = sample_chan;
4557 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4558 alu.src[1].value = 4;
4559 alu.dst.sel = temp;
4560 alu.dst.chan = 0;
4561 alu.dst.write = 1;
4562 alu.last = 1;
4563 r = r600_bytecode_add_alu(ctx->bc, &alu);
4564 if (r)
4565 return r;
4566 }
4567
4568 /* sample_index = temp.w >> temp.x */
4569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4570 alu.op = ALU_OP2_LSHR_INT;
4571 alu.src[0].sel = temp;
4572 alu.src[0].chan = 3;
4573 alu.src[1].sel = temp;
4574 alu.src[1].chan = 0;
4575 alu.dst.sel = src_gpr;
4576 alu.dst.chan = sample_chan;
4577 alu.dst.write = 1;
4578 alu.last = 1;
4579 r = r600_bytecode_add_alu(ctx->bc, &alu);
4580 if (r)
4581 return r;
4582
4583 /* sample_index & 0xF */
4584 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4585 alu.op = ALU_OP2_AND_INT;
4586 alu.src[0].sel = src_gpr;
4587 alu.src[0].chan = sample_chan;
4588 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4589 alu.src[1].value = 0xF;
4590 alu.dst.sel = src_gpr;
4591 alu.dst.chan = sample_chan;
4592 alu.dst.write = 1;
4593 alu.last = 1;
4594 r = r600_bytecode_add_alu(ctx->bc, &alu);
4595 if (r)
4596 return r;
4597 #if 0
4598 /* visualize the FMASK */
4599 for (i = 0; i < 4; i++) {
4600 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4601 alu.op = ALU_OP1_INT_TO_FLT;
4602 alu.src[0].sel = src_gpr;
4603 alu.src[0].chan = sample_chan;
4604 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4605 alu.dst.chan = i;
4606 alu.dst.write = 1;
4607 alu.last = 1;
4608 r = r600_bytecode_add_alu(ctx->bc, &alu);
4609 if (r)
4610 return r;
4611 }
4612 return 0;
4613 #endif
4614 }
4615
4616 /* does this shader want a num layers from TXQ for a cube array? */
4617 if (has_txq_cube_array_z) {
4618 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4619
4620 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4621 alu.op = ALU_OP1_MOV;
4622
4623 alu.src[0].sel = 512 + (id / 4);
4624 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4625 alu.src[0].chan = id % 4;
4626 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4627 alu.last = 1;
4628 r = r600_bytecode_add_alu(ctx->bc, &alu);
4629 if (r)
4630 return r;
4631 /* disable writemask from texture instruction */
4632 inst->Dst[0].Register.WriteMask &= ~4;
4633 }
4634
4635 opcode = ctx->inst_info->op;
4636 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4637 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4638 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4639 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4640 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4641 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4642 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4643 switch (opcode) {
4644 case FETCH_OP_SAMPLE:
4645 opcode = FETCH_OP_SAMPLE_C;
4646 break;
4647 case FETCH_OP_SAMPLE_L:
4648 opcode = FETCH_OP_SAMPLE_C_L;
4649 break;
4650 case FETCH_OP_SAMPLE_LB:
4651 opcode = FETCH_OP_SAMPLE_C_LB;
4652 break;
4653 case FETCH_OP_SAMPLE_G:
4654 opcode = FETCH_OP_SAMPLE_C_G;
4655 break;
4656 }
4657 }
4658
4659 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4660 tex.op = opcode;
4661
4662 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4663 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4664 tex.src_gpr = src_gpr;
4665 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4666 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4667 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4668 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4669 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4670
4671 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4672 tex.src_sel_x = 4;
4673 tex.src_sel_y = 4;
4674 tex.src_sel_z = 4;
4675 tex.src_sel_w = 4;
4676 } else if (src_loaded) {
4677 tex.src_sel_x = 0;
4678 tex.src_sel_y = 1;
4679 tex.src_sel_z = 2;
4680 tex.src_sel_w = 3;
4681 } else {
4682 tex.src_sel_x = ctx->src[0].swizzle[0];
4683 tex.src_sel_y = ctx->src[0].swizzle[1];
4684 tex.src_sel_z = ctx->src[0].swizzle[2];
4685 tex.src_sel_w = ctx->src[0].swizzle[3];
4686 tex.src_rel = ctx->src[0].rel;
4687 }
4688
4689 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4690 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4691 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4692 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4693 tex.src_sel_x = 1;
4694 tex.src_sel_y = 0;
4695 tex.src_sel_z = 3;
4696 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4697 }
4698
4699 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4700 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4701 tex.coord_type_x = 1;
4702 tex.coord_type_y = 1;
4703 }
4704 tex.coord_type_z = 1;
4705 tex.coord_type_w = 1;
4706
4707 tex.offset_x = offset_x;
4708 tex.offset_y = offset_y;
4709 tex.offset_z = offset_z;
4710
4711 /* Put the depth for comparison in W.
4712 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4713 * Some instructions expect the depth in Z. */
4714 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4715 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4716 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4717 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4718 opcode != FETCH_OP_SAMPLE_C_L &&
4719 opcode != FETCH_OP_SAMPLE_C_LB) {
4720 tex.src_sel_w = tex.src_sel_z;
4721 }
4722
4723 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4724 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4725 if (opcode == FETCH_OP_SAMPLE_C_L ||
4726 opcode == FETCH_OP_SAMPLE_C_LB) {
4727 /* the array index is read from Y */
4728 tex.coord_type_y = 0;
4729 } else {
4730 /* the array index is read from Z */
4731 tex.coord_type_z = 0;
4732 tex.src_sel_z = tex.src_sel_y;
4733 }
4734 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4735 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4736 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4737 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4738 (ctx->bc->chip_class >= EVERGREEN)))
4739 /* the array index is read from Z */
4740 tex.coord_type_z = 0;
4741
4742 r = r600_bytecode_add_tex(ctx->bc, &tex);
4743 if (r)
4744 return r;
4745
4746 /* add shadow ambient support - gallium doesn't do it yet */
4747 return 0;
4748 }
4749
4750 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4751 {
4752 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4753 struct r600_bytecode_alu alu;
4754 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4755 unsigned i;
4756 int r;
4757
4758 /* optimize if it's just an equal balance */
4759 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4760 for (i = 0; i < lasti + 1; i++) {
4761 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4762 continue;
4763
4764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4765 alu.op = ALU_OP2_ADD;
4766 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4767 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4768 alu.omod = 3;
4769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4770 alu.dst.chan = i;
4771 if (i == lasti) {
4772 alu.last = 1;
4773 }
4774 r = r600_bytecode_add_alu(ctx->bc, &alu);
4775 if (r)
4776 return r;
4777 }
4778 return 0;
4779 }
4780
4781 /* 1 - src0 */
4782 for (i = 0; i < lasti + 1; i++) {
4783 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4784 continue;
4785
4786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4787 alu.op = ALU_OP2_ADD;
4788 alu.src[0].sel = V_SQ_ALU_SRC_1;
4789 alu.src[0].chan = 0;
4790 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4791 r600_bytecode_src_toggle_neg(&alu.src[1]);
4792 alu.dst.sel = ctx->temp_reg;
4793 alu.dst.chan = i;
4794 if (i == lasti) {
4795 alu.last = 1;
4796 }
4797 alu.dst.write = 1;
4798 r = r600_bytecode_add_alu(ctx->bc, &alu);
4799 if (r)
4800 return r;
4801 }
4802
4803 /* (1 - src0) * src2 */
4804 for (i = 0; i < lasti + 1; i++) {
4805 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4806 continue;
4807
4808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4809 alu.op = ALU_OP2_MUL;
4810 alu.src[0].sel = ctx->temp_reg;
4811 alu.src[0].chan = i;
4812 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4813 alu.dst.sel = ctx->temp_reg;
4814 alu.dst.chan = i;
4815 if (i == lasti) {
4816 alu.last = 1;
4817 }
4818 alu.dst.write = 1;
4819 r = r600_bytecode_add_alu(ctx->bc, &alu);
4820 if (r)
4821 return r;
4822 }
4823
4824 /* src0 * src1 + (1 - src0) * src2 */
4825 for (i = 0; i < lasti + 1; i++) {
4826 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4827 continue;
4828
4829 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4830 alu.op = ALU_OP3_MULADD;
4831 alu.is_op3 = 1;
4832 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4833 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4834 alu.src[2].sel = ctx->temp_reg;
4835 alu.src[2].chan = i;
4836
4837 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4838 alu.dst.chan = i;
4839 if (i == lasti) {
4840 alu.last = 1;
4841 }
4842 r = r600_bytecode_add_alu(ctx->bc, &alu);
4843 if (r)
4844 return r;
4845 }
4846 return 0;
4847 }
4848
4849 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4850 {
4851 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4852 struct r600_bytecode_alu alu;
4853 int i, r;
4854 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4855
4856 for (i = 0; i < lasti + 1; i++) {
4857 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4858 continue;
4859
4860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4861 alu.op = ALU_OP3_CNDGE;
4862 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4863 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4864 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4865 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4866 alu.dst.chan = i;
4867 alu.dst.write = 1;
4868 alu.is_op3 = 1;
4869 if (i == lasti)
4870 alu.last = 1;
4871 r = r600_bytecode_add_alu(ctx->bc, &alu);
4872 if (r)
4873 return r;
4874 }
4875 return 0;
4876 }
4877
4878 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4879 {
4880 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4881 struct r600_bytecode_alu alu;
4882 int i, r;
4883 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4884
4885 for (i = 0; i < lasti + 1; i++) {
4886 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4887 continue;
4888
4889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4890 alu.op = ALU_OP3_CNDGE_INT;
4891 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4892 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4893 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4894 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4895 alu.dst.chan = i;
4896 alu.dst.write = 1;
4897 alu.is_op3 = 1;
4898 if (i == lasti)
4899 alu.last = 1;
4900 r = r600_bytecode_add_alu(ctx->bc, &alu);
4901 if (r)
4902 return r;
4903 }
4904 return 0;
4905 }
4906
4907 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4908 {
4909 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4910 static const unsigned int src0_swizzle[] = {2, 0, 1};
4911 static const unsigned int src1_swizzle[] = {1, 2, 0};
4912 struct r600_bytecode_alu alu;
4913 uint32_t use_temp = 0;
4914 int i, r;
4915
4916 if (inst->Dst[0].Register.WriteMask != 0xf)
4917 use_temp = 1;
4918
4919 for (i = 0; i < 4; i++) {
4920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4921 alu.op = ALU_OP2_MUL;
4922 if (i < 3) {
4923 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4924 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4925 } else {
4926 alu.src[0].sel = V_SQ_ALU_SRC_0;
4927 alu.src[0].chan = i;
4928 alu.src[1].sel = V_SQ_ALU_SRC_0;
4929 alu.src[1].chan = i;
4930 }
4931
4932 alu.dst.sel = ctx->temp_reg;
4933 alu.dst.chan = i;
4934 alu.dst.write = 1;
4935
4936 if (i == 3)
4937 alu.last = 1;
4938 r = r600_bytecode_add_alu(ctx->bc, &alu);
4939 if (r)
4940 return r;
4941 }
4942
4943 for (i = 0; i < 4; i++) {
4944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4945 alu.op = ALU_OP3_MULADD;
4946
4947 if (i < 3) {
4948 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4949 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4950 } else {
4951 alu.src[0].sel = V_SQ_ALU_SRC_0;
4952 alu.src[0].chan = i;
4953 alu.src[1].sel = V_SQ_ALU_SRC_0;
4954 alu.src[1].chan = i;
4955 }
4956
4957 alu.src[2].sel = ctx->temp_reg;
4958 alu.src[2].neg = 1;
4959 alu.src[2].chan = i;
4960
4961 if (use_temp)
4962 alu.dst.sel = ctx->temp_reg;
4963 else
4964 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4965 alu.dst.chan = i;
4966 alu.dst.write = 1;
4967 alu.is_op3 = 1;
4968 if (i == 3)
4969 alu.last = 1;
4970 r = r600_bytecode_add_alu(ctx->bc, &alu);
4971 if (r)
4972 return r;
4973 }
4974 if (use_temp)
4975 return tgsi_helper_copy(ctx, inst);
4976 return 0;
4977 }
4978
4979 static int tgsi_exp(struct r600_shader_ctx *ctx)
4980 {
4981 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4982 struct r600_bytecode_alu alu;
4983 int r;
4984 int i;
4985
4986 /* result.x = 2^floor(src); */
4987 if (inst->Dst[0].Register.WriteMask & 1) {
4988 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4989
4990 alu.op = ALU_OP1_FLOOR;
4991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4992
4993 alu.dst.sel = ctx->temp_reg;
4994 alu.dst.chan = 0;
4995 alu.dst.write = 1;
4996 alu.last = 1;
4997 r = r600_bytecode_add_alu(ctx->bc, &alu);
4998 if (r)
4999 return r;
5000
5001 if (ctx->bc->chip_class == CAYMAN) {
5002 for (i = 0; i < 3; i++) {
5003 alu.op = ALU_OP1_EXP_IEEE;
5004 alu.src[0].sel = ctx->temp_reg;
5005 alu.src[0].chan = 0;
5006
5007 alu.dst.sel = ctx->temp_reg;
5008 alu.dst.chan = i;
5009 alu.dst.write = i == 0;
5010 alu.last = i == 2;
5011 r = r600_bytecode_add_alu(ctx->bc, &alu);
5012 if (r)
5013 return r;
5014 }
5015 } else {
5016 alu.op = ALU_OP1_EXP_IEEE;
5017 alu.src[0].sel = ctx->temp_reg;
5018 alu.src[0].chan = 0;
5019
5020 alu.dst.sel = ctx->temp_reg;
5021 alu.dst.chan = 0;
5022 alu.dst.write = 1;
5023 alu.last = 1;
5024 r = r600_bytecode_add_alu(ctx->bc, &alu);
5025 if (r)
5026 return r;
5027 }
5028 }
5029
5030 /* result.y = tmp - floor(tmp); */
5031 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5033
5034 alu.op = ALU_OP1_FRACT;
5035 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5036
5037 alu.dst.sel = ctx->temp_reg;
5038 #if 0
5039 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5040 if (r)
5041 return r;
5042 #endif
5043 alu.dst.write = 1;
5044 alu.dst.chan = 1;
5045
5046 alu.last = 1;
5047
5048 r = r600_bytecode_add_alu(ctx->bc, &alu);
5049 if (r)
5050 return r;
5051 }
5052
5053 /* result.z = RoughApprox2ToX(tmp);*/
5054 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
5055 if (ctx->bc->chip_class == CAYMAN) {
5056 for (i = 0; i < 3; i++) {
5057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5058 alu.op = ALU_OP1_EXP_IEEE;
5059 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5060
5061 alu.dst.sel = ctx->temp_reg;
5062 alu.dst.chan = i;
5063 if (i == 2) {
5064 alu.dst.write = 1;
5065 alu.last = 1;
5066 }
5067
5068 r = r600_bytecode_add_alu(ctx->bc, &alu);
5069 if (r)
5070 return r;
5071 }
5072 } else {
5073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5074 alu.op = ALU_OP1_EXP_IEEE;
5075 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5076
5077 alu.dst.sel = ctx->temp_reg;
5078 alu.dst.write = 1;
5079 alu.dst.chan = 2;
5080
5081 alu.last = 1;
5082
5083 r = r600_bytecode_add_alu(ctx->bc, &alu);
5084 if (r)
5085 return r;
5086 }
5087 }
5088
5089 /* result.w = 1.0;*/
5090 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
5091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5092
5093 alu.op = ALU_OP1_MOV;
5094 alu.src[0].sel = V_SQ_ALU_SRC_1;
5095 alu.src[0].chan = 0;
5096
5097 alu.dst.sel = ctx->temp_reg;
5098 alu.dst.chan = 3;
5099 alu.dst.write = 1;
5100 alu.last = 1;
5101 r = r600_bytecode_add_alu(ctx->bc, &alu);
5102 if (r)
5103 return r;
5104 }
5105 return tgsi_helper_copy(ctx, inst);
5106 }
5107
5108 static int tgsi_log(struct r600_shader_ctx *ctx)
5109 {
5110 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5111 struct r600_bytecode_alu alu;
5112 int r;
5113 int i;
5114
5115 /* result.x = floor(log2(|src|)); */
5116 if (inst->Dst[0].Register.WriteMask & 1) {
5117 if (ctx->bc->chip_class == CAYMAN) {
5118 for (i = 0; i < 3; i++) {
5119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5120
5121 alu.op = ALU_OP1_LOG_IEEE;
5122 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5123 r600_bytecode_src_set_abs(&alu.src[0]);
5124
5125 alu.dst.sel = ctx->temp_reg;
5126 alu.dst.chan = i;
5127 if (i == 0)
5128 alu.dst.write = 1;
5129 if (i == 2)
5130 alu.last = 1;
5131 r = r600_bytecode_add_alu(ctx->bc, &alu);
5132 if (r)
5133 return r;
5134 }
5135
5136 } else {
5137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5138
5139 alu.op = ALU_OP1_LOG_IEEE;
5140 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5141 r600_bytecode_src_set_abs(&alu.src[0]);
5142
5143 alu.dst.sel = ctx->temp_reg;
5144 alu.dst.chan = 0;
5145 alu.dst.write = 1;
5146 alu.last = 1;
5147 r = r600_bytecode_add_alu(ctx->bc, &alu);
5148 if (r)
5149 return r;
5150 }
5151
5152 alu.op = ALU_OP1_FLOOR;
5153 alu.src[0].sel = ctx->temp_reg;
5154 alu.src[0].chan = 0;
5155
5156 alu.dst.sel = ctx->temp_reg;
5157 alu.dst.chan = 0;
5158 alu.dst.write = 1;
5159 alu.last = 1;
5160
5161 r = r600_bytecode_add_alu(ctx->bc, &alu);
5162 if (r)
5163 return r;
5164 }
5165
5166 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
5167 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5168
5169 if (ctx->bc->chip_class == CAYMAN) {
5170 for (i = 0; i < 3; i++) {
5171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5172
5173 alu.op = ALU_OP1_LOG_IEEE;
5174 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5175 r600_bytecode_src_set_abs(&alu.src[0]);
5176
5177 alu.dst.sel = ctx->temp_reg;
5178 alu.dst.chan = i;
5179 if (i == 1)
5180 alu.dst.write = 1;
5181 if (i == 2)
5182 alu.last = 1;
5183
5184 r = r600_bytecode_add_alu(ctx->bc, &alu);
5185 if (r)
5186 return r;
5187 }
5188 } else {
5189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5190
5191 alu.op = ALU_OP1_LOG_IEEE;
5192 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5193 r600_bytecode_src_set_abs(&alu.src[0]);
5194
5195 alu.dst.sel = ctx->temp_reg;
5196 alu.dst.chan = 1;
5197 alu.dst.write = 1;
5198 alu.last = 1;
5199
5200 r = r600_bytecode_add_alu(ctx->bc, &alu);
5201 if (r)
5202 return r;
5203 }
5204
5205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5206
5207 alu.op = ALU_OP1_FLOOR;
5208 alu.src[0].sel = ctx->temp_reg;
5209 alu.src[0].chan = 1;
5210
5211 alu.dst.sel = ctx->temp_reg;
5212 alu.dst.chan = 1;
5213 alu.dst.write = 1;
5214 alu.last = 1;
5215
5216 r = r600_bytecode_add_alu(ctx->bc, &alu);
5217 if (r)
5218 return r;
5219
5220 if (ctx->bc->chip_class == CAYMAN) {
5221 for (i = 0; i < 3; i++) {
5222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5223 alu.op = ALU_OP1_EXP_IEEE;
5224 alu.src[0].sel = ctx->temp_reg;
5225 alu.src[0].chan = 1;
5226
5227 alu.dst.sel = ctx->temp_reg;
5228 alu.dst.chan = i;
5229 if (i == 1)
5230 alu.dst.write = 1;
5231 if (i == 2)
5232 alu.last = 1;
5233
5234 r = r600_bytecode_add_alu(ctx->bc, &alu);
5235 if (r)
5236 return r;
5237 }
5238 } else {
5239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5240 alu.op = ALU_OP1_EXP_IEEE;
5241 alu.src[0].sel = ctx->temp_reg;
5242 alu.src[0].chan = 1;
5243
5244 alu.dst.sel = ctx->temp_reg;
5245 alu.dst.chan = 1;
5246 alu.dst.write = 1;
5247 alu.last = 1;
5248
5249 r = r600_bytecode_add_alu(ctx->bc, &alu);
5250 if (r)
5251 return r;
5252 }
5253
5254 if (ctx->bc->chip_class == CAYMAN) {
5255 for (i = 0; i < 3; i++) {
5256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5257 alu.op = ALU_OP1_RECIP_IEEE;
5258 alu.src[0].sel = ctx->temp_reg;
5259 alu.src[0].chan = 1;
5260
5261 alu.dst.sel = ctx->temp_reg;
5262 alu.dst.chan = i;
5263 if (i == 1)
5264 alu.dst.write = 1;
5265 if (i == 2)
5266 alu.last = 1;
5267
5268 r = r600_bytecode_add_alu(ctx->bc, &alu);
5269 if (r)
5270 return r;
5271 }
5272 } else {
5273 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5274 alu.op = ALU_OP1_RECIP_IEEE;
5275 alu.src[0].sel = ctx->temp_reg;
5276 alu.src[0].chan = 1;
5277
5278 alu.dst.sel = ctx->temp_reg;
5279 alu.dst.chan = 1;
5280 alu.dst.write = 1;
5281 alu.last = 1;
5282
5283 r = r600_bytecode_add_alu(ctx->bc, &alu);
5284 if (r)
5285 return r;
5286 }
5287
5288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5289
5290 alu.op = ALU_OP2_MUL;
5291
5292 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5293 r600_bytecode_src_set_abs(&alu.src[0]);
5294
5295 alu.src[1].sel = ctx->temp_reg;
5296 alu.src[1].chan = 1;
5297
5298 alu.dst.sel = ctx->temp_reg;
5299 alu.dst.chan = 1;
5300 alu.dst.write = 1;
5301 alu.last = 1;
5302
5303 r = r600_bytecode_add_alu(ctx->bc, &alu);
5304 if (r)
5305 return r;
5306 }
5307
5308 /* result.z = log2(|src|);*/
5309 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5310 if (ctx->bc->chip_class == CAYMAN) {
5311 for (i = 0; i < 3; i++) {
5312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5313
5314 alu.op = ALU_OP1_LOG_IEEE;
5315 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5316 r600_bytecode_src_set_abs(&alu.src[0]);
5317
5318 alu.dst.sel = ctx->temp_reg;
5319 if (i == 2)
5320 alu.dst.write = 1;
5321 alu.dst.chan = i;
5322 if (i == 2)
5323 alu.last = 1;
5324
5325 r = r600_bytecode_add_alu(ctx->bc, &alu);
5326 if (r)
5327 return r;
5328 }
5329 } else {
5330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5331
5332 alu.op = ALU_OP1_LOG_IEEE;
5333 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5334 r600_bytecode_src_set_abs(&alu.src[0]);
5335
5336 alu.dst.sel = ctx->temp_reg;
5337 alu.dst.write = 1;
5338 alu.dst.chan = 2;
5339 alu.last = 1;
5340
5341 r = r600_bytecode_add_alu(ctx->bc, &alu);
5342 if (r)
5343 return r;
5344 }
5345 }
5346
5347 /* result.w = 1.0; */
5348 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5349 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5350
5351 alu.op = ALU_OP1_MOV;
5352 alu.src[0].sel = V_SQ_ALU_SRC_1;
5353 alu.src[0].chan = 0;
5354
5355 alu.dst.sel = ctx->temp_reg;
5356 alu.dst.chan = 3;
5357 alu.dst.write = 1;
5358 alu.last = 1;
5359
5360 r = r600_bytecode_add_alu(ctx->bc, &alu);
5361 if (r)
5362 return r;
5363 }
5364
5365 return tgsi_helper_copy(ctx, inst);
5366 }
5367
5368 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5369 {
5370 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5371 struct r600_bytecode_alu alu;
5372 int r;
5373
5374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5375
5376 switch (inst->Instruction.Opcode) {
5377 case TGSI_OPCODE_ARL:
5378 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5379 break;
5380 case TGSI_OPCODE_ARR:
5381 alu.op = ALU_OP1_FLT_TO_INT;
5382 break;
5383 case TGSI_OPCODE_UARL:
5384 alu.op = ALU_OP1_MOV;
5385 break;
5386 default:
5387 assert(0);
5388 return -1;
5389 }
5390
5391 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5392 alu.last = 1;
5393 alu.dst.sel = ctx->bc->ar_reg;
5394 alu.dst.write = 1;
5395 r = r600_bytecode_add_alu(ctx->bc, &alu);
5396 if (r)
5397 return r;
5398
5399 ctx->bc->ar_loaded = 0;
5400 return 0;
5401 }
5402 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5403 {
5404 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5405 struct r600_bytecode_alu alu;
5406 int r;
5407
5408 switch (inst->Instruction.Opcode) {
5409 case TGSI_OPCODE_ARL:
5410 memset(&alu, 0, sizeof(alu));
5411 alu.op = ALU_OP1_FLOOR;
5412 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5413 alu.dst.sel = ctx->bc->ar_reg;
5414 alu.dst.write = 1;
5415 alu.last = 1;
5416
5417 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5418 return r;
5419
5420 memset(&alu, 0, sizeof(alu));
5421 alu.op = ALU_OP1_FLT_TO_INT;
5422 alu.src[0].sel = ctx->bc->ar_reg;
5423 alu.dst.sel = ctx->bc->ar_reg;
5424 alu.dst.write = 1;
5425 alu.last = 1;
5426
5427 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5428 return r;
5429 break;
5430 case TGSI_OPCODE_ARR:
5431 memset(&alu, 0, sizeof(alu));
5432 alu.op = ALU_OP1_FLT_TO_INT;
5433 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5434 alu.dst.sel = ctx->bc->ar_reg;
5435 alu.dst.write = 1;
5436 alu.last = 1;
5437
5438 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5439 return r;
5440 break;
5441 case TGSI_OPCODE_UARL:
5442 memset(&alu, 0, sizeof(alu));
5443 alu.op = ALU_OP1_MOV;
5444 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5445 alu.dst.sel = ctx->bc->ar_reg;
5446 alu.dst.write = 1;
5447 alu.last = 1;
5448
5449 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5450 return r;
5451 break;
5452 default:
5453 assert(0);
5454 return -1;
5455 }
5456
5457 ctx->bc->ar_loaded = 0;
5458 return 0;
5459 }
5460
5461 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5462 {
5463 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5464 struct r600_bytecode_alu alu;
5465 int i, r = 0;
5466
5467 for (i = 0; i < 4; i++) {
5468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5469
5470 alu.op = ALU_OP2_MUL;
5471 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5472
5473 if (i == 0 || i == 3) {
5474 alu.src[0].sel = V_SQ_ALU_SRC_1;
5475 } else {
5476 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5477 }
5478
5479 if (i == 0 || i == 2) {
5480 alu.src[1].sel = V_SQ_ALU_SRC_1;
5481 } else {
5482 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5483 }
5484 if (i == 3)
5485 alu.last = 1;
5486 r = r600_bytecode_add_alu(ctx->bc, &alu);
5487 if (r)
5488 return r;
5489 }
5490 return 0;
5491 }
5492
5493 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5494 {
5495 struct r600_bytecode_alu alu;
5496 int r;
5497
5498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5499 alu.op = opcode;
5500 alu.execute_mask = 1;
5501 alu.update_pred = 1;
5502
5503 alu.dst.sel = ctx->temp_reg;
5504 alu.dst.write = 1;
5505 alu.dst.chan = 0;
5506
5507 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5508 alu.src[1].sel = V_SQ_ALU_SRC_0;
5509 alu.src[1].chan = 0;
5510
5511 alu.last = 1;
5512
5513 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5514 if (r)
5515 return r;
5516 return 0;
5517 }
5518
5519 static int pops(struct r600_shader_ctx *ctx, int pops)
5520 {
5521 unsigned force_pop = ctx->bc->force_add_cf;
5522
5523 if (!force_pop) {
5524 int alu_pop = 3;
5525 if (ctx->bc->cf_last) {
5526 if (ctx->bc->cf_last->op == CF_OP_ALU)
5527 alu_pop = 0;
5528 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5529 alu_pop = 1;
5530 }
5531 alu_pop += pops;
5532 if (alu_pop == 1) {
5533 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5534 ctx->bc->force_add_cf = 1;
5535 } else if (alu_pop == 2) {
5536 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5537 ctx->bc->force_add_cf = 1;
5538 } else {
5539 force_pop = 1;
5540 }
5541 }
5542
5543 if (force_pop) {
5544 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5545 ctx->bc->cf_last->pop_count = pops;
5546 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5547 }
5548
5549 return 0;
5550 }
5551
5552 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5553 unsigned reason)
5554 {
5555 struct r600_stack_info *stack = &ctx->bc->stack;
5556 unsigned elements, entries;
5557
5558 unsigned entry_size = stack->entry_size;
5559
5560 elements = (stack->loop + stack->push_wqm ) * entry_size;
5561 elements += stack->push;
5562
5563 switch (ctx->bc->chip_class) {
5564 case R600:
5565 case R700:
5566 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5567 * the stack must be reserved to hold the current active/continue
5568 * masks */
5569 if (reason == FC_PUSH_VPM) {
5570 elements += 2;
5571 }
5572 break;
5573
5574 case CAYMAN:
5575 /* r9xx: any stack operation on empty stack consumes 2 additional
5576 * elements */
5577 elements += 2;
5578
5579 /* fallthrough */
5580 /* FIXME: do the two elements added above cover the cases for the
5581 * r8xx+ below? */
5582
5583 case EVERGREEN:
5584 /* r8xx+: 2 extra elements are not always required, but one extra
5585 * element must be added for each of the following cases:
5586 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5587 * stack usage.
5588 * (Currently we don't use ALU_ELSE_AFTER.)
5589 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5590 * PUSH instruction executed.
5591 *
5592 * NOTE: it seems we also need to reserve additional element in some
5593 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5594 * then STACK_SIZE should be 2 instead of 1 */
5595 if (reason == FC_PUSH_VPM) {
5596 elements += 1;
5597 }
5598 break;
5599
5600 default:
5601 assert(0);
5602 break;
5603 }
5604
5605 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5606 * for all chips, so we use 4 in the final formula, not the real entry_size
5607 * for the chip */
5608 entry_size = 4;
5609
5610 entries = (elements + (entry_size - 1)) / entry_size;
5611
5612 if (entries > stack->max_entries)
5613 stack->max_entries = entries;
5614 }
5615
5616 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5617 {
5618 switch(reason) {
5619 case FC_PUSH_VPM:
5620 --ctx->bc->stack.push;
5621 assert(ctx->bc->stack.push >= 0);
5622 break;
5623 case FC_PUSH_WQM:
5624 --ctx->bc->stack.push_wqm;
5625 assert(ctx->bc->stack.push_wqm >= 0);
5626 break;
5627 case FC_LOOP:
5628 --ctx->bc->stack.loop;
5629 assert(ctx->bc->stack.loop >= 0);
5630 break;
5631 default:
5632 assert(0);
5633 break;
5634 }
5635 }
5636
5637 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5638 {
5639 switch (reason) {
5640 case FC_PUSH_VPM:
5641 ++ctx->bc->stack.push;
5642 break;
5643 case FC_PUSH_WQM:
5644 ++ctx->bc->stack.push_wqm;
5645 case FC_LOOP:
5646 ++ctx->bc->stack.loop;
5647 break;
5648 default:
5649 assert(0);
5650 }
5651
5652 callstack_update_max_depth(ctx, reason);
5653 }
5654
5655 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5656 {
5657 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5658
5659 sp->mid = realloc((void *)sp->mid,
5660 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5661 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5662 sp->num_mid++;
5663 }
5664
5665 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5666 {
5667 ctx->bc->fc_sp++;
5668 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5669 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5670 }
5671
5672 static void fc_poplevel(struct r600_shader_ctx *ctx)
5673 {
5674 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5675 free(sp->mid);
5676 sp->mid = NULL;
5677 sp->num_mid = 0;
5678 sp->start = NULL;
5679 sp->type = 0;
5680 ctx->bc->fc_sp--;
5681 }
5682
5683 #if 0
5684 static int emit_return(struct r600_shader_ctx *ctx)
5685 {
5686 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5687 return 0;
5688 }
5689
5690 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5691 {
5692
5693 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5694 ctx->bc->cf_last->pop_count = pops;
5695 /* XXX work out offset */
5696 return 0;
5697 }
5698
5699 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5700 {
5701 return 0;
5702 }
5703
5704 static void emit_testflag(struct r600_shader_ctx *ctx)
5705 {
5706
5707 }
5708
5709 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5710 {
5711 emit_testflag(ctx);
5712 emit_jump_to_offset(ctx, 1, 4);
5713 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5714 pops(ctx, ifidx + 1);
5715 emit_return(ctx);
5716 }
5717
5718 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5719 {
5720 emit_testflag(ctx);
5721
5722 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5723 ctx->bc->cf_last->pop_count = 1;
5724
5725 fc_set_mid(ctx, fc_sp);
5726
5727 pops(ctx, 1);
5728 }
5729 #endif
5730
5731 static int tgsi_if(struct r600_shader_ctx *ctx)
5732 {
5733 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5734
5735 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5736 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5737 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5738 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5739 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5740 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5741 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5742 alu_type = CF_OP_ALU;
5743 }
5744
5745 emit_logic_pred(ctx, ALU_OP2_PRED_SETNE_INT, alu_type);
5746
5747 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5748
5749 fc_pushlevel(ctx, FC_IF);
5750
5751 callstack_push(ctx, FC_PUSH_VPM);
5752 return 0;
5753 }
5754
5755 static int tgsi_else(struct r600_shader_ctx *ctx)
5756 {
5757 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5758 ctx->bc->cf_last->pop_count = 1;
5759
5760 fc_set_mid(ctx, ctx->bc->fc_sp);
5761 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5762 return 0;
5763 }
5764
5765 static int tgsi_endif(struct r600_shader_ctx *ctx)
5766 {
5767 pops(ctx, 1);
5768 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5769 R600_ERR("if/endif unbalanced in shader\n");
5770 return -1;
5771 }
5772
5773 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5774 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5775 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5776 } else {
5777 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5778 }
5779 fc_poplevel(ctx);
5780
5781 callstack_pop(ctx, FC_PUSH_VPM);
5782 return 0;
5783 }
5784
5785 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5786 {
5787 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5788 * limited to 4096 iterations, like the other LOOP_* instructions. */
5789 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5790
5791 fc_pushlevel(ctx, FC_LOOP);
5792
5793 /* check stack depth */
5794 callstack_push(ctx, FC_LOOP);
5795 return 0;
5796 }
5797
5798 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5799 {
5800 int i;
5801
5802 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5803
5804 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5805 R600_ERR("loop/endloop in shader code are not paired.\n");
5806 return -EINVAL;
5807 }
5808
5809 /* fixup loop pointers - from r600isa
5810 LOOP END points to CF after LOOP START,
5811 LOOP START point to CF after LOOP END
5812 BRK/CONT point to LOOP END CF
5813 */
5814 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5815
5816 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5817
5818 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5819 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5820 }
5821 /* XXX add LOOPRET support */
5822 fc_poplevel(ctx);
5823 callstack_pop(ctx, FC_LOOP);
5824 return 0;
5825 }
5826
5827 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5828 {
5829 unsigned int fscp;
5830
5831 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5832 {
5833 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5834 break;
5835 }
5836
5837 if (fscp == 0) {
5838 R600_ERR("Break not inside loop/endloop pair\n");
5839 return -EINVAL;
5840 }
5841
5842 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5843
5844 fc_set_mid(ctx, fscp);
5845
5846 return 0;
5847 }
5848
5849 static int tgsi_umad(struct r600_shader_ctx *ctx)
5850 {
5851 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5852 struct r600_bytecode_alu alu;
5853 int i, j, k, r;
5854 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5855
5856 /* src0 * src1 */
5857 for (i = 0; i < lasti + 1; i++) {
5858 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5859 continue;
5860
5861 if (ctx->bc->chip_class == CAYMAN) {
5862 for (j = 0 ; j < 4; j++) {
5863 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5864
5865 alu.op = ALU_OP2_MULLO_UINT;
5866 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5867 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5868 }
5869 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5870 alu.dst.sel = ctx->temp_reg;
5871 alu.dst.write = (j == i);
5872 if (j == 3)
5873 alu.last = 1;
5874 r = r600_bytecode_add_alu(ctx->bc, &alu);
5875 if (r)
5876 return r;
5877 }
5878 } else {
5879 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5880
5881 alu.dst.chan = i;
5882 alu.dst.sel = ctx->temp_reg;
5883 alu.dst.write = 1;
5884
5885 alu.op = ALU_OP2_MULLO_UINT;
5886 for (j = 0; j < 2; j++) {
5887 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5888 }
5889
5890 alu.last = 1;
5891 r = r600_bytecode_add_alu(ctx->bc, &alu);
5892 if (r)
5893 return r;
5894 }
5895 }
5896
5897
5898 for (i = 0; i < lasti + 1; i++) {
5899 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5900 continue;
5901
5902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5903 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5904
5905 alu.op = ALU_OP2_ADD_INT;
5906
5907 alu.src[0].sel = ctx->temp_reg;
5908 alu.src[0].chan = i;
5909
5910 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5911 if (i == lasti) {
5912 alu.last = 1;
5913 }
5914 r = r600_bytecode_add_alu(ctx->bc, &alu);
5915 if (r)
5916 return r;
5917 }
5918 return 0;
5919 }
5920
5921 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5922 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5923 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5924 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5925
5926 /* XXX:
5927 * For state trackers other than OpenGL, we'll want to use
5928 * _RECIP_IEEE instead.
5929 */
5930 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5931
5932 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5933 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5934 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5935 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5936 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5937 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5938 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5939 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5940 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5941 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5942 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5943 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5944 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5945 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5946 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5947 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5948 /* gap */
5949 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5950 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5951 /* gap */
5952 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5953 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5954 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5955 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5956 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5957 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5958 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5959 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5960 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5961 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5962 /* gap */
5963 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5964 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5965 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5966 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5967 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5968 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5969 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5970 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5971 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5972 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5973 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5974 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5975 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5977 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5978 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5979 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5980 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5981 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5982 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5983 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5984 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5985 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5986 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5987 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5988 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5989 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5990 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5991 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5992 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5993 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5994 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5995 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5996 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5997 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5998 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5999 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6000 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6001 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6002 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6003 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6004 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6005 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6006 /* gap */
6007 {75, 0, ALU_OP0_NOP, tgsi_unsupported},
6008 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6009 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6010 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6011 /* gap */
6012 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6013 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6014 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6015 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6016 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6017 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6018 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6019 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6020 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
6021 /* gap */
6022 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6023 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6024 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6025 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6026 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6027 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6028 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6029 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6030 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6031 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6032 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6033 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6034 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6035 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6036 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6037 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6038 /* gap */
6039 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6040 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6041 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6042 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6043 /* gap */
6044 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6045 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6046 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6047 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6048 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6049 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6050 {TGSI_OPCODE_IFC, 0, ALU_OP0_NOP, tgsi_unsupported},
6051 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6052 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6053 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6054 /* gap */
6055 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6056 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
6057 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6058 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6059 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6060 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6061 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6062 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
6063 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6064 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
6065 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6066 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6067 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6068 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6069 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6070 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6071 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6072 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6073 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6074 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6075 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
6076 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6077 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
6078 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6079 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6080 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6081 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6082 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6083 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6084 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6085 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6086 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6087 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6088 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6089 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6090 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6091 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6092 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6093 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6094 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
6095 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6096 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6097 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6098 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6099 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6100 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6101 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6102 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6103 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6104 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6105 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6106 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6107 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6108 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6109 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6110 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6113 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6114 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6115 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6116 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6117 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6118 };
6119
6120 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
6121 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6122 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6123 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6124 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
6125 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
6126 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6127 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6128 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6129 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6130 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6131 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6132 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6133 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6134 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6135 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6136 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6137 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6138 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6139 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6140 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6141 /* gap */
6142 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6143 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6144 /* gap */
6145 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6146 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6147 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6148 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6149 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6150 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6151 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6152 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6153 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6154 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6155 /* gap */
6156 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6157 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6158 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6159 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6160 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6161 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6162 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6163 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6164 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6165 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6166 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6167 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6168 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6170 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6171 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6172 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6173 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6174 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6175 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6176 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6177 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6178 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6179 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6180 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6181 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6182 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6183 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6184 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6185 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6186 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6187 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6188 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6189 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6190 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6191 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6192 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6193 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6194 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6195 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6196 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6197 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6198 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6199 /* gap */
6200 {75, 0, ALU_OP0_NOP, tgsi_unsupported},
6201 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6202 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6203 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6204 /* gap */
6205 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6206 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6207 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6208 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6209 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6210 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6211 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6212 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6213 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6214 /* gap */
6215 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6216 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6217 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6218 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6219 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6220 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6221 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6222 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6223 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6224 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6225 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6226 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6227 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6228 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6229 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6230 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6231 /* gap */
6232 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6233 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6234 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6235 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6236 /* gap */
6237 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6238 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6239 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6240 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6241 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6242 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6243 {TGSI_OPCODE_IFC, 0, ALU_OP0_NOP, tgsi_unsupported},
6244 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6245 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6246 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6247 /* gap */
6248 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6249 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
6250 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6251 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6252 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6253 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6254 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6255 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6256 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6257 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
6258 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6259 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6260 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6261 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6262 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6263 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6264 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6265 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6266 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6267 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6268 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6269 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6270 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6271 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6272 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6273 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6274 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6275 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6276 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6277 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6278 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6279 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6280 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6281 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6282 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6283 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6284 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6285 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6286 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6287 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6288 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6289 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6290 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6291 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6292 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6293 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6294 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6295 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6296 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6297 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6298 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6299 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6300 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6301 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6302 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6303 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6304 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6305 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6306 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6307 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6308 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6309 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6310 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6311 };
6312
6313 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6314 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6315 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6316 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6317 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6318 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6319 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6320 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6321 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6322 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6323 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6324 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6325 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6326 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6327 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6328 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6329 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6330 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6331 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6332 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6333 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6334 /* gap */
6335 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6336 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6337 /* gap */
6338 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6339 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6340 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6341 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6342 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6343 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6344 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6345 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6346 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6347 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6348 /* gap */
6349 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6350 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6351 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6352 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6353 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6354 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6355 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6356 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6357 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6358 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6359 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6360 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6361 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6362 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6363 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6364 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6365 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6366 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6367 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6368 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6369 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6370 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6371 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6372 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6373 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6374 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6375 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6376 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6377 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6378 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6379 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6380 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6381 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6382 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6383 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6384 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6385 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6386 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6387 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6388 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6389 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6390 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6391 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6392 /* gap */
6393 {75, 0, ALU_OP0_NOP, tgsi_unsupported},
6394 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6395 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6396 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6397 /* gap */
6398 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6399 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6400 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6401 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6402 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6403 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6404 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6405 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6406 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6407 /* gap */
6408 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6409 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6410 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6411 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6412 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6413 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6414 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6415 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6416 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6417 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6418 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6419 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6420 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6421 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6422 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6423 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6424 /* gap */
6425 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6426 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6427 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6428 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6429 /* gap */
6430 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6431 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6432 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6433 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6434 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6435 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6436 {TGSI_OPCODE_IFC, 0, ALU_OP0_NOP, tgsi_unsupported},
6437 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6438 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6439 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6440 /* gap */
6441 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6442 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6443 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6444 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6445 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6446 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6447 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6448 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6449 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6450 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6451 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6452 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6453 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6454 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6455 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6456 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6457 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6458 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6459 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6460 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6461 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6462 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6463 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6464 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6465 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6466 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6467 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6468 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6469 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6470 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6471 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6472 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6473 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6474 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6475 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6476 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6477 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6478 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6479 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6480 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6481 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6482 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6483 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6484 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6485 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6486 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6487 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6488 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6489 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6490 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6491 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6492 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6493 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6494 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6495 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6496 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6497 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6498 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6499 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6500 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6501 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6502 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6503 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6504 };