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r600/shader: Fix all warnings issed with "-Wall -Wextra"
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198 use_sb &= !shader->shader.uses_images;
199
200 /* Check if the bytecode has already been built. */
201 if (!shader->shader.bc.bytecode) {
202 r = r600_bytecode_build(&shader->shader.bc);
203 if (r) {
204 R600_ERR("building bytecode failed !\n");
205 goto error;
206 }
207 }
208
209 if (dump && !sb_disasm) {
210 fprintf(stderr, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader->shader.bc);
212 fprintf(stderr, "______________________________________________________________\n");
213 } else if ((dump && sb_disasm) || use_sb) {
214 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
215 dump, use_sb);
216 if (r) {
217 R600_ERR("r600_sb_bytecode_process failed !\n");
218 goto error;
219 }
220 }
221
222 if (shader->gs_copy_shader) {
223 if (dump) {
224 // dump copy shader
225 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
226 &shader->gs_copy_shader->shader, dump, 0);
227 if (r)
228 goto error;
229 }
230
231 if ((r = store_shader(ctx, shader->gs_copy_shader)))
232 goto error;
233 }
234
235 /* Store the shader in a buffer. */
236 if ((r = store_shader(ctx, shader)))
237 goto error;
238
239 /* Build state. */
240 switch (shader->shader.processor_type) {
241 case PIPE_SHADER_TESS_CTRL:
242 evergreen_update_hs_state(ctx, shader);
243 break;
244 case PIPE_SHADER_TESS_EVAL:
245 if (key.tes.as_es)
246 evergreen_update_es_state(ctx, shader);
247 else
248 evergreen_update_vs_state(ctx, shader);
249 break;
250 case PIPE_SHADER_GEOMETRY:
251 if (rctx->b.chip_class >= EVERGREEN) {
252 evergreen_update_gs_state(ctx, shader);
253 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
254 } else {
255 r600_update_gs_state(ctx, shader);
256 r600_update_vs_state(ctx, shader->gs_copy_shader);
257 }
258 break;
259 case PIPE_SHADER_VERTEX:
260 export_shader = key.vs.as_es;
261 if (rctx->b.chip_class >= EVERGREEN) {
262 if (key.vs.as_ls)
263 evergreen_update_ls_state(ctx, shader);
264 else if (key.vs.as_es)
265 evergreen_update_es_state(ctx, shader);
266 else
267 evergreen_update_vs_state(ctx, shader);
268 } else {
269 if (export_shader)
270 r600_update_es_state(ctx, shader);
271 else
272 r600_update_vs_state(ctx, shader);
273 }
274 break;
275 case PIPE_SHADER_FRAGMENT:
276 if (rctx->b.chip_class >= EVERGREEN) {
277 evergreen_update_ps_state(ctx, shader);
278 } else {
279 r600_update_ps_state(ctx, shader);
280 }
281 break;
282 default:
283 r = -EINVAL;
284 goto error;
285 }
286 return 0;
287
288 error:
289 r600_pipe_shader_destroy(ctx, shader);
290 return r;
291 }
292
293 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
294 {
295 r600_resource_reference(&shader->bo, NULL);
296 r600_bytecode_clear(&shader->shader.bc);
297 r600_release_command_buffer(&shader->command_buffer);
298 }
299
300 /*
301 * tgsi -> r600 shader
302 */
303 struct r600_shader_tgsi_instruction;
304
305 struct r600_shader_src {
306 unsigned sel;
307 unsigned swizzle[4];
308 unsigned neg;
309 unsigned abs;
310 unsigned rel;
311 unsigned kc_bank;
312 boolean kc_rel; /* true if cache bank is indexed */
313 uint32_t value[4];
314 };
315
316 struct eg_interp {
317 boolean enabled;
318 unsigned ij_index;
319 };
320
321 struct r600_shader_ctx {
322 struct tgsi_shader_info info;
323 struct tgsi_parse_context parse;
324 const struct tgsi_token *tokens;
325 unsigned type;
326 unsigned file_offset[TGSI_FILE_COUNT];
327 unsigned temp_reg;
328 const struct r600_shader_tgsi_instruction *inst_info;
329 struct r600_bytecode *bc;
330 struct r600_shader *shader;
331 struct r600_shader_src src[4];
332 uint32_t *literals;
333 uint32_t nliterals;
334 uint32_t max_driver_temp_used;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
338 int face_gpr;
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr;
341 int colors_used;
342 boolean clip_vertex_write;
343 unsigned cv_output;
344 unsigned edgeflag_output;
345 int fragcoord_input;
346 int native_integers;
347 int next_ring_offset;
348 int gs_out_ring_offset;
349 int gs_next_vertex;
350 struct r600_shader *gs_for_vs;
351 int gs_export_gpr_tregs[4];
352 int gs_rotated_input[2];
353 const struct pipe_stream_output_info *gs_stream_output_info;
354 unsigned enabled_stream_buffers_mask;
355 unsigned tess_input_info; /* temp with tess input offsets */
356 unsigned tess_output_info; /* temp with tess input offsets */
357 unsigned thread_id_gpr; /* temp with thread id calculated for images */
358 };
359
360 struct r600_shader_tgsi_instruction {
361 unsigned op;
362 int (*process)(struct r600_shader_ctx *ctx);
363 };
364
365 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
366 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
367 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
368 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
369 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
370 static int tgsi_else(struct r600_shader_ctx *ctx);
371 static int tgsi_endif(struct r600_shader_ctx *ctx);
372 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
373 static int tgsi_endloop(struct r600_shader_ctx *ctx);
374 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
375 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
376 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
377 unsigned int dst_reg);
378 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
379 const struct r600_shader_src *shader_src,
380 unsigned chan);
381 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
382 unsigned dst_reg);
383
384 static int tgsi_last_instruction(unsigned writemask)
385 {
386 int i, lasti = 0;
387
388 for (i = 0; i < 4; i++) {
389 if (writemask & (1 << i)) {
390 lasti = i;
391 }
392 }
393 return lasti;
394 }
395
396 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
397 {
398 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
399 unsigned j;
400
401 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
402 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
403 return -EINVAL;
404 }
405 #if 0
406 if (i->Instruction.Label) {
407 R600_ERR("label unsupported\n");
408 return -EINVAL;
409 }
410 #endif
411 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
412 if (i->Src[j].Register.Dimension) {
413 switch (i->Src[j].Register.File) {
414 case TGSI_FILE_CONSTANT:
415 case TGSI_FILE_HW_ATOMIC:
416 break;
417 case TGSI_FILE_INPUT:
418 if (ctx->type == PIPE_SHADER_GEOMETRY ||
419 ctx->type == PIPE_SHADER_TESS_CTRL ||
420 ctx->type == PIPE_SHADER_TESS_EVAL)
421 break;
422 case TGSI_FILE_OUTPUT:
423 if (ctx->type == PIPE_SHADER_TESS_CTRL)
424 break;
425 default:
426 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
427 i->Src[j].Register.File,
428 i->Src[j].Register.Dimension);
429 return -EINVAL;
430 }
431 }
432 }
433 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
434 if (i->Dst[j].Register.Dimension) {
435 if (ctx->type == PIPE_SHADER_TESS_CTRL)
436 continue;
437 R600_ERR("unsupported dst (dimension)\n");
438 return -EINVAL;
439 }
440 }
441 return 0;
442 }
443
444 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
445 {
446 if (interpolate == TGSI_INTERPOLATE_COLOR ||
447 interpolate == TGSI_INTERPOLATE_LINEAR ||
448 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
449 {
450 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
451 int loc;
452
453 switch(location) {
454 case TGSI_INTERPOLATE_LOC_CENTER:
455 loc = 1;
456 break;
457 case TGSI_INTERPOLATE_LOC_CENTROID:
458 loc = 2;
459 break;
460 case TGSI_INTERPOLATE_LOC_SAMPLE:
461 default:
462 loc = 0; break;
463 }
464
465 return is_linear * 3 + loc;
466 }
467
468 return -1;
469 }
470
471 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
472 int input)
473 {
474 int i = eg_get_interpolator_index(
475 ctx->shader->input[input].interpolate,
476 ctx->shader->input[input].interpolate_location);
477 assert(i >= 0);
478 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
479 }
480
481 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
482 {
483 int i, r;
484 struct r600_bytecode_alu alu;
485 int gpr = 0, base_chan = 0;
486 int ij_index = ctx->shader->input[input].ij_index;
487
488 /* work out gpr and base_chan from index */
489 gpr = ij_index / 2;
490 base_chan = (2 * (ij_index % 2)) + 1;
491
492 for (i = 0; i < 8; i++) {
493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
494
495 if (i < 4)
496 alu.op = ALU_OP2_INTERP_ZW;
497 else
498 alu.op = ALU_OP2_INTERP_XY;
499
500 if ((i > 1) && (i < 6)) {
501 alu.dst.sel = ctx->shader->input[input].gpr;
502 alu.dst.write = 1;
503 }
504
505 alu.dst.chan = i % 4;
506
507 alu.src[0].sel = gpr;
508 alu.src[0].chan = (base_chan - (i % 2));
509
510 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
511
512 alu.bank_swizzle_force = SQ_ALU_VEC_210;
513 if ((i % 4) == 3)
514 alu.last = 1;
515 r = r600_bytecode_add_alu(ctx->bc, &alu);
516 if (r)
517 return r;
518 }
519 return 0;
520 }
521
522 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
523 {
524 int i, r;
525 struct r600_bytecode_alu alu;
526
527 for (i = 0; i < 4; i++) {
528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
529
530 alu.op = ALU_OP1_INTERP_LOAD_P0;
531
532 alu.dst.sel = ctx->shader->input[input].gpr;
533 alu.dst.write = 1;
534
535 alu.dst.chan = i;
536
537 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
538 alu.src[0].chan = i;
539
540 if (i == 3)
541 alu.last = 1;
542 r = r600_bytecode_add_alu(ctx->bc, &alu);
543 if (r)
544 return r;
545 }
546 return 0;
547 }
548
549 /*
550 * Special export handling in shaders
551 *
552 * shader export ARRAY_BASE for EXPORT_POS:
553 * 60 is position
554 * 61 is misc vector
555 * 62, 63 are clip distance vectors
556 *
557 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
558 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
559 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
560 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
561 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
562 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
563 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
564 * exclusive from render target index)
565 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
566 *
567 *
568 * shader export ARRAY_BASE for EXPORT_PIXEL:
569 * 0-7 CB targets
570 * 61 computed Z vector
571 *
572 * The use of the values exported in the computed Z vector are controlled
573 * by DB_SHADER_CONTROL:
574 * Z_EXPORT_ENABLE - Z as a float in RED
575 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
576 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
577 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
578 * DB_SOURCE_FORMAT - export control restrictions
579 *
580 */
581
582
583 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
584 static int r600_spi_sid(struct r600_shader_io * io)
585 {
586 int index, name = io->name;
587
588 /* These params are handled differently, they don't need
589 * semantic indices, so we'll use 0 for them.
590 */
591 if (name == TGSI_SEMANTIC_POSITION ||
592 name == TGSI_SEMANTIC_PSIZE ||
593 name == TGSI_SEMANTIC_EDGEFLAG ||
594 name == TGSI_SEMANTIC_FACE ||
595 name == TGSI_SEMANTIC_SAMPLEMASK)
596 index = 0;
597 else {
598 if (name == TGSI_SEMANTIC_GENERIC) {
599 /* For generic params simply use sid from tgsi */
600 index = io->sid;
601 } else {
602 /* For non-generic params - pack name and sid into 8 bits */
603 index = 0x80 | (name<<3) | (io->sid);
604 }
605
606 /* Make sure that all really used indices have nonzero value, so
607 * we can just compare it to 0 later instead of comparing the name
608 * with different values to detect special cases. */
609 index++;
610 }
611
612 return index;
613 };
614
615 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
616 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
617 {
618 switch (semantic_name) {
619 case TGSI_SEMANTIC_POSITION:
620 return 0;
621 case TGSI_SEMANTIC_PSIZE:
622 return 1;
623 case TGSI_SEMANTIC_CLIPDIST:
624 assert(index <= 1);
625 return 2 + index;
626 case TGSI_SEMANTIC_GENERIC:
627 if (index <= 63-4)
628 return 4 + index - 9;
629 else
630 /* same explanation as in the default statement,
631 * the only user hitting this is st/nine.
632 */
633 return 0;
634
635 /* patch indices are completely separate and thus start from 0 */
636 case TGSI_SEMANTIC_TESSOUTER:
637 return 0;
638 case TGSI_SEMANTIC_TESSINNER:
639 return 1;
640 case TGSI_SEMANTIC_PATCH:
641 return 2 + index;
642
643 default:
644 /* Don't fail here. The result of this function is only used
645 * for LS, TCS, TES, and GS, where legacy GL semantics can't
646 * occur, but this function is called for all vertex shaders
647 * before it's known whether LS will be compiled or not.
648 */
649 return 0;
650 }
651 }
652
653 /* turn input into interpolate on EG */
654 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
655 {
656 int r = 0;
657
658 if (ctx->shader->input[index].spi_sid) {
659 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
660 if (ctx->shader->input[index].interpolate > 0) {
661 evergreen_interp_assign_ij_index(ctx, index);
662 r = evergreen_interp_alu(ctx, index);
663 } else {
664 r = evergreen_interp_flat(ctx, index);
665 }
666 }
667 return r;
668 }
669
670 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
671 {
672 struct r600_bytecode_alu alu;
673 int i, r;
674 int gpr_front = ctx->shader->input[front].gpr;
675 int gpr_back = ctx->shader->input[back].gpr;
676
677 for (i = 0; i < 4; i++) {
678 memset(&alu, 0, sizeof(alu));
679 alu.op = ALU_OP3_CNDGT;
680 alu.is_op3 = 1;
681 alu.dst.write = 1;
682 alu.dst.sel = gpr_front;
683 alu.src[0].sel = ctx->face_gpr;
684 alu.src[1].sel = gpr_front;
685 alu.src[2].sel = gpr_back;
686
687 alu.dst.chan = i;
688 alu.src[1].chan = i;
689 alu.src[2].chan = i;
690 alu.last = (i==3);
691
692 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
693 return r;
694 }
695
696 return 0;
697 }
698
699 /* execute a single slot ALU calculation */
700 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
701 int dst_sel, int dst_chan,
702 int src0_sel, unsigned src0_chan_val,
703 int src1_sel, unsigned src1_chan_val)
704 {
705 struct r600_bytecode_alu alu;
706 int r, i;
707
708 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
709 for (i = 0; i < 4; i++) {
710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
711 alu.op = op;
712 alu.src[0].sel = src0_sel;
713 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
714 alu.src[0].value = src0_chan_val;
715 else
716 alu.src[0].chan = src0_chan_val;
717 alu.src[1].sel = src1_sel;
718 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
719 alu.src[1].value = src1_chan_val;
720 else
721 alu.src[1].chan = src1_chan_val;
722 alu.dst.sel = dst_sel;
723 alu.dst.chan = i;
724 alu.dst.write = i == dst_chan;
725 alu.last = (i == 3);
726 r = r600_bytecode_add_alu(ctx->bc, &alu);
727 if (r)
728 return r;
729 }
730 return 0;
731 }
732
733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
734 alu.op = op;
735 alu.src[0].sel = src0_sel;
736 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
737 alu.src[0].value = src0_chan_val;
738 else
739 alu.src[0].chan = src0_chan_val;
740 alu.src[1].sel = src1_sel;
741 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
742 alu.src[1].value = src1_chan_val;
743 else
744 alu.src[1].chan = src1_chan_val;
745 alu.dst.sel = dst_sel;
746 alu.dst.chan = dst_chan;
747 alu.dst.write = 1;
748 alu.last = 1;
749 r = r600_bytecode_add_alu(ctx->bc, &alu);
750 if (r)
751 return r;
752 return 0;
753 }
754
755 /* execute a single slot ALU calculation */
756 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
757 int dst_sel, int dst_chan,
758 int src0_sel, unsigned src0_chan_val,
759 int src1_sel, unsigned src1_chan_val,
760 int src2_sel, unsigned src2_chan_val)
761 {
762 struct r600_bytecode_alu alu;
763 int r;
764
765 /* validate this for other ops */
766 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
768 alu.op = op;
769 alu.src[0].sel = src0_sel;
770 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
771 alu.src[0].value = src0_chan_val;
772 else
773 alu.src[0].chan = src0_chan_val;
774 alu.src[1].sel = src1_sel;
775 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
776 alu.src[1].value = src1_chan_val;
777 else
778 alu.src[1].chan = src1_chan_val;
779 alu.src[2].sel = src2_sel;
780 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
781 alu.src[2].value = src2_chan_val;
782 else
783 alu.src[2].chan = src2_chan_val;
784 alu.dst.sel = dst_sel;
785 alu.dst.chan = dst_chan;
786 alu.is_op3 = 1;
787 alu.last = 1;
788 r = r600_bytecode_add_alu(ctx->bc, &alu);
789 if (r)
790 return r;
791 return 0;
792 }
793
794 /* put it in temp_reg.x */
795 static int get_lds_offset0(struct r600_shader_ctx *ctx,
796 int rel_patch_chan,
797 int temp_reg, bool is_patch_var)
798 {
799 int r;
800
801 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
802 /* ADD
803 Dimension - patch0_offset (input_vals.z),
804 Non-dim - patch0_data_offset (input_vals.w)
805 */
806 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
807 temp_reg, 0,
808 ctx->tess_output_info, 0,
809 0, rel_patch_chan,
810 ctx->tess_output_info, is_patch_var ? 3 : 2);
811 if (r)
812 return r;
813 return 0;
814 }
815
816 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
817 {
818 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
819 }
820
821 static int r600_get_temp(struct r600_shader_ctx *ctx)
822 {
823 return ctx->temp_reg + ctx->max_driver_temp_used++;
824 }
825
826 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
827 {
828 int i;
829 i = ctx->shader->noutput++;
830 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
831 ctx->shader->output[i].sid = 0;
832 ctx->shader->output[i].gpr = 0;
833 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
834 ctx->shader->output[i].write_mask = 0x4;
835 ctx->shader->output[i].spi_sid = prim_id_sid;
836
837 return 0;
838 }
839
840 static int tgsi_barrier(struct r600_shader_ctx *ctx)
841 {
842 struct r600_bytecode_alu alu;
843 int r;
844
845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
846 alu.op = ctx->inst_info->op;
847 alu.last = 1;
848
849 r = r600_bytecode_add_alu(ctx->bc, &alu);
850 if (r)
851 return r;
852 return 0;
853 }
854
855 static int tgsi_declaration(struct r600_shader_ctx *ctx)
856 {
857 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
858 int r, i, j, count = d->Range.Last - d->Range.First + 1;
859
860 switch (d->Declaration.File) {
861 case TGSI_FILE_INPUT:
862 for (j = 0; j < count; j++) {
863 i = ctx->shader->ninput + j;
864 assert(i < ARRAY_SIZE(ctx->shader->input));
865 ctx->shader->input[i].name = d->Semantic.Name;
866 ctx->shader->input[i].sid = d->Semantic.Index + j;
867 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
868 ctx->shader->input[i].interpolate_location = d->Interp.Location;
869 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
870 if (ctx->type == PIPE_SHADER_FRAGMENT) {
871 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
872 switch (ctx->shader->input[i].name) {
873 case TGSI_SEMANTIC_FACE:
874 if (ctx->face_gpr != -1)
875 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
876 else
877 ctx->face_gpr = ctx->shader->input[i].gpr;
878 break;
879 case TGSI_SEMANTIC_COLOR:
880 ctx->colors_used++;
881 break;
882 case TGSI_SEMANTIC_POSITION:
883 ctx->fragcoord_input = i;
884 break;
885 case TGSI_SEMANTIC_PRIMID:
886 /* set this for now */
887 ctx->shader->gs_prim_id_input = true;
888 ctx->shader->ps_prim_id_input = i;
889 break;
890 }
891 if (ctx->bc->chip_class >= EVERGREEN) {
892 if ((r = evergreen_interp_input(ctx, i)))
893 return r;
894 }
895 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
896 /* FIXME probably skip inputs if they aren't passed in the ring */
897 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
898 ctx->next_ring_offset += 16;
899 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
900 ctx->shader->gs_prim_id_input = true;
901 }
902 }
903 ctx->shader->ninput += count;
904 break;
905 case TGSI_FILE_OUTPUT:
906 for (j = 0; j < count; j++) {
907 i = ctx->shader->noutput + j;
908 assert(i < ARRAY_SIZE(ctx->shader->output));
909 ctx->shader->output[i].name = d->Semantic.Name;
910 ctx->shader->output[i].sid = d->Semantic.Index + j;
911 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
912 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
913 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
914 if (ctx->type == PIPE_SHADER_VERTEX ||
915 ctx->type == PIPE_SHADER_GEOMETRY ||
916 ctx->type == PIPE_SHADER_TESS_EVAL) {
917 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
918 switch (d->Semantic.Name) {
919 case TGSI_SEMANTIC_CLIPDIST:
920 break;
921 case TGSI_SEMANTIC_PSIZE:
922 ctx->shader->vs_out_misc_write = 1;
923 ctx->shader->vs_out_point_size = 1;
924 break;
925 case TGSI_SEMANTIC_EDGEFLAG:
926 ctx->shader->vs_out_misc_write = 1;
927 ctx->shader->vs_out_edgeflag = 1;
928 ctx->edgeflag_output = i;
929 break;
930 case TGSI_SEMANTIC_VIEWPORT_INDEX:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_viewport = 1;
933 break;
934 case TGSI_SEMANTIC_LAYER:
935 ctx->shader->vs_out_misc_write = 1;
936 ctx->shader->vs_out_layer = 1;
937 break;
938 case TGSI_SEMANTIC_CLIPVERTEX:
939 ctx->clip_vertex_write = TRUE;
940 ctx->cv_output = i;
941 break;
942 }
943 if (ctx->type == PIPE_SHADER_GEOMETRY) {
944 ctx->gs_out_ring_offset += 16;
945 }
946 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
947 switch (d->Semantic.Name) {
948 case TGSI_SEMANTIC_COLOR:
949 ctx->shader->nr_ps_max_color_exports++;
950 break;
951 }
952 }
953 }
954 ctx->shader->noutput += count;
955 break;
956 case TGSI_FILE_TEMPORARY:
957 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
958 if (d->Array.ArrayID) {
959 r600_add_gpr_array(ctx->shader,
960 ctx->file_offset[TGSI_FILE_TEMPORARY] +
961 d->Range.First,
962 d->Range.Last - d->Range.First + 1, 0x0F);
963 }
964 }
965 break;
966
967 case TGSI_FILE_CONSTANT:
968 case TGSI_FILE_SAMPLER:
969 case TGSI_FILE_SAMPLER_VIEW:
970 case TGSI_FILE_ADDRESS:
971 case TGSI_FILE_IMAGE:
972 break;
973
974 case TGSI_FILE_HW_ATOMIC:
975 i = ctx->shader->nhwatomic_ranges;
976 ctx->shader->atomics[i].start = d->Range.First;
977 ctx->shader->atomics[i].end = d->Range.Last;
978 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
979 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
980 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
981 ctx->shader->nhwatomic_ranges++;
982 ctx->shader->nhwatomic += count;
983 break;
984
985 case TGSI_FILE_SYSTEM_VALUE:
986 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
987 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
988 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
989 break; /* Already handled from allocate_system_value_inputs */
990 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
991 if (!ctx->native_integers) {
992 struct r600_bytecode_alu alu;
993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
994
995 alu.op = ALU_OP1_INT_TO_FLT;
996 alu.src[0].sel = 0;
997 alu.src[0].chan = 3;
998
999 alu.dst.sel = 0;
1000 alu.dst.chan = 3;
1001 alu.dst.write = 1;
1002 alu.last = 1;
1003
1004 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1005 return r;
1006 }
1007 break;
1008 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1009 break;
1010 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1011 break;
1012 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1013 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1014 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1015 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1016 unsigned temp_reg = r600_get_temp(ctx);
1017
1018 r = get_lds_offset0(ctx, 2, temp_reg, true);
1019 if (r)
1020 return r;
1021
1022 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1023 temp_reg, 0,
1024 temp_reg, 0,
1025 V_SQ_ALU_SRC_LITERAL, param * 16);
1026 if (r)
1027 return r;
1028
1029 do_lds_fetch_values(ctx, temp_reg, dreg);
1030 }
1031 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1032 /* MOV r1.x, r0.x;
1033 MOV r1.y, r0.y;
1034 */
1035 for (i = 0; i < 2; i++) {
1036 struct r600_bytecode_alu alu;
1037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1038 alu.op = ALU_OP1_MOV;
1039 alu.src[0].sel = 0;
1040 alu.src[0].chan = 0 + i;
1041 alu.dst.sel = 1;
1042 alu.dst.chan = 0 + i;
1043 alu.dst.write = 1;
1044 alu.last = (i == 1) ? 1 : 0;
1045 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1046 return r;
1047 }
1048 /* ADD r1.z, 1.0f, -r0.x */
1049 struct r600_bytecode_alu alu;
1050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1051 alu.op = ALU_OP2_ADD;
1052 alu.src[0].sel = V_SQ_ALU_SRC_1;
1053 alu.src[1].sel = 1;
1054 alu.src[1].chan = 0;
1055 alu.src[1].neg = 1;
1056 alu.dst.sel = 1;
1057 alu.dst.chan = 2;
1058 alu.dst.write = 1;
1059 alu.last = 1;
1060 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1061 return r;
1062
1063 /* ADD r1.z, r1.z, -r1.y */
1064 alu.op = ALU_OP2_ADD;
1065 alu.src[0].sel = 1;
1066 alu.src[0].chan = 2;
1067 alu.src[1].sel = 1;
1068 alu.src[1].chan = 1;
1069 alu.src[1].neg = 1;
1070 alu.dst.sel = 1;
1071 alu.dst.chan = 2;
1072 alu.dst.write = 1;
1073 alu.last = 1;
1074 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1075 return r;
1076 break;
1077 }
1078 break;
1079 default:
1080 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1081 return -EINVAL;
1082 }
1083 return 0;
1084 }
1085
1086 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1087 {
1088 struct tgsi_parse_context parse;
1089 struct {
1090 boolean enabled;
1091 int *reg;
1092 unsigned name, alternate_name;
1093 } inputs[2] = {
1094 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1095
1096 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1097 };
1098 int num_regs = 0;
1099 unsigned k, i;
1100
1101 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1102 return 0;
1103 }
1104
1105 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1106 while (!tgsi_parse_end_of_tokens(&parse)) {
1107 tgsi_parse_token(&parse);
1108
1109 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1110 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1111 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1112 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1113 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1114 {
1115 int interpolate, location, k;
1116
1117 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1118 location = TGSI_INTERPOLATE_LOC_CENTER;
1119 inputs[1].enabled = true; /* needs SAMPLEID */
1120 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1121 location = TGSI_INTERPOLATE_LOC_CENTER;
1122 /* Needs sample positions, currently those are always available */
1123 } else {
1124 location = TGSI_INTERPOLATE_LOC_CENTROID;
1125 }
1126
1127 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1128 k = eg_get_interpolator_index(interpolate, location);
1129 if (k >= 0)
1130 ctx->eg_interpolators[k].enabled = true;
1131 }
1132 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1133 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1134 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1135 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1136 if (d->Semantic.Name == inputs[k].name ||
1137 d->Semantic.Name == inputs[k].alternate_name) {
1138 inputs[k].enabled = true;
1139 }
1140 }
1141 }
1142 }
1143 }
1144
1145 tgsi_parse_free(&parse);
1146
1147 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1148 boolean enabled = inputs[i].enabled;
1149 int *reg = inputs[i].reg;
1150 unsigned name = inputs[i].name;
1151
1152 if (enabled) {
1153 int gpr = gpr_offset + num_regs++;
1154 ctx->shader->nsys_inputs++;
1155
1156 // add to inputs, allocate a gpr
1157 k = ctx->shader->ninput++;
1158 ctx->shader->input[k].name = name;
1159 ctx->shader->input[k].sid = 0;
1160 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1161 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1162 *reg = ctx->shader->input[k].gpr = gpr;
1163 }
1164 }
1165
1166 return gpr_offset + num_regs;
1167 }
1168
1169 /*
1170 * for evergreen we need to scan the shader to find the number of GPRs we need to
1171 * reserve for interpolation and system values
1172 *
1173 * we need to know if we are going to emit
1174 * any sample or centroid inputs
1175 * if perspective and linear are required
1176 */
1177 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1178 {
1179 unsigned i;
1180 int num_baryc;
1181 struct tgsi_parse_context parse;
1182
1183 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1184
1185 for (i = 0; i < ctx->info.num_inputs; i++) {
1186 int k;
1187 /* skip position/face/mask/sampleid */
1188 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1189 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1190 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1191 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1192 continue;
1193
1194 k = eg_get_interpolator_index(
1195 ctx->info.input_interpolate[i],
1196 ctx->info.input_interpolate_loc[i]);
1197 if (k >= 0)
1198 ctx->eg_interpolators[k].enabled = TRUE;
1199 }
1200
1201 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1202 return 0;
1203 }
1204
1205 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1206 while (!tgsi_parse_end_of_tokens(&parse)) {
1207 tgsi_parse_token(&parse);
1208
1209 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1210 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1211 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1212 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1213 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1214 {
1215 int interpolate, location, k;
1216
1217 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1218 location = TGSI_INTERPOLATE_LOC_CENTER;
1219 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1220 location = TGSI_INTERPOLATE_LOC_CENTER;
1221 } else {
1222 location = TGSI_INTERPOLATE_LOC_CENTROID;
1223 }
1224
1225 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1226 k = eg_get_interpolator_index(interpolate, location);
1227 if (k >= 0)
1228 ctx->eg_interpolators[k].enabled = true;
1229 }
1230 }
1231 }
1232
1233 tgsi_parse_free(&parse);
1234
1235 /* assign gpr to each interpolator according to priority */
1236 num_baryc = 0;
1237 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1238 if (ctx->eg_interpolators[i].enabled) {
1239 ctx->eg_interpolators[i].ij_index = num_baryc;
1240 num_baryc ++;
1241 }
1242 }
1243
1244 /* XXX PULL MODEL and LINE STIPPLE */
1245
1246 num_baryc = (num_baryc + 1) >> 1;
1247 return allocate_system_value_inputs(ctx, num_baryc);
1248 }
1249
1250 /* sample_id_sel == NULL means fetch for current sample */
1251 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1252 {
1253 struct r600_bytecode_vtx vtx;
1254 int r, t1;
1255
1256 assert(ctx->fixed_pt_position_gpr != -1);
1257
1258 t1 = r600_get_temp(ctx);
1259
1260 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1261 vtx.op = FETCH_OP_VFETCH;
1262 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1263 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1264 if (sample_id == NULL) {
1265 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1266 vtx.src_sel_x = 3;
1267 }
1268 else {
1269 struct r600_bytecode_alu alu;
1270
1271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1272 alu.op = ALU_OP1_MOV;
1273 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1274 alu.dst.sel = t1;
1275 alu.dst.write = 1;
1276 alu.last = 1;
1277 r = r600_bytecode_add_alu(ctx->bc, &alu);
1278 if (r)
1279 return r;
1280
1281 vtx.src_gpr = t1;
1282 vtx.src_sel_x = 0;
1283 }
1284 vtx.mega_fetch_count = 16;
1285 vtx.dst_gpr = t1;
1286 vtx.dst_sel_x = 0;
1287 vtx.dst_sel_y = 1;
1288 vtx.dst_sel_z = 2;
1289 vtx.dst_sel_w = 3;
1290 vtx.data_format = FMT_32_32_32_32_FLOAT;
1291 vtx.num_format_all = 2;
1292 vtx.format_comp_all = 1;
1293 vtx.use_const_fields = 0;
1294 vtx.offset = 1; // first element is size of buffer
1295 vtx.endian = r600_endian_swap(32);
1296 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1297
1298 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1299 if (r)
1300 return r;
1301
1302 return t1;
1303 }
1304
1305 static void tgsi_src(struct r600_shader_ctx *ctx,
1306 const struct tgsi_full_src_register *tgsi_src,
1307 struct r600_shader_src *r600_src)
1308 {
1309 memset(r600_src, 0, sizeof(*r600_src));
1310 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1311 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1312 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1313 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1314 r600_src->neg = tgsi_src->Register.Negate;
1315 r600_src->abs = tgsi_src->Register.Absolute;
1316
1317 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1318 int index;
1319 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1320 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1321 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1322
1323 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1324 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1325 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1326 return;
1327 }
1328 index = tgsi_src->Register.Index;
1329 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1330 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1331 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1332 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1333 r600_src->swizzle[0] = 2; // Z value
1334 r600_src->swizzle[1] = 2;
1335 r600_src->swizzle[2] = 2;
1336 r600_src->swizzle[3] = 2;
1337 r600_src->sel = ctx->face_gpr;
1338 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1339 r600_src->swizzle[0] = 3; // W value
1340 r600_src->swizzle[1] = 3;
1341 r600_src->swizzle[2] = 3;
1342 r600_src->swizzle[3] = 3;
1343 r600_src->sel = ctx->fixed_pt_position_gpr;
1344 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1345 r600_src->swizzle[0] = 0;
1346 r600_src->swizzle[1] = 1;
1347 r600_src->swizzle[2] = 4;
1348 r600_src->swizzle[3] = 4;
1349 r600_src->sel = load_sample_position(ctx, NULL, -1);
1350 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1351 r600_src->swizzle[0] = 3;
1352 r600_src->swizzle[1] = 3;
1353 r600_src->swizzle[2] = 3;
1354 r600_src->swizzle[3] = 3;
1355 r600_src->sel = 0;
1356 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1357 r600_src->swizzle[0] = 0;
1358 r600_src->swizzle[1] = 0;
1359 r600_src->swizzle[2] = 0;
1360 r600_src->swizzle[3] = 0;
1361 r600_src->sel = 0;
1362 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1363 r600_src->swizzle[0] = 3;
1364 r600_src->swizzle[1] = 3;
1365 r600_src->swizzle[2] = 3;
1366 r600_src->swizzle[3] = 3;
1367 r600_src->sel = 1;
1368 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1369 r600_src->swizzle[0] = 2;
1370 r600_src->swizzle[1] = 2;
1371 r600_src->swizzle[2] = 2;
1372 r600_src->swizzle[3] = 2;
1373 r600_src->sel = 0;
1374 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1375 r600_src->sel = 1;
1376 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1377 r600_src->sel = 3;
1378 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1379 r600_src->sel = 2;
1380 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1381 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1382 r600_src->sel = ctx->tess_input_info;
1383 r600_src->swizzle[0] = 2;
1384 r600_src->swizzle[1] = 2;
1385 r600_src->swizzle[2] = 2;
1386 r600_src->swizzle[3] = 2;
1387 } else {
1388 r600_src->sel = ctx->tess_input_info;
1389 r600_src->swizzle[0] = 3;
1390 r600_src->swizzle[1] = 3;
1391 r600_src->swizzle[2] = 3;
1392 r600_src->swizzle[3] = 3;
1393 }
1394 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1395 r600_src->sel = 0;
1396 r600_src->swizzle[0] = 0;
1397 r600_src->swizzle[1] = 0;
1398 r600_src->swizzle[2] = 0;
1399 r600_src->swizzle[3] = 0;
1400 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1401 r600_src->sel = 0;
1402 r600_src->swizzle[0] = 3;
1403 r600_src->swizzle[1] = 3;
1404 r600_src->swizzle[2] = 3;
1405 r600_src->swizzle[3] = 3;
1406 }
1407 } else {
1408 if (tgsi_src->Register.Indirect)
1409 r600_src->rel = V_SQ_REL_RELATIVE;
1410 r600_src->sel = tgsi_src->Register.Index;
1411 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1412 }
1413 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1414 if (tgsi_src->Register.Dimension) {
1415 r600_src->kc_bank = tgsi_src->Dimension.Index;
1416 if (tgsi_src->Dimension.Indirect) {
1417 r600_src->kc_rel = 1;
1418 }
1419 }
1420 }
1421 }
1422
1423 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1424 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1425 unsigned int dst_reg)
1426 {
1427 struct r600_bytecode_vtx vtx;
1428 unsigned int ar_reg;
1429 int r;
1430
1431 if (offset) {
1432 struct r600_bytecode_alu alu;
1433
1434 memset(&alu, 0, sizeof(alu));
1435
1436 alu.op = ALU_OP2_ADD_INT;
1437 alu.src[0].sel = ctx->bc->ar_reg;
1438 alu.src[0].chan = ar_chan;
1439
1440 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1441 alu.src[1].value = offset;
1442
1443 alu.dst.sel = dst_reg;
1444 alu.dst.chan = ar_chan;
1445 alu.dst.write = 1;
1446 alu.last = 1;
1447
1448 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1449 return r;
1450
1451 ar_reg = dst_reg;
1452 } else {
1453 ar_reg = ctx->bc->ar_reg;
1454 }
1455
1456 memset(&vtx, 0, sizeof(vtx));
1457 vtx.buffer_id = cb_idx;
1458 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1459 vtx.src_gpr = ar_reg;
1460 vtx.src_sel_x = ar_chan;
1461 vtx.mega_fetch_count = 16;
1462 vtx.dst_gpr = dst_reg;
1463 vtx.dst_sel_x = 0; /* SEL_X */
1464 vtx.dst_sel_y = 1; /* SEL_Y */
1465 vtx.dst_sel_z = 2; /* SEL_Z */
1466 vtx.dst_sel_w = 3; /* SEL_W */
1467 vtx.data_format = FMT_32_32_32_32_FLOAT;
1468 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1469 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1470 vtx.endian = r600_endian_swap(32);
1471 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1472
1473 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1474 return r;
1475
1476 return 0;
1477 }
1478
1479 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1480 {
1481 struct r600_bytecode_vtx vtx;
1482 int r;
1483 unsigned index = src->Register.Index;
1484 unsigned vtx_id = src->Dimension.Index;
1485 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1486 int offset_chan = vtx_id % 3;
1487 int t2 = 0;
1488
1489 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1490 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1491
1492 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1493 offset_chan = 3;
1494
1495 if (src->Dimension.Indirect || src->Register.Indirect)
1496 t2 = r600_get_temp(ctx);
1497
1498 if (src->Dimension.Indirect) {
1499 int treg[3];
1500 struct r600_bytecode_alu alu;
1501 int r, i;
1502 unsigned addr_reg;
1503 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1504 if (src->DimIndirect.Index > 0) {
1505 r = single_alu_op2(ctx, ALU_OP1_MOV,
1506 ctx->bc->ar_reg, 0,
1507 addr_reg, 0,
1508 0, 0);
1509 if (r)
1510 return r;
1511 }
1512 /*
1513 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1514 at least this is what fglrx seems to do. */
1515 for (i = 0; i < 3; i++) {
1516 treg[i] = r600_get_temp(ctx);
1517 }
1518 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1519
1520 for (i = 0; i < 3; i++) {
1521 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1522 alu.op = ALU_OP1_MOV;
1523 alu.src[0].sel = ctx->gs_rotated_input[0];
1524 alu.src[0].chan = i == 2 ? 3 : i;
1525 alu.dst.sel = treg[i];
1526 alu.dst.chan = 0;
1527 alu.dst.write = 1;
1528 alu.last = 1;
1529 r = r600_bytecode_add_alu(ctx->bc, &alu);
1530 if (r)
1531 return r;
1532 }
1533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1534 alu.op = ALU_OP1_MOV;
1535 alu.src[0].sel = treg[0];
1536 alu.src[0].rel = 1;
1537 alu.dst.sel = t2;
1538 alu.dst.write = 1;
1539 alu.last = 1;
1540 r = r600_bytecode_add_alu(ctx->bc, &alu);
1541 if (r)
1542 return r;
1543 offset_reg = t2;
1544 offset_chan = 0;
1545 }
1546
1547 if (src->Register.Indirect) {
1548 int addr_reg;
1549 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1550
1551 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1552
1553 /* pull the value from index_reg */
1554 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1555 t2, 1,
1556 addr_reg, 0,
1557 V_SQ_ALU_SRC_LITERAL, first);
1558 if (r)
1559 return r;
1560 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1561 t2, 0,
1562 t2, 1,
1563 V_SQ_ALU_SRC_LITERAL, 4,
1564 offset_reg, offset_chan);
1565 if (r)
1566 return r;
1567 offset_reg = t2;
1568 offset_chan = 0;
1569 index = src->Register.Index - first;
1570 }
1571
1572 memset(&vtx, 0, sizeof(vtx));
1573 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1574 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1575 vtx.src_gpr = offset_reg;
1576 vtx.src_sel_x = offset_chan;
1577 vtx.offset = index * 16; /*bytes*/
1578 vtx.mega_fetch_count = 16;
1579 vtx.dst_gpr = dst_reg;
1580 vtx.dst_sel_x = 0; /* SEL_X */
1581 vtx.dst_sel_y = 1; /* SEL_Y */
1582 vtx.dst_sel_z = 2; /* SEL_Z */
1583 vtx.dst_sel_w = 3; /* SEL_W */
1584 if (ctx->bc->chip_class >= EVERGREEN) {
1585 vtx.use_const_fields = 1;
1586 } else {
1587 vtx.data_format = FMT_32_32_32_32_FLOAT;
1588 }
1589
1590 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1591 return r;
1592
1593 return 0;
1594 }
1595
1596 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1597 {
1598 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1599 unsigned i;
1600
1601 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1602 struct tgsi_full_src_register *src = &inst->Src[i];
1603
1604 if (src->Register.File == TGSI_FILE_INPUT) {
1605 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1606 /* primitive id is in R0.z */
1607 ctx->src[i].sel = 0;
1608 ctx->src[i].swizzle[0] = 2;
1609 }
1610 }
1611 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1612 int treg = r600_get_temp(ctx);
1613
1614 fetch_gs_input(ctx, src, treg);
1615 ctx->src[i].sel = treg;
1616 ctx->src[i].rel = 0;
1617 }
1618 }
1619 return 0;
1620 }
1621
1622
1623 /* Tessellation shaders pass outputs to the next shader using LDS.
1624 *
1625 * LS outputs = TCS(HS) inputs
1626 * TCS(HS) outputs = TES(DS) inputs
1627 *
1628 * The LDS layout is:
1629 * - TCS inputs for patch 0
1630 * - TCS inputs for patch 1
1631 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1632 * - ...
1633 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1634 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1635 * - TCS outputs for patch 1
1636 * - Per-patch TCS outputs for patch 1
1637 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1638 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1639 * - ...
1640 *
1641 * All three shaders VS(LS), TCS, TES share the same LDS space.
1642 */
1643 /* this will return with the dw address in temp_reg.x */
1644 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1645 const struct tgsi_full_dst_register *dst,
1646 const struct tgsi_full_src_register *src,
1647 int stride_bytes_reg, int stride_bytes_chan)
1648 {
1649 struct tgsi_full_dst_register reg;
1650 ubyte *name, *index, *array_first;
1651 int r;
1652 int param;
1653 struct tgsi_shader_info *info = &ctx->info;
1654 /* Set the register description. The address computation is the same
1655 * for sources and destinations. */
1656 if (src) {
1657 reg.Register.File = src->Register.File;
1658 reg.Register.Index = src->Register.Index;
1659 reg.Register.Indirect = src->Register.Indirect;
1660 reg.Register.Dimension = src->Register.Dimension;
1661 reg.Indirect = src->Indirect;
1662 reg.Dimension = src->Dimension;
1663 reg.DimIndirect = src->DimIndirect;
1664 } else
1665 reg = *dst;
1666
1667 /* If the register is 2-dimensional (e.g. an array of vertices
1668 * in a primitive), calculate the base address of the vertex. */
1669 if (reg.Register.Dimension) {
1670 int sel, chan;
1671 if (reg.Dimension.Indirect) {
1672 unsigned addr_reg;
1673 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1674
1675 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1676 /* pull the value from index_reg */
1677 sel = addr_reg;
1678 chan = 0;
1679 } else {
1680 sel = V_SQ_ALU_SRC_LITERAL;
1681 chan = reg.Dimension.Index;
1682 }
1683
1684 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1685 temp_reg, 0,
1686 stride_bytes_reg, stride_bytes_chan,
1687 sel, chan,
1688 temp_reg, 0);
1689 if (r)
1690 return r;
1691 }
1692
1693 if (reg.Register.File == TGSI_FILE_INPUT) {
1694 name = info->input_semantic_name;
1695 index = info->input_semantic_index;
1696 array_first = info->input_array_first;
1697 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1698 name = info->output_semantic_name;
1699 index = info->output_semantic_index;
1700 array_first = info->output_array_first;
1701 } else {
1702 assert(0);
1703 return -1;
1704 }
1705 if (reg.Register.Indirect) {
1706 int addr_reg;
1707 int first;
1708 /* Add the relative address of the element. */
1709 if (reg.Indirect.ArrayID)
1710 first = array_first[reg.Indirect.ArrayID];
1711 else
1712 first = reg.Register.Index;
1713
1714 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1715
1716 /* pull the value from index_reg */
1717 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1718 temp_reg, 0,
1719 V_SQ_ALU_SRC_LITERAL, 16,
1720 addr_reg, 0,
1721 temp_reg, 0);
1722 if (r)
1723 return r;
1724
1725 param = r600_get_lds_unique_index(name[first],
1726 index[first]);
1727
1728 } else {
1729 param = r600_get_lds_unique_index(name[reg.Register.Index],
1730 index[reg.Register.Index]);
1731 }
1732
1733 /* add to base_addr - passed in temp_reg.x */
1734 if (param) {
1735 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1736 temp_reg, 0,
1737 temp_reg, 0,
1738 V_SQ_ALU_SRC_LITERAL, param * 16);
1739 if (r)
1740 return r;
1741
1742 }
1743 return 0;
1744 }
1745
1746 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1747 unsigned dst_reg)
1748 {
1749 struct r600_bytecode_alu alu;
1750 int r, i;
1751
1752 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1753 ctx->bc->force_add_cf = 1;
1754 for (i = 1; i < 4; i++) {
1755 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1756 temp_reg, i,
1757 temp_reg, 0,
1758 V_SQ_ALU_SRC_LITERAL, 4 * i);
1759 if (r)
1760 return r;
1761 }
1762 for (i = 0; i < 4; i++) {
1763 /* emit an LDS_READ_RET */
1764 memset(&alu, 0, sizeof(alu));
1765 alu.op = LDS_OP1_LDS_READ_RET;
1766 alu.src[0].sel = temp_reg;
1767 alu.src[0].chan = i;
1768 alu.src[1].sel = V_SQ_ALU_SRC_0;
1769 alu.src[2].sel = V_SQ_ALU_SRC_0;
1770 alu.dst.chan = 0;
1771 alu.is_lds_idx_op = true;
1772 alu.last = 1;
1773 r = r600_bytecode_add_alu(ctx->bc, &alu);
1774 if (r)
1775 return r;
1776 }
1777 for (i = 0; i < 4; i++) {
1778 /* then read from LDS_OQ_A_POP */
1779 memset(&alu, 0, sizeof(alu));
1780
1781 alu.op = ALU_OP1_MOV;
1782 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1783 alu.src[0].chan = 0;
1784 alu.dst.sel = dst_reg;
1785 alu.dst.chan = i;
1786 alu.dst.write = 1;
1787 alu.last = 1;
1788 r = r600_bytecode_add_alu(ctx->bc, &alu);
1789 if (r)
1790 return r;
1791 }
1792 return 0;
1793 }
1794
1795 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1796 {
1797 int r;
1798 unsigned temp_reg = r600_get_temp(ctx);
1799
1800 r = get_lds_offset0(ctx, 2, temp_reg,
1801 src->Register.Dimension ? false : true);
1802 if (r)
1803 return r;
1804
1805 /* the base address is now in temp.x */
1806 r = r600_get_byte_address(ctx, temp_reg,
1807 NULL, src, ctx->tess_output_info, 1);
1808 if (r)
1809 return r;
1810
1811 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1812 if (r)
1813 return r;
1814 return 0;
1815 }
1816
1817 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1818 {
1819 int r;
1820 unsigned temp_reg = r600_get_temp(ctx);
1821
1822 /* t.x = ips * r0.y */
1823 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1824 temp_reg, 0,
1825 ctx->tess_input_info, 0,
1826 0, 1);
1827
1828 if (r)
1829 return r;
1830
1831 /* the base address is now in temp.x */
1832 r = r600_get_byte_address(ctx, temp_reg,
1833 NULL, src, ctx->tess_input_info, 1);
1834 if (r)
1835 return r;
1836
1837 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1838 if (r)
1839 return r;
1840 return 0;
1841 }
1842
1843 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1844 {
1845 int r;
1846 unsigned temp_reg = r600_get_temp(ctx);
1847
1848 r = get_lds_offset0(ctx, 1, temp_reg,
1849 src->Register.Dimension ? false : true);
1850 if (r)
1851 return r;
1852 /* the base address is now in temp.x */
1853 r = r600_get_byte_address(ctx, temp_reg,
1854 NULL, src,
1855 ctx->tess_output_info, 1);
1856 if (r)
1857 return r;
1858
1859 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1860 if (r)
1861 return r;
1862 return 0;
1863 }
1864
1865 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1866 {
1867 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1868 unsigned i;
1869
1870 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1871 struct tgsi_full_src_register *src = &inst->Src[i];
1872
1873 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1874 int treg = r600_get_temp(ctx);
1875 fetch_tes_input(ctx, src, treg);
1876 ctx->src[i].sel = treg;
1877 ctx->src[i].rel = 0;
1878 }
1879 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1880 int treg = r600_get_temp(ctx);
1881 fetch_tcs_input(ctx, src, treg);
1882 ctx->src[i].sel = treg;
1883 ctx->src[i].rel = 0;
1884 }
1885 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1886 int treg = r600_get_temp(ctx);
1887 fetch_tcs_output(ctx, src, treg);
1888 ctx->src[i].sel = treg;
1889 ctx->src[i].rel = 0;
1890 }
1891 }
1892 return 0;
1893 }
1894
1895 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1896 {
1897 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1898 struct r600_bytecode_alu alu;
1899 int i, j, k, nconst, r;
1900
1901 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1902 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1903 nconst++;
1904 }
1905 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1906 }
1907 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1908 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1909 continue;
1910 }
1911
1912 if (ctx->src[i].rel) {
1913 int chan = inst->Src[i].Indirect.Swizzle;
1914 int treg = r600_get_temp(ctx);
1915 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1916 return r;
1917
1918 ctx->src[i].kc_bank = 0;
1919 ctx->src[i].kc_rel = 0;
1920 ctx->src[i].sel = treg;
1921 ctx->src[i].rel = 0;
1922 j--;
1923 } else if (j > 0) {
1924 int treg = r600_get_temp(ctx);
1925 for (k = 0; k < 4; k++) {
1926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1927 alu.op = ALU_OP1_MOV;
1928 alu.src[0].sel = ctx->src[i].sel;
1929 alu.src[0].chan = k;
1930 alu.src[0].rel = ctx->src[i].rel;
1931 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1932 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1933 alu.dst.sel = treg;
1934 alu.dst.chan = k;
1935 alu.dst.write = 1;
1936 if (k == 3)
1937 alu.last = 1;
1938 r = r600_bytecode_add_alu(ctx->bc, &alu);
1939 if (r)
1940 return r;
1941 }
1942 ctx->src[i].sel = treg;
1943 ctx->src[i].rel =0;
1944 j--;
1945 }
1946 }
1947 return 0;
1948 }
1949
1950 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1951 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1952 {
1953 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1954 struct r600_bytecode_alu alu;
1955 int i, j, k, nliteral, r;
1956
1957 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1958 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1959 nliteral++;
1960 }
1961 }
1962 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1963 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1964 int treg = r600_get_temp(ctx);
1965 for (k = 0; k < 4; k++) {
1966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1967 alu.op = ALU_OP1_MOV;
1968 alu.src[0].sel = ctx->src[i].sel;
1969 alu.src[0].chan = k;
1970 alu.src[0].value = ctx->src[i].value[k];
1971 alu.dst.sel = treg;
1972 alu.dst.chan = k;
1973 alu.dst.write = 1;
1974 if (k == 3)
1975 alu.last = 1;
1976 r = r600_bytecode_add_alu(ctx->bc, &alu);
1977 if (r)
1978 return r;
1979 }
1980 ctx->src[i].sel = treg;
1981 j--;
1982 }
1983 }
1984 return 0;
1985 }
1986
1987 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1988 {
1989 int i, r, count = ctx->shader->ninput;
1990
1991 for (i = 0; i < count; i++) {
1992 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1993 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1994 if (r)
1995 return r;
1996 }
1997 }
1998 return 0;
1999 }
2000
2001 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2002 int stream, unsigned *stream_item_size UNUSED)
2003 {
2004 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2005 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2006 int j, r;
2007 unsigned i;
2008
2009 /* Sanity checking. */
2010 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2011 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2012 r = -EINVAL;
2013 goto out_err;
2014 }
2015 for (i = 0; i < so->num_outputs; i++) {
2016 if (so->output[i].output_buffer >= 4) {
2017 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2018 so->output[i].output_buffer);
2019 r = -EINVAL;
2020 goto out_err;
2021 }
2022 }
2023
2024 /* Initialize locations where the outputs are stored. */
2025 for (i = 0; i < so->num_outputs; i++) {
2026
2027 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2028 start_comp[i] = so->output[i].start_component;
2029 /* Lower outputs with dst_offset < start_component.
2030 *
2031 * We can only output 4D vectors with a write mask, e.g. we can
2032 * only output the W component at offset 3, etc. If we want
2033 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2034 * to move it to X and output X. */
2035 if (so->output[i].dst_offset < so->output[i].start_component) {
2036 unsigned tmp = r600_get_temp(ctx);
2037
2038 for (j = 0; j < so->output[i].num_components; j++) {
2039 struct r600_bytecode_alu alu;
2040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2041 alu.op = ALU_OP1_MOV;
2042 alu.src[0].sel = so_gpr[i];
2043 alu.src[0].chan = so->output[i].start_component + j;
2044
2045 alu.dst.sel = tmp;
2046 alu.dst.chan = j;
2047 alu.dst.write = 1;
2048 if (j == so->output[i].num_components - 1)
2049 alu.last = 1;
2050 r = r600_bytecode_add_alu(ctx->bc, &alu);
2051 if (r)
2052 return r;
2053 }
2054 start_comp[i] = 0;
2055 so_gpr[i] = tmp;
2056 }
2057 }
2058
2059 /* Write outputs to buffers. */
2060 for (i = 0; i < so->num_outputs; i++) {
2061 struct r600_bytecode_output output;
2062
2063 if (stream != -1 && stream != so->output[i].output_buffer)
2064 continue;
2065
2066 memset(&output, 0, sizeof(struct r600_bytecode_output));
2067 output.gpr = so_gpr[i];
2068 output.elem_size = so->output[i].num_components - 1;
2069 if (output.elem_size == 2)
2070 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2071 output.array_base = so->output[i].dst_offset - start_comp[i];
2072 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2073 output.burst_count = 1;
2074 /* array_size is an upper limit for the burst_count
2075 * with MEM_STREAM instructions */
2076 output.array_size = 0xFFF;
2077 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2078
2079 if (ctx->bc->chip_class >= EVERGREEN) {
2080 switch (so->output[i].output_buffer) {
2081 case 0:
2082 output.op = CF_OP_MEM_STREAM0_BUF0;
2083 break;
2084 case 1:
2085 output.op = CF_OP_MEM_STREAM0_BUF1;
2086 break;
2087 case 2:
2088 output.op = CF_OP_MEM_STREAM0_BUF2;
2089 break;
2090 case 3:
2091 output.op = CF_OP_MEM_STREAM0_BUF3;
2092 break;
2093 }
2094 output.op += so->output[i].stream * 4;
2095 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2096 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2097 } else {
2098 switch (so->output[i].output_buffer) {
2099 case 0:
2100 output.op = CF_OP_MEM_STREAM0;
2101 break;
2102 case 1:
2103 output.op = CF_OP_MEM_STREAM1;
2104 break;
2105 case 2:
2106 output.op = CF_OP_MEM_STREAM2;
2107 break;
2108 case 3:
2109 output.op = CF_OP_MEM_STREAM3;
2110 break;
2111 }
2112 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2113 }
2114 r = r600_bytecode_add_output(ctx->bc, &output);
2115 if (r)
2116 goto out_err;
2117 }
2118 return 0;
2119 out_err:
2120 return r;
2121 }
2122
2123 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2124 {
2125 struct r600_bytecode_alu alu;
2126 unsigned reg;
2127
2128 if (!ctx->shader->vs_out_edgeflag)
2129 return;
2130
2131 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2132
2133 /* clamp(x, 0, 1) */
2134 memset(&alu, 0, sizeof(alu));
2135 alu.op = ALU_OP1_MOV;
2136 alu.src[0].sel = reg;
2137 alu.dst.sel = reg;
2138 alu.dst.write = 1;
2139 alu.dst.clamp = 1;
2140 alu.last = 1;
2141 r600_bytecode_add_alu(ctx->bc, &alu);
2142
2143 memset(&alu, 0, sizeof(alu));
2144 alu.op = ALU_OP1_FLT_TO_INT;
2145 alu.src[0].sel = reg;
2146 alu.dst.sel = reg;
2147 alu.dst.write = 1;
2148 alu.last = 1;
2149 r600_bytecode_add_alu(ctx->bc, &alu);
2150 }
2151
2152 static int generate_gs_copy_shader(struct r600_context *rctx,
2153 struct r600_pipe_shader *gs,
2154 struct pipe_stream_output_info *so)
2155 {
2156 struct r600_shader_ctx ctx = {};
2157 struct r600_shader *gs_shader = &gs->shader;
2158 struct r600_pipe_shader *cshader;
2159 unsigned ocnt = gs_shader->noutput;
2160 struct r600_bytecode_alu alu;
2161 struct r600_bytecode_vtx vtx;
2162 struct r600_bytecode_output output;
2163 struct r600_bytecode_cf *cf_jump, *cf_pop,
2164 *last_exp_pos = NULL, *last_exp_param = NULL;
2165 int next_clip_pos = 61, next_param = 0;
2166 unsigned i, j;
2167 int ring;
2168 bool only_ring_0 = true;
2169 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2170 if (!cshader)
2171 return 0;
2172
2173 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2174 sizeof(struct r600_shader_io));
2175
2176 cshader->shader.noutput = ocnt;
2177
2178 ctx.shader = &cshader->shader;
2179 ctx.bc = &ctx.shader->bc;
2180 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2181
2182 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2183 rctx->screen->has_compressed_msaa_texturing);
2184
2185 ctx.bc->isa = rctx->isa;
2186
2187 cf_jump = NULL;
2188 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2189
2190 /* R0.x = R0.x & 0x3fffffff */
2191 memset(&alu, 0, sizeof(alu));
2192 alu.op = ALU_OP2_AND_INT;
2193 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2194 alu.src[1].value = 0x3fffffff;
2195 alu.dst.write = 1;
2196 r600_bytecode_add_alu(ctx.bc, &alu);
2197
2198 /* R0.y = R0.x >> 30 */
2199 memset(&alu, 0, sizeof(alu));
2200 alu.op = ALU_OP2_LSHR_INT;
2201 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2202 alu.src[1].value = 0x1e;
2203 alu.dst.chan = 1;
2204 alu.dst.write = 1;
2205 alu.last = 1;
2206 r600_bytecode_add_alu(ctx.bc, &alu);
2207
2208 /* fetch vertex data from GSVS ring */
2209 for (i = 0; i < ocnt; ++i) {
2210 struct r600_shader_io *out = &ctx.shader->output[i];
2211
2212 out->gpr = i + 1;
2213 out->ring_offset = i * 16;
2214
2215 memset(&vtx, 0, sizeof(vtx));
2216 vtx.op = FETCH_OP_VFETCH;
2217 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2218 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2219 vtx.mega_fetch_count = 16;
2220 vtx.offset = out->ring_offset;
2221 vtx.dst_gpr = out->gpr;
2222 vtx.src_gpr = 0;
2223 vtx.dst_sel_x = 0;
2224 vtx.dst_sel_y = 1;
2225 vtx.dst_sel_z = 2;
2226 vtx.dst_sel_w = 3;
2227 if (rctx->b.chip_class >= EVERGREEN) {
2228 vtx.use_const_fields = 1;
2229 } else {
2230 vtx.data_format = FMT_32_32_32_32_FLOAT;
2231 }
2232
2233 r600_bytecode_add_vtx(ctx.bc, &vtx);
2234 }
2235 ctx.temp_reg = i + 1;
2236 for (ring = 3; ring >= 0; --ring) {
2237 bool enabled = false;
2238 for (i = 0; i < so->num_outputs; i++) {
2239 if (so->output[i].stream == ring) {
2240 enabled = true;
2241 if (ring > 0)
2242 only_ring_0 = false;
2243 break;
2244 }
2245 }
2246 if (ring != 0 && !enabled) {
2247 cshader->shader.ring_item_sizes[ring] = 0;
2248 continue;
2249 }
2250
2251 if (cf_jump) {
2252 // Patch up jump label
2253 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2254 cf_pop = ctx.bc->cf_last;
2255
2256 cf_jump->cf_addr = cf_pop->id + 2;
2257 cf_jump->pop_count = 1;
2258 cf_pop->cf_addr = cf_pop->id + 2;
2259 cf_pop->pop_count = 1;
2260 }
2261
2262 /* PRED_SETE_INT __, R0.y, ring */
2263 memset(&alu, 0, sizeof(alu));
2264 alu.op = ALU_OP2_PRED_SETE_INT;
2265 alu.src[0].chan = 1;
2266 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2267 alu.src[1].value = ring;
2268 alu.execute_mask = 1;
2269 alu.update_pred = 1;
2270 alu.last = 1;
2271 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2272
2273 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2274 cf_jump = ctx.bc->cf_last;
2275
2276 if (enabled)
2277 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2278 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2279 }
2280
2281 /* bc adds nops - copy it */
2282 if (ctx.bc->chip_class == R600) {
2283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2284 alu.op = ALU_OP0_NOP;
2285 alu.last = 1;
2286 r600_bytecode_add_alu(ctx.bc, &alu);
2287
2288 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2289 }
2290
2291 /* export vertex data */
2292 /* XXX factor out common code with r600_shader_from_tgsi ? */
2293 for (i = 0; i < ocnt; ++i) {
2294 struct r600_shader_io *out = &ctx.shader->output[i];
2295 bool instream0 = true;
2296 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2297 continue;
2298
2299 for (j = 0; j < so->num_outputs; j++) {
2300 if (so->output[j].register_index == i) {
2301 if (so->output[j].stream == 0)
2302 break;
2303 if (so->output[j].stream > 0)
2304 instream0 = false;
2305 }
2306 }
2307 if (!instream0)
2308 continue;
2309 memset(&output, 0, sizeof(output));
2310 output.gpr = out->gpr;
2311 output.elem_size = 3;
2312 output.swizzle_x = 0;
2313 output.swizzle_y = 1;
2314 output.swizzle_z = 2;
2315 output.swizzle_w = 3;
2316 output.burst_count = 1;
2317 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2318 output.op = CF_OP_EXPORT;
2319 switch (out->name) {
2320 case TGSI_SEMANTIC_POSITION:
2321 output.array_base = 60;
2322 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2323 break;
2324
2325 case TGSI_SEMANTIC_PSIZE:
2326 output.array_base = 61;
2327 if (next_clip_pos == 61)
2328 next_clip_pos = 62;
2329 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2330 output.swizzle_y = 7;
2331 output.swizzle_z = 7;
2332 output.swizzle_w = 7;
2333 ctx.shader->vs_out_misc_write = 1;
2334 ctx.shader->vs_out_point_size = 1;
2335 break;
2336 case TGSI_SEMANTIC_LAYER:
2337 if (out->spi_sid) {
2338 /* duplicate it as PARAM to pass to the pixel shader */
2339 output.array_base = next_param++;
2340 r600_bytecode_add_output(ctx.bc, &output);
2341 last_exp_param = ctx.bc->cf_last;
2342 }
2343 output.array_base = 61;
2344 if (next_clip_pos == 61)
2345 next_clip_pos = 62;
2346 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2347 output.swizzle_x = 7;
2348 output.swizzle_y = 7;
2349 output.swizzle_z = 0;
2350 output.swizzle_w = 7;
2351 ctx.shader->vs_out_misc_write = 1;
2352 ctx.shader->vs_out_layer = 1;
2353 break;
2354 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2355 if (out->spi_sid) {
2356 /* duplicate it as PARAM to pass to the pixel shader */
2357 output.array_base = next_param++;
2358 r600_bytecode_add_output(ctx.bc, &output);
2359 last_exp_param = ctx.bc->cf_last;
2360 }
2361 output.array_base = 61;
2362 if (next_clip_pos == 61)
2363 next_clip_pos = 62;
2364 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2365 ctx.shader->vs_out_misc_write = 1;
2366 ctx.shader->vs_out_viewport = 1;
2367 output.swizzle_x = 7;
2368 output.swizzle_y = 7;
2369 output.swizzle_z = 7;
2370 output.swizzle_w = 0;
2371 break;
2372 case TGSI_SEMANTIC_CLIPDIST:
2373 /* spi_sid is 0 for clipdistance outputs that were generated
2374 * for clipvertex - we don't need to pass them to PS */
2375 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2376 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2377 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2378 if (out->spi_sid) {
2379 /* duplicate it as PARAM to pass to the pixel shader */
2380 output.array_base = next_param++;
2381 r600_bytecode_add_output(ctx.bc, &output);
2382 last_exp_param = ctx.bc->cf_last;
2383 }
2384 output.array_base = next_clip_pos++;
2385 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2386 break;
2387 case TGSI_SEMANTIC_FOG:
2388 output.swizzle_y = 4; /* 0 */
2389 output.swizzle_z = 4; /* 0 */
2390 output.swizzle_w = 5; /* 1 */
2391 break;
2392 default:
2393 output.array_base = next_param++;
2394 break;
2395 }
2396 r600_bytecode_add_output(ctx.bc, &output);
2397 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2398 last_exp_param = ctx.bc->cf_last;
2399 else
2400 last_exp_pos = ctx.bc->cf_last;
2401 }
2402
2403 if (!last_exp_pos) {
2404 memset(&output, 0, sizeof(output));
2405 output.gpr = 0;
2406 output.elem_size = 3;
2407 output.swizzle_x = 7;
2408 output.swizzle_y = 7;
2409 output.swizzle_z = 7;
2410 output.swizzle_w = 7;
2411 output.burst_count = 1;
2412 output.type = 2;
2413 output.op = CF_OP_EXPORT;
2414 output.array_base = 60;
2415 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2416 r600_bytecode_add_output(ctx.bc, &output);
2417 last_exp_pos = ctx.bc->cf_last;
2418 }
2419
2420 if (!last_exp_param) {
2421 memset(&output, 0, sizeof(output));
2422 output.gpr = 0;
2423 output.elem_size = 3;
2424 output.swizzle_x = 7;
2425 output.swizzle_y = 7;
2426 output.swizzle_z = 7;
2427 output.swizzle_w = 7;
2428 output.burst_count = 1;
2429 output.type = 2;
2430 output.op = CF_OP_EXPORT;
2431 output.array_base = next_param++;
2432 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2433 r600_bytecode_add_output(ctx.bc, &output);
2434 last_exp_param = ctx.bc->cf_last;
2435 }
2436
2437 last_exp_pos->op = CF_OP_EXPORT_DONE;
2438 last_exp_param->op = CF_OP_EXPORT_DONE;
2439
2440 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2441 cf_pop = ctx.bc->cf_last;
2442
2443 cf_jump->cf_addr = cf_pop->id + 2;
2444 cf_jump->pop_count = 1;
2445 cf_pop->cf_addr = cf_pop->id + 2;
2446 cf_pop->pop_count = 1;
2447
2448 if (ctx.bc->chip_class == CAYMAN)
2449 cm_bytecode_add_cf_end(ctx.bc);
2450 else {
2451 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2452 ctx.bc->cf_last->end_of_program = 1;
2453 }
2454
2455 gs->gs_copy_shader = cshader;
2456 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2457
2458 ctx.bc->nstack = 1;
2459
2460 return r600_bytecode_build(ctx.bc);
2461 }
2462
2463 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2464 {
2465 if (ind) {
2466 struct r600_bytecode_alu alu;
2467 int r;
2468
2469 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2470 alu.op = ALU_OP2_ADD_INT;
2471 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2472 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2473 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2474 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2475 alu.dst.write = 1;
2476 alu.last = 1;
2477 r = r600_bytecode_add_alu(ctx->bc, &alu);
2478 if (r)
2479 return r;
2480 }
2481 return 0;
2482 }
2483
2484 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2485 {
2486 struct r600_bytecode_output output;
2487 int ring_offset;
2488 unsigned i, k;
2489 int effective_stream = stream == -1 ? 0 : stream;
2490 int idx = 0;
2491
2492 for (i = 0; i < ctx->shader->noutput; i++) {
2493 if (ctx->gs_for_vs) {
2494 /* for ES we need to lookup corresponding ring offset expected by GS
2495 * (map this output to GS input by name and sid) */
2496 /* FIXME precompute offsets */
2497 ring_offset = -1;
2498 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2499 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2500 struct r600_shader_io *out = &ctx->shader->output[i];
2501 if (in->name == out->name && in->sid == out->sid)
2502 ring_offset = in->ring_offset;
2503 }
2504
2505 if (ring_offset == -1)
2506 continue;
2507 } else {
2508 ring_offset = idx * 16;
2509 idx++;
2510 }
2511
2512 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2513 continue;
2514 /* next_ring_offset after parsing input decls contains total size of
2515 * single vertex data, gs_next_vertex - current vertex index */
2516 if (!ind)
2517 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2518
2519 memset(&output, 0, sizeof(struct r600_bytecode_output));
2520 output.gpr = ctx->shader->output[i].gpr;
2521 output.elem_size = 3;
2522 output.comp_mask = 0xF;
2523 output.burst_count = 1;
2524
2525 if (ind)
2526 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2527 else
2528 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2529
2530 switch (stream) {
2531 default:
2532 case 0:
2533 output.op = CF_OP_MEM_RING; break;
2534 case 1:
2535 output.op = CF_OP_MEM_RING1; break;
2536 case 2:
2537 output.op = CF_OP_MEM_RING2; break;
2538 case 3:
2539 output.op = CF_OP_MEM_RING3; break;
2540 }
2541
2542 if (ind) {
2543 output.array_base = ring_offset >> 2; /* in dwords */
2544 output.array_size = 0xfff;
2545 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2546 } else
2547 output.array_base = ring_offset >> 2; /* in dwords */
2548 r600_bytecode_add_output(ctx->bc, &output);
2549 }
2550
2551 ++ctx->gs_next_vertex;
2552 return 0;
2553 }
2554
2555
2556 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2557 {
2558 int r;
2559 struct r600_bytecode_vtx vtx;
2560 int temp_val = ctx->temp_reg;
2561 /* need to store the TCS output somewhere */
2562 r = single_alu_op2(ctx, ALU_OP1_MOV,
2563 temp_val, 0,
2564 V_SQ_ALU_SRC_LITERAL, 0,
2565 0, 0);
2566 if (r)
2567 return r;
2568
2569 /* used by VS/TCS */
2570 if (ctx->tess_input_info) {
2571 /* fetch tcs input values into resv space */
2572 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2573 vtx.op = FETCH_OP_VFETCH;
2574 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2575 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2576 vtx.mega_fetch_count = 16;
2577 vtx.data_format = FMT_32_32_32_32;
2578 vtx.num_format_all = 2;
2579 vtx.format_comp_all = 1;
2580 vtx.use_const_fields = 0;
2581 vtx.endian = r600_endian_swap(32);
2582 vtx.srf_mode_all = 1;
2583 vtx.offset = 0;
2584 vtx.dst_gpr = ctx->tess_input_info;
2585 vtx.dst_sel_x = 0;
2586 vtx.dst_sel_y = 1;
2587 vtx.dst_sel_z = 2;
2588 vtx.dst_sel_w = 3;
2589 vtx.src_gpr = temp_val;
2590 vtx.src_sel_x = 0;
2591
2592 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2593 if (r)
2594 return r;
2595 }
2596
2597 /* used by TCS/TES */
2598 if (ctx->tess_output_info) {
2599 /* fetch tcs output values into resv space */
2600 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2601 vtx.op = FETCH_OP_VFETCH;
2602 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2603 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2604 vtx.mega_fetch_count = 16;
2605 vtx.data_format = FMT_32_32_32_32;
2606 vtx.num_format_all = 2;
2607 vtx.format_comp_all = 1;
2608 vtx.use_const_fields = 0;
2609 vtx.endian = r600_endian_swap(32);
2610 vtx.srf_mode_all = 1;
2611 vtx.offset = 16;
2612 vtx.dst_gpr = ctx->tess_output_info;
2613 vtx.dst_sel_x = 0;
2614 vtx.dst_sel_y = 1;
2615 vtx.dst_sel_z = 2;
2616 vtx.dst_sel_w = 3;
2617 vtx.src_gpr = temp_val;
2618 vtx.src_sel_x = 0;
2619
2620 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2621 if (r)
2622 return r;
2623 }
2624 return 0;
2625 }
2626
2627 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2628 {
2629 int j, r;
2630 int temp_reg;
2631 unsigned i;
2632
2633 /* fetch tcs input values into input_vals */
2634 ctx->tess_input_info = r600_get_temp(ctx);
2635 ctx->tess_output_info = 0;
2636 r = r600_fetch_tess_io_info(ctx);
2637 if (r)
2638 return r;
2639
2640 temp_reg = r600_get_temp(ctx);
2641 /* dst reg contains LDS address stride * idx */
2642 /* MUL vertexID, vertex_dw_stride */
2643 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2644 temp_reg, 0,
2645 ctx->tess_input_info, 1,
2646 0, 1); /* rel id in r0.y? */
2647 if (r)
2648 return r;
2649
2650 for (i = 0; i < ctx->shader->noutput; i++) {
2651 struct r600_bytecode_alu alu;
2652 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2653
2654 if (param) {
2655 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2656 temp_reg, 1,
2657 temp_reg, 0,
2658 V_SQ_ALU_SRC_LITERAL, param * 16);
2659 if (r)
2660 return r;
2661 }
2662
2663 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2664 temp_reg, 2,
2665 temp_reg, param ? 1 : 0,
2666 V_SQ_ALU_SRC_LITERAL, 8);
2667 if (r)
2668 return r;
2669
2670
2671 for (j = 0; j < 2; j++) {
2672 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2673 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2674 alu.op = LDS_OP3_LDS_WRITE_REL;
2675 alu.src[0].sel = temp_reg;
2676 alu.src[0].chan = chan;
2677 alu.src[1].sel = ctx->shader->output[i].gpr;
2678 alu.src[1].chan = j * 2;
2679 alu.src[2].sel = ctx->shader->output[i].gpr;
2680 alu.src[2].chan = (j * 2) + 1;
2681 alu.last = 1;
2682 alu.dst.chan = 0;
2683 alu.lds_idx = 1;
2684 alu.is_lds_idx_op = true;
2685 r = r600_bytecode_add_alu(ctx->bc, &alu);
2686 if (r)
2687 return r;
2688 }
2689 }
2690 return 0;
2691 }
2692
2693 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2694 {
2695 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2696 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2697 int i, r, lasti;
2698 int temp_reg = r600_get_temp(ctx);
2699 struct r600_bytecode_alu alu;
2700 unsigned write_mask = dst->Register.WriteMask;
2701
2702 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2703 return 0;
2704
2705 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2706 if (r)
2707 return r;
2708
2709 /* the base address is now in temp.x */
2710 r = r600_get_byte_address(ctx, temp_reg,
2711 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2712 if (r)
2713 return r;
2714
2715 /* LDS write */
2716 lasti = tgsi_last_instruction(write_mask);
2717 for (i = 1; i <= lasti; i++) {
2718
2719 if (!(write_mask & (1 << i)))
2720 continue;
2721 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2722 temp_reg, i,
2723 temp_reg, 0,
2724 V_SQ_ALU_SRC_LITERAL, 4 * i);
2725 if (r)
2726 return r;
2727 }
2728
2729 for (i = 0; i <= lasti; i++) {
2730 if (!(write_mask & (1 << i)))
2731 continue;
2732
2733 if ((i == 0 && ((write_mask & 3) == 3)) ||
2734 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2736 alu.op = LDS_OP3_LDS_WRITE_REL;
2737 alu.src[0].sel = temp_reg;
2738 alu.src[0].chan = i;
2739
2740 alu.src[1].sel = dst->Register.Index;
2741 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2742 alu.src[1].chan = i;
2743
2744 alu.src[2].sel = dst->Register.Index;
2745 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2746 alu.src[2].chan = i + 1;
2747 alu.lds_idx = 1;
2748 alu.dst.chan = 0;
2749 alu.last = 1;
2750 alu.is_lds_idx_op = true;
2751 r = r600_bytecode_add_alu(ctx->bc, &alu);
2752 if (r)
2753 return r;
2754 i += 1;
2755 continue;
2756 }
2757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2758 alu.op = LDS_OP2_LDS_WRITE;
2759 alu.src[0].sel = temp_reg;
2760 alu.src[0].chan = i;
2761
2762 alu.src[1].sel = dst->Register.Index;
2763 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2764 alu.src[1].chan = i;
2765
2766 alu.src[2].sel = V_SQ_ALU_SRC_0;
2767 alu.dst.chan = 0;
2768 alu.last = 1;
2769 alu.is_lds_idx_op = true;
2770 r = r600_bytecode_add_alu(ctx->bc, &alu);
2771 if (r)
2772 return r;
2773 }
2774 return 0;
2775 }
2776
2777 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2778 int output_idx)
2779 {
2780 int param;
2781 unsigned temp_reg = r600_get_temp(ctx);
2782 unsigned name = ctx->shader->output[output_idx].name;
2783 int dreg = ctx->shader->output[output_idx].gpr;
2784 int r;
2785
2786 param = r600_get_lds_unique_index(name, 0);
2787 r = get_lds_offset0(ctx, 1, temp_reg, true);
2788 if (r)
2789 return r;
2790
2791 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2792 temp_reg, 0,
2793 temp_reg, 0,
2794 V_SQ_ALU_SRC_LITERAL, param * 16);
2795 if (r)
2796 return r;
2797
2798 do_lds_fetch_values(ctx, temp_reg, dreg);
2799 return 0;
2800 }
2801
2802 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2803 {
2804 int stride, outer_comps, inner_comps;
2805 int tessinner_idx = -1, tessouter_idx = -1;
2806 int i, r;
2807 unsigned j;
2808 int temp_reg = r600_get_temp(ctx);
2809 int treg[3] = {-1, -1, -1};
2810 struct r600_bytecode_alu alu;
2811 struct r600_bytecode_cf *cf_jump, *cf_pop;
2812
2813 /* only execute factor emission for invocation 0 */
2814 /* PRED_SETE_INT __, R0.x, 0 */
2815 memset(&alu, 0, sizeof(alu));
2816 alu.op = ALU_OP2_PRED_SETE_INT;
2817 alu.src[0].chan = 2;
2818 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2819 alu.execute_mask = 1;
2820 alu.update_pred = 1;
2821 alu.last = 1;
2822 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2823
2824 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2825 cf_jump = ctx->bc->cf_last;
2826
2827 treg[0] = r600_get_temp(ctx);
2828 switch (ctx->shader->tcs_prim_mode) {
2829 case PIPE_PRIM_LINES:
2830 stride = 8; /* 2 dwords, 1 vec2 store */
2831 outer_comps = 2;
2832 inner_comps = 0;
2833 break;
2834 case PIPE_PRIM_TRIANGLES:
2835 stride = 16; /* 4 dwords, 1 vec4 store */
2836 outer_comps = 3;
2837 inner_comps = 1;
2838 treg[1] = r600_get_temp(ctx);
2839 break;
2840 case PIPE_PRIM_QUADS:
2841 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2842 outer_comps = 4;
2843 inner_comps = 2;
2844 treg[1] = r600_get_temp(ctx);
2845 treg[2] = r600_get_temp(ctx);
2846 break;
2847 default:
2848 assert(0);
2849 return -1;
2850 }
2851
2852 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2853 /* TF_WRITE takes index in R.x, value in R.y */
2854 for (j = 0; j < ctx->shader->noutput; j++) {
2855 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
2856 tessinner_idx = j;
2857 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
2858 tessouter_idx = j;
2859 }
2860
2861 if (tessouter_idx == -1)
2862 return -1;
2863
2864 if (tessinner_idx == -1 && inner_comps)
2865 return -1;
2866
2867 if (tessouter_idx != -1) {
2868 r = r600_tess_factor_read(ctx, tessouter_idx);
2869 if (r)
2870 return r;
2871 }
2872
2873 if (tessinner_idx != -1) {
2874 r = r600_tess_factor_read(ctx, tessinner_idx);
2875 if (r)
2876 return r;
2877 }
2878
2879 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2880 /* r.x = relpatchid(r0.y) * tf_stride */
2881
2882 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2883 /* add incoming r0.w to it: t.x = t.x + r0.w */
2884 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2885 temp_reg, 0,
2886 0, 1,
2887 V_SQ_ALU_SRC_LITERAL, stride,
2888 0, 3);
2889 if (r)
2890 return r;
2891
2892 for (i = 0; i < outer_comps + inner_comps; i++) {
2893 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2894 int out_comp = i >= outer_comps ? i - outer_comps : i;
2895
2896 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2897 if (out_comp == 1)
2898 out_comp = 0;
2899 else if (out_comp == 0)
2900 out_comp = 1;
2901 }
2902
2903 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2904 treg[i / 2], (2 * (i % 2)),
2905 temp_reg, 0,
2906 V_SQ_ALU_SRC_LITERAL, 4 * i);
2907 if (r)
2908 return r;
2909 r = single_alu_op2(ctx, ALU_OP1_MOV,
2910 treg[i / 2], 1 + (2 * (i%2)),
2911 ctx->shader->output[out_idx].gpr, out_comp,
2912 0, 0);
2913 if (r)
2914 return r;
2915 }
2916 for (i = 0; i < outer_comps + inner_comps; i++) {
2917 struct r600_bytecode_gds gds;
2918
2919 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2920 gds.src_gpr = treg[i / 2];
2921 gds.src_sel_x = 2 * (i % 2);
2922 gds.src_sel_y = 1 + (2 * (i % 2));
2923 gds.src_sel_z = 4;
2924 gds.dst_sel_x = 7;
2925 gds.dst_sel_y = 7;
2926 gds.dst_sel_z = 7;
2927 gds.dst_sel_w = 7;
2928 gds.op = FETCH_OP_TF_WRITE;
2929 r = r600_bytecode_add_gds(ctx->bc, &gds);
2930 if (r)
2931 return r;
2932 }
2933
2934 // Patch up jump label
2935 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2936 cf_pop = ctx->bc->cf_last;
2937
2938 cf_jump->cf_addr = cf_pop->id + 2;
2939 cf_jump->pop_count = 1;
2940 cf_pop->cf_addr = cf_pop->id + 2;
2941 cf_pop->pop_count = 1;
2942
2943 return 0;
2944 }
2945
2946 /*
2947 * We have to work out the thread ID for load and atomic
2948 * operations, which store the returned value to an index
2949 * in an intermediate buffer.
2950 * The index is calculated by taking the thread id,
2951 * calculated from the MBCNT instructions.
2952 * Then the shader engine ID is multiplied by 256,
2953 * and the wave id is added.
2954 * Then the result is multipled by 64 and thread id is
2955 * added.
2956 */
2957 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
2958 {
2959 struct r600_bytecode_alu alu;
2960 int r;
2961
2962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2963 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
2964 alu.dst.sel = ctx->temp_reg;
2965 alu.dst.chan = 0;
2966 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2967 alu.src[0].value = 0xffffffff;
2968 alu.dst.write = 1;
2969 r = r600_bytecode_add_alu(ctx->bc, &alu);
2970 if (r)
2971 return r;
2972
2973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2974 alu.op = ALU_OP1_MBCNT_32HI_INT;
2975 alu.dst.sel = ctx->temp_reg;
2976 alu.dst.chan = 1;
2977 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2978 alu.src[0].value = 0xffffffff;
2979 alu.dst.write = 1;
2980 r = r600_bytecode_add_alu(ctx->bc, &alu);
2981 if (r)
2982 return r;
2983
2984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2985 alu.op = ALU_OP3_MULADD_UINT24;
2986 alu.dst.sel = ctx->temp_reg;
2987 alu.dst.chan = 2;
2988 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
2989 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2990 alu.src[1].value = 256;
2991 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
2992 alu.dst.write = 1;
2993 alu.is_op3 = 1;
2994 alu.last = 1;
2995 r = r600_bytecode_add_alu(ctx->bc, &alu);
2996 if (r)
2997 return r;
2998
2999 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3000 ctx->thread_id_gpr, 1,
3001 ctx->temp_reg, 2,
3002 V_SQ_ALU_SRC_LITERAL, 0x40,
3003 ctx->temp_reg, 0);
3004 if (r)
3005 return r;
3006 return 0;
3007 }
3008
3009 static int r600_shader_from_tgsi(struct r600_context *rctx,
3010 struct r600_pipe_shader *pipeshader,
3011 union r600_shader_key key)
3012 {
3013 struct r600_screen *rscreen = rctx->screen;
3014 struct r600_shader *shader = &pipeshader->shader;
3015 struct tgsi_token *tokens = pipeshader->selector->tokens;
3016 struct pipe_stream_output_info so = pipeshader->selector->so;
3017 struct tgsi_full_immediate *immediate;
3018 struct r600_shader_ctx ctx;
3019 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3020 unsigned output_done, noutput;
3021 unsigned opcode;
3022 int j, k, r = 0;
3023 unsigned i;
3024 int next_param_base = 0, next_clip_base;
3025 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3026 bool indirect_gprs;
3027 bool ring_outputs = false;
3028 bool lds_outputs = false;
3029 bool lds_inputs = false;
3030 bool pos_emitted = false;
3031
3032 ctx.bc = &shader->bc;
3033 ctx.shader = shader;
3034 ctx.native_integers = true;
3035
3036 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3037 rscreen->has_compressed_msaa_texturing);
3038 ctx.tokens = tokens;
3039 tgsi_scan_shader(tokens, &ctx.info);
3040 shader->indirect_files = ctx.info.indirect_files;
3041
3042 shader->uses_doubles = ctx.info.uses_doubles;
3043 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3044 shader->nsys_inputs = 0;
3045
3046 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0;
3047 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3048 tgsi_parse_init(&ctx.parse, tokens);
3049 ctx.type = ctx.info.processor;
3050 shader->processor_type = ctx.type;
3051 ctx.bc->type = shader->processor_type;
3052
3053 switch (ctx.type) {
3054 case PIPE_SHADER_VERTEX:
3055 shader->vs_as_gs_a = key.vs.as_gs_a;
3056 shader->vs_as_es = key.vs.as_es;
3057 shader->vs_as_ls = key.vs.as_ls;
3058 shader->atomic_base = key.vs.first_atomic_counter;
3059 if (shader->vs_as_es)
3060 ring_outputs = true;
3061 if (shader->vs_as_ls)
3062 lds_outputs = true;
3063 break;
3064 case PIPE_SHADER_GEOMETRY:
3065 ring_outputs = true;
3066 shader->atomic_base = key.gs.first_atomic_counter;
3067 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3068 break;
3069 case PIPE_SHADER_TESS_CTRL:
3070 shader->tcs_prim_mode = key.tcs.prim_mode;
3071 shader->atomic_base = key.tcs.first_atomic_counter;
3072 lds_outputs = true;
3073 lds_inputs = true;
3074 break;
3075 case PIPE_SHADER_TESS_EVAL:
3076 shader->tes_as_es = key.tes.as_es;
3077 shader->atomic_base = key.tes.first_atomic_counter;
3078 lds_inputs = true;
3079 if (shader->tes_as_es)
3080 ring_outputs = true;
3081 break;
3082 case PIPE_SHADER_FRAGMENT:
3083 shader->two_side = key.ps.color_two_side;
3084 shader->atomic_base = key.ps.first_atomic_counter;
3085 shader->rat_base = key.ps.nr_cbufs;
3086 shader->image_size_const_offset = key.ps.image_size_const_offset;
3087 break;
3088 default:
3089 break;
3090 }
3091
3092 if (shader->vs_as_es || shader->tes_as_es) {
3093 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3094 } else {
3095 ctx.gs_for_vs = NULL;
3096 }
3097
3098 ctx.next_ring_offset = 0;
3099 ctx.gs_out_ring_offset = 0;
3100 ctx.gs_next_vertex = 0;
3101 ctx.gs_stream_output_info = &so;
3102
3103 ctx.face_gpr = -1;
3104 ctx.fixed_pt_position_gpr = -1;
3105 ctx.fragcoord_input = -1;
3106 ctx.colors_used = 0;
3107 ctx.clip_vertex_write = 0;
3108
3109 shader->nr_ps_color_exports = 0;
3110 shader->nr_ps_max_color_exports = 0;
3111
3112
3113 /* register allocations */
3114 /* Values [0,127] correspond to GPR[0..127].
3115 * Values [128,159] correspond to constant buffer bank 0
3116 * Values [160,191] correspond to constant buffer bank 1
3117 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3118 * Values [256,287] correspond to constant buffer bank 2 (EG)
3119 * Values [288,319] correspond to constant buffer bank 3 (EG)
3120 * Other special values are shown in the list below.
3121 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3122 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3123 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3124 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3125 * 248 SQ_ALU_SRC_0: special constant 0.0.
3126 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3127 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3128 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3129 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3130 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3131 * 254 SQ_ALU_SRC_PV: previous vector result.
3132 * 255 SQ_ALU_SRC_PS: previous scalar result.
3133 */
3134 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3135 ctx.file_offset[i] = 0;
3136 }
3137
3138 if (ctx.type == PIPE_SHADER_VERTEX) {
3139
3140 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3141 if (ctx.info.num_inputs)
3142 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3143 }
3144 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3145 if (ctx.bc->chip_class >= EVERGREEN)
3146 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3147 else
3148 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3149 }
3150 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3151 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3152 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3153 }
3154 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3155 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3156 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3157 bool add_tesscoord = false, add_tess_inout = false;
3158 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3159 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3160 /* if we have tesscoord save one reg */
3161 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3162 add_tesscoord = true;
3163 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3164 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3165 add_tess_inout = true;
3166 }
3167 if (add_tesscoord || add_tess_inout)
3168 ctx.file_offset[TGSI_FILE_INPUT]++;
3169 if (add_tess_inout)
3170 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3171 }
3172
3173 ctx.file_offset[TGSI_FILE_OUTPUT] =
3174 ctx.file_offset[TGSI_FILE_INPUT] +
3175 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3176 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3177 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3178
3179 /* Outside the GPR range. This will be translated to one of the
3180 * kcache banks later. */
3181 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3182
3183 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3184 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3185 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3186 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3187 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3188
3189 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3190 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3191 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3192 ctx.temp_reg = ctx.bc->ar_reg + 5;
3193 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3194 ctx.tess_input_info = 0;
3195 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3196 ctx.temp_reg = ctx.bc->ar_reg + 4;
3197 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3198 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3199 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3200 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3201 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3202 ctx.temp_reg = ctx.bc->ar_reg + 7;
3203 if (ctx.shader->gs_tri_strip_adj_fix) {
3204 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3205 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3206 ctx.temp_reg += 2;
3207 } else {
3208 ctx.gs_rotated_input[0] = 0;
3209 ctx.gs_rotated_input[1] = 1;
3210 }
3211 } else {
3212 ctx.temp_reg = ctx.bc->ar_reg + 3;
3213 }
3214
3215 if (shader->uses_images && ctx.type == PIPE_SHADER_FRAGMENT) {
3216 ctx.thread_id_gpr = ctx.temp_reg;
3217 ctx.temp_reg++;
3218 } else
3219 ctx.thread_id_gpr = 0;
3220
3221 shader->max_arrays = 0;
3222 shader->num_arrays = 0;
3223 if (indirect_gprs) {
3224
3225 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3226 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3227 ctx.file_offset[TGSI_FILE_OUTPUT] -
3228 ctx.file_offset[TGSI_FILE_INPUT],
3229 0x0F);
3230 }
3231 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3232 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3233 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3234 ctx.file_offset[TGSI_FILE_OUTPUT],
3235 0x0F);
3236 }
3237 }
3238
3239 ctx.nliterals = 0;
3240 ctx.literals = NULL;
3241
3242 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3243 ctx.info.colors_written == 1;
3244 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3245 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3246
3247 if (ctx.type == PIPE_SHADER_VERTEX ||
3248 ctx.type == PIPE_SHADER_GEOMETRY ||
3249 ctx.type == PIPE_SHADER_TESS_EVAL) {
3250 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3251 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3252 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3253 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3254 }
3255
3256 if (shader->vs_as_gs_a)
3257 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3258
3259 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3260 r600_fetch_tess_io_info(&ctx);
3261
3262 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3263 tgsi_parse_token(&ctx.parse);
3264 switch (ctx.parse.FullToken.Token.Type) {
3265 case TGSI_TOKEN_TYPE_IMMEDIATE:
3266 immediate = &ctx.parse.FullToken.FullImmediate;
3267 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3268 if(ctx.literals == NULL) {
3269 r = -ENOMEM;
3270 goto out_err;
3271 }
3272 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3273 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3274 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3275 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3276 ctx.nliterals++;
3277 break;
3278 case TGSI_TOKEN_TYPE_DECLARATION:
3279 r = tgsi_declaration(&ctx);
3280 if (r)
3281 goto out_err;
3282 break;
3283 case TGSI_TOKEN_TYPE_INSTRUCTION:
3284 case TGSI_TOKEN_TYPE_PROPERTY:
3285 break;
3286 default:
3287 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3288 r = -EINVAL;
3289 goto out_err;
3290 }
3291 }
3292
3293 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3294 shader->ring_item_sizes[1] = 0;
3295 shader->ring_item_sizes[2] = 0;
3296 shader->ring_item_sizes[3] = 0;
3297
3298 /* Process two side if needed */
3299 if (shader->two_side && ctx.colors_used) {
3300 int i, count = ctx.shader->ninput;
3301 unsigned next_lds_loc = ctx.shader->nlds;
3302
3303 /* additional inputs will be allocated right after the existing inputs,
3304 * we won't need them after the color selection, so we don't need to
3305 * reserve these gprs for the rest of the shader code and to adjust
3306 * output offsets etc. */
3307 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3308 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3309
3310 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3311 if (ctx.face_gpr == -1) {
3312 i = ctx.shader->ninput++;
3313 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3314 ctx.shader->input[i].spi_sid = 0;
3315 ctx.shader->input[i].gpr = gpr++;
3316 ctx.face_gpr = ctx.shader->input[i].gpr;
3317 }
3318
3319 for (i = 0; i < count; i++) {
3320 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3321 int ni = ctx.shader->ninput++;
3322 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3323 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3324 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3325 ctx.shader->input[ni].gpr = gpr++;
3326 // TGSI to LLVM needs to know the lds position of inputs.
3327 // Non LLVM path computes it later (in process_twoside_color)
3328 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3329 ctx.shader->input[i].back_color_input = ni;
3330 if (ctx.bc->chip_class >= EVERGREEN) {
3331 if ((r = evergreen_interp_input(&ctx, ni)))
3332 return r;
3333 }
3334 }
3335 }
3336 }
3337
3338 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3339 shader->nr_ps_max_color_exports = 8;
3340
3341 if (ctx.fragcoord_input >= 0) {
3342 if (ctx.bc->chip_class == CAYMAN) {
3343 for (j = 0 ; j < 4; j++) {
3344 struct r600_bytecode_alu alu;
3345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3346 alu.op = ALU_OP1_RECIP_IEEE;
3347 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3348 alu.src[0].chan = 3;
3349
3350 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3351 alu.dst.chan = j;
3352 alu.dst.write = (j == 3);
3353 alu.last = 1;
3354 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3355 return r;
3356 }
3357 } else {
3358 struct r600_bytecode_alu alu;
3359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3360 alu.op = ALU_OP1_RECIP_IEEE;
3361 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3362 alu.src[0].chan = 3;
3363
3364 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3365 alu.dst.chan = 3;
3366 alu.dst.write = 1;
3367 alu.last = 1;
3368 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3369 return r;
3370 }
3371 }
3372
3373 if (ctx.thread_id_gpr) {
3374 load_thread_id_gpr(&ctx);
3375 }
3376
3377 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3378 struct r600_bytecode_alu alu;
3379 int r;
3380
3381 /* GS thread with no output workaround - emit a cut at start of GS */
3382 if (ctx.bc->chip_class == R600)
3383 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3384
3385 for (j = 0; j < 4; j++) {
3386 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3387 alu.op = ALU_OP1_MOV;
3388 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3389 alu.src[0].value = 0;
3390 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3391 alu.dst.write = 1;
3392 alu.last = 1;
3393 r = r600_bytecode_add_alu(ctx.bc, &alu);
3394 if (r)
3395 return r;
3396 }
3397
3398 if (ctx.shader->gs_tri_strip_adj_fix) {
3399 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3400 ctx.gs_rotated_input[0], 2,
3401 0, 2,
3402 V_SQ_ALU_SRC_LITERAL, 1);
3403 if (r)
3404 return r;
3405
3406 for (i = 0; i < 6; i++) {
3407 int rotated = (i + 4) % 6;
3408 int offset_reg = i / 3;
3409 int offset_chan = i % 3;
3410 int rotated_offset_reg = rotated / 3;
3411 int rotated_offset_chan = rotated % 3;
3412
3413 if (offset_reg == 0 && offset_chan == 2)
3414 offset_chan = 3;
3415 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3416 rotated_offset_chan = 3;
3417
3418 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3419 ctx.gs_rotated_input[offset_reg], offset_chan,
3420 ctx.gs_rotated_input[0], 2,
3421 offset_reg, offset_chan,
3422 rotated_offset_reg, rotated_offset_chan);
3423 if (r)
3424 return r;
3425 }
3426 }
3427 }
3428
3429 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3430 r600_fetch_tess_io_info(&ctx);
3431
3432 if (shader->two_side && ctx.colors_used) {
3433 if ((r = process_twoside_color_inputs(&ctx)))
3434 return r;
3435 }
3436
3437 tgsi_parse_init(&ctx.parse, tokens);
3438 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3439 tgsi_parse_token(&ctx.parse);
3440 switch (ctx.parse.FullToken.Token.Type) {
3441 case TGSI_TOKEN_TYPE_INSTRUCTION:
3442 r = tgsi_is_supported(&ctx);
3443 if (r)
3444 goto out_err;
3445 ctx.max_driver_temp_used = 0;
3446 /* reserve first tmp for everyone */
3447 r600_get_temp(&ctx);
3448
3449 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3450 if ((r = tgsi_split_constant(&ctx)))
3451 goto out_err;
3452 if ((r = tgsi_split_literal_constant(&ctx)))
3453 goto out_err;
3454 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3455 if ((r = tgsi_split_gs_inputs(&ctx)))
3456 goto out_err;
3457 } else if (lds_inputs) {
3458 if ((r = tgsi_split_lds_inputs(&ctx)))
3459 goto out_err;
3460 }
3461 if (ctx.bc->chip_class == CAYMAN)
3462 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3463 else if (ctx.bc->chip_class >= EVERGREEN)
3464 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3465 else
3466 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3467 r = ctx.inst_info->process(&ctx);
3468 if (r)
3469 goto out_err;
3470
3471 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3472 r = r600_store_tcs_output(&ctx);
3473 if (r)
3474 goto out_err;
3475 }
3476 break;
3477 default:
3478 break;
3479 }
3480 }
3481
3482 /* Reset the temporary register counter. */
3483 ctx.max_driver_temp_used = 0;
3484
3485 noutput = shader->noutput;
3486
3487 if (!ring_outputs && ctx.clip_vertex_write) {
3488 unsigned clipdist_temp[2];
3489
3490 clipdist_temp[0] = r600_get_temp(&ctx);
3491 clipdist_temp[1] = r600_get_temp(&ctx);
3492
3493 /* need to convert a clipvertex write into clipdistance writes and not export
3494 the clip vertex anymore */
3495
3496 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3497 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3498 shader->output[noutput].gpr = clipdist_temp[0];
3499 noutput++;
3500 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3501 shader->output[noutput].gpr = clipdist_temp[1];
3502 noutput++;
3503
3504 /* reset spi_sid for clipvertex output to avoid confusing spi */
3505 shader->output[ctx.cv_output].spi_sid = 0;
3506
3507 shader->clip_dist_write = 0xFF;
3508 shader->cc_dist_mask = 0xFF;
3509
3510 for (i = 0; i < 8; i++) {
3511 int oreg = i >> 2;
3512 int ochan = i & 3;
3513
3514 for (j = 0; j < 4; j++) {
3515 struct r600_bytecode_alu alu;
3516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3517 alu.op = ALU_OP2_DOT4;
3518 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3519 alu.src[0].chan = j;
3520
3521 alu.src[1].sel = 512 + i;
3522 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3523 alu.src[1].chan = j;
3524
3525 alu.dst.sel = clipdist_temp[oreg];
3526 alu.dst.chan = j;
3527 alu.dst.write = (j == ochan);
3528 if (j == 3)
3529 alu.last = 1;
3530 r = r600_bytecode_add_alu(ctx.bc, &alu);
3531 if (r)
3532 return r;
3533 }
3534 }
3535 }
3536
3537 /* Add stream outputs. */
3538 if (so.num_outputs) {
3539 bool emit = false;
3540 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3541 emit = true;
3542 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3543 emit = true;
3544 if (emit)
3545 emit_streamout(&ctx, &so, -1, NULL);
3546 }
3547 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3548 convert_edgeflag_to_int(&ctx);
3549
3550 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3551 r600_emit_tess_factor(&ctx);
3552
3553 if (lds_outputs) {
3554 if (ctx.type == PIPE_SHADER_VERTEX) {
3555 if (ctx.shader->noutput)
3556 emit_lds_vs_writes(&ctx);
3557 }
3558 } else if (ring_outputs) {
3559 if (shader->vs_as_es || shader->tes_as_es) {
3560 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3561 ctx.gs_export_gpr_tregs[1] = -1;
3562 ctx.gs_export_gpr_tregs[2] = -1;
3563 ctx.gs_export_gpr_tregs[3] = -1;
3564
3565 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3566 }
3567 } else {
3568 /* Export output */
3569 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3570
3571 for (i = 0, j = 0; i < noutput; i++, j++) {
3572 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3573 output[j].gpr = shader->output[i].gpr;
3574 output[j].elem_size = 3;
3575 output[j].swizzle_x = 0;
3576 output[j].swizzle_y = 1;
3577 output[j].swizzle_z = 2;
3578 output[j].swizzle_w = 3;
3579 output[j].burst_count = 1;
3580 output[j].type = 0xffffffff;
3581 output[j].op = CF_OP_EXPORT;
3582 switch (ctx.type) {
3583 case PIPE_SHADER_VERTEX:
3584 case PIPE_SHADER_TESS_EVAL:
3585 switch (shader->output[i].name) {
3586 case TGSI_SEMANTIC_POSITION:
3587 output[j].array_base = 60;
3588 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3589 pos_emitted = true;
3590 break;
3591
3592 case TGSI_SEMANTIC_PSIZE:
3593 output[j].array_base = 61;
3594 output[j].swizzle_y = 7;
3595 output[j].swizzle_z = 7;
3596 output[j].swizzle_w = 7;
3597 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3598 pos_emitted = true;
3599 break;
3600 case TGSI_SEMANTIC_EDGEFLAG:
3601 output[j].array_base = 61;
3602 output[j].swizzle_x = 7;
3603 output[j].swizzle_y = 0;
3604 output[j].swizzle_z = 7;
3605 output[j].swizzle_w = 7;
3606 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3607 pos_emitted = true;
3608 break;
3609 case TGSI_SEMANTIC_LAYER:
3610 /* spi_sid is 0 for outputs that are
3611 * not consumed by PS */
3612 if (shader->output[i].spi_sid) {
3613 output[j].array_base = next_param_base++;
3614 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3615 j++;
3616 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3617 }
3618 output[j].array_base = 61;
3619 output[j].swizzle_x = 7;
3620 output[j].swizzle_y = 7;
3621 output[j].swizzle_z = 0;
3622 output[j].swizzle_w = 7;
3623 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3624 pos_emitted = true;
3625 break;
3626 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3627 /* spi_sid is 0 for outputs that are
3628 * not consumed by PS */
3629 if (shader->output[i].spi_sid) {
3630 output[j].array_base = next_param_base++;
3631 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3632 j++;
3633 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3634 }
3635 output[j].array_base = 61;
3636 output[j].swizzle_x = 7;
3637 output[j].swizzle_y = 7;
3638 output[j].swizzle_z = 7;
3639 output[j].swizzle_w = 0;
3640 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3641 pos_emitted = true;
3642 break;
3643 case TGSI_SEMANTIC_CLIPVERTEX:
3644 j--;
3645 break;
3646 case TGSI_SEMANTIC_CLIPDIST:
3647 output[j].array_base = next_clip_base++;
3648 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3649 pos_emitted = true;
3650 /* spi_sid is 0 for clipdistance outputs that were generated
3651 * for clipvertex - we don't need to pass them to PS */
3652 if (shader->output[i].spi_sid) {
3653 j++;
3654 /* duplicate it as PARAM to pass to the pixel shader */
3655 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3656 output[j].array_base = next_param_base++;
3657 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3658 }
3659 break;
3660 case TGSI_SEMANTIC_FOG:
3661 output[j].swizzle_y = 4; /* 0 */
3662 output[j].swizzle_z = 4; /* 0 */
3663 output[j].swizzle_w = 5; /* 1 */
3664 break;
3665 case TGSI_SEMANTIC_PRIMID:
3666 output[j].swizzle_x = 2;
3667 output[j].swizzle_y = 4; /* 0 */
3668 output[j].swizzle_z = 4; /* 0 */
3669 output[j].swizzle_w = 4; /* 0 */
3670 break;
3671 }
3672
3673 break;
3674 case PIPE_SHADER_FRAGMENT:
3675 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3676 /* never export more colors than the number of CBs */
3677 if (shader->output[i].sid >= max_color_exports) {
3678 /* skip export */
3679 j--;
3680 continue;
3681 }
3682 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3683 output[j].array_base = shader->output[i].sid;
3684 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3685 shader->nr_ps_color_exports++;
3686 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3687 for (k = 1; k < max_color_exports; k++) {
3688 j++;
3689 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3690 output[j].gpr = shader->output[i].gpr;
3691 output[j].elem_size = 3;
3692 output[j].swizzle_x = 0;
3693 output[j].swizzle_y = 1;
3694 output[j].swizzle_z = 2;
3695 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3696 output[j].burst_count = 1;
3697 output[j].array_base = k;
3698 output[j].op = CF_OP_EXPORT;
3699 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3700 shader->nr_ps_color_exports++;
3701 }
3702 }
3703 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3704 output[j].array_base = 61;
3705 output[j].swizzle_x = 2;
3706 output[j].swizzle_y = 7;
3707 output[j].swizzle_z = output[j].swizzle_w = 7;
3708 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3709 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3710 output[j].array_base = 61;
3711 output[j].swizzle_x = 7;
3712 output[j].swizzle_y = 1;
3713 output[j].swizzle_z = output[j].swizzle_w = 7;
3714 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3715 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3716 output[j].array_base = 61;
3717 output[j].swizzle_x = 7;
3718 output[j].swizzle_y = 7;
3719 output[j].swizzle_z = 0;
3720 output[j].swizzle_w = 7;
3721 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3722 } else {
3723 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3724 r = -EINVAL;
3725 goto out_err;
3726 }
3727 break;
3728 case PIPE_SHADER_TESS_CTRL:
3729 break;
3730 default:
3731 R600_ERR("unsupported processor type %d\n", ctx.type);
3732 r = -EINVAL;
3733 goto out_err;
3734 }
3735
3736 if (output[j].type == 0xffffffff) {
3737 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3738 output[j].array_base = next_param_base++;
3739 }
3740 }
3741
3742 /* add fake position export */
3743 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3744 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3745 output[j].gpr = 0;
3746 output[j].elem_size = 3;
3747 output[j].swizzle_x = 7;
3748 output[j].swizzle_y = 7;
3749 output[j].swizzle_z = 7;
3750 output[j].swizzle_w = 7;
3751 output[j].burst_count = 1;
3752 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3753 output[j].array_base = 60;
3754 output[j].op = CF_OP_EXPORT;
3755 j++;
3756 }
3757
3758 /* add fake param output for vertex shader if no param is exported */
3759 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3760 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3761 output[j].gpr = 0;
3762 output[j].elem_size = 3;
3763 output[j].swizzle_x = 7;
3764 output[j].swizzle_y = 7;
3765 output[j].swizzle_z = 7;
3766 output[j].swizzle_w = 7;
3767 output[j].burst_count = 1;
3768 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3769 output[j].array_base = 0;
3770 output[j].op = CF_OP_EXPORT;
3771 j++;
3772 }
3773
3774 /* add fake pixel export */
3775 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3776 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3777 output[j].gpr = 0;
3778 output[j].elem_size = 3;
3779 output[j].swizzle_x = 7;
3780 output[j].swizzle_y = 7;
3781 output[j].swizzle_z = 7;
3782 output[j].swizzle_w = 7;
3783 output[j].burst_count = 1;
3784 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3785 output[j].array_base = 0;
3786 output[j].op = CF_OP_EXPORT;
3787 j++;
3788 shader->nr_ps_color_exports++;
3789 }
3790
3791 noutput = j;
3792
3793 /* set export done on last export of each type */
3794 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
3795 if (!(output_done & (1 << output[k].type))) {
3796 output_done |= (1 << output[k].type);
3797 output[k].op = CF_OP_EXPORT_DONE;
3798 }
3799 }
3800 /* add output to bytecode */
3801 for (i = 0; i < noutput; i++) {
3802 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3803 if (r)
3804 goto out_err;
3805 }
3806 }
3807
3808 /* add program end */
3809 if (ctx.bc->chip_class == CAYMAN)
3810 cm_bytecode_add_cf_end(ctx.bc);
3811 else {
3812 const struct cf_op_info *last = NULL;
3813
3814 if (ctx.bc->cf_last)
3815 last = r600_isa_cf(ctx.bc->cf_last->op);
3816
3817 /* alu clause instructions don't have EOP bit, so add NOP */
3818 if (!last || last->flags & CF_ALU)
3819 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3820
3821 ctx.bc->cf_last->end_of_program = 1;
3822 }
3823
3824 /* check GPR limit - we have 124 = 128 - 4
3825 * (4 are reserved as alu clause temporary registers) */
3826 if (ctx.bc->ngpr > 124) {
3827 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3828 r = -ENOMEM;
3829 goto out_err;
3830 }
3831
3832 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3833 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3834 return r;
3835 }
3836
3837 free(ctx.literals);
3838 tgsi_parse_free(&ctx.parse);
3839 return 0;
3840 out_err:
3841 free(ctx.literals);
3842 tgsi_parse_free(&ctx.parse);
3843 return r;
3844 }
3845
3846 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3847 {
3848 const unsigned tgsi_opcode =
3849 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3850 R600_ERR("%s tgsi opcode unsupported\n",
3851 tgsi_get_opcode_name(tgsi_opcode));
3852 return -EINVAL;
3853 }
3854
3855 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
3856 {
3857 return 0;
3858 }
3859
3860 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3861 const struct r600_shader_src *shader_src,
3862 unsigned chan)
3863 {
3864 bc_src->sel = shader_src->sel;
3865 bc_src->chan = shader_src->swizzle[chan];
3866 bc_src->neg = shader_src->neg;
3867 bc_src->abs = shader_src->abs;
3868 bc_src->rel = shader_src->rel;
3869 bc_src->value = shader_src->value[bc_src->chan];
3870 bc_src->kc_bank = shader_src->kc_bank;
3871 bc_src->kc_rel = shader_src->kc_rel;
3872 }
3873
3874 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3875 {
3876 bc_src->abs = 1;
3877 bc_src->neg = 0;
3878 }
3879
3880 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3881 {
3882 bc_src->neg = !bc_src->neg;
3883 }
3884
3885 static void tgsi_dst(struct r600_shader_ctx *ctx,
3886 const struct tgsi_full_dst_register *tgsi_dst,
3887 unsigned swizzle,
3888 struct r600_bytecode_alu_dst *r600_dst)
3889 {
3890 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3891
3892 r600_dst->sel = tgsi_dst->Register.Index;
3893 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3894 r600_dst->chan = swizzle;
3895 r600_dst->write = 1;
3896 if (inst->Instruction.Saturate) {
3897 r600_dst->clamp = 1;
3898 }
3899 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3900 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3901 return;
3902 }
3903 }
3904 if (tgsi_dst->Register.Indirect)
3905 r600_dst->rel = V_SQ_REL_RELATIVE;
3906
3907 }
3908
3909 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3910 {
3911 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3912 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3913 struct r600_bytecode_alu alu;
3914 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3915 int use_tmp = 0;
3916
3917 if (singledest) {
3918 switch (write_mask) {
3919 case 0x1:
3920 write_mask = 0x3;
3921 break;
3922 case 0x2:
3923 use_tmp = 1;
3924 write_mask = 0x3;
3925 break;
3926 case 0x4:
3927 write_mask = 0xc;
3928 break;
3929 case 0x8:
3930 write_mask = 0xc;
3931 use_tmp = 3;
3932 break;
3933 }
3934 }
3935
3936 lasti = tgsi_last_instruction(write_mask);
3937 for (i = 0; i <= lasti; i++) {
3938
3939 if (!(write_mask & (1 << i)))
3940 continue;
3941
3942 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3943
3944 if (singledest) {
3945 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3946 if (use_tmp) {
3947 alu.dst.sel = ctx->temp_reg;
3948 alu.dst.chan = i;
3949 alu.dst.write = 1;
3950 }
3951 if (i == 1 || i == 3)
3952 alu.dst.write = 0;
3953 } else
3954 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3955
3956 alu.op = ctx->inst_info->op;
3957 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3958 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3959 } else if (!swap) {
3960 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3961 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3962 }
3963 } else {
3964 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3965 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3966 }
3967
3968 /* handle some special cases */
3969 if (i == 1 || i == 3) {
3970 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3971 case TGSI_OPCODE_DABS:
3972 r600_bytecode_src_set_abs(&alu.src[0]);
3973 break;
3974 default:
3975 break;
3976 }
3977 }
3978 if (i == lasti) {
3979 alu.last = 1;
3980 }
3981 r = r600_bytecode_add_alu(ctx->bc, &alu);
3982 if (r)
3983 return r;
3984 }
3985
3986 if (use_tmp) {
3987 write_mask = inst->Dst[0].Register.WriteMask;
3988
3989 /* move result from temp to dst */
3990 for (i = 0; i <= lasti; i++) {
3991 if (!(write_mask & (1 << i)))
3992 continue;
3993
3994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3995 alu.op = ALU_OP1_MOV;
3996 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3997 alu.src[0].sel = ctx->temp_reg;
3998 alu.src[0].chan = use_tmp - 1;
3999 alu.last = (i == lasti);
4000
4001 r = r600_bytecode_add_alu(ctx->bc, &alu);
4002 if (r)
4003 return r;
4004 }
4005 }
4006 return 0;
4007 }
4008
4009 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4010 {
4011 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4012 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4013 /* confirm writemasking */
4014 if ((write_mask & 0x3) != 0x3 &&
4015 (write_mask & 0xc) != 0xc) {
4016 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4017 return -1;
4018 }
4019 return tgsi_op2_64_params(ctx, false, false);
4020 }
4021
4022 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4023 {
4024 return tgsi_op2_64_params(ctx, true, false);
4025 }
4026
4027 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4028 {
4029 return tgsi_op2_64_params(ctx, true, true);
4030 }
4031
4032 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4033 {
4034 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4035 struct r600_bytecode_alu alu;
4036 int i, j, r;
4037 int lasti = 3;
4038 int tmp = r600_get_temp(ctx);
4039
4040 for (i = 0; i < lasti + 1; i++) {
4041
4042 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4043 alu.op = ctx->inst_info->op;
4044 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4045 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4046 }
4047
4048 if (inst->Dst[0].Register.WriteMask & (1 << i))
4049 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4050 else
4051 alu.dst.sel = tmp;
4052
4053 alu.dst.chan = i;
4054 alu.is_op3 = 1;
4055 if (i == lasti) {
4056 alu.last = 1;
4057 }
4058 r = r600_bytecode_add_alu(ctx->bc, &alu);
4059 if (r)
4060 return r;
4061 }
4062 return 0;
4063 }
4064
4065 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4066 {
4067 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4068 struct r600_bytecode_alu alu;
4069 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4070 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4071 /* use temp register if trans_only and more than one dst component */
4072 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4073 unsigned op = ctx->inst_info->op;
4074
4075 if (op == ALU_OP2_MUL_IEEE &&
4076 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4077 op = ALU_OP2_MUL;
4078
4079 for (i = 0; i <= lasti; i++) {
4080 if (!(write_mask & (1 << i)))
4081 continue;
4082
4083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4084 if (use_tmp) {
4085 alu.dst.sel = ctx->temp_reg;
4086 alu.dst.chan = i;
4087 alu.dst.write = 1;
4088 } else
4089 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4090
4091 alu.op = op;
4092 if (!swap) {
4093 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4094 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4095 }
4096 } else {
4097 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4098 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4099 }
4100 if (i == lasti || trans_only) {
4101 alu.last = 1;
4102 }
4103 r = r600_bytecode_add_alu(ctx->bc, &alu);
4104 if (r)
4105 return r;
4106 }
4107
4108 if (use_tmp) {
4109 /* move result from temp to dst */
4110 for (i = 0; i <= lasti; i++) {
4111 if (!(write_mask & (1 << i)))
4112 continue;
4113
4114 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4115 alu.op = ALU_OP1_MOV;
4116 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4117 alu.src[0].sel = ctx->temp_reg;
4118 alu.src[0].chan = i;
4119 alu.last = (i == lasti);
4120
4121 r = r600_bytecode_add_alu(ctx->bc, &alu);
4122 if (r)
4123 return r;
4124 }
4125 }
4126 return 0;
4127 }
4128
4129 static int tgsi_op2(struct r600_shader_ctx *ctx)
4130 {
4131 return tgsi_op2_s(ctx, 0, 0);
4132 }
4133
4134 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4135 {
4136 return tgsi_op2_s(ctx, 1, 0);
4137 }
4138
4139 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4140 {
4141 return tgsi_op2_s(ctx, 0, 1);
4142 }
4143
4144 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4145 {
4146 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4147 struct r600_bytecode_alu alu;
4148 int i, r;
4149 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4150
4151 for (i = 0; i < lasti + 1; i++) {
4152
4153 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4154 continue;
4155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4156 alu.op = ctx->inst_info->op;
4157
4158 alu.src[0].sel = V_SQ_ALU_SRC_0;
4159
4160 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4161
4162 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4163
4164 if (i == lasti) {
4165 alu.last = 1;
4166 }
4167 r = r600_bytecode_add_alu(ctx->bc, &alu);
4168 if (r)
4169 return r;
4170 }
4171 return 0;
4172
4173 }
4174
4175 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4176 {
4177 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4178 struct r600_bytecode_alu alu;
4179 int i, r;
4180 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4181
4182 for (i = 0; i < lasti + 1; i++) {
4183
4184 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4185 continue;
4186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4187 alu.op = ALU_OP1_MOV;
4188
4189 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4190
4191 if (i == 1 || i == 3)
4192 r600_bytecode_src_toggle_neg(&alu.src[0]);
4193 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4194
4195 if (i == lasti) {
4196 alu.last = 1;
4197 }
4198 r = r600_bytecode_add_alu(ctx->bc, &alu);
4199 if (r)
4200 return r;
4201 }
4202 return 0;
4203
4204 }
4205
4206 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4207 {
4208 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4209 struct r600_bytecode_alu alu;
4210 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4211 int i, j, r;
4212
4213 for (i = 0; i <= 3; i++) {
4214 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4215 alu.op = ctx->inst_info->op;
4216
4217 alu.dst.sel = ctx->temp_reg;
4218 alu.dst.chan = i;
4219 alu.dst.write = 1;
4220 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4221 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4222 }
4223
4224 if (i == 3)
4225 alu.last = 1;
4226
4227 r = r600_bytecode_add_alu(ctx->bc, &alu);
4228 if (r)
4229 return r;
4230 }
4231
4232 /* Replicate significand result across channels. */
4233 for (i = 0; i <= 3; i++) {
4234 if (!(write_mask & (1 << i)))
4235 continue;
4236
4237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4238 alu.op = ALU_OP1_MOV;
4239 alu.src[0].chan = (i & 1) + 2;
4240 alu.src[0].sel = ctx->temp_reg;
4241
4242 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4243 alu.dst.write = 1;
4244 alu.last = 1;
4245 r = r600_bytecode_add_alu(ctx->bc, &alu);
4246 if (r)
4247 return r;
4248 }
4249
4250 for (i = 0; i <= 3; i++) {
4251 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4252 /* MOV third channels to writemask dst1 */
4253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4254 alu.op = ALU_OP1_MOV;
4255 alu.src[0].chan = 1;
4256 alu.src[0].sel = ctx->temp_reg;
4257
4258 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4259 alu.last = 1;
4260 r = r600_bytecode_add_alu(ctx->bc, &alu);
4261 if (r)
4262 return r;
4263 break;
4264 }
4265 }
4266 return 0;
4267 }
4268
4269
4270 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4271 {
4272 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4273 struct r600_bytecode_alu alu;
4274 int i, r;
4275 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4276
4277 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4278 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4279
4280 for (i = 0; i <= (lasti+1)/2; i++) {
4281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4282 alu.op = ctx->inst_info->op;
4283
4284 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4285 alu.dst.sel = ctx->temp_reg;
4286 alu.dst.chan = i;
4287 alu.dst.write = 1;
4288 alu.last = 1;
4289
4290 r = r600_bytecode_add_alu(ctx->bc, &alu);
4291 if (r)
4292 return r;
4293 }
4294
4295 for (i = 0; i <= lasti; i++) {
4296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4297 alu.op = ALU_OP1_FLT32_TO_FLT64;
4298
4299 alu.src[0].chan = i/2;
4300 if (i%2 == 0)
4301 alu.src[0].sel = ctx->temp_reg;
4302 else {
4303 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4304 alu.src[0].value = 0x0;
4305 }
4306 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4307 alu.last = i == lasti;
4308
4309 r = r600_bytecode_add_alu(ctx->bc, &alu);
4310 if (r)
4311 return r;
4312 }
4313
4314 return 0;
4315 }
4316
4317 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4318 {
4319 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4320 struct r600_bytecode_alu alu;
4321 int i, r;
4322 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4323
4324 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4325 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4326
4327 for (i = 0; i <= lasti; i++) {
4328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4329 alu.op = ALU_OP1_FLT64_TO_FLT32;
4330
4331 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4332 alu.dst.chan = i;
4333 alu.dst.sel = ctx->temp_reg;
4334 alu.dst.write = i%2 == 0;
4335 alu.last = i == lasti;
4336
4337 r = r600_bytecode_add_alu(ctx->bc, &alu);
4338 if (r)
4339 return r;
4340 }
4341
4342 for (i = 0; i <= (lasti+1)/2; i++) {
4343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4344 alu.op = ctx->inst_info->op;
4345
4346 alu.src[0].chan = i*2;
4347 alu.src[0].sel = ctx->temp_reg;
4348 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4349 alu.last = 1;
4350
4351 r = r600_bytecode_add_alu(ctx->bc, &alu);
4352 if (r)
4353 return r;
4354 }
4355
4356 return 0;
4357 }
4358
4359 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4360 unsigned op,
4361 int dst_reg,
4362 struct r600_shader_src *src,
4363 bool abs)
4364 {
4365 struct r600_bytecode_alu alu;
4366 const int last_slot = 3;
4367 int r;
4368
4369 /* these have to write the result to X/Y by the looks of it */
4370 for (int i = 0 ; i < last_slot; i++) {
4371 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4372 alu.op = op;
4373
4374 r600_bytecode_src(&alu.src[0], src, 1);
4375 r600_bytecode_src(&alu.src[1], src, 0);
4376
4377 if (abs)
4378 r600_bytecode_src_set_abs(&alu.src[1]);
4379
4380 alu.dst.sel = dst_reg;
4381 alu.dst.chan = i;
4382 alu.dst.write = (i == 0 || i == 1);
4383
4384 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4385 alu.last = 1;
4386 r = r600_bytecode_add_alu(bc, &alu);
4387 if (r)
4388 return r;
4389 }
4390
4391 return 0;
4392 }
4393
4394 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4395 {
4396 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4397 int i, r;
4398 struct r600_bytecode_alu alu;
4399 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4400 int t1 = ctx->temp_reg;
4401
4402 /* should only be one src regs */
4403 assert(inst->Instruction.NumSrcRegs == 1);
4404
4405 /* only support one double at a time */
4406 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4407 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4408
4409 r = cayman_emit_unary_double_raw(
4410 ctx->bc, ctx->inst_info->op, t1,
4411 &ctx->src[0],
4412 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4413 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4414 if (r)
4415 return r;
4416
4417 for (i = 0 ; i <= lasti; i++) {
4418 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4419 continue;
4420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4421 alu.op = ALU_OP1_MOV;
4422 alu.src[0].sel = t1;
4423 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4424 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4425 alu.dst.write = 1;
4426 if (i == lasti)
4427 alu.last = 1;
4428 r = r600_bytecode_add_alu(ctx->bc, &alu);
4429 if (r)
4430 return r;
4431 }
4432 return 0;
4433 }
4434
4435 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4436 {
4437 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4438 int i, j, r;
4439 struct r600_bytecode_alu alu;
4440 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4441
4442 for (i = 0 ; i < last_slot; i++) {
4443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4444 alu.op = ctx->inst_info->op;
4445 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4446 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4447
4448 /* RSQ should take the absolute value of src */
4449 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4450 r600_bytecode_src_set_abs(&alu.src[j]);
4451 }
4452 }
4453 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4454 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4455
4456 if (i == last_slot - 1)
4457 alu.last = 1;
4458 r = r600_bytecode_add_alu(ctx->bc, &alu);
4459 if (r)
4460 return r;
4461 }
4462 return 0;
4463 }
4464
4465 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4466 {
4467 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4468 int i, j, k, r;
4469 struct r600_bytecode_alu alu;
4470 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4471 int t1 = ctx->temp_reg;
4472
4473 for (k = 0; k <= lasti; k++) {
4474 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4475 continue;
4476
4477 for (i = 0 ; i < 4; i++) {
4478 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4479 alu.op = ctx->inst_info->op;
4480 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4481 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4482 }
4483 alu.dst.sel = t1;
4484 alu.dst.chan = i;
4485 alu.dst.write = (i == k);
4486 if (i == 3)
4487 alu.last = 1;
4488 r = r600_bytecode_add_alu(ctx->bc, &alu);
4489 if (r)
4490 return r;
4491 }
4492 }
4493
4494 for (i = 0 ; i <= lasti; i++) {
4495 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4496 continue;
4497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4498 alu.op = ALU_OP1_MOV;
4499 alu.src[0].sel = t1;
4500 alu.src[0].chan = i;
4501 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4502 alu.dst.write = 1;
4503 if (i == lasti)
4504 alu.last = 1;
4505 r = r600_bytecode_add_alu(ctx->bc, &alu);
4506 if (r)
4507 return r;
4508 }
4509
4510 return 0;
4511 }
4512
4513
4514 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4515 {
4516 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4517 int i, j, k, r;
4518 struct r600_bytecode_alu alu;
4519 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4520 int t1 = ctx->temp_reg;
4521
4522 /* t1 would get overwritten below if we actually tried to
4523 * multiply two pairs of doubles at a time. */
4524 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4525 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4526
4527 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4528
4529 for (i = 0; i < 4; i++) {
4530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4531 alu.op = ctx->inst_info->op;
4532 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4533 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4534 }
4535 alu.dst.sel = t1;
4536 alu.dst.chan = i;
4537 alu.dst.write = 1;
4538 if (i == 3)
4539 alu.last = 1;
4540 r = r600_bytecode_add_alu(ctx->bc, &alu);
4541 if (r)
4542 return r;
4543 }
4544
4545 for (i = 0; i <= lasti; i++) {
4546 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4547 continue;
4548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4549 alu.op = ALU_OP1_MOV;
4550 alu.src[0].sel = t1;
4551 alu.src[0].chan = i;
4552 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4553 alu.dst.write = 1;
4554 if (i == lasti)
4555 alu.last = 1;
4556 r = r600_bytecode_add_alu(ctx->bc, &alu);
4557 if (r)
4558 return r;
4559 }
4560
4561 return 0;
4562 }
4563
4564 /*
4565 * Emit RECIP_64 + MUL_64 to implement division.
4566 */
4567 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4568 {
4569 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4570 int r;
4571 struct r600_bytecode_alu alu;
4572 int t1 = ctx->temp_reg;
4573 int k;
4574
4575 /* Only support one double at a time. This is the same constraint as
4576 * in DMUL lowering. */
4577 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4578 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4579
4580 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4581
4582 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4583 if (r)
4584 return r;
4585
4586 for (int i = 0; i < 4; i++) {
4587 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4588 alu.op = ALU_OP2_MUL_64;
4589
4590 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4591
4592 alu.src[1].sel = t1;
4593 alu.src[1].chan = (i == 3) ? 0 : 1;
4594
4595 alu.dst.sel = t1;
4596 alu.dst.chan = i;
4597 alu.dst.write = 1;
4598 if (i == 3)
4599 alu.last = 1;
4600 r = r600_bytecode_add_alu(ctx->bc, &alu);
4601 if (r)
4602 return r;
4603 }
4604
4605 for (int i = 0; i < 2; i++) {
4606 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4607 alu.op = ALU_OP1_MOV;
4608 alu.src[0].sel = t1;
4609 alu.src[0].chan = i;
4610 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4611 alu.dst.write = 1;
4612 if (i == 1)
4613 alu.last = 1;
4614 r = r600_bytecode_add_alu(ctx->bc, &alu);
4615 if (r)
4616 return r;
4617 }
4618 return 0;
4619 }
4620
4621 /*
4622 * r600 - trunc to -PI..PI range
4623 * r700 - normalize by dividing by 2PI
4624 * see fdo bug 27901
4625 */
4626 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4627 {
4628 int r;
4629 struct r600_bytecode_alu alu;
4630
4631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4632 alu.op = ALU_OP3_MULADD;
4633 alu.is_op3 = 1;
4634
4635 alu.dst.chan = 0;
4636 alu.dst.sel = ctx->temp_reg;
4637 alu.dst.write = 1;
4638
4639 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4640
4641 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4642 alu.src[1].chan = 0;
4643 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4644 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4645 alu.src[2].chan = 0;
4646 alu.last = 1;
4647 r = r600_bytecode_add_alu(ctx->bc, &alu);
4648 if (r)
4649 return r;
4650
4651 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4652 alu.op = ALU_OP1_FRACT;
4653
4654 alu.dst.chan = 0;
4655 alu.dst.sel = ctx->temp_reg;
4656 alu.dst.write = 1;
4657
4658 alu.src[0].sel = ctx->temp_reg;
4659 alu.src[0].chan = 0;
4660 alu.last = 1;
4661 r = r600_bytecode_add_alu(ctx->bc, &alu);
4662 if (r)
4663 return r;
4664
4665 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4666 alu.op = ALU_OP3_MULADD;
4667 alu.is_op3 = 1;
4668
4669 alu.dst.chan = 0;
4670 alu.dst.sel = ctx->temp_reg;
4671 alu.dst.write = 1;
4672
4673 alu.src[0].sel = ctx->temp_reg;
4674 alu.src[0].chan = 0;
4675
4676 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4677 alu.src[1].chan = 0;
4678 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4679 alu.src[2].chan = 0;
4680
4681 if (ctx->bc->chip_class == R600) {
4682 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4683 alu.src[2].value = u_bitcast_f2u(-M_PI);
4684 } else {
4685 alu.src[1].sel = V_SQ_ALU_SRC_1;
4686 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4687 alu.src[2].neg = 1;
4688 }
4689
4690 alu.last = 1;
4691 r = r600_bytecode_add_alu(ctx->bc, &alu);
4692 if (r)
4693 return r;
4694 return 0;
4695 }
4696
4697 static int cayman_trig(struct r600_shader_ctx *ctx)
4698 {
4699 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4700 struct r600_bytecode_alu alu;
4701 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4702 int i, r;
4703
4704 r = tgsi_setup_trig(ctx);
4705 if (r)
4706 return r;
4707
4708
4709 for (i = 0; i < last_slot; i++) {
4710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4711 alu.op = ctx->inst_info->op;
4712 alu.dst.chan = i;
4713
4714 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4715 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4716
4717 alu.src[0].sel = ctx->temp_reg;
4718 alu.src[0].chan = 0;
4719 if (i == last_slot - 1)
4720 alu.last = 1;
4721 r = r600_bytecode_add_alu(ctx->bc, &alu);
4722 if (r)
4723 return r;
4724 }
4725 return 0;
4726 }
4727
4728 static int tgsi_trig(struct r600_shader_ctx *ctx)
4729 {
4730 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4731 struct r600_bytecode_alu alu;
4732 int i, r;
4733 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4734
4735 r = tgsi_setup_trig(ctx);
4736 if (r)
4737 return r;
4738
4739 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4740 alu.op = ctx->inst_info->op;
4741 alu.dst.chan = 0;
4742 alu.dst.sel = ctx->temp_reg;
4743 alu.dst.write = 1;
4744
4745 alu.src[0].sel = ctx->temp_reg;
4746 alu.src[0].chan = 0;
4747 alu.last = 1;
4748 r = r600_bytecode_add_alu(ctx->bc, &alu);
4749 if (r)
4750 return r;
4751
4752 /* replicate result */
4753 for (i = 0; i < lasti + 1; i++) {
4754 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4755 continue;
4756
4757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4758 alu.op = ALU_OP1_MOV;
4759
4760 alu.src[0].sel = ctx->temp_reg;
4761 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4762 if (i == lasti)
4763 alu.last = 1;
4764 r = r600_bytecode_add_alu(ctx->bc, &alu);
4765 if (r)
4766 return r;
4767 }
4768 return 0;
4769 }
4770
4771 static int tgsi_kill(struct r600_shader_ctx *ctx)
4772 {
4773 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4774 struct r600_bytecode_alu alu;
4775 int i, r;
4776
4777 for (i = 0; i < 4; i++) {
4778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4779 alu.op = ctx->inst_info->op;
4780
4781 alu.dst.chan = i;
4782
4783 alu.src[0].sel = V_SQ_ALU_SRC_0;
4784
4785 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4786 alu.src[1].sel = V_SQ_ALU_SRC_1;
4787 alu.src[1].neg = 1;
4788 } else {
4789 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4790 }
4791 if (i == 3) {
4792 alu.last = 1;
4793 }
4794 r = r600_bytecode_add_alu(ctx->bc, &alu);
4795 if (r)
4796 return r;
4797 }
4798
4799 /* kill must be last in ALU */
4800 ctx->bc->force_add_cf = 1;
4801 ctx->shader->uses_kill = TRUE;
4802 return 0;
4803 }
4804
4805 static int tgsi_lit(struct r600_shader_ctx *ctx)
4806 {
4807 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4808 struct r600_bytecode_alu alu;
4809 int r;
4810
4811 /* tmp.x = max(src.y, 0.0) */
4812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4813 alu.op = ALU_OP2_MAX;
4814 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4815 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4816 alu.src[1].chan = 1;
4817
4818 alu.dst.sel = ctx->temp_reg;
4819 alu.dst.chan = 0;
4820 alu.dst.write = 1;
4821
4822 alu.last = 1;
4823 r = r600_bytecode_add_alu(ctx->bc, &alu);
4824 if (r)
4825 return r;
4826
4827 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4828 {
4829 int chan;
4830 int sel;
4831 unsigned i;
4832
4833 if (ctx->bc->chip_class == CAYMAN) {
4834 for (i = 0; i < 3; i++) {
4835 /* tmp.z = log(tmp.x) */
4836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4837 alu.op = ALU_OP1_LOG_CLAMPED;
4838 alu.src[0].sel = ctx->temp_reg;
4839 alu.src[0].chan = 0;
4840 alu.dst.sel = ctx->temp_reg;
4841 alu.dst.chan = i;
4842 if (i == 2) {
4843 alu.dst.write = 1;
4844 alu.last = 1;
4845 } else
4846 alu.dst.write = 0;
4847
4848 r = r600_bytecode_add_alu(ctx->bc, &alu);
4849 if (r)
4850 return r;
4851 }
4852 } else {
4853 /* tmp.z = log(tmp.x) */
4854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4855 alu.op = ALU_OP1_LOG_CLAMPED;
4856 alu.src[0].sel = ctx->temp_reg;
4857 alu.src[0].chan = 0;
4858 alu.dst.sel = ctx->temp_reg;
4859 alu.dst.chan = 2;
4860 alu.dst.write = 1;
4861 alu.last = 1;
4862 r = r600_bytecode_add_alu(ctx->bc, &alu);
4863 if (r)
4864 return r;
4865 }
4866
4867 chan = alu.dst.chan;
4868 sel = alu.dst.sel;
4869
4870 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4872 alu.op = ALU_OP3_MUL_LIT;
4873 alu.src[0].sel = sel;
4874 alu.src[0].chan = chan;
4875 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4876 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4877 alu.dst.sel = ctx->temp_reg;
4878 alu.dst.chan = 0;
4879 alu.dst.write = 1;
4880 alu.is_op3 = 1;
4881 alu.last = 1;
4882 r = r600_bytecode_add_alu(ctx->bc, &alu);
4883 if (r)
4884 return r;
4885
4886 if (ctx->bc->chip_class == CAYMAN) {
4887 for (i = 0; i < 3; i++) {
4888 /* dst.z = exp(tmp.x) */
4889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4890 alu.op = ALU_OP1_EXP_IEEE;
4891 alu.src[0].sel = ctx->temp_reg;
4892 alu.src[0].chan = 0;
4893 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4894 if (i == 2) {
4895 alu.dst.write = 1;
4896 alu.last = 1;
4897 } else
4898 alu.dst.write = 0;
4899 r = r600_bytecode_add_alu(ctx->bc, &alu);
4900 if (r)
4901 return r;
4902 }
4903 } else {
4904 /* dst.z = exp(tmp.x) */
4905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4906 alu.op = ALU_OP1_EXP_IEEE;
4907 alu.src[0].sel = ctx->temp_reg;
4908 alu.src[0].chan = 0;
4909 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4910 alu.last = 1;
4911 r = r600_bytecode_add_alu(ctx->bc, &alu);
4912 if (r)
4913 return r;
4914 }
4915 }
4916
4917 /* dst.x, <- 1.0 */
4918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4919 alu.op = ALU_OP1_MOV;
4920 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4921 alu.src[0].chan = 0;
4922 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4923 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4924 r = r600_bytecode_add_alu(ctx->bc, &alu);
4925 if (r)
4926 return r;
4927
4928 /* dst.y = max(src.x, 0.0) */
4929 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4930 alu.op = ALU_OP2_MAX;
4931 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4932 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4933 alu.src[1].chan = 0;
4934 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4935 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4936 r = r600_bytecode_add_alu(ctx->bc, &alu);
4937 if (r)
4938 return r;
4939
4940 /* dst.w, <- 1.0 */
4941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4942 alu.op = ALU_OP1_MOV;
4943 alu.src[0].sel = V_SQ_ALU_SRC_1;
4944 alu.src[0].chan = 0;
4945 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4946 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4947 alu.last = 1;
4948 r = r600_bytecode_add_alu(ctx->bc, &alu);
4949 if (r)
4950 return r;
4951
4952 return 0;
4953 }
4954
4955 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4956 {
4957 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4958 struct r600_bytecode_alu alu;
4959 int i, r;
4960
4961 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4962
4963 alu.op = ALU_OP1_RECIPSQRT_IEEE;
4964
4965 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4966 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4967 r600_bytecode_src_set_abs(&alu.src[i]);
4968 }
4969 alu.dst.sel = ctx->temp_reg;
4970 alu.dst.write = 1;
4971 alu.last = 1;
4972 r = r600_bytecode_add_alu(ctx->bc, &alu);
4973 if (r)
4974 return r;
4975 /* replicate result */
4976 return tgsi_helper_tempx_replicate(ctx);
4977 }
4978
4979 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4980 {
4981 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4982 struct r600_bytecode_alu alu;
4983 int i, r;
4984
4985 for (i = 0; i < 4; i++) {
4986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4987 alu.src[0].sel = ctx->temp_reg;
4988 alu.op = ALU_OP1_MOV;
4989 alu.dst.chan = i;
4990 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4991 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4992 if (i == 3)
4993 alu.last = 1;
4994 r = r600_bytecode_add_alu(ctx->bc, &alu);
4995 if (r)
4996 return r;
4997 }
4998 return 0;
4999 }
5000
5001 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5002 {
5003 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5004 struct r600_bytecode_alu alu;
5005 int i, r;
5006
5007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5008 alu.op = ctx->inst_info->op;
5009 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5010 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5011 }
5012 alu.dst.sel = ctx->temp_reg;
5013 alu.dst.write = 1;
5014 alu.last = 1;
5015 r = r600_bytecode_add_alu(ctx->bc, &alu);
5016 if (r)
5017 return r;
5018 /* replicate result */
5019 return tgsi_helper_tempx_replicate(ctx);
5020 }
5021
5022 static int cayman_pow(struct r600_shader_ctx *ctx)
5023 {
5024 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5025 int i, r;
5026 struct r600_bytecode_alu alu;
5027 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5028
5029 for (i = 0; i < 3; i++) {
5030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5031 alu.op = ALU_OP1_LOG_IEEE;
5032 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5033 alu.dst.sel = ctx->temp_reg;
5034 alu.dst.chan = i;
5035 alu.dst.write = 1;
5036 if (i == 2)
5037 alu.last = 1;
5038 r = r600_bytecode_add_alu(ctx->bc, &alu);
5039 if (r)
5040 return r;
5041 }
5042
5043 /* b * LOG2(a) */
5044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5045 alu.op = ALU_OP2_MUL;
5046 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5047 alu.src[1].sel = ctx->temp_reg;
5048 alu.dst.sel = ctx->temp_reg;
5049 alu.dst.write = 1;
5050 alu.last = 1;
5051 r = r600_bytecode_add_alu(ctx->bc, &alu);
5052 if (r)
5053 return r;
5054
5055 for (i = 0; i < last_slot; i++) {
5056 /* POW(a,b) = EXP2(b * LOG2(a))*/
5057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5058 alu.op = ALU_OP1_EXP_IEEE;
5059 alu.src[0].sel = ctx->temp_reg;
5060
5061 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5062 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5063 if (i == last_slot - 1)
5064 alu.last = 1;
5065 r = r600_bytecode_add_alu(ctx->bc, &alu);
5066 if (r)
5067 return r;
5068 }
5069 return 0;
5070 }
5071
5072 static int tgsi_pow(struct r600_shader_ctx *ctx)
5073 {
5074 struct r600_bytecode_alu alu;
5075 int r;
5076
5077 /* LOG2(a) */
5078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5079 alu.op = ALU_OP1_LOG_IEEE;
5080 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5081 alu.dst.sel = ctx->temp_reg;
5082 alu.dst.write = 1;
5083 alu.last = 1;
5084 r = r600_bytecode_add_alu(ctx->bc, &alu);
5085 if (r)
5086 return r;
5087 /* b * LOG2(a) */
5088 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5089 alu.op = ALU_OP2_MUL;
5090 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5091 alu.src[1].sel = ctx->temp_reg;
5092 alu.dst.sel = ctx->temp_reg;
5093 alu.dst.write = 1;
5094 alu.last = 1;
5095 r = r600_bytecode_add_alu(ctx->bc, &alu);
5096 if (r)
5097 return r;
5098 /* POW(a,b) = EXP2(b * LOG2(a))*/
5099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5100 alu.op = ALU_OP1_EXP_IEEE;
5101 alu.src[0].sel = ctx->temp_reg;
5102 alu.dst.sel = ctx->temp_reg;
5103 alu.dst.write = 1;
5104 alu.last = 1;
5105 r = r600_bytecode_add_alu(ctx->bc, &alu);
5106 if (r)
5107 return r;
5108 return tgsi_helper_tempx_replicate(ctx);
5109 }
5110
5111 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5112 {
5113 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5114 struct r600_bytecode_alu alu;
5115 int i, r, j;
5116 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5117 int tmp0 = ctx->temp_reg;
5118 int tmp1 = r600_get_temp(ctx);
5119 int tmp2 = r600_get_temp(ctx);
5120 int tmp3 = r600_get_temp(ctx);
5121 /* Unsigned path:
5122 *
5123 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5124 *
5125 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5126 * 2. tmp0.z = lo (tmp0.x * src2)
5127 * 3. tmp0.w = -tmp0.z
5128 * 4. tmp0.y = hi (tmp0.x * src2)
5129 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5130 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5131 * 7. tmp1.x = tmp0.x - tmp0.w
5132 * 8. tmp1.y = tmp0.x + tmp0.w
5133 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5134 * 10. tmp0.z = hi(tmp0.x * src1) = q
5135 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5136 *
5137 * 12. tmp0.w = src1 - tmp0.y = r
5138 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5139 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5140 *
5141 * if DIV
5142 *
5143 * 15. tmp1.z = tmp0.z + 1 = q + 1
5144 * 16. tmp1.w = tmp0.z - 1 = q - 1
5145 *
5146 * else MOD
5147 *
5148 * 15. tmp1.z = tmp0.w - src2 = r - src2
5149 * 16. tmp1.w = tmp0.w + src2 = r + src2
5150 *
5151 * endif
5152 *
5153 * 17. tmp1.x = tmp1.x & tmp1.y
5154 *
5155 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5156 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5157 *
5158 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5159 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5160 *
5161 * Signed path:
5162 *
5163 * Same as unsigned, using abs values of the operands,
5164 * and fixing the sign of the result in the end.
5165 */
5166
5167 for (i = 0; i < 4; i++) {
5168 if (!(write_mask & (1<<i)))
5169 continue;
5170
5171 if (signed_op) {
5172
5173 /* tmp2.x = -src0 */
5174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5175 alu.op = ALU_OP2_SUB_INT;
5176
5177 alu.dst.sel = tmp2;
5178 alu.dst.chan = 0;
5179 alu.dst.write = 1;
5180
5181 alu.src[0].sel = V_SQ_ALU_SRC_0;
5182
5183 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5184
5185 alu.last = 1;
5186 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5187 return r;
5188
5189 /* tmp2.y = -src1 */
5190 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5191 alu.op = ALU_OP2_SUB_INT;
5192
5193 alu.dst.sel = tmp2;
5194 alu.dst.chan = 1;
5195 alu.dst.write = 1;
5196
5197 alu.src[0].sel = V_SQ_ALU_SRC_0;
5198
5199 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5200
5201 alu.last = 1;
5202 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5203 return r;
5204
5205 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5206 /* it will be a sign of the quotient */
5207 if (!mod) {
5208
5209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5210 alu.op = ALU_OP2_XOR_INT;
5211
5212 alu.dst.sel = tmp2;
5213 alu.dst.chan = 2;
5214 alu.dst.write = 1;
5215
5216 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5217 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5218
5219 alu.last = 1;
5220 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5221 return r;
5222 }
5223
5224 /* tmp2.x = |src0| */
5225 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5226 alu.op = ALU_OP3_CNDGE_INT;
5227 alu.is_op3 = 1;
5228
5229 alu.dst.sel = tmp2;
5230 alu.dst.chan = 0;
5231 alu.dst.write = 1;
5232
5233 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5234 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5235 alu.src[2].sel = tmp2;
5236 alu.src[2].chan = 0;
5237
5238 alu.last = 1;
5239 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5240 return r;
5241
5242 /* tmp2.y = |src1| */
5243 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5244 alu.op = ALU_OP3_CNDGE_INT;
5245 alu.is_op3 = 1;
5246
5247 alu.dst.sel = tmp2;
5248 alu.dst.chan = 1;
5249 alu.dst.write = 1;
5250
5251 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5252 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5253 alu.src[2].sel = tmp2;
5254 alu.src[2].chan = 1;
5255
5256 alu.last = 1;
5257 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5258 return r;
5259
5260 }
5261
5262 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5263 if (ctx->bc->chip_class == CAYMAN) {
5264 /* tmp3.x = u2f(src2) */
5265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5266 alu.op = ALU_OP1_UINT_TO_FLT;
5267
5268 alu.dst.sel = tmp3;
5269 alu.dst.chan = 0;
5270 alu.dst.write = 1;
5271
5272 if (signed_op) {
5273 alu.src[0].sel = tmp2;
5274 alu.src[0].chan = 1;
5275 } else {
5276 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5277 }
5278
5279 alu.last = 1;
5280 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5281 return r;
5282
5283 /* tmp0.x = recip(tmp3.x) */
5284 for (j = 0 ; j < 3; j++) {
5285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5286 alu.op = ALU_OP1_RECIP_IEEE;
5287
5288 alu.dst.sel = tmp0;
5289 alu.dst.chan = j;
5290 alu.dst.write = (j == 0);
5291
5292 alu.src[0].sel = tmp3;
5293 alu.src[0].chan = 0;
5294
5295 if (j == 2)
5296 alu.last = 1;
5297 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5298 return r;
5299 }
5300
5301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5302 alu.op = ALU_OP2_MUL;
5303
5304 alu.src[0].sel = tmp0;
5305 alu.src[0].chan = 0;
5306
5307 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5308 alu.src[1].value = 0x4f800000;
5309
5310 alu.dst.sel = tmp3;
5311 alu.dst.write = 1;
5312 alu.last = 1;
5313 r = r600_bytecode_add_alu(ctx->bc, &alu);
5314 if (r)
5315 return r;
5316
5317 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5318 alu.op = ALU_OP1_FLT_TO_UINT;
5319
5320 alu.dst.sel = tmp0;
5321 alu.dst.chan = 0;
5322 alu.dst.write = 1;
5323
5324 alu.src[0].sel = tmp3;
5325 alu.src[0].chan = 0;
5326
5327 alu.last = 1;
5328 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5329 return r;
5330
5331 } else {
5332 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5333 alu.op = ALU_OP1_RECIP_UINT;
5334
5335 alu.dst.sel = tmp0;
5336 alu.dst.chan = 0;
5337 alu.dst.write = 1;
5338
5339 if (signed_op) {
5340 alu.src[0].sel = tmp2;
5341 alu.src[0].chan = 1;
5342 } else {
5343 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5344 }
5345
5346 alu.last = 1;
5347 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5348 return r;
5349 }
5350
5351 /* 2. tmp0.z = lo (tmp0.x * src2) */
5352 if (ctx->bc->chip_class == CAYMAN) {
5353 for (j = 0 ; j < 4; j++) {
5354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5355 alu.op = ALU_OP2_MULLO_UINT;
5356
5357 alu.dst.sel = tmp0;
5358 alu.dst.chan = j;
5359 alu.dst.write = (j == 2);
5360
5361 alu.src[0].sel = tmp0;
5362 alu.src[0].chan = 0;
5363 if (signed_op) {
5364 alu.src[1].sel = tmp2;
5365 alu.src[1].chan = 1;
5366 } else {
5367 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5368 }
5369
5370 alu.last = (j == 3);
5371 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5372 return r;
5373 }
5374 } else {
5375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5376 alu.op = ALU_OP2_MULLO_UINT;
5377
5378 alu.dst.sel = tmp0;
5379 alu.dst.chan = 2;
5380 alu.dst.write = 1;
5381
5382 alu.src[0].sel = tmp0;
5383 alu.src[0].chan = 0;
5384 if (signed_op) {
5385 alu.src[1].sel = tmp2;
5386 alu.src[1].chan = 1;
5387 } else {
5388 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5389 }
5390
5391 alu.last = 1;
5392 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5393 return r;
5394 }
5395
5396 /* 3. tmp0.w = -tmp0.z */
5397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5398 alu.op = ALU_OP2_SUB_INT;
5399
5400 alu.dst.sel = tmp0;
5401 alu.dst.chan = 3;
5402 alu.dst.write = 1;
5403
5404 alu.src[0].sel = V_SQ_ALU_SRC_0;
5405 alu.src[1].sel = tmp0;
5406 alu.src[1].chan = 2;
5407
5408 alu.last = 1;
5409 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5410 return r;
5411
5412 /* 4. tmp0.y = hi (tmp0.x * src2) */
5413 if (ctx->bc->chip_class == CAYMAN) {
5414 for (j = 0 ; j < 4; j++) {
5415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5416 alu.op = ALU_OP2_MULHI_UINT;
5417
5418 alu.dst.sel = tmp0;
5419 alu.dst.chan = j;
5420 alu.dst.write = (j == 1);
5421
5422 alu.src[0].sel = tmp0;
5423 alu.src[0].chan = 0;
5424
5425 if (signed_op) {
5426 alu.src[1].sel = tmp2;
5427 alu.src[1].chan = 1;
5428 } else {
5429 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5430 }
5431 alu.last = (j == 3);
5432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5433 return r;
5434 }
5435 } else {
5436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5437 alu.op = ALU_OP2_MULHI_UINT;
5438
5439 alu.dst.sel = tmp0;
5440 alu.dst.chan = 1;
5441 alu.dst.write = 1;
5442
5443 alu.src[0].sel = tmp0;
5444 alu.src[0].chan = 0;
5445
5446 if (signed_op) {
5447 alu.src[1].sel = tmp2;
5448 alu.src[1].chan = 1;
5449 } else {
5450 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5451 }
5452
5453 alu.last = 1;
5454 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5455 return r;
5456 }
5457
5458 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5460 alu.op = ALU_OP3_CNDE_INT;
5461 alu.is_op3 = 1;
5462
5463 alu.dst.sel = tmp0;
5464 alu.dst.chan = 2;
5465 alu.dst.write = 1;
5466
5467 alu.src[0].sel = tmp0;
5468 alu.src[0].chan = 1;
5469 alu.src[1].sel = tmp0;
5470 alu.src[1].chan = 3;
5471 alu.src[2].sel = tmp0;
5472 alu.src[2].chan = 2;
5473
5474 alu.last = 1;
5475 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5476 return r;
5477
5478 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5479 if (ctx->bc->chip_class == CAYMAN) {
5480 for (j = 0 ; j < 4; j++) {
5481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5482 alu.op = ALU_OP2_MULHI_UINT;
5483
5484 alu.dst.sel = tmp0;
5485 alu.dst.chan = j;
5486 alu.dst.write = (j == 3);
5487
5488 alu.src[0].sel = tmp0;
5489 alu.src[0].chan = 2;
5490
5491 alu.src[1].sel = tmp0;
5492 alu.src[1].chan = 0;
5493
5494 alu.last = (j == 3);
5495 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5496 return r;
5497 }
5498 } else {
5499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5500 alu.op = ALU_OP2_MULHI_UINT;
5501
5502 alu.dst.sel = tmp0;
5503 alu.dst.chan = 3;
5504 alu.dst.write = 1;
5505
5506 alu.src[0].sel = tmp0;
5507 alu.src[0].chan = 2;
5508
5509 alu.src[1].sel = tmp0;
5510 alu.src[1].chan = 0;
5511
5512 alu.last = 1;
5513 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5514 return r;
5515 }
5516
5517 /* 7. tmp1.x = tmp0.x - tmp0.w */
5518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5519 alu.op = ALU_OP2_SUB_INT;
5520
5521 alu.dst.sel = tmp1;
5522 alu.dst.chan = 0;
5523 alu.dst.write = 1;
5524
5525 alu.src[0].sel = tmp0;
5526 alu.src[0].chan = 0;
5527 alu.src[1].sel = tmp0;
5528 alu.src[1].chan = 3;
5529
5530 alu.last = 1;
5531 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5532 return r;
5533
5534 /* 8. tmp1.y = tmp0.x + tmp0.w */
5535 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5536 alu.op = ALU_OP2_ADD_INT;
5537
5538 alu.dst.sel = tmp1;
5539 alu.dst.chan = 1;
5540 alu.dst.write = 1;
5541
5542 alu.src[0].sel = tmp0;
5543 alu.src[0].chan = 0;
5544 alu.src[1].sel = tmp0;
5545 alu.src[1].chan = 3;
5546
5547 alu.last = 1;
5548 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5549 return r;
5550
5551 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5552 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5553 alu.op = ALU_OP3_CNDE_INT;
5554 alu.is_op3 = 1;
5555
5556 alu.dst.sel = tmp0;
5557 alu.dst.chan = 0;
5558 alu.dst.write = 1;
5559
5560 alu.src[0].sel = tmp0;
5561 alu.src[0].chan = 1;
5562 alu.src[1].sel = tmp1;
5563 alu.src[1].chan = 1;
5564 alu.src[2].sel = tmp1;
5565 alu.src[2].chan = 0;
5566
5567 alu.last = 1;
5568 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5569 return r;
5570
5571 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5572 if (ctx->bc->chip_class == CAYMAN) {
5573 for (j = 0 ; j < 4; j++) {
5574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5575 alu.op = ALU_OP2_MULHI_UINT;
5576
5577 alu.dst.sel = tmp0;
5578 alu.dst.chan = j;
5579 alu.dst.write = (j == 2);
5580
5581 alu.src[0].sel = tmp0;
5582 alu.src[0].chan = 0;
5583
5584 if (signed_op) {
5585 alu.src[1].sel = tmp2;
5586 alu.src[1].chan = 0;
5587 } else {
5588 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5589 }
5590
5591 alu.last = (j == 3);
5592 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5593 return r;
5594 }
5595 } else {
5596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5597 alu.op = ALU_OP2_MULHI_UINT;
5598
5599 alu.dst.sel = tmp0;
5600 alu.dst.chan = 2;
5601 alu.dst.write = 1;
5602
5603 alu.src[0].sel = tmp0;
5604 alu.src[0].chan = 0;
5605
5606 if (signed_op) {
5607 alu.src[1].sel = tmp2;
5608 alu.src[1].chan = 0;
5609 } else {
5610 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5611 }
5612
5613 alu.last = 1;
5614 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5615 return r;
5616 }
5617
5618 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5619 if (ctx->bc->chip_class == CAYMAN) {
5620 for (j = 0 ; j < 4; j++) {
5621 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5622 alu.op = ALU_OP2_MULLO_UINT;
5623
5624 alu.dst.sel = tmp0;
5625 alu.dst.chan = j;
5626 alu.dst.write = (j == 1);
5627
5628 if (signed_op) {
5629 alu.src[0].sel = tmp2;
5630 alu.src[0].chan = 1;
5631 } else {
5632 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5633 }
5634
5635 alu.src[1].sel = tmp0;
5636 alu.src[1].chan = 2;
5637
5638 alu.last = (j == 3);
5639 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5640 return r;
5641 }
5642 } else {
5643 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5644 alu.op = ALU_OP2_MULLO_UINT;
5645
5646 alu.dst.sel = tmp0;
5647 alu.dst.chan = 1;
5648 alu.dst.write = 1;
5649
5650 if (signed_op) {
5651 alu.src[0].sel = tmp2;
5652 alu.src[0].chan = 1;
5653 } else {
5654 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5655 }
5656
5657 alu.src[1].sel = tmp0;
5658 alu.src[1].chan = 2;
5659
5660 alu.last = 1;
5661 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5662 return r;
5663 }
5664
5665 /* 12. tmp0.w = src1 - tmp0.y = r */
5666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5667 alu.op = ALU_OP2_SUB_INT;
5668
5669 alu.dst.sel = tmp0;
5670 alu.dst.chan = 3;
5671 alu.dst.write = 1;
5672
5673 if (signed_op) {
5674 alu.src[0].sel = tmp2;
5675 alu.src[0].chan = 0;
5676 } else {
5677 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5678 }
5679
5680 alu.src[1].sel = tmp0;
5681 alu.src[1].chan = 1;
5682
5683 alu.last = 1;
5684 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5685 return r;
5686
5687 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5688 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5689 alu.op = ALU_OP2_SETGE_UINT;
5690
5691 alu.dst.sel = tmp1;
5692 alu.dst.chan = 0;
5693 alu.dst.write = 1;
5694
5695 alu.src[0].sel = tmp0;
5696 alu.src[0].chan = 3;
5697 if (signed_op) {
5698 alu.src[1].sel = tmp2;
5699 alu.src[1].chan = 1;
5700 } else {
5701 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5702 }
5703
5704 alu.last = 1;
5705 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5706 return r;
5707
5708 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5710 alu.op = ALU_OP2_SETGE_UINT;
5711
5712 alu.dst.sel = tmp1;
5713 alu.dst.chan = 1;
5714 alu.dst.write = 1;
5715
5716 if (signed_op) {
5717 alu.src[0].sel = tmp2;
5718 alu.src[0].chan = 0;
5719 } else {
5720 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5721 }
5722
5723 alu.src[1].sel = tmp0;
5724 alu.src[1].chan = 1;
5725
5726 alu.last = 1;
5727 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5728 return r;
5729
5730 if (mod) { /* UMOD */
5731
5732 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5734 alu.op = ALU_OP2_SUB_INT;
5735
5736 alu.dst.sel = tmp1;
5737 alu.dst.chan = 2;
5738 alu.dst.write = 1;
5739
5740 alu.src[0].sel = tmp0;
5741 alu.src[0].chan = 3;
5742
5743 if (signed_op) {
5744 alu.src[1].sel = tmp2;
5745 alu.src[1].chan = 1;
5746 } else {
5747 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5748 }
5749
5750 alu.last = 1;
5751 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5752 return r;
5753
5754 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5755 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5756 alu.op = ALU_OP2_ADD_INT;
5757
5758 alu.dst.sel = tmp1;
5759 alu.dst.chan = 3;
5760 alu.dst.write = 1;
5761
5762 alu.src[0].sel = tmp0;
5763 alu.src[0].chan = 3;
5764 if (signed_op) {
5765 alu.src[1].sel = tmp2;
5766 alu.src[1].chan = 1;
5767 } else {
5768 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5769 }
5770
5771 alu.last = 1;
5772 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5773 return r;
5774
5775 } else { /* UDIV */
5776
5777 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5779 alu.op = ALU_OP2_ADD_INT;
5780
5781 alu.dst.sel = tmp1;
5782 alu.dst.chan = 2;
5783 alu.dst.write = 1;
5784
5785 alu.src[0].sel = tmp0;
5786 alu.src[0].chan = 2;
5787 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5788
5789 alu.last = 1;
5790 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5791 return r;
5792
5793 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5795 alu.op = ALU_OP2_ADD_INT;
5796
5797 alu.dst.sel = tmp1;
5798 alu.dst.chan = 3;
5799 alu.dst.write = 1;
5800
5801 alu.src[0].sel = tmp0;
5802 alu.src[0].chan = 2;
5803 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5804
5805 alu.last = 1;
5806 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5807 return r;
5808
5809 }
5810
5811 /* 17. tmp1.x = tmp1.x & tmp1.y */
5812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5813 alu.op = ALU_OP2_AND_INT;
5814
5815 alu.dst.sel = tmp1;
5816 alu.dst.chan = 0;
5817 alu.dst.write = 1;
5818
5819 alu.src[0].sel = tmp1;
5820 alu.src[0].chan = 0;
5821 alu.src[1].sel = tmp1;
5822 alu.src[1].chan = 1;
5823
5824 alu.last = 1;
5825 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5826 return r;
5827
5828 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5829 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5831 alu.op = ALU_OP3_CNDE_INT;
5832 alu.is_op3 = 1;
5833
5834 alu.dst.sel = tmp0;
5835 alu.dst.chan = 2;
5836 alu.dst.write = 1;
5837
5838 alu.src[0].sel = tmp1;
5839 alu.src[0].chan = 0;
5840 alu.src[1].sel = tmp0;
5841 alu.src[1].chan = mod ? 3 : 2;
5842 alu.src[2].sel = tmp1;
5843 alu.src[2].chan = 2;
5844
5845 alu.last = 1;
5846 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5847 return r;
5848
5849 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5850 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5851 alu.op = ALU_OP3_CNDE_INT;
5852 alu.is_op3 = 1;
5853
5854 if (signed_op) {
5855 alu.dst.sel = tmp0;
5856 alu.dst.chan = 2;
5857 alu.dst.write = 1;
5858 } else {
5859 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5860 }
5861
5862 alu.src[0].sel = tmp1;
5863 alu.src[0].chan = 1;
5864 alu.src[1].sel = tmp1;
5865 alu.src[1].chan = 3;
5866 alu.src[2].sel = tmp0;
5867 alu.src[2].chan = 2;
5868
5869 alu.last = 1;
5870 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5871 return r;
5872
5873 if (signed_op) {
5874
5875 /* fix the sign of the result */
5876
5877 if (mod) {
5878
5879 /* tmp0.x = -tmp0.z */
5880 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5881 alu.op = ALU_OP2_SUB_INT;
5882
5883 alu.dst.sel = tmp0;
5884 alu.dst.chan = 0;
5885 alu.dst.write = 1;
5886
5887 alu.src[0].sel = V_SQ_ALU_SRC_0;
5888 alu.src[1].sel = tmp0;
5889 alu.src[1].chan = 2;
5890
5891 alu.last = 1;
5892 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5893 return r;
5894
5895 /* sign of the remainder is the same as the sign of src0 */
5896 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5898 alu.op = ALU_OP3_CNDGE_INT;
5899 alu.is_op3 = 1;
5900
5901 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5902
5903 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5904 alu.src[1].sel = tmp0;
5905 alu.src[1].chan = 2;
5906 alu.src[2].sel = tmp0;
5907 alu.src[2].chan = 0;
5908
5909 alu.last = 1;
5910 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5911 return r;
5912
5913 } else {
5914
5915 /* tmp0.x = -tmp0.z */
5916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5917 alu.op = ALU_OP2_SUB_INT;
5918
5919 alu.dst.sel = tmp0;
5920 alu.dst.chan = 0;
5921 alu.dst.write = 1;
5922
5923 alu.src[0].sel = V_SQ_ALU_SRC_0;
5924 alu.src[1].sel = tmp0;
5925 alu.src[1].chan = 2;
5926
5927 alu.last = 1;
5928 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5929 return r;
5930
5931 /* fix the quotient sign (same as the sign of src0*src1) */
5932 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5934 alu.op = ALU_OP3_CNDGE_INT;
5935 alu.is_op3 = 1;
5936
5937 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5938
5939 alu.src[0].sel = tmp2;
5940 alu.src[0].chan = 2;
5941 alu.src[1].sel = tmp0;
5942 alu.src[1].chan = 2;
5943 alu.src[2].sel = tmp0;
5944 alu.src[2].chan = 0;
5945
5946 alu.last = 1;
5947 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5948 return r;
5949 }
5950 }
5951 }
5952 return 0;
5953 }
5954
5955 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5956 {
5957 return tgsi_divmod(ctx, 0, 0);
5958 }
5959
5960 static int tgsi_umod(struct r600_shader_ctx *ctx)
5961 {
5962 return tgsi_divmod(ctx, 1, 0);
5963 }
5964
5965 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5966 {
5967 return tgsi_divmod(ctx, 0, 1);
5968 }
5969
5970 static int tgsi_imod(struct r600_shader_ctx *ctx)
5971 {
5972 return tgsi_divmod(ctx, 1, 1);
5973 }
5974
5975
5976 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5977 {
5978 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5979 struct r600_bytecode_alu alu;
5980 int i, r;
5981 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5982 int last_inst = tgsi_last_instruction(write_mask);
5983
5984 for (i = 0; i < 4; i++) {
5985 if (!(write_mask & (1<<i)))
5986 continue;
5987
5988 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5989 alu.op = ALU_OP1_TRUNC;
5990
5991 alu.dst.sel = ctx->temp_reg;
5992 alu.dst.chan = i;
5993 alu.dst.write = 1;
5994
5995 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5996 if (i == last_inst)
5997 alu.last = 1;
5998 r = r600_bytecode_add_alu(ctx->bc, &alu);
5999 if (r)
6000 return r;
6001 }
6002
6003 for (i = 0; i < 4; i++) {
6004 if (!(write_mask & (1<<i)))
6005 continue;
6006
6007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6008 alu.op = ctx->inst_info->op;
6009
6010 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6011
6012 alu.src[0].sel = ctx->temp_reg;
6013 alu.src[0].chan = i;
6014
6015 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6016 alu.last = 1;
6017 r = r600_bytecode_add_alu(ctx->bc, &alu);
6018 if (r)
6019 return r;
6020 }
6021
6022 return 0;
6023 }
6024
6025 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6026 {
6027 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6028 struct r600_bytecode_alu alu;
6029 int i, r;
6030 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6031 int last_inst = tgsi_last_instruction(write_mask);
6032
6033 /* tmp = -src */
6034 for (i = 0; i < 4; i++) {
6035 if (!(write_mask & (1<<i)))
6036 continue;
6037
6038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6039 alu.op = ALU_OP2_SUB_INT;
6040
6041 alu.dst.sel = ctx->temp_reg;
6042 alu.dst.chan = i;
6043 alu.dst.write = 1;
6044
6045 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6046 alu.src[0].sel = V_SQ_ALU_SRC_0;
6047
6048 if (i == last_inst)
6049 alu.last = 1;
6050 r = r600_bytecode_add_alu(ctx->bc, &alu);
6051 if (r)
6052 return r;
6053 }
6054
6055 /* dst = (src >= 0 ? src : tmp) */
6056 for (i = 0; i < 4; i++) {
6057 if (!(write_mask & (1<<i)))
6058 continue;
6059
6060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6061 alu.op = ALU_OP3_CNDGE_INT;
6062 alu.is_op3 = 1;
6063 alu.dst.write = 1;
6064
6065 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6066
6067 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6068 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6069 alu.src[2].sel = ctx->temp_reg;
6070 alu.src[2].chan = i;
6071
6072 if (i == last_inst)
6073 alu.last = 1;
6074 r = r600_bytecode_add_alu(ctx->bc, &alu);
6075 if (r)
6076 return r;
6077 }
6078 return 0;
6079 }
6080
6081 static int tgsi_issg(struct r600_shader_ctx *ctx)
6082 {
6083 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6084 struct r600_bytecode_alu alu;
6085 int i, r;
6086 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6087 int last_inst = tgsi_last_instruction(write_mask);
6088
6089 /* tmp = (src >= 0 ? src : -1) */
6090 for (i = 0; i < 4; i++) {
6091 if (!(write_mask & (1<<i)))
6092 continue;
6093
6094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6095 alu.op = ALU_OP3_CNDGE_INT;
6096 alu.is_op3 = 1;
6097
6098 alu.dst.sel = ctx->temp_reg;
6099 alu.dst.chan = i;
6100 alu.dst.write = 1;
6101
6102 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6103 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6104 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6105
6106 if (i == last_inst)
6107 alu.last = 1;
6108 r = r600_bytecode_add_alu(ctx->bc, &alu);
6109 if (r)
6110 return r;
6111 }
6112
6113 /* dst = (tmp > 0 ? 1 : tmp) */
6114 for (i = 0; i < 4; i++) {
6115 if (!(write_mask & (1<<i)))
6116 continue;
6117
6118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6119 alu.op = ALU_OP3_CNDGT_INT;
6120 alu.is_op3 = 1;
6121 alu.dst.write = 1;
6122
6123 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6124
6125 alu.src[0].sel = ctx->temp_reg;
6126 alu.src[0].chan = i;
6127
6128 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6129
6130 alu.src[2].sel = ctx->temp_reg;
6131 alu.src[2].chan = i;
6132
6133 if (i == last_inst)
6134 alu.last = 1;
6135 r = r600_bytecode_add_alu(ctx->bc, &alu);
6136 if (r)
6137 return r;
6138 }
6139 return 0;
6140 }
6141
6142
6143
6144 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6145 {
6146 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6147 struct r600_bytecode_alu alu;
6148 int i, r;
6149
6150 /* tmp = (src > 0 ? 1 : src) */
6151 for (i = 0; i < 4; i++) {
6152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6153 alu.op = ALU_OP3_CNDGT;
6154 alu.is_op3 = 1;
6155
6156 alu.dst.sel = ctx->temp_reg;
6157 alu.dst.chan = i;
6158
6159 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6160 alu.src[1].sel = V_SQ_ALU_SRC_1;
6161 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6162
6163 if (i == 3)
6164 alu.last = 1;
6165 r = r600_bytecode_add_alu(ctx->bc, &alu);
6166 if (r)
6167 return r;
6168 }
6169
6170 /* dst = (-tmp > 0 ? -1 : tmp) */
6171 for (i = 0; i < 4; i++) {
6172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6173 alu.op = ALU_OP3_CNDGT;
6174 alu.is_op3 = 1;
6175 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6176
6177 alu.src[0].sel = ctx->temp_reg;
6178 alu.src[0].chan = i;
6179 alu.src[0].neg = 1;
6180
6181 alu.src[1].sel = V_SQ_ALU_SRC_1;
6182 alu.src[1].neg = 1;
6183
6184 alu.src[2].sel = ctx->temp_reg;
6185 alu.src[2].chan = i;
6186
6187 if (i == 3)
6188 alu.last = 1;
6189 r = r600_bytecode_add_alu(ctx->bc, &alu);
6190 if (r)
6191 return r;
6192 }
6193 return 0;
6194 }
6195
6196 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6197 {
6198 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6199 struct r600_bytecode_alu alu;
6200 int i, r, t1, t2;
6201
6202 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6203 int last_inst = tgsi_last_instruction(write_mask);
6204
6205 t1 = r600_get_temp(ctx);
6206
6207 for (i = 0; i < 4; i++) {
6208 if (!(write_mask & (1<<i)))
6209 continue;
6210
6211 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6212 alu.op = ALU_OP2_SETGE_INT;
6213 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6214 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6215 alu.src[1].value = 32;
6216 alu.dst.sel = ctx->temp_reg;
6217 alu.dst.chan = i;
6218 alu.dst.write = 1;
6219 alu.last = i == last_inst;
6220 r = r600_bytecode_add_alu(ctx->bc, &alu);
6221 if (r)
6222 return r;
6223 }
6224
6225 for (i = 0; i < 4; i++) {
6226 if (!(write_mask & (1<<i)))
6227 continue;
6228
6229 /* create mask tmp */
6230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6231 alu.op = ALU_OP2_BFM_INT;
6232 alu.dst.sel = t1;
6233 alu.dst.chan = i;
6234 alu.dst.write = 1;
6235 alu.last = i == last_inst;
6236
6237 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6238 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6239
6240 r = r600_bytecode_add_alu(ctx->bc, &alu);
6241 if (r)
6242 return r;
6243 }
6244
6245 t2 = r600_get_temp(ctx);
6246
6247 for (i = 0; i < 4; i++) {
6248 if (!(write_mask & (1<<i)))
6249 continue;
6250
6251 /* shift insert left */
6252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6253 alu.op = ALU_OP2_LSHL_INT;
6254 alu.dst.sel = t2;
6255 alu.dst.chan = i;
6256 alu.dst.write = 1;
6257 alu.last = i == last_inst;
6258
6259 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6260 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6261
6262 r = r600_bytecode_add_alu(ctx->bc, &alu);
6263 if (r)
6264 return r;
6265 }
6266
6267 for (i = 0; i < 4; i++) {
6268 if (!(write_mask & (1<<i)))
6269 continue;
6270
6271 /* actual bitfield insert */
6272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6273 alu.op = ALU_OP3_BFI_INT;
6274 alu.is_op3 = 1;
6275 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6276 alu.dst.chan = i;
6277 alu.dst.write = 1;
6278 alu.last = i == last_inst;
6279
6280 alu.src[0].sel = t1;
6281 alu.src[0].chan = i;
6282 alu.src[1].sel = t2;
6283 alu.src[1].chan = i;
6284 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6285
6286 r = r600_bytecode_add_alu(ctx->bc, &alu);
6287 if (r)
6288 return r;
6289 }
6290
6291 for (i = 0; i < 4; i++) {
6292 if (!(write_mask & (1<<i)))
6293 continue;
6294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6295 alu.op = ALU_OP3_CNDE_INT;
6296 alu.is_op3 = 1;
6297 alu.src[0].sel = ctx->temp_reg;
6298 alu.src[0].chan = i;
6299 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6300
6301 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6302
6303 alu.src[1].sel = alu.dst.sel;
6304 alu.src[1].chan = i;
6305
6306 alu.last = i == last_inst;
6307 r = r600_bytecode_add_alu(ctx->bc, &alu);
6308 if (r)
6309 return r;
6310 }
6311 return 0;
6312 }
6313
6314 static int tgsi_msb(struct r600_shader_ctx *ctx)
6315 {
6316 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6317 struct r600_bytecode_alu alu;
6318 int i, r, t1, t2;
6319
6320 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6321 int last_inst = tgsi_last_instruction(write_mask);
6322
6323 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6324 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6325
6326 t1 = ctx->temp_reg;
6327
6328 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6329 for (i = 0; i < 4; i++) {
6330 if (!(write_mask & (1<<i)))
6331 continue;
6332
6333 /* t1 = FFBH_INT / FFBH_UINT */
6334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6335 alu.op = ctx->inst_info->op;
6336 alu.dst.sel = t1;
6337 alu.dst.chan = i;
6338 alu.dst.write = 1;
6339 alu.last = i == last_inst;
6340
6341 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6342
6343 r = r600_bytecode_add_alu(ctx->bc, &alu);
6344 if (r)
6345 return r;
6346 }
6347
6348 t2 = r600_get_temp(ctx);
6349
6350 for (i = 0; i < 4; i++) {
6351 if (!(write_mask & (1<<i)))
6352 continue;
6353
6354 /* t2 = 31 - t1 */
6355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6356 alu.op = ALU_OP2_SUB_INT;
6357 alu.dst.sel = t2;
6358 alu.dst.chan = i;
6359 alu.dst.write = 1;
6360 alu.last = i == last_inst;
6361
6362 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6363 alu.src[0].value = 31;
6364 alu.src[1].sel = t1;
6365 alu.src[1].chan = i;
6366
6367 r = r600_bytecode_add_alu(ctx->bc, &alu);
6368 if (r)
6369 return r;
6370 }
6371
6372 for (i = 0; i < 4; i++) {
6373 if (!(write_mask & (1<<i)))
6374 continue;
6375
6376 /* result = t1 >= 0 ? t2 : t1 */
6377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6378 alu.op = ALU_OP3_CNDGE_INT;
6379 alu.is_op3 = 1;
6380 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6381 alu.dst.chan = i;
6382 alu.dst.write = 1;
6383 alu.last = i == last_inst;
6384
6385 alu.src[0].sel = t1;
6386 alu.src[0].chan = i;
6387 alu.src[1].sel = t2;
6388 alu.src[1].chan = i;
6389 alu.src[2].sel = t1;
6390 alu.src[2].chan = i;
6391
6392 r = r600_bytecode_add_alu(ctx->bc, &alu);
6393 if (r)
6394 return r;
6395 }
6396
6397 return 0;
6398 }
6399
6400 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6401 {
6402 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6403 struct r600_bytecode_alu alu;
6404 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6405 unsigned location;
6406 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6407
6408 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6409
6410 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6411 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6412 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6413 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6414 }
6415 else {
6416 location = TGSI_INTERPOLATE_LOC_CENTROID;
6417 }
6418
6419 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6420 if (k < 0)
6421 k = 0;
6422 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6423 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6424
6425 /* NOTE: currently offset is not perspective correct */
6426 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6427 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6428 int sample_gpr = -1;
6429 int gradientsH, gradientsV;
6430 struct r600_bytecode_tex tex;
6431
6432 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6433 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6434 }
6435
6436 gradientsH = r600_get_temp(ctx);
6437 gradientsV = r600_get_temp(ctx);
6438 for (i = 0; i < 2; i++) {
6439 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6440 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6441 tex.src_gpr = interp_gpr;
6442 tex.src_sel_x = interp_base_chan + 0;
6443 tex.src_sel_y = interp_base_chan + 1;
6444 tex.src_sel_z = 0;
6445 tex.src_sel_w = 0;
6446 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6447 tex.dst_sel_x = 0;
6448 tex.dst_sel_y = 1;
6449 tex.dst_sel_z = 7;
6450 tex.dst_sel_w = 7;
6451 tex.inst_mod = 1; // Use per pixel gradient calculation
6452 tex.sampler_id = 0;
6453 tex.resource_id = tex.sampler_id;
6454 r = r600_bytecode_add_tex(ctx->bc, &tex);
6455 if (r)
6456 return r;
6457 }
6458
6459 for (i = 0; i < 2; i++) {
6460 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6461 alu.op = ALU_OP3_MULADD;
6462 alu.is_op3 = 1;
6463 alu.src[0].sel = gradientsH;
6464 alu.src[0].chan = i;
6465 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6466 alu.src[1].sel = sample_gpr;
6467 alu.src[1].chan = 2;
6468 }
6469 else {
6470 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6471 }
6472 alu.src[2].sel = interp_gpr;
6473 alu.src[2].chan = interp_base_chan + i;
6474 alu.dst.sel = ctx->temp_reg;
6475 alu.dst.chan = i;
6476 alu.last = i == 1;
6477
6478 r = r600_bytecode_add_alu(ctx->bc, &alu);
6479 if (r)
6480 return r;
6481 }
6482
6483 for (i = 0; i < 2; i++) {
6484 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6485 alu.op = ALU_OP3_MULADD;
6486 alu.is_op3 = 1;
6487 alu.src[0].sel = gradientsV;
6488 alu.src[0].chan = i;
6489 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6490 alu.src[1].sel = sample_gpr;
6491 alu.src[1].chan = 3;
6492 }
6493 else {
6494 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6495 }
6496 alu.src[2].sel = ctx->temp_reg;
6497 alu.src[2].chan = i;
6498 alu.dst.sel = ctx->temp_reg;
6499 alu.dst.chan = i;
6500 alu.last = i == 1;
6501
6502 r = r600_bytecode_add_alu(ctx->bc, &alu);
6503 if (r)
6504 return r;
6505 }
6506 }
6507
6508 tmp = r600_get_temp(ctx);
6509 for (i = 0; i < 8; i++) {
6510 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6511 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6512
6513 alu.dst.sel = tmp;
6514 if ((i > 1 && i < 6)) {
6515 alu.dst.write = 1;
6516 }
6517 else {
6518 alu.dst.write = 0;
6519 }
6520 alu.dst.chan = i % 4;
6521
6522 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6523 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6524 alu.src[0].sel = ctx->temp_reg;
6525 alu.src[0].chan = 1 - (i % 2);
6526 } else {
6527 alu.src[0].sel = interp_gpr;
6528 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6529 }
6530 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6531 alu.src[1].chan = 0;
6532
6533 alu.last = i % 4 == 3;
6534 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6535
6536 r = r600_bytecode_add_alu(ctx->bc, &alu);
6537 if (r)
6538 return r;
6539 }
6540
6541 // INTERP can't swizzle dst
6542 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6543 for (i = 0; i <= lasti; i++) {
6544 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6545 continue;
6546
6547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6548 alu.op = ALU_OP1_MOV;
6549 alu.src[0].sel = tmp;
6550 alu.src[0].chan = ctx->src[0].swizzle[i];
6551 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6552 alu.dst.write = 1;
6553 alu.last = i == lasti;
6554 r = r600_bytecode_add_alu(ctx->bc, &alu);
6555 if (r)
6556 return r;
6557 }
6558
6559 return 0;
6560 }
6561
6562
6563 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6564 {
6565 struct r600_bytecode_alu alu;
6566 int i, r;
6567
6568 for (i = 0; i < 4; i++) {
6569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6570 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6571 alu.op = ALU_OP0_NOP;
6572 alu.dst.chan = i;
6573 } else {
6574 alu.op = ALU_OP1_MOV;
6575 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6576 alu.src[0].sel = ctx->temp_reg;
6577 alu.src[0].chan = i;
6578 }
6579 if (i == 3) {
6580 alu.last = 1;
6581 }
6582 r = r600_bytecode_add_alu(ctx->bc, &alu);
6583 if (r)
6584 return r;
6585 }
6586 return 0;
6587 }
6588
6589 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6590 unsigned temp, int chan,
6591 struct r600_bytecode_alu_src *bc_src,
6592 const struct r600_shader_src *shader_src)
6593 {
6594 struct r600_bytecode_alu alu;
6595 int r;
6596
6597 r600_bytecode_src(bc_src, shader_src, chan);
6598
6599 /* op3 operands don't support abs modifier */
6600 if (bc_src->abs) {
6601 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6602 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6603 alu.op = ALU_OP1_MOV;
6604 alu.dst.sel = temp;
6605 alu.dst.chan = chan;
6606 alu.dst.write = 1;
6607
6608 alu.src[0] = *bc_src;
6609 alu.last = true; // sufficient?
6610 r = r600_bytecode_add_alu(ctx->bc, &alu);
6611 if (r)
6612 return r;
6613
6614 memset(bc_src, 0, sizeof(*bc_src));
6615 bc_src->sel = temp;
6616 bc_src->chan = chan;
6617 }
6618 return 0;
6619 }
6620
6621 static int tgsi_op3(struct r600_shader_ctx *ctx)
6622 {
6623 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6624 struct r600_bytecode_alu alu;
6625 int i, j, r;
6626 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6627 int temp_regs[4];
6628 unsigned op = ctx->inst_info->op;
6629
6630 if (op == ALU_OP3_MULADD_IEEE &&
6631 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6632 op = ALU_OP3_MULADD;
6633
6634 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6635 temp_regs[j] = 0;
6636 if (ctx->src[j].abs)
6637 temp_regs[j] = r600_get_temp(ctx);
6638 }
6639 for (i = 0; i < lasti + 1; i++) {
6640 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6641 continue;
6642
6643 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6644 alu.op = op;
6645 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6646 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6647 if (r)
6648 return r;
6649 }
6650
6651 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6652 alu.dst.chan = i;
6653 alu.dst.write = 1;
6654 alu.is_op3 = 1;
6655 if (i == lasti) {
6656 alu.last = 1;
6657 }
6658 r = r600_bytecode_add_alu(ctx->bc, &alu);
6659 if (r)
6660 return r;
6661 }
6662 return 0;
6663 }
6664
6665 static int tgsi_dp(struct r600_shader_ctx *ctx)
6666 {
6667 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6668 struct r600_bytecode_alu alu;
6669 int i, j, r;
6670 unsigned op = ctx->inst_info->op;
6671 if (op == ALU_OP2_DOT4_IEEE &&
6672 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6673 op = ALU_OP2_DOT4;
6674
6675 for (i = 0; i < 4; i++) {
6676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6677 alu.op = op;
6678 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6679 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6680 }
6681
6682 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6683 alu.dst.chan = i;
6684 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6685 /* handle some special cases */
6686 switch (inst->Instruction.Opcode) {
6687 case TGSI_OPCODE_DP2:
6688 if (i > 1) {
6689 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6690 alu.src[0].chan = alu.src[1].chan = 0;
6691 }
6692 break;
6693 case TGSI_OPCODE_DP3:
6694 if (i > 2) {
6695 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6696 alu.src[0].chan = alu.src[1].chan = 0;
6697 }
6698 break;
6699 default:
6700 break;
6701 }
6702 if (i == 3) {
6703 alu.last = 1;
6704 }
6705 r = r600_bytecode_add_alu(ctx->bc, &alu);
6706 if (r)
6707 return r;
6708 }
6709 return 0;
6710 }
6711
6712 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6713 unsigned index)
6714 {
6715 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6716 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6717 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6718 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6719 ctx->src[index].neg || ctx->src[index].abs ||
6720 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6721 }
6722
6723 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6724 unsigned index)
6725 {
6726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6727 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6728 }
6729
6730 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6731 {
6732 struct r600_bytecode_vtx vtx;
6733 struct r600_bytecode_alu alu;
6734 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6735 int src_gpr, r, i;
6736 int id = tgsi_tex_get_src_gpr(ctx, 1);
6737
6738 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6739 if (src_requires_loading) {
6740 for (i = 0; i < 4; i++) {
6741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6742 alu.op = ALU_OP1_MOV;
6743 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6744 alu.dst.sel = ctx->temp_reg;
6745 alu.dst.chan = i;
6746 if (i == 3)
6747 alu.last = 1;
6748 alu.dst.write = 1;
6749 r = r600_bytecode_add_alu(ctx->bc, &alu);
6750 if (r)
6751 return r;
6752 }
6753 src_gpr = ctx->temp_reg;
6754 }
6755
6756 memset(&vtx, 0, sizeof(vtx));
6757 vtx.op = FETCH_OP_VFETCH;
6758 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6759 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6760 vtx.src_gpr = src_gpr;
6761 vtx.mega_fetch_count = 16;
6762 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6763 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6764 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6765 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6766 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6767 vtx.use_const_fields = 1;
6768
6769 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6770 return r;
6771
6772 if (ctx->bc->chip_class >= EVERGREEN)
6773 return 0;
6774
6775 for (i = 0; i < 4; i++) {
6776 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6777 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6778 continue;
6779
6780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6781 alu.op = ALU_OP2_AND_INT;
6782
6783 alu.dst.chan = i;
6784 alu.dst.sel = vtx.dst_gpr;
6785 alu.dst.write = 1;
6786
6787 alu.src[0].sel = vtx.dst_gpr;
6788 alu.src[0].chan = i;
6789
6790 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6791 alu.src[1].sel += (id * 2);
6792 alu.src[1].chan = i % 4;
6793 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6794
6795 if (i == lasti)
6796 alu.last = 1;
6797 r = r600_bytecode_add_alu(ctx->bc, &alu);
6798 if (r)
6799 return r;
6800 }
6801
6802 if (inst->Dst[0].Register.WriteMask & 3) {
6803 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6804 alu.op = ALU_OP2_OR_INT;
6805
6806 alu.dst.chan = 3;
6807 alu.dst.sel = vtx.dst_gpr;
6808 alu.dst.write = 1;
6809
6810 alu.src[0].sel = vtx.dst_gpr;
6811 alu.src[0].chan = 3;
6812
6813 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6814 alu.src[1].chan = 0;
6815 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6816
6817 alu.last = 1;
6818 r = r600_bytecode_add_alu(ctx->bc, &alu);
6819 if (r)
6820 return r;
6821 }
6822 return 0;
6823 }
6824
6825 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset)
6826 {
6827 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6828 struct r600_bytecode_alu alu;
6829 int r;
6830 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
6831
6832 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6833 alu.op = ALU_OP1_MOV;
6834 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6835 if (ctx->bc->chip_class >= EVERGREEN) {
6836 /* channel 0 or 2 of each word */
6837 alu.src[0].sel += (id / 2);
6838 alu.src[0].chan = (id % 2) * 2;
6839 } else {
6840 /* r600 we have them at channel 2 of the second dword */
6841 alu.src[0].sel += (id * 2) + 1;
6842 alu.src[0].chan = 1;
6843 }
6844 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6845 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6846 alu.last = 1;
6847 r = r600_bytecode_add_alu(ctx->bc, &alu);
6848 if (r)
6849 return r;
6850 return 0;
6851 }
6852
6853 static int tgsi_tex(struct r600_shader_ctx *ctx)
6854 {
6855 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6856 struct r600_bytecode_tex tex;
6857 struct r600_bytecode_alu alu;
6858 unsigned src_gpr;
6859 int r, i, j;
6860 int opcode;
6861 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6862 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6863 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6864 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6865
6866 bool txf_add_offsets = inst->Texture.NumOffsets &&
6867 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6868 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6869
6870 /* Texture fetch instructions can only use gprs as source.
6871 * Also they cannot negate the source or take the absolute value */
6872 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6873 tgsi_tex_src_requires_loading(ctx, 0)) ||
6874 read_compressed_msaa || txf_add_offsets;
6875
6876 boolean src_loaded = FALSE;
6877 unsigned sampler_src_reg = 1;
6878 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6879 boolean has_txq_cube_array_z = false;
6880 unsigned sampler_index_mode;
6881
6882 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6883 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6884 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6885 if (inst->Dst[0].Register.WriteMask & 4) {
6886 ctx->shader->has_txq_cube_array_z_comp = true;
6887 has_txq_cube_array_z = true;
6888 }
6889
6890 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6891 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6892 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6893 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6894 sampler_src_reg = 2;
6895
6896 /* TGSI moves the sampler to src reg 3 for TXD */
6897 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6898 sampler_src_reg = 3;
6899
6900 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6901
6902 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6903
6904 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6905 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6906 ctx->shader->uses_tex_buffers = true;
6907 return r600_do_buffer_txq(ctx, 1, 0);
6908 }
6909 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6910 if (ctx->bc->chip_class < EVERGREEN)
6911 ctx->shader->uses_tex_buffers = true;
6912 return do_vtx_fetch_inst(ctx, src_requires_loading);
6913 }
6914 }
6915
6916 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6917 int out_chan;
6918 /* Add perspective divide */
6919 if (ctx->bc->chip_class == CAYMAN) {
6920 out_chan = 2;
6921 for (i = 0; i < 3; i++) {
6922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6923 alu.op = ALU_OP1_RECIP_IEEE;
6924 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6925
6926 alu.dst.sel = ctx->temp_reg;
6927 alu.dst.chan = i;
6928 if (i == 2)
6929 alu.last = 1;
6930 if (out_chan == i)
6931 alu.dst.write = 1;
6932 r = r600_bytecode_add_alu(ctx->bc, &alu);
6933 if (r)
6934 return r;
6935 }
6936
6937 } else {
6938 out_chan = 3;
6939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6940 alu.op = ALU_OP1_RECIP_IEEE;
6941 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6942
6943 alu.dst.sel = ctx->temp_reg;
6944 alu.dst.chan = out_chan;
6945 alu.last = 1;
6946 alu.dst.write = 1;
6947 r = r600_bytecode_add_alu(ctx->bc, &alu);
6948 if (r)
6949 return r;
6950 }
6951
6952 for (i = 0; i < 3; i++) {
6953 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6954 alu.op = ALU_OP2_MUL;
6955 alu.src[0].sel = ctx->temp_reg;
6956 alu.src[0].chan = out_chan;
6957 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6958 alu.dst.sel = ctx->temp_reg;
6959 alu.dst.chan = i;
6960 alu.dst.write = 1;
6961 r = r600_bytecode_add_alu(ctx->bc, &alu);
6962 if (r)
6963 return r;
6964 }
6965 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6966 alu.op = ALU_OP1_MOV;
6967 alu.src[0].sel = V_SQ_ALU_SRC_1;
6968 alu.src[0].chan = 0;
6969 alu.dst.sel = ctx->temp_reg;
6970 alu.dst.chan = 3;
6971 alu.last = 1;
6972 alu.dst.write = 1;
6973 r = r600_bytecode_add_alu(ctx->bc, &alu);
6974 if (r)
6975 return r;
6976 src_loaded = TRUE;
6977 src_gpr = ctx->temp_reg;
6978 }
6979
6980
6981 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6982 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6983 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6984 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6985 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
6986
6987 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6988 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6989
6990 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6991 for (i = 0; i < 4; i++) {
6992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6993 alu.op = ALU_OP2_CUBE;
6994 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6995 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6996 alu.dst.sel = ctx->temp_reg;
6997 alu.dst.chan = i;
6998 if (i == 3)
6999 alu.last = 1;
7000 alu.dst.write = 1;
7001 r = r600_bytecode_add_alu(ctx->bc, &alu);
7002 if (r)
7003 return r;
7004 }
7005
7006 /* tmp1.z = RCP_e(|tmp1.z|) */
7007 if (ctx->bc->chip_class == CAYMAN) {
7008 for (i = 0; i < 3; i++) {
7009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7010 alu.op = ALU_OP1_RECIP_IEEE;
7011 alu.src[0].sel = ctx->temp_reg;
7012 alu.src[0].chan = 2;
7013 alu.src[0].abs = 1;
7014 alu.dst.sel = ctx->temp_reg;
7015 alu.dst.chan = i;
7016 if (i == 2)
7017 alu.dst.write = 1;
7018 if (i == 2)
7019 alu.last = 1;
7020 r = r600_bytecode_add_alu(ctx->bc, &alu);
7021 if (r)
7022 return r;
7023 }
7024 } else {
7025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7026 alu.op = ALU_OP1_RECIP_IEEE;
7027 alu.src[0].sel = ctx->temp_reg;
7028 alu.src[0].chan = 2;
7029 alu.src[0].abs = 1;
7030 alu.dst.sel = ctx->temp_reg;
7031 alu.dst.chan = 2;
7032 alu.dst.write = 1;
7033 alu.last = 1;
7034 r = r600_bytecode_add_alu(ctx->bc, &alu);
7035 if (r)
7036 return r;
7037 }
7038
7039 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7040 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7041 * muladd has no writemask, have to use another temp
7042 */
7043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7044 alu.op = ALU_OP3_MULADD;
7045 alu.is_op3 = 1;
7046
7047 alu.src[0].sel = ctx->temp_reg;
7048 alu.src[0].chan = 0;
7049 alu.src[1].sel = ctx->temp_reg;
7050 alu.src[1].chan = 2;
7051
7052 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7053 alu.src[2].chan = 0;
7054 alu.src[2].value = u_bitcast_f2u(1.5f);
7055
7056 alu.dst.sel = ctx->temp_reg;
7057 alu.dst.chan = 0;
7058 alu.dst.write = 1;
7059
7060 r = r600_bytecode_add_alu(ctx->bc, &alu);
7061 if (r)
7062 return r;
7063
7064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7065 alu.op = ALU_OP3_MULADD;
7066 alu.is_op3 = 1;
7067
7068 alu.src[0].sel = ctx->temp_reg;
7069 alu.src[0].chan = 1;
7070 alu.src[1].sel = ctx->temp_reg;
7071 alu.src[1].chan = 2;
7072
7073 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7074 alu.src[2].chan = 0;
7075 alu.src[2].value = u_bitcast_f2u(1.5f);
7076
7077 alu.dst.sel = ctx->temp_reg;
7078 alu.dst.chan = 1;
7079 alu.dst.write = 1;
7080
7081 alu.last = 1;
7082 r = r600_bytecode_add_alu(ctx->bc, &alu);
7083 if (r)
7084 return r;
7085 /* write initial compare value into Z component
7086 - W src 0 for shadow cube
7087 - X src 1 for shadow cube array */
7088 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7089 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7091 alu.op = ALU_OP1_MOV;
7092 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7093 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7094 else
7095 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7096 alu.dst.sel = ctx->temp_reg;
7097 alu.dst.chan = 2;
7098 alu.dst.write = 1;
7099 alu.last = 1;
7100 r = r600_bytecode_add_alu(ctx->bc, &alu);
7101 if (r)
7102 return r;
7103 }
7104
7105 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7106 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7107 if (ctx->bc->chip_class >= EVERGREEN) {
7108 int mytmp = r600_get_temp(ctx);
7109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7110 alu.op = ALU_OP1_MOV;
7111 alu.src[0].sel = ctx->temp_reg;
7112 alu.src[0].chan = 3;
7113 alu.dst.sel = mytmp;
7114 alu.dst.chan = 0;
7115 alu.dst.write = 1;
7116 alu.last = 1;
7117 r = r600_bytecode_add_alu(ctx->bc, &alu);
7118 if (r)
7119 return r;
7120
7121 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7123 alu.op = ALU_OP3_MULADD;
7124 alu.is_op3 = 1;
7125 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7126 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7127 alu.src[1].chan = 0;
7128 alu.src[1].value = u_bitcast_f2u(8.0f);
7129 alu.src[2].sel = mytmp;
7130 alu.src[2].chan = 0;
7131 alu.dst.sel = ctx->temp_reg;
7132 alu.dst.chan = 3;
7133 alu.dst.write = 1;
7134 alu.last = 1;
7135 r = r600_bytecode_add_alu(ctx->bc, &alu);
7136 if (r)
7137 return r;
7138 } else if (ctx->bc->chip_class < EVERGREEN) {
7139 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7140 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7141 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7142 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7143 tex.src_gpr = r600_get_temp(ctx);
7144 tex.src_sel_x = 0;
7145 tex.src_sel_y = 0;
7146 tex.src_sel_z = 0;
7147 tex.src_sel_w = 0;
7148 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7149 tex.coord_type_x = 1;
7150 tex.coord_type_y = 1;
7151 tex.coord_type_z = 1;
7152 tex.coord_type_w = 1;
7153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7154 alu.op = ALU_OP1_MOV;
7155 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7156 alu.dst.sel = tex.src_gpr;
7157 alu.dst.chan = 0;
7158 alu.last = 1;
7159 alu.dst.write = 1;
7160 r = r600_bytecode_add_alu(ctx->bc, &alu);
7161 if (r)
7162 return r;
7163
7164 r = r600_bytecode_add_tex(ctx->bc, &tex);
7165 if (r)
7166 return r;
7167 }
7168
7169 }
7170
7171 /* for cube forms of lod and bias we need to route things */
7172 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7173 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7174 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7175 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7176 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7177 alu.op = ALU_OP1_MOV;
7178 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7179 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7180 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7181 else
7182 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7183 alu.dst.sel = ctx->temp_reg;
7184 alu.dst.chan = 2;
7185 alu.last = 1;
7186 alu.dst.write = 1;
7187 r = r600_bytecode_add_alu(ctx->bc, &alu);
7188 if (r)
7189 return r;
7190 }
7191
7192 src_loaded = TRUE;
7193 src_gpr = ctx->temp_reg;
7194 }
7195
7196 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7197 int temp_h = 0, temp_v = 0;
7198 int start_val = 0;
7199
7200 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7201 if (src_loaded == TRUE)
7202 start_val = 1;
7203 else
7204 src_loaded = TRUE;
7205 for (i = start_val; i < 3; i++) {
7206 int treg = r600_get_temp(ctx);
7207
7208 if (i == 0)
7209 src_gpr = treg;
7210 else if (i == 1)
7211 temp_h = treg;
7212 else
7213 temp_v = treg;
7214
7215 for (j = 0; j < 4; j++) {
7216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7217 alu.op = ALU_OP1_MOV;
7218 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7219 alu.dst.sel = treg;
7220 alu.dst.chan = j;
7221 if (j == 3)
7222 alu.last = 1;
7223 alu.dst.write = 1;
7224 r = r600_bytecode_add_alu(ctx->bc, &alu);
7225 if (r)
7226 return r;
7227 }
7228 }
7229 for (i = 1; i < 3; i++) {
7230 /* set gradients h/v */
7231 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7232 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7233 FETCH_OP_SET_GRADIENTS_V;
7234 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7235 tex.sampler_index_mode = sampler_index_mode;
7236 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7237 tex.resource_index_mode = sampler_index_mode;
7238
7239 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7240 tex.src_sel_x = 0;
7241 tex.src_sel_y = 1;
7242 tex.src_sel_z = 2;
7243 tex.src_sel_w = 3;
7244
7245 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7246 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7247 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7248 tex.coord_type_x = 1;
7249 tex.coord_type_y = 1;
7250 tex.coord_type_z = 1;
7251 tex.coord_type_w = 1;
7252 }
7253 r = r600_bytecode_add_tex(ctx->bc, &tex);
7254 if (r)
7255 return r;
7256 }
7257 }
7258
7259 if (src_requires_loading && !src_loaded) {
7260 for (i = 0; i < 4; i++) {
7261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7262 alu.op = ALU_OP1_MOV;
7263 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7264 alu.dst.sel = ctx->temp_reg;
7265 alu.dst.chan = i;
7266 if (i == 3)
7267 alu.last = 1;
7268 alu.dst.write = 1;
7269 r = r600_bytecode_add_alu(ctx->bc, &alu);
7270 if (r)
7271 return r;
7272 }
7273 src_loaded = TRUE;
7274 src_gpr = ctx->temp_reg;
7275 }
7276
7277 /* get offset values */
7278 if (inst->Texture.NumOffsets) {
7279 assert(inst->Texture.NumOffsets == 1);
7280
7281 /* The texture offset feature doesn't work with the TXF instruction
7282 * and must be emulated by adding the offset to the texture coordinates. */
7283 if (txf_add_offsets) {
7284 const struct tgsi_texture_offset *off = inst->TexOffsets;
7285
7286 switch (inst->Texture.Texture) {
7287 case TGSI_TEXTURE_3D:
7288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7289 alu.op = ALU_OP2_ADD_INT;
7290 alu.src[0].sel = src_gpr;
7291 alu.src[0].chan = 2;
7292 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7293 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7294 alu.dst.sel = src_gpr;
7295 alu.dst.chan = 2;
7296 alu.dst.write = 1;
7297 alu.last = 1;
7298 r = r600_bytecode_add_alu(ctx->bc, &alu);
7299 if (r)
7300 return r;
7301 /* fall through */
7302
7303 case TGSI_TEXTURE_2D:
7304 case TGSI_TEXTURE_SHADOW2D:
7305 case TGSI_TEXTURE_RECT:
7306 case TGSI_TEXTURE_SHADOWRECT:
7307 case TGSI_TEXTURE_2D_ARRAY:
7308 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7310 alu.op = ALU_OP2_ADD_INT;
7311 alu.src[0].sel = src_gpr;
7312 alu.src[0].chan = 1;
7313 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7314 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7315 alu.dst.sel = src_gpr;
7316 alu.dst.chan = 1;
7317 alu.dst.write = 1;
7318 alu.last = 1;
7319 r = r600_bytecode_add_alu(ctx->bc, &alu);
7320 if (r)
7321 return r;
7322 /* fall through */
7323
7324 case TGSI_TEXTURE_1D:
7325 case TGSI_TEXTURE_SHADOW1D:
7326 case TGSI_TEXTURE_1D_ARRAY:
7327 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7329 alu.op = ALU_OP2_ADD_INT;
7330 alu.src[0].sel = src_gpr;
7331 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7332 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7333 alu.dst.sel = src_gpr;
7334 alu.dst.write = 1;
7335 alu.last = 1;
7336 r = r600_bytecode_add_alu(ctx->bc, &alu);
7337 if (r)
7338 return r;
7339 break;
7340 /* texture offsets do not apply to other texture targets */
7341 }
7342 } else {
7343 switch (inst->Texture.Texture) {
7344 case TGSI_TEXTURE_3D:
7345 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7346 /* fallthrough */
7347 case TGSI_TEXTURE_2D:
7348 case TGSI_TEXTURE_SHADOW2D:
7349 case TGSI_TEXTURE_RECT:
7350 case TGSI_TEXTURE_SHADOWRECT:
7351 case TGSI_TEXTURE_2D_ARRAY:
7352 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7353 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7354 /* fallthrough */
7355 case TGSI_TEXTURE_1D:
7356 case TGSI_TEXTURE_SHADOW1D:
7357 case TGSI_TEXTURE_1D_ARRAY:
7358 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7359 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7360 }
7361 }
7362 }
7363
7364 /* Obtain the sample index for reading a compressed MSAA color texture.
7365 * To read the FMASK, we use the ldfptr instruction, which tells us
7366 * where the samples are stored.
7367 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7368 * which is the identity mapping. Each nibble says which physical sample
7369 * should be fetched to get that sample.
7370 *
7371 * Assume src.z contains the sample index. It should be modified like this:
7372 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7373 * Then fetch the texel with src.
7374 */
7375 if (read_compressed_msaa) {
7376 unsigned sample_chan = 3;
7377 unsigned temp = r600_get_temp(ctx);
7378 assert(src_loaded);
7379
7380 /* temp.w = ldfptr() */
7381 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7382 tex.op = FETCH_OP_LD;
7383 tex.inst_mod = 1; /* to indicate this is ldfptr */
7384 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7385 tex.sampler_index_mode = sampler_index_mode;
7386 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7387 tex.resource_index_mode = sampler_index_mode;
7388 tex.src_gpr = src_gpr;
7389 tex.dst_gpr = temp;
7390 tex.dst_sel_x = 7; /* mask out these components */
7391 tex.dst_sel_y = 7;
7392 tex.dst_sel_z = 7;
7393 tex.dst_sel_w = 0; /* store X */
7394 tex.src_sel_x = 0;
7395 tex.src_sel_y = 1;
7396 tex.src_sel_z = 2;
7397 tex.src_sel_w = 3;
7398 tex.offset_x = offset_x;
7399 tex.offset_y = offset_y;
7400 tex.offset_z = offset_z;
7401 r = r600_bytecode_add_tex(ctx->bc, &tex);
7402 if (r)
7403 return r;
7404
7405 /* temp.x = sample_index*4 */
7406 if (ctx->bc->chip_class == CAYMAN) {
7407 for (i = 0 ; i < 4; i++) {
7408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7409 alu.op = ALU_OP2_MULLO_INT;
7410 alu.src[0].sel = src_gpr;
7411 alu.src[0].chan = sample_chan;
7412 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7413 alu.src[1].value = 4;
7414 alu.dst.sel = temp;
7415 alu.dst.chan = i;
7416 alu.dst.write = i == 0;
7417 if (i == 3)
7418 alu.last = 1;
7419 r = r600_bytecode_add_alu(ctx->bc, &alu);
7420 if (r)
7421 return r;
7422 }
7423 } else {
7424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7425 alu.op = ALU_OP2_MULLO_INT;
7426 alu.src[0].sel = src_gpr;
7427 alu.src[0].chan = sample_chan;
7428 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7429 alu.src[1].value = 4;
7430 alu.dst.sel = temp;
7431 alu.dst.chan = 0;
7432 alu.dst.write = 1;
7433 alu.last = 1;
7434 r = r600_bytecode_add_alu(ctx->bc, &alu);
7435 if (r)
7436 return r;
7437 }
7438
7439 /* sample_index = temp.w >> temp.x */
7440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7441 alu.op = ALU_OP2_LSHR_INT;
7442 alu.src[0].sel = temp;
7443 alu.src[0].chan = 3;
7444 alu.src[1].sel = temp;
7445 alu.src[1].chan = 0;
7446 alu.dst.sel = src_gpr;
7447 alu.dst.chan = sample_chan;
7448 alu.dst.write = 1;
7449 alu.last = 1;
7450 r = r600_bytecode_add_alu(ctx->bc, &alu);
7451 if (r)
7452 return r;
7453
7454 /* sample_index & 0xF */
7455 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7456 alu.op = ALU_OP2_AND_INT;
7457 alu.src[0].sel = src_gpr;
7458 alu.src[0].chan = sample_chan;
7459 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7460 alu.src[1].value = 0xF;
7461 alu.dst.sel = src_gpr;
7462 alu.dst.chan = sample_chan;
7463 alu.dst.write = 1;
7464 alu.last = 1;
7465 r = r600_bytecode_add_alu(ctx->bc, &alu);
7466 if (r)
7467 return r;
7468 #if 0
7469 /* visualize the FMASK */
7470 for (i = 0; i < 4; i++) {
7471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7472 alu.op = ALU_OP1_INT_TO_FLT;
7473 alu.src[0].sel = src_gpr;
7474 alu.src[0].chan = sample_chan;
7475 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7476 alu.dst.chan = i;
7477 alu.dst.write = 1;
7478 alu.last = 1;
7479 r = r600_bytecode_add_alu(ctx->bc, &alu);
7480 if (r)
7481 return r;
7482 }
7483 return 0;
7484 #endif
7485 }
7486
7487 /* does this shader want a num layers from TXQ for a cube array? */
7488 if (has_txq_cube_array_z) {
7489 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7490
7491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7492 alu.op = ALU_OP1_MOV;
7493
7494 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7495 if (ctx->bc->chip_class >= EVERGREEN) {
7496 /* channel 1 or 3 of each word */
7497 alu.src[0].sel += (id / 2);
7498 alu.src[0].chan = ((id % 2) * 2) + 1;
7499 } else {
7500 /* r600 we have them at channel 2 of the second dword */
7501 alu.src[0].sel += (id * 2) + 1;
7502 alu.src[0].chan = 2;
7503 }
7504 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7505 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7506 alu.last = 1;
7507 r = r600_bytecode_add_alu(ctx->bc, &alu);
7508 if (r)
7509 return r;
7510 /* disable writemask from texture instruction */
7511 inst->Dst[0].Register.WriteMask &= ~4;
7512 }
7513
7514 opcode = ctx->inst_info->op;
7515 if (opcode == FETCH_OP_GATHER4 &&
7516 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7517 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7518 opcode = FETCH_OP_GATHER4_O;
7519
7520 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7521 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7522 encoded in the instruction are ignored. */
7523 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7524 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7525 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7526 tex.sampler_index_mode = sampler_index_mode;
7527 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7528 tex.resource_index_mode = sampler_index_mode;
7529
7530 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7531 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7532 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7533 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7534 tex.src_sel_w = 4;
7535
7536 tex.dst_sel_x = 7;
7537 tex.dst_sel_y = 7;
7538 tex.dst_sel_z = 7;
7539 tex.dst_sel_w = 7;
7540
7541 r = r600_bytecode_add_tex(ctx->bc, &tex);
7542 if (r)
7543 return r;
7544 }
7545
7546 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7547 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7548 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7549 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7550 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7551 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7552 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7553 switch (opcode) {
7554 case FETCH_OP_SAMPLE:
7555 opcode = FETCH_OP_SAMPLE_C;
7556 break;
7557 case FETCH_OP_SAMPLE_L:
7558 opcode = FETCH_OP_SAMPLE_C_L;
7559 break;
7560 case FETCH_OP_SAMPLE_LB:
7561 opcode = FETCH_OP_SAMPLE_C_LB;
7562 break;
7563 case FETCH_OP_SAMPLE_G:
7564 opcode = FETCH_OP_SAMPLE_C_G;
7565 break;
7566 /* Texture gather variants */
7567 case FETCH_OP_GATHER4:
7568 opcode = FETCH_OP_GATHER4_C;
7569 break;
7570 case FETCH_OP_GATHER4_O:
7571 opcode = FETCH_OP_GATHER4_C_O;
7572 break;
7573 }
7574 }
7575
7576 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7577 tex.op = opcode;
7578
7579 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7580 tex.sampler_index_mode = sampler_index_mode;
7581 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7582 tex.resource_index_mode = sampler_index_mode;
7583 tex.src_gpr = src_gpr;
7584 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7585
7586 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7587 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7588 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7589 }
7590
7591 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7592 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7593 tex.inst_mod = texture_component_select;
7594
7595 if (ctx->bc->chip_class == CAYMAN) {
7596 /* GATHER4 result order is different from TGSI TG4 */
7597 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7598 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7599 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7600 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7601 } else {
7602 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7603 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7604 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7605 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7606 }
7607 }
7608 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7609 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7610 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7611 tex.dst_sel_z = 7;
7612 tex.dst_sel_w = 7;
7613 }
7614 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7615 tex.dst_sel_x = 3;
7616 tex.dst_sel_y = 7;
7617 tex.dst_sel_z = 7;
7618 tex.dst_sel_w = 7;
7619 }
7620 else {
7621 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7622 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7623 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7624 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7625 }
7626
7627
7628 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7629 tex.src_sel_x = 4;
7630 tex.src_sel_y = 4;
7631 tex.src_sel_z = 4;
7632 tex.src_sel_w = 4;
7633 } else if (src_loaded) {
7634 tex.src_sel_x = 0;
7635 tex.src_sel_y = 1;
7636 tex.src_sel_z = 2;
7637 tex.src_sel_w = 3;
7638 } else {
7639 tex.src_sel_x = ctx->src[0].swizzle[0];
7640 tex.src_sel_y = ctx->src[0].swizzle[1];
7641 tex.src_sel_z = ctx->src[0].swizzle[2];
7642 tex.src_sel_w = ctx->src[0].swizzle[3];
7643 tex.src_rel = ctx->src[0].rel;
7644 }
7645
7646 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7647 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7648 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7649 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7650 tex.src_sel_x = 1;
7651 tex.src_sel_y = 0;
7652 tex.src_sel_z = 3;
7653 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7654 }
7655
7656 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7657 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7658 tex.coord_type_x = 1;
7659 tex.coord_type_y = 1;
7660 }
7661 tex.coord_type_z = 1;
7662 tex.coord_type_w = 1;
7663
7664 tex.offset_x = offset_x;
7665 tex.offset_y = offset_y;
7666 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7667 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7668 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7669 tex.offset_z = 0;
7670 }
7671 else {
7672 tex.offset_z = offset_z;
7673 }
7674
7675 /* Put the depth for comparison in W.
7676 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7677 * Some instructions expect the depth in Z. */
7678 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7679 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7680 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7681 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7682 opcode != FETCH_OP_SAMPLE_C_L &&
7683 opcode != FETCH_OP_SAMPLE_C_LB) {
7684 tex.src_sel_w = tex.src_sel_z;
7685 }
7686
7687 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7688 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7689 if (opcode == FETCH_OP_SAMPLE_C_L ||
7690 opcode == FETCH_OP_SAMPLE_C_LB) {
7691 /* the array index is read from Y */
7692 tex.coord_type_y = 0;
7693 } else {
7694 /* the array index is read from Z */
7695 tex.coord_type_z = 0;
7696 tex.src_sel_z = tex.src_sel_y;
7697 }
7698 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7699 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7700 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7701 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7702 (ctx->bc->chip_class >= EVERGREEN)))
7703 /* the array index is read from Z */
7704 tex.coord_type_z = 0;
7705
7706 /* mask unused source components */
7707 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7708 switch (inst->Texture.Texture) {
7709 case TGSI_TEXTURE_2D:
7710 case TGSI_TEXTURE_RECT:
7711 tex.src_sel_z = 7;
7712 tex.src_sel_w = 7;
7713 break;
7714 case TGSI_TEXTURE_1D_ARRAY:
7715 tex.src_sel_y = 7;
7716 tex.src_sel_w = 7;
7717 break;
7718 case TGSI_TEXTURE_1D:
7719 tex.src_sel_y = 7;
7720 tex.src_sel_z = 7;
7721 tex.src_sel_w = 7;
7722 break;
7723 }
7724 }
7725
7726 r = r600_bytecode_add_tex(ctx->bc, &tex);
7727 if (r)
7728 return r;
7729
7730 /* add shadow ambient support - gallium doesn't do it yet */
7731 return 0;
7732 }
7733
7734 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7735 struct tgsi_full_src_register *src)
7736 {
7737 unsigned i;
7738
7739 if (src->Register.Indirect) {
7740 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7741 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7742 return ctx->shader->atomics[i].hw_idx;
7743 }
7744 } else {
7745 uint32_t index = src->Register.Index;
7746 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7747 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
7748 continue;
7749 if (index > ctx->shader->atomics[i].end)
7750 continue;
7751 if (index < ctx->shader->atomics[i].start)
7752 continue;
7753 uint32_t offset = (index - ctx->shader->atomics[i].start);
7754 return ctx->shader->atomics[i].hw_idx + offset;
7755 }
7756 }
7757 assert(0);
7758 return -1;
7759 }
7760
7761
7762 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7763 {
7764 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7765 int r;
7766 struct r600_bytecode_gds gds;
7767 int uav_id = 0;
7768 int uav_index_mode = 0;
7769
7770 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7771
7772 if (inst->Src[0].Register.Indirect)
7773 uav_index_mode = 2;
7774
7775 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7776 gds.op = FETCH_OP_GDS_READ_RET;
7777 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7778 gds.uav_id = uav_id;
7779 gds.uav_index_mode = uav_index_mode;
7780 gds.src_gpr = ctx->temp_reg;
7781 gds.src_sel_x = 4;
7782 gds.src_sel_y = 4;
7783 gds.src_sel_z = 4;
7784 gds.dst_sel_x = 0;
7785 gds.dst_sel_y = 7;
7786 gds.dst_sel_z = 7;
7787 gds.dst_sel_w = 7;
7788 gds.src_gpr2 = ctx->temp_reg;
7789 gds.alloc_consume = 1;
7790 r = r600_bytecode_add_gds(ctx->bc, &gds);
7791 if (r)
7792 return r;
7793
7794 ctx->bc->cf_last->vpm = 1;
7795 return 0;
7796 }
7797
7798 /* this fixes up 1D arrays properly */
7799 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
7800 {
7801 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7802 int r, i;
7803 struct r600_bytecode_alu alu;
7804 int temp_reg = r600_get_temp(ctx);
7805
7806 for (i = 0; i < 4; i++) {
7807 bool def_val = true, write_zero = false;
7808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7809 alu.op = ALU_OP1_MOV;
7810 alu.dst.sel = temp_reg;
7811 alu.dst.chan = i;
7812
7813 switch (inst->Memory.Texture) {
7814 case TGSI_TEXTURE_BUFFER:
7815 case TGSI_TEXTURE_1D:
7816 if (i == 1 || i == 2 || i == 3) {
7817 write_zero = true;
7818 }
7819 break;
7820 case TGSI_TEXTURE_1D_ARRAY:
7821 if (i == 1 || i == 3)
7822 write_zero = true;
7823 else if (i == 2) {
7824 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
7825 def_val = false;
7826 }
7827 break;
7828 case TGSI_TEXTURE_2D:
7829 if (i == 2 || i == 3)
7830 write_zero = true;
7831 break;
7832 default:
7833 if (i == 3)
7834 write_zero = true;
7835 break;
7836 }
7837
7838 if (write_zero) {
7839 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7840 alu.src[0].value = 0;
7841 } else if (def_val) {
7842 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
7843 }
7844
7845 if (i == 3)
7846 alu.last = 1;
7847 alu.dst.write = 1;
7848 r = r600_bytecode_add_alu(ctx->bc, &alu);
7849 if (r)
7850 return r;
7851 }
7852 *idx_gpr = temp_reg;
7853 return 0;
7854 }
7855
7856 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
7857 {
7858 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7859 /* have to work out the offset into the RAT immediate return buffer */
7860 struct r600_bytecode_vtx vtx;
7861 struct r600_bytecode_cf *cf;
7862 int r;
7863 int idx_gpr;
7864 unsigned format, num_format, format_comp, endian;
7865 const struct util_format_description *desc;
7866 unsigned rat_index_mode;
7867 unsigned immed_base;
7868
7869 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7870
7871 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
7872 r = load_index_src(ctx, 1, &idx_gpr);
7873 if (r)
7874 return r;
7875
7876 if (rat_index_mode)
7877 egcm_load_index_reg(ctx->bc, 1, false);
7878
7879 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
7880 cf = ctx->bc->cf_last;
7881
7882 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
7883 cf->rat.inst = V_RAT_INST_NOP_RTN;
7884 cf->rat.index_mode = rat_index_mode;
7885 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
7886 cf->output.gpr = ctx->thread_id_gpr;
7887 cf->output.index_gpr = idx_gpr;
7888 cf->output.comp_mask = 0xf;
7889 cf->output.burst_count = 1;
7890 cf->vpm = 1;
7891 cf->barrier = 1;
7892 cf->mark = 1;
7893 cf->output.elem_size = 0;
7894
7895 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
7896 cf = ctx->bc->cf_last;
7897 cf->barrier = 1;
7898
7899 desc = util_format_description(inst->Memory.Format);
7900 r600_vertex_data_type(inst->Memory.Format,
7901 &format, &num_format, &format_comp, &endian);
7902 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
7903 vtx.op = FETCH_OP_VFETCH;
7904 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
7905 vtx.buffer_index_mode = rat_index_mode;
7906 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7907 vtx.src_gpr = ctx->thread_id_gpr;
7908 vtx.src_sel_x = 1;
7909 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7910 vtx.dst_sel_x = desc->swizzle[0];
7911 vtx.dst_sel_y = desc->swizzle[1];
7912 vtx.dst_sel_z = desc->swizzle[2];
7913 vtx.dst_sel_w = desc->swizzle[3];
7914 vtx.srf_mode_all = 1;
7915 vtx.data_format = format;
7916 vtx.num_format_all = num_format;
7917 vtx.format_comp_all = format_comp;
7918 vtx.endian = endian;
7919 vtx.offset = 0;
7920 vtx.mega_fetch_count = 3;
7921 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
7922 if (r)
7923 return r;
7924 cf = ctx->bc->cf_last;
7925 cf->barrier = 1;
7926 return 0;
7927 }
7928
7929 static int tgsi_load(struct r600_shader_ctx *ctx)
7930 {
7931 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7932 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
7933 return tgsi_load_rat(ctx);
7934 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7935 return tgsi_load_gds(ctx);
7936 return 0;
7937 }
7938
7939 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
7940 {
7941 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7942 struct r600_bytecode_cf *cf;
7943 bool src_requires_loading = false;
7944 int val_gpr, idx_gpr;
7945 int r, i;
7946 unsigned rat_index_mode;
7947
7948 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7949
7950 r = load_index_src(ctx, 0, &idx_gpr);
7951 if (r)
7952 return r;
7953
7954 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
7955 src_requires_loading = true;
7956
7957 if (src_requires_loading) {
7958 struct r600_bytecode_alu alu;
7959 for (i = 0; i < 4; i++) {
7960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7961 alu.op = ALU_OP1_MOV;
7962 alu.dst.sel = ctx->temp_reg;
7963 alu.dst.chan = i;
7964
7965 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7966 if (i == 3)
7967 alu.last = 1;
7968 alu.dst.write = 1;
7969 r = r600_bytecode_add_alu(ctx->bc, &alu);
7970 if (r)
7971 return r;
7972 }
7973 val_gpr = ctx->temp_reg;
7974 } else
7975 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
7976 if (rat_index_mode)
7977 egcm_load_index_reg(ctx->bc, 1, false);
7978
7979 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
7980 cf = ctx->bc->cf_last;
7981
7982 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
7983 cf->rat.inst = V_RAT_INST_STORE_TYPED;
7984 cf->rat.index_mode = rat_index_mode;
7985 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
7986 cf->output.gpr = val_gpr;
7987 cf->output.index_gpr = idx_gpr;
7988 cf->output.comp_mask = 0xf;
7989 cf->output.burst_count = 1;
7990 cf->vpm = 1;
7991 cf->barrier = 1;
7992 cf->output.elem_size = 0;
7993 return 0;
7994 }
7995
7996 static int tgsi_store(struct r600_shader_ctx *ctx)
7997 {
7998 return tgsi_store_rat(ctx);
7999 }
8000
8001 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8002 {
8003 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8004 /* have to work out the offset into the RAT immediate return buffer */
8005 struct r600_bytecode_alu alu;
8006 struct r600_bytecode_vtx vtx;
8007 struct r600_bytecode_cf *cf;
8008 int r;
8009 int idx_gpr;
8010 unsigned format, num_format, format_comp, endian;
8011 const struct util_format_description *desc;
8012 unsigned rat_index_mode;
8013 unsigned immed_base;
8014
8015 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8016
8017 assert (inst->Src[0].Register.File == TGSI_FILE_IMAGE);
8018 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8019
8020 r = load_index_src(ctx, 1, &idx_gpr);
8021 if (r)
8022 return r;
8023
8024 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8026 alu.op = ALU_OP1_MOV;
8027 alu.dst.sel = ctx->thread_id_gpr;
8028 alu.dst.chan = 0;
8029 alu.dst.write = 1;
8030 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8031 alu.last = 1;
8032 r = r600_bytecode_add_alu(ctx->bc, &alu);
8033 if (r)
8034 return r;
8035
8036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8037 alu.op = ALU_OP1_MOV;
8038 alu.dst.sel = ctx->thread_id_gpr;
8039 alu.dst.chan = 3;
8040 alu.dst.write = 1;
8041 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8042 alu.last = 1;
8043 r = r600_bytecode_add_alu(ctx->bc, &alu);
8044 if (r)
8045 return r;
8046 } else {
8047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8048 alu.op = ALU_OP1_MOV;
8049 alu.dst.sel = ctx->thread_id_gpr;
8050 alu.dst.chan = 0;
8051 alu.dst.write = 1;
8052 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8053 alu.last = 1;
8054 r = r600_bytecode_add_alu(ctx->bc, &alu);
8055 if (r)
8056 return r;
8057 }
8058
8059 if (rat_index_mode)
8060 egcm_load_index_reg(ctx->bc, 1, false);
8061 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8062 cf = ctx->bc->cf_last;
8063
8064 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8065 cf->rat.inst = ctx->inst_info->op;
8066 cf->rat.index_mode = rat_index_mode;
8067 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8068 cf->output.gpr = ctx->thread_id_gpr;
8069 cf->output.index_gpr = idx_gpr;
8070 cf->output.comp_mask = 0xf;
8071 cf->output.burst_count = 1;
8072 cf->vpm = 1;
8073 cf->barrier = 1;
8074 cf->mark = 1;
8075 cf->output.elem_size = 0;
8076 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8077 cf = ctx->bc->cf_last;
8078 cf->barrier = 1;
8079 cf->cf_addr = 1;
8080
8081 desc = util_format_description(inst->Memory.Format);
8082 r600_vertex_data_type(inst->Memory.Format,
8083 &format, &num_format, &format_comp, &endian);
8084 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8085 vtx.op = FETCH_OP_VFETCH;
8086 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8087 vtx.buffer_index_mode = rat_index_mode;
8088 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8089 vtx.src_gpr = ctx->thread_id_gpr;
8090 vtx.src_sel_x = 1;
8091 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8092 vtx.dst_sel_x = desc->swizzle[0];
8093 vtx.dst_sel_y = 7;
8094 vtx.dst_sel_z = 7;
8095 vtx.dst_sel_w = 7;
8096 vtx.use_const_fields = 0;
8097 vtx.srf_mode_all = 1;
8098 vtx.data_format = format;
8099 vtx.num_format_all = num_format;
8100 vtx.format_comp_all = format_comp;
8101 vtx.endian = endian;
8102 vtx.offset = 0;
8103 vtx.mega_fetch_count = 0xf;
8104 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8105 if (r)
8106 return r;
8107 cf = ctx->bc->cf_last;
8108 cf->vpm = 1;
8109 cf->barrier = 1;
8110 return 0;
8111 }
8112
8113 static int get_gds_op(int opcode)
8114 {
8115 switch (opcode) {
8116 case TGSI_OPCODE_ATOMUADD:
8117 return FETCH_OP_GDS_ADD_RET;
8118 case TGSI_OPCODE_ATOMAND:
8119 return FETCH_OP_GDS_AND_RET;
8120 case TGSI_OPCODE_ATOMOR:
8121 return FETCH_OP_GDS_OR_RET;
8122 case TGSI_OPCODE_ATOMXOR:
8123 return FETCH_OP_GDS_XOR_RET;
8124 case TGSI_OPCODE_ATOMUMIN:
8125 return FETCH_OP_GDS_MIN_UINT_RET;
8126 case TGSI_OPCODE_ATOMUMAX:
8127 return FETCH_OP_GDS_MAX_UINT_RET;
8128 case TGSI_OPCODE_ATOMXCHG:
8129 return FETCH_OP_GDS_XCHG_RET;
8130 case TGSI_OPCODE_ATOMCAS:
8131 return FETCH_OP_GDS_CMP_XCHG_RET;
8132 default:
8133 return -1;
8134 }
8135 }
8136
8137 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8138 {
8139 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8140 struct r600_bytecode_gds gds;
8141 struct r600_bytecode_alu alu;
8142 int gds_op = get_gds_op(inst->Instruction.Opcode);
8143 int r;
8144 int uav_id = 0;
8145 int uav_index_mode = 0;
8146
8147 if (gds_op == -1) {
8148 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8149 return -1;
8150 }
8151
8152 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
8153
8154 if (inst->Src[0].Register.Indirect)
8155 uav_index_mode = 2;
8156
8157 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8158 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8159 int abs_value = abs(value);
8160 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8161 gds_op = FETCH_OP_GDS_SUB_RET;
8162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8163 alu.op = ALU_OP1_MOV;
8164 alu.dst.sel = ctx->temp_reg;
8165 alu.dst.chan = 0;
8166 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8167 alu.src[0].value = abs_value;
8168 alu.last = 1;
8169 alu.dst.write = 1;
8170 r = r600_bytecode_add_alu(ctx->bc, &alu);
8171 if (r)
8172 return r;
8173 } else {
8174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8175 alu.op = ALU_OP1_MOV;
8176 alu.dst.sel = ctx->temp_reg;
8177 alu.dst.chan = 0;
8178 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8179 alu.last = 1;
8180 alu.dst.write = 1;
8181 r = r600_bytecode_add_alu(ctx->bc, &alu);
8182 if (r)
8183 return r;
8184 }
8185
8186 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8187 gds.op = gds_op;
8188 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8189 gds.uav_id = uav_id;
8190 gds.uav_index_mode = uav_index_mode;
8191 gds.src_gpr = ctx->temp_reg;
8192 gds.src_gpr2 = ctx->temp_reg;
8193 gds.src_sel_x = 4;
8194 gds.src_sel_y = 0;
8195 gds.src_sel_z = 4;
8196 gds.dst_sel_x = 0;
8197 gds.dst_sel_y = 7;
8198 gds.dst_sel_z = 7;
8199 gds.dst_sel_w = 7;
8200 gds.alloc_consume = 1;
8201 r = r600_bytecode_add_gds(ctx->bc, &gds);
8202 if (r)
8203 return r;
8204 ctx->bc->cf_last->vpm = 1;
8205 return 0;
8206 }
8207
8208 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8209 {
8210 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8211 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8212 return tgsi_atomic_op_rat(ctx);
8213 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8214 return tgsi_atomic_op_gds(ctx);
8215 return 0;
8216 }
8217
8218 static int tgsi_resq(struct r600_shader_ctx *ctx)
8219 {
8220 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8221 unsigned sampler_index_mode;
8222 struct r600_bytecode_tex tex;
8223 int r;
8224 boolean has_txq_cube_array_z = false;
8225
8226 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
8227 ctx->shader->uses_tex_buffers = true;
8228 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset);
8229 }
8230
8231 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
8232 inst->Dst[0].Register.WriteMask & 4) {
8233 ctx->shader->has_txq_cube_array_z_comp = true;
8234 has_txq_cube_array_z = true;
8235 }
8236
8237 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8238 if (sampler_index_mode)
8239 egcm_load_index_reg(ctx->bc, 1, false);
8240
8241
8242 /* does this shader want a num layers from TXQ for a cube array? */
8243 if (has_txq_cube_array_z) {
8244 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
8245 struct r600_bytecode_alu alu;
8246
8247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8248 alu.op = ALU_OP1_MOV;
8249
8250 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8251 /* channel 1 or 3 of each word */
8252 alu.src[0].sel += (id / 2);
8253 alu.src[0].chan = ((id % 2) * 2) + 1;
8254 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8255 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8256 alu.last = 1;
8257 r = r600_bytecode_add_alu(ctx->bc, &alu);
8258 if (r)
8259 return r;
8260 /* disable writemask from texture instruction */
8261 inst->Dst[0].Register.WriteMask &= ~4;
8262 }
8263 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8264 tex.op = ctx->inst_info->op;
8265 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
8266 tex.sampler_index_mode = sampler_index_mode;
8267 tex.resource_id = tex.sampler_id;
8268 tex.resource_index_mode = sampler_index_mode;
8269 tex.src_sel_x = 4;
8270 tex.src_sel_y = 4;
8271 tex.src_sel_z = 4;
8272 tex.src_sel_w = 4;
8273 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8274 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8275 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8276 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8277 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8278 r = r600_bytecode_add_tex(ctx->bc, &tex);
8279 if (r)
8280 return r;
8281
8282 return 0;
8283 }
8284
8285 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8286 {
8287 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8288 struct r600_bytecode_alu alu;
8289 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8290 unsigned i, temp_regs[2];
8291 int r;
8292
8293 /* optimize if it's just an equal balance */
8294 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8295 for (i = 0; i < lasti + 1; i++) {
8296 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8297 continue;
8298
8299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8300 alu.op = ALU_OP2_ADD;
8301 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8302 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8303 alu.omod = 3;
8304 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8305 alu.dst.chan = i;
8306 if (i == lasti) {
8307 alu.last = 1;
8308 }
8309 r = r600_bytecode_add_alu(ctx->bc, &alu);
8310 if (r)
8311 return r;
8312 }
8313 return 0;
8314 }
8315
8316 /* 1 - src0 */
8317 for (i = 0; i < lasti + 1; i++) {
8318 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8319 continue;
8320
8321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8322 alu.op = ALU_OP2_ADD;
8323 alu.src[0].sel = V_SQ_ALU_SRC_1;
8324 alu.src[0].chan = 0;
8325 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8326 r600_bytecode_src_toggle_neg(&alu.src[1]);
8327 alu.dst.sel = ctx->temp_reg;
8328 alu.dst.chan = i;
8329 if (i == lasti) {
8330 alu.last = 1;
8331 }
8332 alu.dst.write = 1;
8333 r = r600_bytecode_add_alu(ctx->bc, &alu);
8334 if (r)
8335 return r;
8336 }
8337
8338 /* (1 - src0) * src2 */
8339 for (i = 0; i < lasti + 1; i++) {
8340 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8341 continue;
8342
8343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8344 alu.op = ALU_OP2_MUL;
8345 alu.src[0].sel = ctx->temp_reg;
8346 alu.src[0].chan = i;
8347 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8348 alu.dst.sel = ctx->temp_reg;
8349 alu.dst.chan = i;
8350 if (i == lasti) {
8351 alu.last = 1;
8352 }
8353 alu.dst.write = 1;
8354 r = r600_bytecode_add_alu(ctx->bc, &alu);
8355 if (r)
8356 return r;
8357 }
8358
8359 /* src0 * src1 + (1 - src0) * src2 */
8360 if (ctx->src[0].abs)
8361 temp_regs[0] = r600_get_temp(ctx);
8362 else
8363 temp_regs[0] = 0;
8364 if (ctx->src[1].abs)
8365 temp_regs[1] = r600_get_temp(ctx);
8366 else
8367 temp_regs[1] = 0;
8368
8369 for (i = 0; i < lasti + 1; i++) {
8370 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8371 continue;
8372
8373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8374 alu.op = ALU_OP3_MULADD;
8375 alu.is_op3 = 1;
8376 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8377 if (r)
8378 return r;
8379 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
8380 if (r)
8381 return r;
8382 alu.src[2].sel = ctx->temp_reg;
8383 alu.src[2].chan = i;
8384
8385 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8386 alu.dst.chan = i;
8387 if (i == lasti) {
8388 alu.last = 1;
8389 }
8390 r = r600_bytecode_add_alu(ctx->bc, &alu);
8391 if (r)
8392 return r;
8393 }
8394 return 0;
8395 }
8396
8397 static int tgsi_cmp(struct r600_shader_ctx *ctx)
8398 {
8399 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8400 struct r600_bytecode_alu alu;
8401 int i, r, j;
8402 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8403 int temp_regs[3];
8404 unsigned op;
8405
8406 if (ctx->src[0].abs && ctx->src[0].neg) {
8407 op = ALU_OP3_CNDE;
8408 ctx->src[0].abs = 0;
8409 ctx->src[0].neg = 0;
8410 } else {
8411 op = ALU_OP3_CNDGE;
8412 }
8413
8414 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
8415 temp_regs[j] = 0;
8416 if (ctx->src[j].abs)
8417 temp_regs[j] = r600_get_temp(ctx);
8418 }
8419
8420 for (i = 0; i < lasti + 1; i++) {
8421 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8422 continue;
8423
8424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8425 alu.op = op;
8426 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8427 if (r)
8428 return r;
8429 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
8430 if (r)
8431 return r;
8432 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
8433 if (r)
8434 return r;
8435 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8436 alu.dst.chan = i;
8437 alu.dst.write = 1;
8438 alu.is_op3 = 1;
8439 if (i == lasti)
8440 alu.last = 1;
8441 r = r600_bytecode_add_alu(ctx->bc, &alu);
8442 if (r)
8443 return r;
8444 }
8445 return 0;
8446 }
8447
8448 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
8449 {
8450 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8451 struct r600_bytecode_alu alu;
8452 int i, r;
8453 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8454
8455 for (i = 0; i < lasti + 1; i++) {
8456 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8457 continue;
8458
8459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8460 alu.op = ALU_OP3_CNDE_INT;
8461 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8462 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8463 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
8464 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8465 alu.dst.chan = i;
8466 alu.dst.write = 1;
8467 alu.is_op3 = 1;
8468 if (i == lasti)
8469 alu.last = 1;
8470 r = r600_bytecode_add_alu(ctx->bc, &alu);
8471 if (r)
8472 return r;
8473 }
8474 return 0;
8475 }
8476
8477 static int tgsi_exp(struct r600_shader_ctx *ctx)
8478 {
8479 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8480 struct r600_bytecode_alu alu;
8481 int r;
8482 unsigned i;
8483
8484 /* result.x = 2^floor(src); */
8485 if (inst->Dst[0].Register.WriteMask & 1) {
8486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8487
8488 alu.op = ALU_OP1_FLOOR;
8489 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8490
8491 alu.dst.sel = ctx->temp_reg;
8492 alu.dst.chan = 0;
8493 alu.dst.write = 1;
8494 alu.last = 1;
8495 r = r600_bytecode_add_alu(ctx->bc, &alu);
8496 if (r)
8497 return r;
8498
8499 if (ctx->bc->chip_class == CAYMAN) {
8500 for (i = 0; i < 3; i++) {
8501 alu.op = ALU_OP1_EXP_IEEE;
8502 alu.src[0].sel = ctx->temp_reg;
8503 alu.src[0].chan = 0;
8504
8505 alu.dst.sel = ctx->temp_reg;
8506 alu.dst.chan = i;
8507 alu.dst.write = i == 0;
8508 alu.last = i == 2;
8509 r = r600_bytecode_add_alu(ctx->bc, &alu);
8510 if (r)
8511 return r;
8512 }
8513 } else {
8514 alu.op = ALU_OP1_EXP_IEEE;
8515 alu.src[0].sel = ctx->temp_reg;
8516 alu.src[0].chan = 0;
8517
8518 alu.dst.sel = ctx->temp_reg;
8519 alu.dst.chan = 0;
8520 alu.dst.write = 1;
8521 alu.last = 1;
8522 r = r600_bytecode_add_alu(ctx->bc, &alu);
8523 if (r)
8524 return r;
8525 }
8526 }
8527
8528 /* result.y = tmp - floor(tmp); */
8529 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8531
8532 alu.op = ALU_OP1_FRACT;
8533 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8534
8535 alu.dst.sel = ctx->temp_reg;
8536 #if 0
8537 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8538 if (r)
8539 return r;
8540 #endif
8541 alu.dst.write = 1;
8542 alu.dst.chan = 1;
8543
8544 alu.last = 1;
8545
8546 r = r600_bytecode_add_alu(ctx->bc, &alu);
8547 if (r)
8548 return r;
8549 }
8550
8551 /* result.z = RoughApprox2ToX(tmp);*/
8552 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8553 if (ctx->bc->chip_class == CAYMAN) {
8554 for (i = 0; i < 3; i++) {
8555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8556 alu.op = ALU_OP1_EXP_IEEE;
8557 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8558
8559 alu.dst.sel = ctx->temp_reg;
8560 alu.dst.chan = i;
8561 if (i == 2) {
8562 alu.dst.write = 1;
8563 alu.last = 1;
8564 }
8565
8566 r = r600_bytecode_add_alu(ctx->bc, &alu);
8567 if (r)
8568 return r;
8569 }
8570 } else {
8571 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8572 alu.op = ALU_OP1_EXP_IEEE;
8573 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8574
8575 alu.dst.sel = ctx->temp_reg;
8576 alu.dst.write = 1;
8577 alu.dst.chan = 2;
8578
8579 alu.last = 1;
8580
8581 r = r600_bytecode_add_alu(ctx->bc, &alu);
8582 if (r)
8583 return r;
8584 }
8585 }
8586
8587 /* result.w = 1.0;*/
8588 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8590
8591 alu.op = ALU_OP1_MOV;
8592 alu.src[0].sel = V_SQ_ALU_SRC_1;
8593 alu.src[0].chan = 0;
8594
8595 alu.dst.sel = ctx->temp_reg;
8596 alu.dst.chan = 3;
8597 alu.dst.write = 1;
8598 alu.last = 1;
8599 r = r600_bytecode_add_alu(ctx->bc, &alu);
8600 if (r)
8601 return r;
8602 }
8603 return tgsi_helper_copy(ctx, inst);
8604 }
8605
8606 static int tgsi_log(struct r600_shader_ctx *ctx)
8607 {
8608 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8609 struct r600_bytecode_alu alu;
8610 int r;
8611 unsigned i;
8612
8613 /* result.x = floor(log2(|src|)); */
8614 if (inst->Dst[0].Register.WriteMask & 1) {
8615 if (ctx->bc->chip_class == CAYMAN) {
8616 for (i = 0; i < 3; i++) {
8617 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8618
8619 alu.op = ALU_OP1_LOG_IEEE;
8620 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8621 r600_bytecode_src_set_abs(&alu.src[0]);
8622
8623 alu.dst.sel = ctx->temp_reg;
8624 alu.dst.chan = i;
8625 if (i == 0)
8626 alu.dst.write = 1;
8627 if (i == 2)
8628 alu.last = 1;
8629 r = r600_bytecode_add_alu(ctx->bc, &alu);
8630 if (r)
8631 return r;
8632 }
8633
8634 } else {
8635 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8636
8637 alu.op = ALU_OP1_LOG_IEEE;
8638 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8639 r600_bytecode_src_set_abs(&alu.src[0]);
8640
8641 alu.dst.sel = ctx->temp_reg;
8642 alu.dst.chan = 0;
8643 alu.dst.write = 1;
8644 alu.last = 1;
8645 r = r600_bytecode_add_alu(ctx->bc, &alu);
8646 if (r)
8647 return r;
8648 }
8649
8650 alu.op = ALU_OP1_FLOOR;
8651 alu.src[0].sel = ctx->temp_reg;
8652 alu.src[0].chan = 0;
8653
8654 alu.dst.sel = ctx->temp_reg;
8655 alu.dst.chan = 0;
8656 alu.dst.write = 1;
8657 alu.last = 1;
8658
8659 r = r600_bytecode_add_alu(ctx->bc, &alu);
8660 if (r)
8661 return r;
8662 }
8663
8664 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8665 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8666
8667 if (ctx->bc->chip_class == CAYMAN) {
8668 for (i = 0; i < 3; i++) {
8669 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8670
8671 alu.op = ALU_OP1_LOG_IEEE;
8672 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8673 r600_bytecode_src_set_abs(&alu.src[0]);
8674
8675 alu.dst.sel = ctx->temp_reg;
8676 alu.dst.chan = i;
8677 if (i == 1)
8678 alu.dst.write = 1;
8679 if (i == 2)
8680 alu.last = 1;
8681
8682 r = r600_bytecode_add_alu(ctx->bc, &alu);
8683 if (r)
8684 return r;
8685 }
8686 } else {
8687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8688
8689 alu.op = ALU_OP1_LOG_IEEE;
8690 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8691 r600_bytecode_src_set_abs(&alu.src[0]);
8692
8693 alu.dst.sel = ctx->temp_reg;
8694 alu.dst.chan = 1;
8695 alu.dst.write = 1;
8696 alu.last = 1;
8697
8698 r = r600_bytecode_add_alu(ctx->bc, &alu);
8699 if (r)
8700 return r;
8701 }
8702
8703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8704
8705 alu.op = ALU_OP1_FLOOR;
8706 alu.src[0].sel = ctx->temp_reg;
8707 alu.src[0].chan = 1;
8708
8709 alu.dst.sel = ctx->temp_reg;
8710 alu.dst.chan = 1;
8711 alu.dst.write = 1;
8712 alu.last = 1;
8713
8714 r = r600_bytecode_add_alu(ctx->bc, &alu);
8715 if (r)
8716 return r;
8717
8718 if (ctx->bc->chip_class == CAYMAN) {
8719 for (i = 0; i < 3; i++) {
8720 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8721 alu.op = ALU_OP1_EXP_IEEE;
8722 alu.src[0].sel = ctx->temp_reg;
8723 alu.src[0].chan = 1;
8724
8725 alu.dst.sel = ctx->temp_reg;
8726 alu.dst.chan = i;
8727 if (i == 1)
8728 alu.dst.write = 1;
8729 if (i == 2)
8730 alu.last = 1;
8731
8732 r = r600_bytecode_add_alu(ctx->bc, &alu);
8733 if (r)
8734 return r;
8735 }
8736 } else {
8737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8738 alu.op = ALU_OP1_EXP_IEEE;
8739 alu.src[0].sel = ctx->temp_reg;
8740 alu.src[0].chan = 1;
8741
8742 alu.dst.sel = ctx->temp_reg;
8743 alu.dst.chan = 1;
8744 alu.dst.write = 1;
8745 alu.last = 1;
8746
8747 r = r600_bytecode_add_alu(ctx->bc, &alu);
8748 if (r)
8749 return r;
8750 }
8751
8752 if (ctx->bc->chip_class == CAYMAN) {
8753 for (i = 0; i < 3; i++) {
8754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8755 alu.op = ALU_OP1_RECIP_IEEE;
8756 alu.src[0].sel = ctx->temp_reg;
8757 alu.src[0].chan = 1;
8758
8759 alu.dst.sel = ctx->temp_reg;
8760 alu.dst.chan = i;
8761 if (i == 1)
8762 alu.dst.write = 1;
8763 if (i == 2)
8764 alu.last = 1;
8765
8766 r = r600_bytecode_add_alu(ctx->bc, &alu);
8767 if (r)
8768 return r;
8769 }
8770 } else {
8771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8772 alu.op = ALU_OP1_RECIP_IEEE;
8773 alu.src[0].sel = ctx->temp_reg;
8774 alu.src[0].chan = 1;
8775
8776 alu.dst.sel = ctx->temp_reg;
8777 alu.dst.chan = 1;
8778 alu.dst.write = 1;
8779 alu.last = 1;
8780
8781 r = r600_bytecode_add_alu(ctx->bc, &alu);
8782 if (r)
8783 return r;
8784 }
8785
8786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8787
8788 alu.op = ALU_OP2_MUL;
8789
8790 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8791 r600_bytecode_src_set_abs(&alu.src[0]);
8792
8793 alu.src[1].sel = ctx->temp_reg;
8794 alu.src[1].chan = 1;
8795
8796 alu.dst.sel = ctx->temp_reg;
8797 alu.dst.chan = 1;
8798 alu.dst.write = 1;
8799 alu.last = 1;
8800
8801 r = r600_bytecode_add_alu(ctx->bc, &alu);
8802 if (r)
8803 return r;
8804 }
8805
8806 /* result.z = log2(|src|);*/
8807 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8808 if (ctx->bc->chip_class == CAYMAN) {
8809 for (i = 0; i < 3; i++) {
8810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8811
8812 alu.op = ALU_OP1_LOG_IEEE;
8813 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8814 r600_bytecode_src_set_abs(&alu.src[0]);
8815
8816 alu.dst.sel = ctx->temp_reg;
8817 if (i == 2)
8818 alu.dst.write = 1;
8819 alu.dst.chan = i;
8820 if (i == 2)
8821 alu.last = 1;
8822
8823 r = r600_bytecode_add_alu(ctx->bc, &alu);
8824 if (r)
8825 return r;
8826 }
8827 } else {
8828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8829
8830 alu.op = ALU_OP1_LOG_IEEE;
8831 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8832 r600_bytecode_src_set_abs(&alu.src[0]);
8833
8834 alu.dst.sel = ctx->temp_reg;
8835 alu.dst.write = 1;
8836 alu.dst.chan = 2;
8837 alu.last = 1;
8838
8839 r = r600_bytecode_add_alu(ctx->bc, &alu);
8840 if (r)
8841 return r;
8842 }
8843 }
8844
8845 /* result.w = 1.0; */
8846 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8848
8849 alu.op = ALU_OP1_MOV;
8850 alu.src[0].sel = V_SQ_ALU_SRC_1;
8851 alu.src[0].chan = 0;
8852
8853 alu.dst.sel = ctx->temp_reg;
8854 alu.dst.chan = 3;
8855 alu.dst.write = 1;
8856 alu.last = 1;
8857
8858 r = r600_bytecode_add_alu(ctx->bc, &alu);
8859 if (r)
8860 return r;
8861 }
8862
8863 return tgsi_helper_copy(ctx, inst);
8864 }
8865
8866 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8867 {
8868 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8869 struct r600_bytecode_alu alu;
8870 int r;
8871 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8872 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8873
8874 assert(inst->Dst[0].Register.Index < 3);
8875 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8876
8877 switch (inst->Instruction.Opcode) {
8878 case TGSI_OPCODE_ARL:
8879 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8880 break;
8881 case TGSI_OPCODE_ARR:
8882 alu.op = ALU_OP1_FLT_TO_INT;
8883 break;
8884 case TGSI_OPCODE_UARL:
8885 alu.op = ALU_OP1_MOV;
8886 break;
8887 default:
8888 assert(0);
8889 return -1;
8890 }
8891
8892 for (i = 0; i <= lasti; ++i) {
8893 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8894 continue;
8895 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8896 alu.last = i == lasti;
8897 alu.dst.sel = reg;
8898 alu.dst.chan = i;
8899 alu.dst.write = 1;
8900 r = r600_bytecode_add_alu(ctx->bc, &alu);
8901 if (r)
8902 return r;
8903 }
8904
8905 if (inst->Dst[0].Register.Index > 0)
8906 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8907 else
8908 ctx->bc->ar_loaded = 0;
8909
8910 return 0;
8911 }
8912 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8913 {
8914 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8915 struct r600_bytecode_alu alu;
8916 int r;
8917 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8918
8919 switch (inst->Instruction.Opcode) {
8920 case TGSI_OPCODE_ARL:
8921 memset(&alu, 0, sizeof(alu));
8922 alu.op = ALU_OP1_FLOOR;
8923 alu.dst.sel = ctx->bc->ar_reg;
8924 alu.dst.write = 1;
8925 for (i = 0; i <= lasti; ++i) {
8926 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8927 alu.dst.chan = i;
8928 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8929 alu.last = i == lasti;
8930 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8931 return r;
8932 }
8933 }
8934
8935 memset(&alu, 0, sizeof(alu));
8936 alu.op = ALU_OP1_FLT_TO_INT;
8937 alu.src[0].sel = ctx->bc->ar_reg;
8938 alu.dst.sel = ctx->bc->ar_reg;
8939 alu.dst.write = 1;
8940 /* FLT_TO_INT is trans-only on r600/r700 */
8941 alu.last = TRUE;
8942 for (i = 0; i <= lasti; ++i) {
8943 alu.dst.chan = i;
8944 alu.src[0].chan = i;
8945 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8946 return r;
8947 }
8948 break;
8949 case TGSI_OPCODE_ARR:
8950 memset(&alu, 0, sizeof(alu));
8951 alu.op = ALU_OP1_FLT_TO_INT;
8952 alu.dst.sel = ctx->bc->ar_reg;
8953 alu.dst.write = 1;
8954 /* FLT_TO_INT is trans-only on r600/r700 */
8955 alu.last = TRUE;
8956 for (i = 0; i <= lasti; ++i) {
8957 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8958 alu.dst.chan = i;
8959 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8960 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8961 return r;
8962 }
8963 }
8964 break;
8965 case TGSI_OPCODE_UARL:
8966 memset(&alu, 0, sizeof(alu));
8967 alu.op = ALU_OP1_MOV;
8968 alu.dst.sel = ctx->bc->ar_reg;
8969 alu.dst.write = 1;
8970 for (i = 0; i <= lasti; ++i) {
8971 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8972 alu.dst.chan = i;
8973 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8974 alu.last = i == lasti;
8975 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8976 return r;
8977 }
8978 }
8979 break;
8980 default:
8981 assert(0);
8982 return -1;
8983 }
8984
8985 ctx->bc->ar_loaded = 0;
8986 return 0;
8987 }
8988
8989 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8990 {
8991 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8992 struct r600_bytecode_alu alu;
8993 int i, r = 0;
8994
8995 for (i = 0; i < 4; i++) {
8996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8997
8998 alu.op = ALU_OP2_MUL;
8999 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9000
9001 if (i == 0 || i == 3) {
9002 alu.src[0].sel = V_SQ_ALU_SRC_1;
9003 } else {
9004 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9005 }
9006
9007 if (i == 0 || i == 2) {
9008 alu.src[1].sel = V_SQ_ALU_SRC_1;
9009 } else {
9010 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
9011 }
9012 if (i == 3)
9013 alu.last = 1;
9014 r = r600_bytecode_add_alu(ctx->bc, &alu);
9015 if (r)
9016 return r;
9017 }
9018 return 0;
9019 }
9020
9021 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
9022 {
9023 struct r600_bytecode_alu alu;
9024 int r;
9025
9026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9027 alu.op = opcode;
9028 alu.execute_mask = 1;
9029 alu.update_pred = 1;
9030
9031 alu.dst.sel = ctx->temp_reg;
9032 alu.dst.write = 1;
9033 alu.dst.chan = 0;
9034
9035 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9036 alu.src[1].sel = V_SQ_ALU_SRC_0;
9037 alu.src[1].chan = 0;
9038
9039 alu.last = 1;
9040
9041 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
9042 if (r)
9043 return r;
9044 return 0;
9045 }
9046
9047 static int pops(struct r600_shader_ctx *ctx, int pops)
9048 {
9049 unsigned force_pop = ctx->bc->force_add_cf;
9050
9051 if (!force_pop) {
9052 int alu_pop = 3;
9053 if (ctx->bc->cf_last) {
9054 if (ctx->bc->cf_last->op == CF_OP_ALU)
9055 alu_pop = 0;
9056 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
9057 alu_pop = 1;
9058 }
9059 alu_pop += pops;
9060 if (alu_pop == 1) {
9061 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
9062 ctx->bc->force_add_cf = 1;
9063 } else if (alu_pop == 2) {
9064 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
9065 ctx->bc->force_add_cf = 1;
9066 } else {
9067 force_pop = 1;
9068 }
9069 }
9070
9071 if (force_pop) {
9072 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
9073 ctx->bc->cf_last->pop_count = pops;
9074 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9075 }
9076
9077 return 0;
9078 }
9079
9080 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
9081 unsigned reason)
9082 {
9083 struct r600_stack_info *stack = &ctx->bc->stack;
9084 unsigned elements;
9085 int entries;
9086
9087 unsigned entry_size = stack->entry_size;
9088
9089 elements = (stack->loop + stack->push_wqm ) * entry_size;
9090 elements += stack->push;
9091
9092 switch (ctx->bc->chip_class) {
9093 case R600:
9094 case R700:
9095 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9096 * the stack must be reserved to hold the current active/continue
9097 * masks */
9098 if (reason == FC_PUSH_VPM) {
9099 elements += 2;
9100 }
9101 break;
9102
9103 case CAYMAN:
9104 /* r9xx: any stack operation on empty stack consumes 2 additional
9105 * elements */
9106 elements += 2;
9107
9108 /* fallthrough */
9109 /* FIXME: do the two elements added above cover the cases for the
9110 * r8xx+ below? */
9111
9112 case EVERGREEN:
9113 /* r8xx+: 2 extra elements are not always required, but one extra
9114 * element must be added for each of the following cases:
9115 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9116 * stack usage.
9117 * (Currently we don't use ALU_ELSE_AFTER.)
9118 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9119 * PUSH instruction executed.
9120 *
9121 * NOTE: it seems we also need to reserve additional element in some
9122 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9123 * then STACK_SIZE should be 2 instead of 1 */
9124 if (reason == FC_PUSH_VPM) {
9125 elements += 1;
9126 }
9127 break;
9128
9129 default:
9130 assert(0);
9131 break;
9132 }
9133
9134 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9135 * for all chips, so we use 4 in the final formula, not the real entry_size
9136 * for the chip */
9137 entry_size = 4;
9138
9139 entries = (elements + (entry_size - 1)) / entry_size;
9140
9141 if (entries > stack->max_entries)
9142 stack->max_entries = entries;
9143 }
9144
9145 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9146 {
9147 switch(reason) {
9148 case FC_PUSH_VPM:
9149 --ctx->bc->stack.push;
9150 assert(ctx->bc->stack.push >= 0);
9151 break;
9152 case FC_PUSH_WQM:
9153 --ctx->bc->stack.push_wqm;
9154 assert(ctx->bc->stack.push_wqm >= 0);
9155 break;
9156 case FC_LOOP:
9157 --ctx->bc->stack.loop;
9158 assert(ctx->bc->stack.loop >= 0);
9159 break;
9160 default:
9161 assert(0);
9162 break;
9163 }
9164 }
9165
9166 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9167 {
9168 switch (reason) {
9169 case FC_PUSH_VPM:
9170 ++ctx->bc->stack.push;
9171 break;
9172 case FC_PUSH_WQM:
9173 ++ctx->bc->stack.push_wqm;
9174 case FC_LOOP:
9175 ++ctx->bc->stack.loop;
9176 break;
9177 default:
9178 assert(0);
9179 }
9180
9181 callstack_update_max_depth(ctx, reason);
9182 }
9183
9184 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9185 {
9186 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9187
9188 sp->mid = realloc((void *)sp->mid,
9189 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9190 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9191 sp->num_mid++;
9192 }
9193
9194 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9195 {
9196 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9197 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9198 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9199 ctx->bc->fc_sp++;
9200 }
9201
9202 static void fc_poplevel(struct r600_shader_ctx *ctx)
9203 {
9204 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9205 free(sp->mid);
9206 sp->mid = NULL;
9207 sp->num_mid = 0;
9208 sp->start = NULL;
9209 sp->type = 0;
9210 ctx->bc->fc_sp--;
9211 }
9212
9213 #if 0
9214 static int emit_return(struct r600_shader_ctx *ctx)
9215 {
9216 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9217 return 0;
9218 }
9219
9220 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9221 {
9222
9223 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9224 ctx->bc->cf_last->pop_count = pops;
9225 /* XXX work out offset */
9226 return 0;
9227 }
9228
9229 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9230 {
9231 return 0;
9232 }
9233
9234 static void emit_testflag(struct r600_shader_ctx *ctx)
9235 {
9236
9237 }
9238
9239 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9240 {
9241 emit_testflag(ctx);
9242 emit_jump_to_offset(ctx, 1, 4);
9243 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9244 pops(ctx, ifidx + 1);
9245 emit_return(ctx);
9246 }
9247
9248 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9249 {
9250 emit_testflag(ctx);
9251
9252 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9253 ctx->bc->cf_last->pop_count = 1;
9254
9255 fc_set_mid(ctx, fc_sp);
9256
9257 pops(ctx, 1);
9258 }
9259 #endif
9260
9261 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
9262 {
9263 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9264
9265 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9266 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9267 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9268 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9269 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9270 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9271 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9272 alu_type = CF_OP_ALU;
9273 }
9274
9275 emit_logic_pred(ctx, opcode, alu_type);
9276
9277 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9278
9279 fc_pushlevel(ctx, FC_IF);
9280
9281 callstack_push(ctx, FC_PUSH_VPM);
9282 return 0;
9283 }
9284
9285 static int tgsi_if(struct r600_shader_ctx *ctx)
9286 {
9287 return emit_if(ctx, ALU_OP2_PRED_SETNE);
9288 }
9289
9290 static int tgsi_uif(struct r600_shader_ctx *ctx)
9291 {
9292 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
9293 }
9294
9295 static int tgsi_else(struct r600_shader_ctx *ctx)
9296 {
9297 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9298 ctx->bc->cf_last->pop_count = 1;
9299
9300 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9301 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9302 return 0;
9303 }
9304
9305 static int tgsi_endif(struct r600_shader_ctx *ctx)
9306 {
9307 pops(ctx, 1);
9308 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9309 R600_ERR("if/endif unbalanced in shader\n");
9310 return -1;
9311 }
9312
9313 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9314 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9315 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9316 } else {
9317 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9318 }
9319 fc_poplevel(ctx);
9320
9321 callstack_pop(ctx, FC_PUSH_VPM);
9322 return 0;
9323 }
9324
9325 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
9326 {
9327 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9328 * limited to 4096 iterations, like the other LOOP_* instructions. */
9329 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
9330
9331 fc_pushlevel(ctx, FC_LOOP);
9332
9333 /* check stack depth */
9334 callstack_push(ctx, FC_LOOP);
9335 return 0;
9336 }
9337
9338 static int tgsi_endloop(struct r600_shader_ctx *ctx)
9339 {
9340 int i;
9341
9342 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
9343
9344 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
9345 R600_ERR("loop/endloop in shader code are not paired.\n");
9346 return -EINVAL;
9347 }
9348
9349 /* fixup loop pointers - from r600isa
9350 LOOP END points to CF after LOOP START,
9351 LOOP START point to CF after LOOP END
9352 BRK/CONT point to LOOP END CF
9353 */
9354 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
9355
9356 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9357
9358 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
9359 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
9360 }
9361 /* XXX add LOOPRET support */
9362 fc_poplevel(ctx);
9363 callstack_pop(ctx, FC_LOOP);
9364 return 0;
9365 }
9366
9367 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
9368 {
9369 unsigned int fscp;
9370
9371 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
9372 {
9373 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
9374 break;
9375 }
9376
9377 if (fscp == 0) {
9378 R600_ERR("Break not inside loop/endloop pair\n");
9379 return -EINVAL;
9380 }
9381
9382 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9383
9384 fc_set_mid(ctx, fscp - 1);
9385
9386 return 0;
9387 }
9388
9389 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
9390 {
9391 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9392 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
9393 int r;
9394
9395 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9396 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
9397
9398 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9399 if (!r) {
9400 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
9401 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9402 return emit_inc_ring_offset(ctx, stream, TRUE);
9403 }
9404 return r;
9405 }
9406
9407 static int tgsi_umad(struct r600_shader_ctx *ctx)
9408 {
9409 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9410 struct r600_bytecode_alu alu;
9411 int i, j, k, r;
9412 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9413
9414 /* src0 * src1 */
9415 for (i = 0; i < lasti + 1; i++) {
9416 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9417 continue;
9418
9419 if (ctx->bc->chip_class == CAYMAN) {
9420 for (j = 0 ; j < 4; j++) {
9421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9422
9423 alu.op = ALU_OP2_MULLO_UINT;
9424 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
9425 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
9426 }
9427 alu.dst.chan = j;
9428 alu.dst.sel = ctx->temp_reg;
9429 alu.dst.write = (j == i);
9430 if (j == 3)
9431 alu.last = 1;
9432 r = r600_bytecode_add_alu(ctx->bc, &alu);
9433 if (r)
9434 return r;
9435 }
9436 } else {
9437 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9438
9439 alu.dst.chan = i;
9440 alu.dst.sel = ctx->temp_reg;
9441 alu.dst.write = 1;
9442
9443 alu.op = ALU_OP2_MULLO_UINT;
9444 for (j = 0; j < 2; j++) {
9445 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
9446 }
9447
9448 alu.last = 1;
9449 r = r600_bytecode_add_alu(ctx->bc, &alu);
9450 if (r)
9451 return r;
9452 }
9453 }
9454
9455
9456 for (i = 0; i < lasti + 1; i++) {
9457 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9458 continue;
9459
9460 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9461 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9462
9463 alu.op = ALU_OP2_ADD_INT;
9464
9465 alu.src[0].sel = ctx->temp_reg;
9466 alu.src[0].chan = i;
9467
9468 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9469 if (i == lasti) {
9470 alu.last = 1;
9471 }
9472 r = r600_bytecode_add_alu(ctx->bc, &alu);
9473 if (r)
9474 return r;
9475 }
9476 return 0;
9477 }
9478
9479 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
9480 {
9481 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9482 struct r600_bytecode_alu alu;
9483 int r, i;
9484 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9485
9486 /* temp.xy = f32_to_f16(src) */
9487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9488 alu.op = ALU_OP1_FLT32_TO_FLT16;
9489 alu.dst.chan = 0;
9490 alu.dst.sel = ctx->temp_reg;
9491 alu.dst.write = 1;
9492 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9493 r = r600_bytecode_add_alu(ctx->bc, &alu);
9494 if (r)
9495 return r;
9496 alu.dst.chan = 1;
9497 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
9498 alu.last = 1;
9499 r = r600_bytecode_add_alu(ctx->bc, &alu);
9500 if (r)
9501 return r;
9502
9503 /* dst.x = temp.y * 0x10000 + temp.x */
9504 for (i = 0; i < lasti + 1; i++) {
9505 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9506 continue;
9507
9508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9509 alu.op = ALU_OP3_MULADD_UINT24;
9510 alu.is_op3 = 1;
9511 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9512 alu.last = i == lasti;
9513 alu.src[0].sel = ctx->temp_reg;
9514 alu.src[0].chan = 1;
9515 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9516 alu.src[1].value = 0x10000;
9517 alu.src[2].sel = ctx->temp_reg;
9518 alu.src[2].chan = 0;
9519 r = r600_bytecode_add_alu(ctx->bc, &alu);
9520 if (r)
9521 return r;
9522 }
9523
9524 return 0;
9525 }
9526
9527 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9528 {
9529 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9530 struct r600_bytecode_alu alu;
9531 int r, i;
9532 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9533
9534 /* temp.x = src.x */
9535 /* note: no need to mask out the high bits */
9536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9537 alu.op = ALU_OP1_MOV;
9538 alu.dst.chan = 0;
9539 alu.dst.sel = ctx->temp_reg;
9540 alu.dst.write = 1;
9541 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9542 r = r600_bytecode_add_alu(ctx->bc, &alu);
9543 if (r)
9544 return r;
9545
9546 /* temp.y = src.x >> 16 */
9547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9548 alu.op = ALU_OP2_LSHR_INT;
9549 alu.dst.chan = 1;
9550 alu.dst.sel = ctx->temp_reg;
9551 alu.dst.write = 1;
9552 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9553 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9554 alu.src[1].value = 16;
9555 alu.last = 1;
9556 r = r600_bytecode_add_alu(ctx->bc, &alu);
9557 if (r)
9558 return r;
9559
9560 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9561 for (i = 0; i < lasti + 1; i++) {
9562 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9563 continue;
9564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9565 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9566 alu.op = ALU_OP1_FLT16_TO_FLT32;
9567 alu.src[0].sel = ctx->temp_reg;
9568 alu.src[0].chan = i % 2;
9569 alu.last = i == lasti;
9570 r = r600_bytecode_add_alu(ctx->bc, &alu);
9571 if (r)
9572 return r;
9573 }
9574
9575 return 0;
9576 }
9577
9578 static int tgsi_bfe(struct r600_shader_ctx *ctx)
9579 {
9580 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9581 struct r600_bytecode_alu alu;
9582 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9583 int r, i;
9584
9585 r = tgsi_op3(ctx);
9586 if (r)
9587 return r;
9588
9589 for (i = 0; i < lasti + 1; i++) {
9590 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9591 alu.op = ALU_OP2_SETGE_INT;
9592 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
9593 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9594 alu.src[1].value = 32;
9595 alu.dst.sel = ctx->temp_reg;
9596 alu.dst.chan = i;
9597 alu.dst.write = 1;
9598 if (i == lasti)
9599 alu.last = 1;
9600 r = r600_bytecode_add_alu(ctx->bc, &alu);
9601 if (r)
9602 return r;
9603 }
9604
9605 for (i = 0; i < lasti + 1; i++) {
9606 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9607 alu.op = ALU_OP3_CNDE_INT;
9608 alu.is_op3 = 1;
9609 alu.src[0].sel = ctx->temp_reg;
9610 alu.src[1].chan = i;
9611
9612 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9613 alu.src[1].sel = alu.dst.sel;
9614 alu.src[1].chan = i;
9615 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
9616 alu.dst.write = 1;
9617 if (i == lasti)
9618 alu.last = 1;
9619 r = r600_bytecode_add_alu(ctx->bc, &alu);
9620 if (r)
9621 return r;
9622 }
9623
9624 return 0;
9625 }
9626
9627 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9628 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9629 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9630 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9631
9632 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9633
9634 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9635 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9636 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9637 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9638 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9639 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9640 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9641 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9642 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
9643 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9644 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9645 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9646 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9647 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9648 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9649 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9650 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9651 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9652 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9653 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9654 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9655 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9656 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9657 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9658 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9659 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9660 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9661 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9662 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9663 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9664 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9665 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9666 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9667 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9668 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9669 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9670 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9671 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9672 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9673 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9674 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9675 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9676 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9677 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9678 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9679 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9680 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9681 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9682 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9683 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9684 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9685 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9686 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9687 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9688 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9689 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9690 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9691 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9692 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9693 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9694 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9695 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9696 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9697 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9698 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9699 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9700 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9701 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9702 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9703 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9704 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9705 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9706 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9707 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9708 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9709 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9710 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9711 [81] = { ALU_OP0_NOP, tgsi_unsupported},
9712 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9713 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9714 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9715 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9716 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9717 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9718 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9719 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9720 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9721 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9722 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9723 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9724 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9725 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9726 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9727 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9728 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9729 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9730 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9731 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9732 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9733 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9734 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9735 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9736 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9737 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9738 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9739 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9740 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9741 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9742 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9743 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9744 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9745 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9746 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9747 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9748 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9749 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9750 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9751 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9752 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9753 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9754 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9755 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9756 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9757 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9758 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9759 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9760 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9761 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9762 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9763 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9764 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9765 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9766 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9767 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9768 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9769 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9770 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9771 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9772 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9773 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9774 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9775 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9776 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9777 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9778 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9779 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9780 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9781 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9782 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9783 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9784 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9785 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9786 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9787 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9788 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9789 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9790 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9791 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9792 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9793 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9794 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9795 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9796 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9797 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9798 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9799 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9800 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9801 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9802 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9803 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9804 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9805 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9806 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9807 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9808 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9809 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9810 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9811 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9812 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9813 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9814 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9815 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9816 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9817 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9818 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9819 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9820 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9821 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9822 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9823 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9824 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9825 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9826 };
9827
9828 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9829 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9830 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9831 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9832 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9833 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9834 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9835 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9836 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9837 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9838 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9839 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9840 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9841 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9842 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9843 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9844 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9845 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9846 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9847 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9848 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9849 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9850 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9851 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9852 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9853 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9854 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9855 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9856 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9857 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9858 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9859 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9860 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9861 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9862 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9863 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9864 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9865 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9866 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9867 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9868 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9869 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9870 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9871 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9872 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9873 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9874 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9875 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9876 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9877 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9878 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9879 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9880 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9881 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9882 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9883 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9884 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9885 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9886 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9887 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9888 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9889 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9890 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9891 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9892 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9893 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9894 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9895 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9896 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9897 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9898 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9899 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9900 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9901 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9902 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9903 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9904 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9905 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9906 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9907 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9908 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9909 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9910 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9911 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9912 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9913 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9914 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9915 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9916 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9917 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9918 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9919 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9920 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9921 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9922 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9923 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9924 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9925 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9926 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9927 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9928 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9929 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9930 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9931 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9932 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
9933 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9934 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9935 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9936 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9937 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9938 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9939 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9940 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9941 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9942 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9943 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9944 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9945 /* Refer below for TGSI_OPCODE_DFMA */
9946 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9947 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9948 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9949 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9950 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9951 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9952 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9953 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9954 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9955 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9956 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9957 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9958 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9959 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9960 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9961 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9962 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9963 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9964 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9965 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9966 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9967 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9968 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9969 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9970 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9971 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9972 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9973 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9974 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9975 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9976 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9977 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9978 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9979 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9980 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9981 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9982 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9983 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9984 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9985 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9986 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9987 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9988 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9989 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
9990 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9991 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9992 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9993 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9994 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9995 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9996 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9997 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9998 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9999 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10000 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10001 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10002 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10003 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10004 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10005 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10006 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10007 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
10008 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
10009 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10010 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10011 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10012 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10013 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10014 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10015 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10016 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10017 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10018 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10019 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10020 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10021 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10022 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10023 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10024 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10025 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10026 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10027 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10028 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10029 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10030 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10031 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10032 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10033 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10034 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10035 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10036 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10037 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10038 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10039 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10040 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10041 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10042 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10043 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10044 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10045 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10046 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10047 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10048 };
10049
10050 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
10051 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10052 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10053 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10054 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
10055 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
10056 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10057 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10058 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10059 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10060 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10061 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10062 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10063 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10064 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10065 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10066 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10067 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10068 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10069 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10070 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
10071 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10072 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10073 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10074 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10075 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10076 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10077 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10078 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
10079 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
10080 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
10081 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10082 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10083 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10084 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10085 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10086 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
10087 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10088 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10089 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10090 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10091 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10092 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10093 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10094 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10095 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10096 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10097 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10098 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
10099 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10100 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10101 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10102 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10103 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10104 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10105 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10106 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10107 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10108 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10109 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10110 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10111 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10112 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10113 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10114 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10115 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10116 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10117 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10118 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10119 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10120 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10121 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10122 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10123 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10124 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10125 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10126 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10127 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10128 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10129 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10130 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10131 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10132 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10133 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
10134 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10135 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10136 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10137 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10138 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10139 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10140 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10141 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10142 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10143 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10144 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10145 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10146 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10147 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10148 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10149 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10150 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10151 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10152 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10153 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10154 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10155 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10156 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10157 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10158 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10159 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10160 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10161 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10162 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10163 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10164 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10165 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10166 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10167 /* Refer below for TGSI_OPCODE_DFMA */
10168 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
10169 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10170 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10171 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10172 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10173 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10174 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10175 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10176 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
10177 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
10178 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10179 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10180 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10181 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10182 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10183 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10184 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
10185 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10186 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10187 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10188 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10189 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10190 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10191 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10192 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10193 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10194 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10195 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10196 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10197 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10198 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10199 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10200 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10201 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10202 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10203 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10204 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10205 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10206 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10207 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10208 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10209 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10210 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10211 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10212 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10213 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10214 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10215 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10216 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10217 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10218 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10219 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10220 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10221 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10222 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10223 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10224 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10225 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10226 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10227 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10228 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10229 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
10230 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
10231 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10232 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10233 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10234 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10235 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10236 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10237 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10238 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10239 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10240 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10241 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10242 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10243 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10244 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10245 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10246 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10247 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10248 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10249 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10250 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10251 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10252 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10253 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10254 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10255 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10256 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10257 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10258 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10259 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10260 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10261 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10262 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10263 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10264 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10265 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10266 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10267 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10268 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10269 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10270 };