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r600g: initial translate state support
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_index_modify.h>
41 #include <util/u_framebuffer.h>
42 #include "translate/translate_cache.h"
43 #include "translate/translate.h"
44 #include <pipebuffer/pb_buffer.h>
45 #include "r600.h"
46 #include "r600d.h"
47 #include "r600_resource.h"
48 #include "r600_shader.h"
49 #include "r600_pipe.h"
50 #include "r600_state_inlines.h"
51
52 static void r600_draw_common(struct r600_drawl *draw)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
55 struct r600_pipe_state *rstate;
56 struct r600_resource *rbuffer;
57 unsigned i, j, offset, prim;
58 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
59 struct pipe_vertex_buffer *vertex_buffer;
60 struct r600_draw rdraw;
61 struct r600_pipe_state vgt;
62
63 switch (draw->index_size) {
64 case 2:
65 vgt_draw_initiator = 0;
66 vgt_dma_index_type = 0;
67 break;
68 case 4:
69 vgt_draw_initiator = 0;
70 vgt_dma_index_type = 1;
71 break;
72 case 0:
73 vgt_draw_initiator = 2;
74 vgt_dma_index_type = 0;
75 break;
76 default:
77 R600_ERR("unsupported index size %d\n", draw->index_size);
78 return;
79 }
80 if (r600_conv_pipe_prim(draw->mode, &prim))
81 return;
82
83
84 /* rebuild vertex shader if input format changed */
85 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
86 return;
87 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
88 return;
89
90 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
91 uint32_t word2, format;
92
93 rstate = &rctx->vs_resource[i];
94 rstate->id = R600_PIPE_STATE_RESOURCE;
95 rstate->nregs = 0;
96
97 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
98 vertex_buffer = &rctx->vertex_buffer[j];
99 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
100 offset = rctx->vertex_elements->elements[i].src_offset +
101 vertex_buffer->buffer_offset +
102 r600_bo_offset(rbuffer->bo);
103
104 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
105
106 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
107
108 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
109 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
112 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
113 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
114 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
115 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
116 }
117
118 mask = 0;
119 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
120 mask |= (0xF << (i * 4));
121 }
122
123 vgt.id = R600_PIPE_STATE_VGT;
124 vgt.nregs = 0;
125 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
126 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
127 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
128 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
129 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
130 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
131 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
132 /* build late state */
133 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
134 float offset_units = rctx->rasterizer->offset_units;
135 unsigned offset_db_fmt_cntl = 0, depth;
136
137 switch (rctx->framebuffer.zsbuf->texture->format) {
138 case PIPE_FORMAT_Z24X8_UNORM:
139 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
140 depth = -24;
141 offset_units *= 2.0f;
142 break;
143 case PIPE_FORMAT_Z32_FLOAT:
144 depth = -23;
145 offset_units *= 1.0f;
146 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
147 break;
148 case PIPE_FORMAT_Z16_UNORM:
149 depth = -16;
150 offset_units *= 4.0f;
151 break;
152 default:
153 return;
154 }
155 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
156 r600_pipe_state_add_reg(&vgt,
157 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
158 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
159 r600_pipe_state_add_reg(&vgt,
160 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
161 fui(offset_units), 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(&vgt,
163 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
164 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
165 r600_pipe_state_add_reg(&vgt,
166 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
167 fui(offset_units), 0xFFFFFFFF, NULL);
168 r600_pipe_state_add_reg(&vgt,
169 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
170 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
171 }
172 r600_context_pipe_state_set(&rctx->ctx, &vgt);
173
174 rdraw.vgt_num_indices = draw->count;
175 rdraw.vgt_num_instances = 1;
176 rdraw.vgt_index_type = vgt_dma_index_type;
177 rdraw.vgt_draw_initiator = vgt_draw_initiator;
178 rdraw.indices = NULL;
179 if (draw->index_buffer) {
180 rbuffer = (struct r600_resource*)draw->index_buffer;
181 rdraw.indices = rbuffer->bo;
182 rdraw.indices_bo_offset = draw->index_buffer_offset;
183 }
184 r600_context_draw(&rctx->ctx, &rdraw);
185 }
186
187 static void r600_begin_vertex_translate(struct r600_pipe_context *rctx)
188 {
189 struct pipe_context *pipe = &rctx->context;
190 struct translate_key key = {0};
191 struct translate_element *te;
192 unsigned tr_elem_index[PIPE_MAX_ATTRIBS] = {0};
193 struct translate *tr;
194 struct r600_vertex_element *ve = rctx->vertex_elements;
195 boolean vb_translated[PIPE_MAX_ATTRIBS] = {0};
196 void *vb_map[PIPE_MAX_ATTRIBS] = {0}, *out_map;
197 struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS] = {0}, *out_transfer;
198 struct pipe_resource *out_buffer;
199 unsigned i, num_verts;
200
201 /* Initialize the translate key, i.e. the recipe how vertices should be
202 * translated. */
203 for (i = 0; i < ve->count; i++) {
204 struct pipe_vertex_buffer *vb =
205 &rctx->vertex_buffer[ve->elements[i].vertex_buffer_index];
206 enum pipe_format output_format = ve->hw_format[i];
207 unsigned output_format_size = ve->hw_format_size[i];
208
209 /* Check for support. */
210 if (ve->elements[i].src_format == ve->hw_format[i] &&
211 (vb->buffer_offset + ve->elements[i].src_offset) % 4 == 0 &&
212 vb->stride % 4 == 0) {
213 continue;
214 }
215
216 /* Workaround for translate: output floats instead of halfs. */
217 switch (output_format) {
218 case PIPE_FORMAT_R16_FLOAT:
219 output_format = PIPE_FORMAT_R32_FLOAT;
220 output_format_size = 4;
221 break;
222 case PIPE_FORMAT_R16G16_FLOAT:
223 output_format = PIPE_FORMAT_R32G32_FLOAT;
224 output_format_size = 8;
225 break;
226 case PIPE_FORMAT_R16G16B16_FLOAT:
227 output_format = PIPE_FORMAT_R32G32B32_FLOAT;
228 output_format_size = 12;
229 break;
230 case PIPE_FORMAT_R16G16B16A16_FLOAT:
231 output_format = PIPE_FORMAT_R32G32B32A32_FLOAT;
232 output_format_size = 16;
233 break;
234 default:;
235 }
236
237 /* Add this vertex element. */
238 te = &key.element[key.nr_elements];
239 /*te->type;
240 te->instance_divisor;*/
241 te->input_buffer = ve->elements[i].vertex_buffer_index;
242 te->input_format = ve->elements[i].src_format;
243 te->input_offset = vb->buffer_offset + ve->elements[i].src_offset;
244 te->output_format = output_format;
245 te->output_offset = key.output_stride;
246
247 key.output_stride += output_format_size;
248 vb_translated[ve->elements[i].vertex_buffer_index] = TRUE;
249 tr_elem_index[i] = key.nr_elements;
250 key.nr_elements++;
251 }
252
253 /* Get a translate object. */
254 tr = translate_cache_find(rctx->tran.translate_cache, &key);
255
256 /* Map buffers we want to translate. */
257 for (i = 0; i < rctx->nvertex_buffer; i++) {
258 if (vb_translated[i]) {
259 struct pipe_vertex_buffer *vb = &rctx->vertex_buffer[i];
260
261 vb_map[i] = pipe_buffer_map(pipe, vb->buffer,
262 PIPE_TRANSFER_READ, &vb_transfer[i]);
263
264 tr->set_buffer(tr, i, vb_map[i], vb->stride, vb->max_index);
265 }
266 }
267
268 /* Create and map the output buffer. */
269 num_verts = rctx->vb_max_index + 1;
270
271 out_buffer = pipe_buffer_create(&rctx->screen->screen,
272 PIPE_BIND_VERTEX_BUFFER,
273 key.output_stride * num_verts);
274
275 out_map = pipe_buffer_map(pipe, out_buffer, PIPE_TRANSFER_WRITE,
276 &out_transfer);
277
278 /* Translate. */
279 tr->run(tr, 0, num_verts, 0, out_map);
280
281 /* Unmap all buffers. */
282 for (i = 0; i < rctx->nvertex_buffer; i++) {
283 if (vb_translated[i]) {
284 pipe_buffer_unmap(pipe, rctx->vertex_buffer[i].buffer,
285 vb_transfer[i]);
286 }
287 }
288
289 {
290 float *flt = out_map;
291 fprintf(stderr,"num verts is %d\n", num_verts);
292 for (i = 0; i < num_verts; i++) {
293 fprintf(stderr,"%f %f\n", flt[i*2], flt[i*2+1]);
294 }
295 }
296 pipe_buffer_unmap(pipe, out_buffer, out_transfer);
297
298 /* Setup the new vertex buffer in the first free slot. */
299 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
300 struct pipe_vertex_buffer *vb = &rctx->vertex_buffer[i];
301
302 if (!vb->buffer) {
303 pipe_resource_reference(&vb->buffer, out_buffer);
304 vb->buffer_offset = 0;
305 vb->max_index = num_verts - 1;
306 vb->stride = key.output_stride;
307 rctx->tran.vb_slot = i;
308 break;
309 }
310 }
311
312 /* Save and replace vertex elements. */
313 {
314 struct pipe_vertex_element new_velems[PIPE_MAX_ATTRIBS];
315
316 rctx->tran.saved_velems = rctx->vertex_elements;
317
318 for (i = 0; i < ve->count; i++) {
319 if (vb_translated[ve->elements[i].vertex_buffer_index]) {
320 te = &key.element[tr_elem_index[i]];
321 new_velems[i].instance_divisor = ve->elements[i].instance_divisor;
322 new_velems[i].src_format = te->output_format;
323 new_velems[i].src_offset = te->output_offset;
324 new_velems[i].vertex_buffer_index = rctx->tran.vb_slot;
325 } else {
326 memcpy(&new_velems[i], &ve->elements[i],
327 sizeof(struct pipe_vertex_element));
328 }
329 }
330
331 rctx->tran.new_velems =
332 pipe->create_vertex_elements_state(pipe, ve->count, new_velems);
333 pipe->bind_vertex_elements_state(pipe, rctx->tran.new_velems);
334 }
335
336 pipe_resource_reference(&out_buffer, NULL);
337 }
338
339 static void r600_end_vertex_translate(struct r600_pipe_context *rctx)
340 {
341 struct pipe_context *pipe = &rctx->context;
342
343 /* Restore vertex elements. */
344 pipe->bind_vertex_elements_state(pipe, rctx->tran.saved_velems);
345 pipe->delete_vertex_elements_state(pipe, rctx->tran.new_velems);
346
347 /* Delete the now-unused VBO. */
348 pipe_resource_reference(&rctx->vertex_buffer[rctx->tran.vb_slot].buffer,
349 NULL);
350 }
351
352 void r600_translate_index_buffer(struct r600_pipe_context *r600,
353 struct pipe_resource **index_buffer,
354 unsigned *index_size,
355 unsigned *start, unsigned count)
356 {
357 switch (*index_size) {
358 case 1:
359 util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
360 *index_size = 2;
361 *start = 0;
362 break;
363
364 case 2:
365 if (*start % 2 != 0) {
366 util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
367 *start = 0;
368 }
369 break;
370
371 case 4:
372 break;
373 }
374 }
375
376 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
377 {
378 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
379 struct r600_drawl draw;
380 boolean translate = FALSE;
381
382 if (rctx->vertex_elements->incompatible_layout) {
383 r600_begin_vertex_translate(rctx);
384 translate = TRUE;
385 }
386
387 if (rctx->any_user_vbs) {
388 r600_upload_user_buffers(rctx);
389 rctx->any_user_vbs = FALSE;
390 }
391 memset(&draw, 0, sizeof(struct r600_drawl));
392 draw.ctx = ctx;
393 draw.mode = info->mode;
394 draw.start = info->start;
395 draw.count = info->count;
396 if (info->indexed && rctx->index_buffer.buffer) {
397 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
398 draw.min_index = info->min_index;
399 draw.max_index = info->max_index;
400 draw.index_bias = info->index_bias;
401
402 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
403 &rctx->index_buffer.index_size,
404 &draw.start,
405 info->count);
406
407 draw.index_size = rctx->index_buffer.index_size;
408 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
409 draw.index_buffer_offset = draw.start * draw.index_size;
410 draw.start = 0;
411 r600_upload_index_buffer(rctx, &draw);
412 } else {
413 draw.index_size = 0;
414 draw.index_buffer = NULL;
415 draw.min_index = info->min_index;
416 draw.max_index = info->max_index;
417 draw.index_bias = info->start;
418 }
419 r600_draw_common(&draw);
420
421 if (translate)
422 r600_end_vertex_translate(rctx);
423
424 pipe_resource_reference(&draw.index_buffer, NULL);
425 }
426
427 static void r600_set_blend_color(struct pipe_context *ctx,
428 const struct pipe_blend_color *state)
429 {
430 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
431 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
432
433 if (rstate == NULL)
434 return;
435
436 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
437 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
438 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
439 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
440 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
441 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
442 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
443 r600_context_pipe_state_set(&rctx->ctx, rstate);
444 }
445
446 static void *r600_create_blend_state(struct pipe_context *ctx,
447 const struct pipe_blend_state *state)
448 {
449 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
450 struct r600_pipe_state *rstate;
451 u32 color_control, target_mask;
452
453 if (blend == NULL) {
454 return NULL;
455 }
456 rstate = &blend->rstate;
457
458 rstate->id = R600_PIPE_STATE_BLEND;
459
460 target_mask = 0;
461 color_control = S_028808_PER_MRT_BLEND(1);
462 if (state->logicop_enable) {
463 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
464 } else {
465 color_control |= (0xcc << 16);
466 }
467 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
468 if (state->independent_blend_enable) {
469 for (int i = 0; i < 8; i++) {
470 if (state->rt[i].blend_enable) {
471 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
472 }
473 target_mask |= (state->rt[i].colormask << (4 * i));
474 }
475 } else {
476 for (int i = 0; i < 8; i++) {
477 if (state->rt[0].blend_enable) {
478 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
479 }
480 target_mask |= (state->rt[0].colormask << (4 * i));
481 }
482 }
483 blend->cb_target_mask = target_mask;
484 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
485 color_control, 0xFFFFFFFF, NULL);
486
487 for (int i = 0; i < 8; i++) {
488 unsigned eqRGB = state->rt[i].rgb_func;
489 unsigned srcRGB = state->rt[i].rgb_src_factor;
490 unsigned dstRGB = state->rt[i].rgb_dst_factor;
491
492 unsigned eqA = state->rt[i].alpha_func;
493 unsigned srcA = state->rt[i].alpha_src_factor;
494 unsigned dstA = state->rt[i].alpha_dst_factor;
495 uint32_t bc = 0;
496
497 if (!state->rt[i].blend_enable)
498 continue;
499
500 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
501 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
502 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
503
504 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
505 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
506 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
507 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
508 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
509 }
510
511 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
512 if (i == 0) {
513 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
514 }
515 }
516 return rstate;
517 }
518
519 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
520 {
521 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
522 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
523 struct r600_pipe_state *rstate;
524
525 if (state == NULL)
526 return;
527 rstate = &blend->rstate;
528 rctx->states[rstate->id] = rstate;
529 rctx->cb_target_mask = blend->cb_target_mask;
530 r600_context_pipe_state_set(&rctx->ctx, rstate);
531 }
532
533 static void *r600_create_dsa_state(struct pipe_context *ctx,
534 const struct pipe_depth_stencil_alpha_state *state)
535 {
536 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
537 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
538 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
539
540 if (rstate == NULL) {
541 return NULL;
542 }
543
544 rstate->id = R600_PIPE_STATE_DSA;
545 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
546 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
547 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
548 * be set if shader use texkill instruction
549 */
550 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
551 stencil_ref_mask = 0;
552 stencil_ref_mask_bf = 0;
553 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
554 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
555 S_028800_ZFUNC(state->depth.func);
556
557 /* stencil */
558 if (state->stencil[0].enabled) {
559 db_depth_control |= S_028800_STENCIL_ENABLE(1);
560 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
561 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
562 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
563 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
564
565
566 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
567 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
568 if (state->stencil[1].enabled) {
569 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
570 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
571 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
572 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
573 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
574 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
575 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
576 }
577 }
578
579 /* alpha */
580 alpha_test_control = 0;
581 alpha_ref = 0;
582 if (state->alpha.enabled) {
583 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
584 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
585 alpha_ref = fui(state->alpha.ref_value);
586 }
587
588 /* misc */
589 db_render_control = 0;
590 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
591 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
592 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
593 /* TODO db_render_override depends on query */
594 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
595 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
596 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
597 r600_pipe_state_add_reg(rstate,
598 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
599 0xFFFFFFFF & C_028430_STENCILREF, NULL);
600 r600_pipe_state_add_reg(rstate,
601 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
602 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
603 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
604 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
605 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
606 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
607 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
608 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
609 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
610 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
611 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
612 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
613 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
614
615 return rstate;
616 }
617
618 static void *r600_create_rs_state(struct pipe_context *ctx,
619 const struct pipe_rasterizer_state *state)
620 {
621 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
622 struct r600_pipe_state *rstate;
623 unsigned tmp;
624 unsigned prov_vtx = 1, polygon_dual_mode;
625 unsigned clip_rule;
626
627 if (rs == NULL) {
628 return NULL;
629 }
630
631 rstate = &rs->rstate;
632 rs->flatshade = state->flatshade;
633 rs->sprite_coord_enable = state->sprite_coord_enable;
634
635 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
636 /* offset */
637 rs->offset_units = state->offset_units;
638 rs->offset_scale = state->offset_scale * 12.0f;
639
640 rstate->id = R600_PIPE_STATE_RASTERIZER;
641 if (state->flatshade_first)
642 prov_vtx = 0;
643 tmp = 0x00000001;
644 if (state->sprite_coord_enable) {
645 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
646 S_0286D4_PNT_SPRITE_OVRD_X(2) |
647 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
648 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
649 S_0286D4_PNT_SPRITE_OVRD_W(1);
650 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
651 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
652 }
653 }
654 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
655
656 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
657 state->fill_back != PIPE_POLYGON_MODE_FILL);
658 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
659 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
660 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
661 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
662 S_028814_FACE(!state->front_ccw) |
663 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
664 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
665 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
666 S_028814_POLY_MODE(polygon_dual_mode) |
667 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
668 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
669 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
670 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
671 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
672 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
673 /* point size 12.4 fixed point */
674 tmp = (unsigned)(state->point_size * 8.0);
675 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
676 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
677
678 tmp = (unsigned)(state->line_width * 8.0);
679 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
680
681 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
682 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
683 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
684 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
685 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
686 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
687 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
688 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
689 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
690
691 return rstate;
692 }
693
694 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
695 {
696 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
697 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
698
699 if (state == NULL)
700 return;
701
702 rctx->flatshade = rs->flatshade;
703 rctx->sprite_coord_enable = rs->sprite_coord_enable;
704 rctx->rasterizer = rs;
705
706 rctx->states[rs->rstate.id] = &rs->rstate;
707 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
708 }
709
710 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
711 {
712 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
713 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
714
715 if (rctx->rasterizer == rs) {
716 rctx->rasterizer = NULL;
717 }
718 if (rctx->states[rs->rstate.id] == &rs->rstate) {
719 rctx->states[rs->rstate.id] = NULL;
720 }
721 free(rs);
722 }
723
724 static void *r600_create_sampler_state(struct pipe_context *ctx,
725 const struct pipe_sampler_state *state)
726 {
727 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
728 union util_color uc;
729
730 if (rstate == NULL) {
731 return NULL;
732 }
733
734 rstate->id = R600_PIPE_STATE_SAMPLER;
735 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
736 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
737 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
738 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
739 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
740 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
741 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
742 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
743 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
744 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
745 /* FIXME LOD it depends on texture base level ... */
746 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
747 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
748 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
749 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
750 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
751 if (uc.ui) {
752 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
753 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
754 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
755 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
756 }
757 return rstate;
758 }
759
760 #define FORMAT_REPLACE(what, withwhat) \
761 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break
762
763 static void *r600_create_vertex_elements(struct pipe_context *ctx,
764 unsigned count,
765 const struct pipe_vertex_element *elements)
766 {
767 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
768 int i;
769 enum pipe_format *format;
770
771 assert(count < 32);
772 if (!v)
773 return NULL;
774
775 v->count = count;
776 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
777
778 for (i = 0; i < count; i++) {
779 v->hw_format[i] = v->elements[i].src_format;
780 format = &v->hw_format[i];
781
782 switch (*format) {
783 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT);
784 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT);
785 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT);
786 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT);
787 default:;
788 }
789 v->incompatible_layout =
790 v->incompatible_layout ||
791 v->elements[i].src_format != v->hw_format[i] ||
792 v->elements[i].src_offset % 4 != 0;
793
794 v->hw_format_size[i] =
795 align(util_format_get_blocksize(v->hw_format[i]), 4);
796 }
797
798 v->refcount = 1;
799 return v;
800 }
801
802 static void r600_sampler_view_destroy(struct pipe_context *ctx,
803 struct pipe_sampler_view *state)
804 {
805 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
806
807 pipe_resource_reference(&state->texture, NULL);
808 FREE(resource);
809 }
810
811 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
812 struct pipe_resource *texture,
813 const struct pipe_sampler_view *state)
814 {
815 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
816 struct r600_pipe_state *rstate;
817 const struct util_format_description *desc;
818 struct r600_resource_texture *tmp;
819 struct r600_resource *rbuffer;
820 unsigned format;
821 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
822 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
823 struct r600_bo *bo[2];
824
825 if (resource == NULL)
826 return NULL;
827 rstate = &resource->state;
828
829 /* initialize base object */
830 resource->base = *state;
831 resource->base.texture = NULL;
832 pipe_reference(NULL, &texture->reference);
833 resource->base.texture = texture;
834 resource->base.reference.count = 1;
835 resource->base.context = ctx;
836
837 swizzle[0] = state->swizzle_r;
838 swizzle[1] = state->swizzle_g;
839 swizzle[2] = state->swizzle_b;
840 swizzle[3] = state->swizzle_a;
841 format = r600_translate_texformat(state->format,
842 swizzle,
843 &word4, &yuv_format);
844 if (format == ~0) {
845 format = 0;
846 }
847 desc = util_format_description(state->format);
848 if (desc == NULL) {
849 R600_ERR("unknow format %d\n", state->format);
850 }
851 tmp = (struct r600_resource_texture*)texture;
852 rbuffer = &tmp->resource;
853 bo[0] = rbuffer->bo;
854 bo[1] = rbuffer->bo;
855 /* FIXME depth texture decompression */
856 if (tmp->depth) {
857 r600_texture_depth_flush(ctx, texture);
858 tmp = (struct r600_resource_texture*)texture;
859 rbuffer = &tmp->flushed_depth_texture->resource;
860 bo[0] = rbuffer->bo;
861 bo[1] = rbuffer->bo;
862 }
863 pitch = align(tmp->pitch_in_pixels[0], 8);
864 if (tmp->tiled) {
865 array_mode = tmp->array_mode[0];
866 tile_type = tmp->tile_type;
867 }
868
869 /* FIXME properly handle first level != 0 */
870 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
871 S_038000_DIM(r600_tex_dim(texture->target)) |
872 S_038000_TILE_MODE(array_mode) |
873 S_038000_TILE_TYPE(tile_type) |
874 S_038000_PITCH((pitch / 8) - 1) |
875 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
876 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
877 S_038004_TEX_HEIGHT(texture->height0 - 1) |
878 S_038004_TEX_DEPTH(texture->depth0 - 1) |
879 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
880 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
881 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
882 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
883 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
884 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
885 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
886 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
887 S_038010_REQUEST_SIZE(1) |
888 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
889 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
890 S_038014_LAST_LEVEL(state->last_level) |
891 S_038014_BASE_ARRAY(0) |
892 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
894 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
895
896 return &resource->base;
897 }
898
899 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
900 struct pipe_sampler_view **views)
901 {
902 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
903 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
904
905 for (int i = 0; i < count; i++) {
906 if (resource[i]) {
907 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
908 }
909 }
910 }
911
912 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
913 struct pipe_sampler_view **views)
914 {
915 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
916 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
917 int i;
918
919 for (i = 0; i < count; i++) {
920 if (&rctx->ps_samplers.views[i]->base != views[i]) {
921 if (resource[i])
922 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
923 else
924 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
925
926 pipe_sampler_view_reference(
927 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
928 views[i]);
929
930 }
931 }
932 for (i = count; i < NUM_TEX_UNITS; i++) {
933 if (rctx->ps_samplers.views[i]) {
934 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
935 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
936 }
937 }
938 rctx->ps_samplers.n_views = count;
939 }
940
941 static void r600_bind_state(struct pipe_context *ctx, void *state)
942 {
943 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
944 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
945
946 if (state == NULL)
947 return;
948 rctx->states[rstate->id] = rstate;
949 r600_context_pipe_state_set(&rctx->ctx, rstate);
950 }
951
952 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
953 {
954 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
955 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
956
957 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
958 rctx->ps_samplers.n_samplers = count;
959
960 for (int i = 0; i < count; i++) {
961 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
962 }
963 }
964
965 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
966 {
967 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
968 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
969
970 for (int i = 0; i < count; i++) {
971 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
972 }
973 }
974
975 static void r600_delete_state(struct pipe_context *ctx, void *state)
976 {
977 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
978 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
979
980 if (rctx->states[rstate->id] == rstate) {
981 rctx->states[rstate->id] = NULL;
982 }
983 for (int i = 0; i < rstate->nregs; i++) {
984 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
985 }
986 free(rstate);
987 }
988
989 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
990 {
991 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
992
993 if (v == NULL)
994 return;
995 if (--v->refcount)
996 return;
997 free(v);
998 }
999
1000 static void r600_set_clip_state(struct pipe_context *ctx,
1001 const struct pipe_clip_state *state)
1002 {
1003 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1004 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1005
1006 if (rstate == NULL)
1007 return;
1008
1009 rctx->clip = *state;
1010 rstate->id = R600_PIPE_STATE_CLIP;
1011 for (int i = 0; i < state->nr; i++) {
1012 r600_pipe_state_add_reg(rstate,
1013 R_028E20_PA_CL_UCP0_X + i * 4,
1014 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
1015 r600_pipe_state_add_reg(rstate,
1016 R_028E24_PA_CL_UCP0_Y + i * 4,
1017 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
1018 r600_pipe_state_add_reg(rstate,
1019 R_028E28_PA_CL_UCP0_Z + i * 4,
1020 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
1021 r600_pipe_state_add_reg(rstate,
1022 R_028E2C_PA_CL_UCP0_W + i * 4,
1023 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
1024 }
1025 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1026 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1027 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1028 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
1029
1030 free(rctx->states[R600_PIPE_STATE_CLIP]);
1031 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1032 r600_context_pipe_state_set(&rctx->ctx, rstate);
1033 }
1034
1035 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
1036 {
1037 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1038 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
1039
1040 r600_delete_vertex_element(ctx, rctx->vertex_elements);
1041 rctx->vertex_elements = v;
1042 if (v) {
1043 v->refcount++;
1044 // rctx->vs_rebuild = TRUE;
1045 }
1046 }
1047
1048 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1049 const struct pipe_poly_stipple *state)
1050 {
1051 }
1052
1053 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1054 {
1055 }
1056
1057 static void r600_set_scissor_state(struct pipe_context *ctx,
1058 const struct pipe_scissor_state *state)
1059 {
1060 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1061 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1062 u32 tl, br;
1063
1064 if (rstate == NULL)
1065 return;
1066
1067 rstate->id = R600_PIPE_STATE_SCISSOR;
1068 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1069 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1070 r600_pipe_state_add_reg(rstate,
1071 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1072 0xFFFFFFFF, NULL);
1073 r600_pipe_state_add_reg(rstate,
1074 R_028214_PA_SC_CLIPRECT_0_BR, br,
1075 0xFFFFFFFF, NULL);
1076 r600_pipe_state_add_reg(rstate,
1077 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1078 0xFFFFFFFF, NULL);
1079 r600_pipe_state_add_reg(rstate,
1080 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1081 0xFFFFFFFF, NULL);
1082 r600_pipe_state_add_reg(rstate,
1083 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1084 0xFFFFFFFF, NULL);
1085 r600_pipe_state_add_reg(rstate,
1086 R_028224_PA_SC_CLIPRECT_2_BR, br,
1087 0xFFFFFFFF, NULL);
1088 r600_pipe_state_add_reg(rstate,
1089 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1090 0xFFFFFFFF, NULL);
1091 r600_pipe_state_add_reg(rstate,
1092 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1093 0xFFFFFFFF, NULL);
1094
1095 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1096 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1097 r600_context_pipe_state_set(&rctx->ctx, rstate);
1098 }
1099
1100 static void r600_set_stencil_ref(struct pipe_context *ctx,
1101 const struct pipe_stencil_ref *state)
1102 {
1103 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1104 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1105 u32 tmp;
1106
1107 if (rstate == NULL)
1108 return;
1109
1110 rctx->stencil_ref = *state;
1111 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1112 tmp = S_028430_STENCILREF(state->ref_value[0]);
1113 r600_pipe_state_add_reg(rstate,
1114 R_028430_DB_STENCILREFMASK, tmp,
1115 ~C_028430_STENCILREF, NULL);
1116 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1117 r600_pipe_state_add_reg(rstate,
1118 R_028434_DB_STENCILREFMASK_BF, tmp,
1119 ~C_028434_STENCILREF_BF, NULL);
1120
1121 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1122 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1123 r600_context_pipe_state_set(&rctx->ctx, rstate);
1124 }
1125
1126 static void r600_set_viewport_state(struct pipe_context *ctx,
1127 const struct pipe_viewport_state *state)
1128 {
1129 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1130 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1131
1132 if (rstate == NULL)
1133 return;
1134
1135 rctx->viewport = *state;
1136 rstate->id = R600_PIPE_STATE_VIEWPORT;
1137 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
1138 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
1139 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
1140 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
1141 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
1142 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
1143 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
1144 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
1145 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
1146
1147 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1148 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1149 r600_context_pipe_state_set(&rctx->ctx, rstate);
1150 }
1151
1152 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1153 const struct pipe_framebuffer_state *state, int cb)
1154 {
1155 struct r600_resource_texture *rtex;
1156 struct r600_resource *rbuffer;
1157 struct r600_surface *surf;
1158 unsigned level = state->cbufs[cb]->level;
1159 unsigned pitch, slice;
1160 unsigned color_info;
1161 unsigned format, swap, ntype;
1162 const struct util_format_description *desc;
1163 struct r600_bo *bo[3];
1164
1165 surf = (struct r600_surface *)state->cbufs[cb];
1166 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1167 rbuffer = &rtex->resource;
1168 bo[0] = rbuffer->bo;
1169 bo[1] = rbuffer->bo;
1170 bo[2] = rbuffer->bo;
1171
1172 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
1173 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
1174 ntype = 0;
1175 desc = util_format_description(rtex->resource.base.b.format);
1176 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1177 ntype = V_0280A0_NUMBER_SRGB;
1178
1179 format = r600_translate_colorformat(rtex->resource.base.b.format);
1180 swap = r600_translate_colorswap(rtex->resource.base.b.format);
1181 color_info = S_0280A0_FORMAT(format) |
1182 S_0280A0_COMP_SWAP(swap) |
1183 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1184 S_0280A0_BLEND_CLAMP(1) |
1185 S_0280A0_NUMBER_TYPE(ntype);
1186 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1187 color_info |= S_0280A0_SOURCE_FORMAT(1);
1188
1189 r600_pipe_state_add_reg(rstate,
1190 R_028040_CB_COLOR0_BASE + cb * 4,
1191 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
1192 r600_pipe_state_add_reg(rstate,
1193 R_0280A0_CB_COLOR0_INFO + cb * 4,
1194 color_info, 0xFFFFFFFF, bo[0]);
1195 r600_pipe_state_add_reg(rstate,
1196 R_028060_CB_COLOR0_SIZE + cb * 4,
1197 S_028060_PITCH_TILE_MAX(pitch) |
1198 S_028060_SLICE_TILE_MAX(slice),
1199 0xFFFFFFFF, NULL);
1200 r600_pipe_state_add_reg(rstate,
1201 R_028080_CB_COLOR0_VIEW + cb * 4,
1202 0x00000000, 0xFFFFFFFF, NULL);
1203 r600_pipe_state_add_reg(rstate,
1204 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1205 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
1206 r600_pipe_state_add_reg(rstate,
1207 R_0280C0_CB_COLOR0_TILE + cb * 4,
1208 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
1209 r600_pipe_state_add_reg(rstate,
1210 R_028100_CB_COLOR0_MASK + cb * 4,
1211 0x00000000, 0xFFFFFFFF, NULL);
1212 }
1213
1214 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1215 const struct pipe_framebuffer_state *state)
1216 {
1217 struct r600_resource_texture *rtex;
1218 struct r600_resource *rbuffer;
1219 struct r600_surface *surf;
1220 unsigned level;
1221 unsigned pitch, slice, format;
1222
1223 if (state->zsbuf == NULL)
1224 return;
1225
1226 level = state->zsbuf->level;
1227
1228 surf = (struct r600_surface *)state->zsbuf;
1229 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1230 rtex->tiled = 1;
1231 rtex->array_mode[level] = 2;
1232 rtex->tile_type = 1;
1233 rtex->depth = 1;
1234 rbuffer = &rtex->resource;
1235
1236 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
1237 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
1238 format = r600_translate_dbformat(state->zsbuf->texture->format);
1239
1240 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1241 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1242 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1243 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1244 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1247 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1248 0xFFFFFFFF, rbuffer->bo);
1249 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1250 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1251 }
1252
1253 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1254 const struct pipe_framebuffer_state *state)
1255 {
1256 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1257 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1258 u32 shader_mask, tl, br, shader_control, target_mask;
1259
1260 if (rstate == NULL)
1261 return;
1262
1263 /* unreference old buffer and reference new one */
1264 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1265
1266 util_copy_framebuffer_state(&rctx->framebuffer, state);
1267
1268 rctx->pframebuffer = &rctx->framebuffer;
1269
1270 /* build states */
1271 for (int i = 0; i < state->nr_cbufs; i++) {
1272 r600_cb(rctx, rstate, state, i);
1273 }
1274 if (state->zsbuf) {
1275 r600_db(rctx, rstate, state);
1276 }
1277
1278 target_mask = 0x00000000;
1279 target_mask = 0xFFFFFFFF;
1280 shader_mask = 0;
1281 shader_control = 0;
1282 for (int i = 0; i < state->nr_cbufs; i++) {
1283 target_mask ^= 0xf << (i * 4);
1284 shader_mask |= 0xf << (i * 4);
1285 shader_control |= 1 << i;
1286 }
1287 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1288 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1289
1290 r600_pipe_state_add_reg(rstate,
1291 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1292 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate,
1294 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1295 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate,
1297 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1298 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate,
1300 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1301 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate,
1303 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1304 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate,
1306 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1307 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate,
1309 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1310 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate,
1312 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1313 0xFFFFFFFF, NULL);
1314 r600_pipe_state_add_reg(rstate,
1315 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1316 0xFFFFFFFF, NULL);
1317 if (rctx->family >= CHIP_RV770) {
1318 r600_pipe_state_add_reg(rstate,
1319 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1320 0xFFFFFFFF, NULL);
1321 }
1322
1323 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1324 shader_control, 0xFFFFFFFF, NULL);
1325 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1326 0x00000000, target_mask, NULL);
1327 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1328 shader_mask, 0xFFFFFFFF, NULL);
1329 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1330 0x00000000, 0xFFFFFFFF, NULL);
1331 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1332 0x00000000, 0xFFFFFFFF, NULL);
1333 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1334 0x00000000, 0xFFFFFFFF, NULL);
1335 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1336 0x01000000, 0xFFFFFFFF, NULL);
1337 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1338 0x00000000, 0xFFFFFFFF, NULL);
1339 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1340 0x000000FF, 0xFFFFFFFF, NULL);
1341 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1342 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1343 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1344 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1345
1346 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1347 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1348 r600_context_pipe_state_set(&rctx->ctx, rstate);
1349 }
1350
1351 static void r600_set_index_buffer(struct pipe_context *ctx,
1352 const struct pipe_index_buffer *ib)
1353 {
1354 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1355
1356 if (ib) {
1357 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1358 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1359 } else {
1360 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1361 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1362 }
1363
1364 /* TODO make this more like a state */
1365 }
1366
1367 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1368 const struct pipe_vertex_buffer *buffers)
1369 {
1370 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1371 struct pipe_vertex_buffer *vbo;
1372 unsigned max_index = (unsigned)-1, vbo_max_index;
1373
1374 for (int i = 0; i < rctx->nvertex_buffer; i++) {
1375 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1376 }
1377 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1378
1379 for (int i = 0; i < count; i++) {
1380 vbo = (struct pipe_vertex_buffer*)&buffers[i];
1381
1382 rctx->vertex_buffer[i].buffer = NULL;
1383 if (r600_buffer_is_user_buffer(buffers[i].buffer))
1384 rctx->any_user_vbs = TRUE;
1385 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1386
1387 if (vbo->max_index == ~0) {
1388 if (!vbo->stride)
1389 vbo->max_index = 1;
1390 else
1391 vbo->max_index = (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride;
1392 }
1393
1394 max_index = MIN2(vbo->max_index, max_index);
1395 }
1396 rctx->nvertex_buffer = count;
1397 rctx->vb_max_index = max_index;
1398 }
1399
1400 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1401 struct pipe_resource *buffer)
1402 {
1403 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1404 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1405
1406 switch (shader) {
1407 case PIPE_SHADER_VERTEX:
1408 rctx->vs_const_buffer.nregs = 0;
1409 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1410 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1411 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1412 0xFFFFFFFF, NULL);
1413 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1414 R_028980_ALU_CONST_CACHE_VS_0,
1415 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1416 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1417 break;
1418 case PIPE_SHADER_FRAGMENT:
1419 rctx->ps_const_buffer.nregs = 0;
1420 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1421 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1422 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1423 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1425 R_028940_ALU_CONST_CACHE_PS_0,
1426 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1427 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1428 break;
1429 default:
1430 R600_ERR("unsupported %d\n", shader);
1431 return;
1432 }
1433 }
1434
1435 static void *r600_create_shader_state(struct pipe_context *ctx,
1436 const struct pipe_shader_state *state)
1437 {
1438 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1439 int r;
1440
1441 r = r600_pipe_shader_create(ctx, shader, state->tokens);
1442 if (r) {
1443 return NULL;
1444 }
1445 return shader;
1446 }
1447
1448 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1449 {
1450 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1451
1452 /* TODO delete old shader */
1453 rctx->ps_shader = (struct r600_pipe_shader *)state;
1454 }
1455
1456 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1457 {
1458 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1459
1460 /* TODO delete old shader */
1461 rctx->vs_shader = (struct r600_pipe_shader *)state;
1462 }
1463
1464 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1465 {
1466 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1467 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1468
1469 if (rctx->ps_shader == shader) {
1470 rctx->ps_shader = NULL;
1471 }
1472 /* TODO proper delete */
1473 free(shader);
1474 }
1475
1476 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1477 {
1478 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1479 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1480
1481 if (rctx->vs_shader == shader) {
1482 rctx->vs_shader = NULL;
1483 }
1484 /* TODO proper delete */
1485 free(shader);
1486 }
1487
1488 void r600_init_state_functions(struct r600_pipe_context *rctx)
1489 {
1490 rctx->context.create_blend_state = r600_create_blend_state;
1491 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1492 rctx->context.create_fs_state = r600_create_shader_state;
1493 rctx->context.create_rasterizer_state = r600_create_rs_state;
1494 rctx->context.create_sampler_state = r600_create_sampler_state;
1495 rctx->context.create_sampler_view = r600_create_sampler_view;
1496 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1497 rctx->context.create_vs_state = r600_create_shader_state;
1498 rctx->context.bind_blend_state = r600_bind_blend_state;
1499 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1500 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1501 rctx->context.bind_fs_state = r600_bind_ps_shader;
1502 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1503 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1504 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1505 rctx->context.bind_vs_state = r600_bind_vs_shader;
1506 rctx->context.delete_blend_state = r600_delete_state;
1507 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1508 rctx->context.delete_fs_state = r600_delete_ps_shader;
1509 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1510 rctx->context.delete_sampler_state = r600_delete_state;
1511 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1512 rctx->context.delete_vs_state = r600_delete_vs_shader;
1513 rctx->context.set_blend_color = r600_set_blend_color;
1514 rctx->context.set_clip_state = r600_set_clip_state;
1515 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1516 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1517 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1518 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1519 rctx->context.set_sample_mask = r600_set_sample_mask;
1520 rctx->context.set_scissor_state = r600_set_scissor_state;
1521 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1522 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1523 rctx->context.set_index_buffer = r600_set_index_buffer;
1524 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1525 rctx->context.set_viewport_state = r600_set_viewport_state;
1526 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1527 }
1528
1529 void r600_init_config(struct r600_pipe_context *rctx)
1530 {
1531 int ps_prio;
1532 int vs_prio;
1533 int gs_prio;
1534 int es_prio;
1535 int num_ps_gprs;
1536 int num_vs_gprs;
1537 int num_gs_gprs;
1538 int num_es_gprs;
1539 int num_temp_gprs;
1540 int num_ps_threads;
1541 int num_vs_threads;
1542 int num_gs_threads;
1543 int num_es_threads;
1544 int num_ps_stack_entries;
1545 int num_vs_stack_entries;
1546 int num_gs_stack_entries;
1547 int num_es_stack_entries;
1548 enum radeon_family family;
1549 struct r600_pipe_state *rstate = &rctx->config;
1550 u32 tmp;
1551
1552 family = r600_get_family(rctx->radeon);
1553 ps_prio = 0;
1554 vs_prio = 1;
1555 gs_prio = 2;
1556 es_prio = 3;
1557 switch (family) {
1558 case CHIP_R600:
1559 num_ps_gprs = 192;
1560 num_vs_gprs = 56;
1561 num_temp_gprs = 4;
1562 num_gs_gprs = 0;
1563 num_es_gprs = 0;
1564 num_ps_threads = 136;
1565 num_vs_threads = 48;
1566 num_gs_threads = 4;
1567 num_es_threads = 4;
1568 num_ps_stack_entries = 128;
1569 num_vs_stack_entries = 128;
1570 num_gs_stack_entries = 0;
1571 num_es_stack_entries = 0;
1572 break;
1573 case CHIP_RV630:
1574 case CHIP_RV635:
1575 num_ps_gprs = 84;
1576 num_vs_gprs = 36;
1577 num_temp_gprs = 4;
1578 num_gs_gprs = 0;
1579 num_es_gprs = 0;
1580 num_ps_threads = 144;
1581 num_vs_threads = 40;
1582 num_gs_threads = 4;
1583 num_es_threads = 4;
1584 num_ps_stack_entries = 40;
1585 num_vs_stack_entries = 40;
1586 num_gs_stack_entries = 32;
1587 num_es_stack_entries = 16;
1588 break;
1589 case CHIP_RV610:
1590 case CHIP_RV620:
1591 case CHIP_RS780:
1592 case CHIP_RS880:
1593 default:
1594 num_ps_gprs = 84;
1595 num_vs_gprs = 36;
1596 num_temp_gprs = 4;
1597 num_gs_gprs = 0;
1598 num_es_gprs = 0;
1599 num_ps_threads = 136;
1600 num_vs_threads = 48;
1601 num_gs_threads = 4;
1602 num_es_threads = 4;
1603 num_ps_stack_entries = 40;
1604 num_vs_stack_entries = 40;
1605 num_gs_stack_entries = 32;
1606 num_es_stack_entries = 16;
1607 break;
1608 case CHIP_RV670:
1609 num_ps_gprs = 144;
1610 num_vs_gprs = 40;
1611 num_temp_gprs = 4;
1612 num_gs_gprs = 0;
1613 num_es_gprs = 0;
1614 num_ps_threads = 136;
1615 num_vs_threads = 48;
1616 num_gs_threads = 4;
1617 num_es_threads = 4;
1618 num_ps_stack_entries = 40;
1619 num_vs_stack_entries = 40;
1620 num_gs_stack_entries = 32;
1621 num_es_stack_entries = 16;
1622 break;
1623 case CHIP_RV770:
1624 num_ps_gprs = 192;
1625 num_vs_gprs = 56;
1626 num_temp_gprs = 4;
1627 num_gs_gprs = 0;
1628 num_es_gprs = 0;
1629 num_ps_threads = 188;
1630 num_vs_threads = 60;
1631 num_gs_threads = 0;
1632 num_es_threads = 0;
1633 num_ps_stack_entries = 256;
1634 num_vs_stack_entries = 256;
1635 num_gs_stack_entries = 0;
1636 num_es_stack_entries = 0;
1637 break;
1638 case CHIP_RV730:
1639 case CHIP_RV740:
1640 num_ps_gprs = 84;
1641 num_vs_gprs = 36;
1642 num_temp_gprs = 4;
1643 num_gs_gprs = 0;
1644 num_es_gprs = 0;
1645 num_ps_threads = 188;
1646 num_vs_threads = 60;
1647 num_gs_threads = 0;
1648 num_es_threads = 0;
1649 num_ps_stack_entries = 128;
1650 num_vs_stack_entries = 128;
1651 num_gs_stack_entries = 0;
1652 num_es_stack_entries = 0;
1653 break;
1654 case CHIP_RV710:
1655 num_ps_gprs = 192;
1656 num_vs_gprs = 56;
1657 num_temp_gprs = 4;
1658 num_gs_gprs = 0;
1659 num_es_gprs = 0;
1660 num_ps_threads = 144;
1661 num_vs_threads = 48;
1662 num_gs_threads = 0;
1663 num_es_threads = 0;
1664 num_ps_stack_entries = 128;
1665 num_vs_stack_entries = 128;
1666 num_gs_stack_entries = 0;
1667 num_es_stack_entries = 0;
1668 break;
1669 }
1670
1671 rstate->id = R600_PIPE_STATE_CONFIG;
1672
1673 /* SQ_CONFIG */
1674 tmp = 0;
1675 switch (family) {
1676 case CHIP_RV610:
1677 case CHIP_RV620:
1678 case CHIP_RS780:
1679 case CHIP_RS880:
1680 case CHIP_RV710:
1681 break;
1682 default:
1683 tmp |= S_008C00_VC_ENABLE(1);
1684 break;
1685 }
1686 tmp |= S_008C00_DX9_CONSTS(0);
1687 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1688 tmp |= S_008C00_PS_PRIO(ps_prio);
1689 tmp |= S_008C00_VS_PRIO(vs_prio);
1690 tmp |= S_008C00_GS_PRIO(gs_prio);
1691 tmp |= S_008C00_ES_PRIO(es_prio);
1692 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1693
1694 /* SQ_GPR_RESOURCE_MGMT_1 */
1695 tmp = 0;
1696 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1697 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1698 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1699 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1700
1701 /* SQ_GPR_RESOURCE_MGMT_2 */
1702 tmp = 0;
1703 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1704 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1705 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1706
1707 /* SQ_THREAD_RESOURCE_MGMT */
1708 tmp = 0;
1709 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1710 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1711 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1712 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1713 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1714
1715 /* SQ_STACK_RESOURCE_MGMT_1 */
1716 tmp = 0;
1717 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1718 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1719 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1720
1721 /* SQ_STACK_RESOURCE_MGMT_2 */
1722 tmp = 0;
1723 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1724 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1725 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1726
1727 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1728 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1729
1730 if (family >= CHIP_RV770) {
1731 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1732 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1733 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1734 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1735 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1736 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1737 } else {
1738 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1739 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1740 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1741 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1742 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1743 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1744 }
1745 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1746 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1747 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1748 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1749 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1750 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1751 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1752 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1753 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1754 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1755 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1756 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1757 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1758 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1759 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1760 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1761 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1762 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1763 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1764 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1765 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1766 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1767 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1768 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1769 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1770 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1771
1772 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1773 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1774 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1775 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1776 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1777 r600_context_pipe_state_set(&rctx->ctx, rstate);
1778 }
1779
1780 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1781 {
1782 struct pipe_depth_stencil_alpha_state dsa;
1783 struct r600_pipe_state *rstate;
1784 boolean quirk = false;
1785
1786 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1787 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1788 quirk = true;
1789
1790 memset(&dsa, 0, sizeof(dsa));
1791
1792 if (quirk) {
1793 dsa.depth.enabled = 1;
1794 dsa.depth.func = PIPE_FUNC_LEQUAL;
1795 dsa.stencil[0].enabled = 1;
1796 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1797 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1798 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1799 dsa.stencil[0].writemask = 0xff;
1800 }
1801
1802 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1803 r600_pipe_state_add_reg(rstate,
1804 R_02880C_DB_SHADER_CONTROL,
1805 0x0,
1806 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1807 r600_pipe_state_add_reg(rstate,
1808 R_028D0C_DB_RENDER_CONTROL,
1809 S_028D0C_DEPTH_COPY_ENABLE(1) |
1810 S_028D0C_STENCIL_COPY_ENABLE(1) |
1811 S_028D0C_COPY_CENTROID(1),
1812 S_028D0C_DEPTH_COPY_ENABLE(1) |
1813 S_028D0C_STENCIL_COPY_ENABLE(1) |
1814 S_028D0C_COPY_CENTROID(1), NULL);
1815 return rstate;
1816 }