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[g3dvl] move zscan into shaders
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 static void r600_set_blend_color(struct pipe_context *ctx,
99 const struct pipe_blend_color *state)
100 {
101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
103
104 if (rstate == NULL)
105 return;
106
107 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
114 r600_context_pipe_state_set(&rctx->ctx, rstate);
115 }
116
117 static void *r600_create_blend_state(struct pipe_context *ctx,
118 const struct pipe_blend_state *state)
119 {
120 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
121 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
122 struct r600_pipe_state *rstate;
123 u32 color_control = 0, target_mask;
124
125 if (blend == NULL) {
126 return NULL;
127 }
128 rstate = &blend->rstate;
129
130 rstate->id = R600_PIPE_STATE_BLEND;
131
132 target_mask = 0;
133
134 /* R600 does not support per-MRT blends */
135 if (rctx->family > CHIP_R600)
136 color_control |= S_028808_PER_MRT_BLEND(1);
137 if (state->logicop_enable) {
138 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
139 } else {
140 color_control |= (0xcc << 16);
141 }
142 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
143 if (state->independent_blend_enable) {
144 for (int i = 0; i < 8; i++) {
145 if (state->rt[i].blend_enable) {
146 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
147 }
148 target_mask |= (state->rt[i].colormask << (4 * i));
149 }
150 } else {
151 for (int i = 0; i < 8; i++) {
152 if (state->rt[0].blend_enable) {
153 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
154 }
155 target_mask |= (state->rt[0].colormask << (4 * i));
156 }
157 }
158 blend->cb_target_mask = target_mask;
159 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
160 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
161 color_control, 0xFFFFFFFD, NULL);
162
163 for (int i = 0; i < 8; i++) {
164 /* state->rt entries > 0 only written if independent blending */
165 const int j = state->independent_blend_enable ? i : 0;
166
167 unsigned eqRGB = state->rt[j].rgb_func;
168 unsigned srcRGB = state->rt[j].rgb_src_factor;
169 unsigned dstRGB = state->rt[j].rgb_dst_factor;
170
171 unsigned eqA = state->rt[j].alpha_func;
172 unsigned srcA = state->rt[j].alpha_src_factor;
173 unsigned dstA = state->rt[j].alpha_dst_factor;
174 uint32_t bc = 0;
175
176 if (!state->rt[j].blend_enable)
177 continue;
178
179 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
180 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
181 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
182
183 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
184 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
185 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
186 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
187 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
188 }
189
190 /* R600 does not support per-MRT blends */
191 if (rctx->family > CHIP_R600)
192 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
193 if (i == 0)
194 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
195 }
196 return rstate;
197 }
198
199 static void *r600_create_dsa_state(struct pipe_context *ctx,
200 const struct pipe_depth_stencil_alpha_state *state)
201 {
202 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
203 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
204 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
205
206 if (rstate == NULL) {
207 return NULL;
208 }
209
210 rstate->id = R600_PIPE_STATE_DSA;
211 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
212 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
213 stencil_ref_mask = 0;
214 stencil_ref_mask_bf = 0;
215 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
216 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
217 S_028800_ZFUNC(state->depth.func);
218
219 /* stencil */
220 if (state->stencil[0].enabled) {
221 db_depth_control |= S_028800_STENCIL_ENABLE(1);
222 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
223 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
224 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
225 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
226
227
228 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
229 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
230 if (state->stencil[1].enabled) {
231 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
232 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
233 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
234 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
235 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
236 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
237 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
238 }
239 }
240
241 /* alpha */
242 alpha_test_control = 0;
243 alpha_ref = 0;
244 if (state->alpha.enabled) {
245 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
246 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
247 alpha_ref = fui(state->alpha.ref_value);
248 }
249
250 /* misc */
251 db_render_control = 0;
252 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
253 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
254 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
255 /* TODO db_render_override depends on query */
256 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
257 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
258 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
259 r600_pipe_state_add_reg(rstate,
260 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
261 0xFFFFFFFF & C_028430_STENCILREF, NULL);
262 r600_pipe_state_add_reg(rstate,
263 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
264 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
265 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
266 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
267 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
268 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
269 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
270 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
271 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
272 * r600_pipe_shader_ps().*/
273 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
274 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
275 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
276 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
277 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
278 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
279
280 return rstate;
281 }
282
283 static void *r600_create_rs_state(struct pipe_context *ctx,
284 const struct pipe_rasterizer_state *state)
285 {
286 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
287 struct r600_pipe_state *rstate;
288 unsigned tmp, cb;
289 unsigned prov_vtx = 1, polygon_dual_mode;
290 unsigned clip_rule;
291
292 if (rs == NULL) {
293 return NULL;
294 }
295
296 rstate = &rs->rstate;
297 rs->flatshade = state->flatshade;
298 rs->sprite_coord_enable = state->sprite_coord_enable;
299
300 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
301 /* offset */
302 rs->offset_units = state->offset_units;
303 rs->offset_scale = state->offset_scale * 12.0f;
304
305 rstate->id = R600_PIPE_STATE_RASTERIZER;
306 if (state->flatshade_first)
307 prov_vtx = 0;
308 tmp = S_0286D4_FLAT_SHADE_ENA(1);
309 if (state->sprite_coord_enable) {
310 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
311 S_0286D4_PNT_SPRITE_OVRD_X(2) |
312 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
313 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
314 S_0286D4_PNT_SPRITE_OVRD_W(1);
315 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
316 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
317 }
318 }
319 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
320
321 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
322 state->fill_back != PIPE_POLYGON_MODE_FILL);
323 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
324 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
325 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
326 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
327 S_028814_FACE(!state->front_ccw) |
328 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
329 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
330 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
331 S_028814_POLY_MODE(polygon_dual_mode) |
332 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
333 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
334 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
335 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
336 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
337 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
338 /* point size 12.4 fixed point */
339 tmp = (unsigned)(state->point_size * 8.0);
340 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
341 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
342
343 tmp = (unsigned)state->line_width * 8;
344 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
345
346 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
347 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
348 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
349
350 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
351 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
352 0xFFFFFFFF, NULL);
353
354 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
355 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
356 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
357 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
358 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
359 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
360
361 for (cb = 0; cb < 7; ++cb)
362 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + cb * 4,
363 S_0280A0_BLEND_CLAMP(state->clamp_fragment_color),
364 S_0280A0_BLEND_CLAMP(1), NULL);
365
366 return rstate;
367 }
368
369 static void *r600_create_sampler_state(struct pipe_context *ctx,
370 const struct pipe_sampler_state *state)
371 {
372 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
373 union util_color uc;
374 uint32_t coord_trunc = 0;
375
376 if (rstate == NULL) {
377 return NULL;
378 }
379
380 if ((state->mag_img_filter == PIPE_TEX_FILTER_NEAREST) ||
381 (state->min_img_filter == PIPE_TEX_FILTER_NEAREST))
382 coord_trunc = 1;
383
384 rstate->id = R600_PIPE_STATE_SAMPLER;
385 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
386 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
387 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
388 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
389 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
390 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
391 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
392 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
393 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
394 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
395 /* FIXME LOD it depends on texture base level ... */
396 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
397 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
398 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
399 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
400 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
401 S_03C008_MC_COORD_TRUNCATE(coord_trunc) |
402 S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
403 if (uc.ui) {
404 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
405 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
406 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
407 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
408 }
409 return rstate;
410 }
411
412 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
413 struct pipe_resource *texture,
414 const struct pipe_sampler_view *state)
415 {
416 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
417 struct r600_pipe_state *rstate;
418 const struct util_format_description *desc;
419 struct r600_resource_texture *tmp;
420 struct r600_resource *rbuffer;
421 unsigned format, endian;
422 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
423 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
424 struct r600_bo *bo[2];
425 unsigned height, depth;
426
427 if (resource == NULL)
428 return NULL;
429 rstate = &resource->state;
430
431 /* initialize base object */
432 resource->base = *state;
433 resource->base.texture = NULL;
434 pipe_reference(NULL, &texture->reference);
435 resource->base.texture = texture;
436 resource->base.reference.count = 1;
437 resource->base.context = ctx;
438
439 swizzle[0] = state->swizzle_r;
440 swizzle[1] = state->swizzle_g;
441 swizzle[2] = state->swizzle_b;
442 swizzle[3] = state->swizzle_a;
443 format = r600_translate_texformat(ctx->screen, state->format,
444 swizzle,
445 &word4, &yuv_format);
446 if (format == ~0) {
447 format = 0;
448 }
449 desc = util_format_description(state->format);
450 if (desc == NULL) {
451 R600_ERR("unknow format %d\n", state->format);
452 }
453 tmp = (struct r600_resource_texture *)texture;
454 if (tmp->depth && !tmp->is_flushing_texture) {
455 r600_texture_depth_flush(ctx, texture, TRUE);
456 tmp = tmp->flushed_depth_texture;
457 }
458 endian = r600_colorformat_endian_swap(format);
459
460 if (tmp->force_int_type) {
461 word4 &= C_038010_NUM_FORMAT_ALL;
462 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
463 }
464 rbuffer = &tmp->resource;
465 bo[0] = rbuffer->bo;
466 bo[1] = rbuffer->bo;
467 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
468 array_mode = tmp->array_mode[0];
469 tile_type = tmp->tile_type;
470
471 height = texture->height0;
472 depth = texture->depth0;
473 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
474 height = 1;
475 depth = texture->array_size;
476 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
477 depth = texture->array_size;
478 }
479
480 /* FIXME properly handle first level != 0 */
481 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
482 S_038000_DIM(r600_tex_dim(texture->target)) |
483 S_038000_TILE_MODE(array_mode) |
484 S_038000_TILE_TYPE(tile_type) |
485 S_038000_PITCH((pitch / 8) - 1) |
486 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
487 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
488 S_038004_TEX_HEIGHT(height - 1) |
489 S_038004_TEX_DEPTH(depth - 1) |
490 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
491 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
492 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
493 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
494 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
495 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
496 word4 |
497 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
498 S_038010_REQUEST_SIZE(1) |
499 S_038010_ENDIAN_SWAP(endian) |
500 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
501 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
502 S_038014_LAST_LEVEL(state->u.tex.last_level) |
503 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
504 S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
505 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
506 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
507
508 return &resource->base;
509 }
510
511 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
512 struct pipe_sampler_view **views)
513 {
514 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
515 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
516
517 for (int i = 0; i < count; i++) {
518 if (resource[i]) {
519 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
520 i + R600_MAX_CONST_BUFFERS);
521 }
522 }
523 }
524
525 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
526 struct pipe_sampler_view **views)
527 {
528 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
529 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
530 int i;
531
532 for (i = 0; i < count; i++) {
533 if (&rctx->ps_samplers.views[i]->base != views[i]) {
534 if (resource[i])
535 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
536 i + R600_MAX_CONST_BUFFERS);
537 else
538 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
539 i + R600_MAX_CONST_BUFFERS);
540
541 pipe_sampler_view_reference(
542 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
543 views[i]);
544
545 }
546 }
547 for (i = count; i < NUM_TEX_UNITS; i++) {
548 if (rctx->ps_samplers.views[i]) {
549 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
550 i + R600_MAX_CONST_BUFFERS);
551 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
552 }
553 }
554 rctx->ps_samplers.n_views = count;
555 }
556
557 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
558 {
559 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
560 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
561
562 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
563 rctx->ps_samplers.n_samplers = count;
564
565 for (int i = 0; i < count; i++) {
566 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
567 }
568 }
569
570 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
571 {
572 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
573 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
574
575 for (int i = 0; i < count; i++) {
576 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
577 }
578 }
579
580 static void r600_set_clip_state(struct pipe_context *ctx,
581 const struct pipe_clip_state *state)
582 {
583 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
584 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
585
586 if (rstate == NULL)
587 return;
588
589 rctx->clip = *state;
590 rstate->id = R600_PIPE_STATE_CLIP;
591 for (int i = 0; i < state->nr; i++) {
592 r600_pipe_state_add_reg(rstate,
593 R_028E20_PA_CL_UCP0_X + i * 16,
594 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
595 r600_pipe_state_add_reg(rstate,
596 R_028E24_PA_CL_UCP0_Y + i * 16,
597 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
598 r600_pipe_state_add_reg(rstate,
599 R_028E28_PA_CL_UCP0_Z + i * 16,
600 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
601 r600_pipe_state_add_reg(rstate,
602 R_028E2C_PA_CL_UCP0_W + i * 16,
603 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
604 }
605 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
606 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
607 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
608 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
609
610 free(rctx->states[R600_PIPE_STATE_CLIP]);
611 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
612 r600_context_pipe_state_set(&rctx->ctx, rstate);
613 }
614
615 static void r600_set_polygon_stipple(struct pipe_context *ctx,
616 const struct pipe_poly_stipple *state)
617 {
618 }
619
620 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
621 {
622 }
623
624 static void r600_set_scissor_state(struct pipe_context *ctx,
625 const struct pipe_scissor_state *state)
626 {
627 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
628 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
629 u32 tl, br;
630
631 if (rstate == NULL)
632 return;
633
634 rstate->id = R600_PIPE_STATE_SCISSOR;
635 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
636 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
637 r600_pipe_state_add_reg(rstate,
638 R_028210_PA_SC_CLIPRECT_0_TL, tl,
639 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate,
641 R_028214_PA_SC_CLIPRECT_0_BR, br,
642 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate,
644 R_028218_PA_SC_CLIPRECT_1_TL, tl,
645 0xFFFFFFFF, NULL);
646 r600_pipe_state_add_reg(rstate,
647 R_02821C_PA_SC_CLIPRECT_1_BR, br,
648 0xFFFFFFFF, NULL);
649 r600_pipe_state_add_reg(rstate,
650 R_028220_PA_SC_CLIPRECT_2_TL, tl,
651 0xFFFFFFFF, NULL);
652 r600_pipe_state_add_reg(rstate,
653 R_028224_PA_SC_CLIPRECT_2_BR, br,
654 0xFFFFFFFF, NULL);
655 r600_pipe_state_add_reg(rstate,
656 R_028228_PA_SC_CLIPRECT_3_TL, tl,
657 0xFFFFFFFF, NULL);
658 r600_pipe_state_add_reg(rstate,
659 R_02822C_PA_SC_CLIPRECT_3_BR, br,
660 0xFFFFFFFF, NULL);
661
662 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
663 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
664 r600_context_pipe_state_set(&rctx->ctx, rstate);
665 }
666
667 static void r600_set_stencil_ref(struct pipe_context *ctx,
668 const struct pipe_stencil_ref *state)
669 {
670 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
671 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
672 u32 tmp;
673
674 if (rstate == NULL)
675 return;
676
677 rctx->stencil_ref = *state;
678 rstate->id = R600_PIPE_STATE_STENCIL_REF;
679 tmp = S_028430_STENCILREF(state->ref_value[0]);
680 r600_pipe_state_add_reg(rstate,
681 R_028430_DB_STENCILREFMASK, tmp,
682 ~C_028430_STENCILREF, NULL);
683 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
684 r600_pipe_state_add_reg(rstate,
685 R_028434_DB_STENCILREFMASK_BF, tmp,
686 ~C_028434_STENCILREF_BF, NULL);
687
688 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
689 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
690 r600_context_pipe_state_set(&rctx->ctx, rstate);
691 }
692
693 static void r600_set_viewport_state(struct pipe_context *ctx,
694 const struct pipe_viewport_state *state)
695 {
696 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
697 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
698
699 if (rstate == NULL)
700 return;
701
702 rctx->viewport = *state;
703 rstate->id = R600_PIPE_STATE_VIEWPORT;
704 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
705 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
706 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
707 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
708 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
709 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
710 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
711 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
712 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
713
714 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
715 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
716 r600_context_pipe_state_set(&rctx->ctx, rstate);
717 }
718
719 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
720 const struct pipe_framebuffer_state *state, int cb)
721 {
722 struct r600_resource_texture *rtex;
723 struct r600_resource *rbuffer;
724 struct r600_surface *surf;
725 unsigned level = state->cbufs[cb]->u.tex.level;
726 unsigned pitch, slice;
727 unsigned color_info, color_info_mask;
728 unsigned format, swap, ntype, endian;
729 unsigned offset;
730 const struct util_format_description *desc;
731 struct r600_bo *bo[3];
732 int i;
733
734 surf = (struct r600_surface *)state->cbufs[cb];
735 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
736
737 if (rtex->depth && !rtex->is_flushing_texture) {
738 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
739 rtex = rtex->flushed_depth_texture;
740 }
741
742 rbuffer = &rtex->resource;
743 bo[0] = rbuffer->bo;
744 bo[1] = rbuffer->bo;
745 bo[2] = rbuffer->bo;
746
747 /* XXX quite sure for dx10+ hw don't need any offset hacks */
748 offset = r600_texture_get_offset(rtex,
749 level, state->cbufs[cb]->u.tex.first_layer);
750 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
751 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
752 desc = util_format_description(surf->base.format);
753
754 for (i = 0; i < 4; i++) {
755 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
756 break;
757 }
758 }
759 ntype = V_0280A0_NUMBER_UNORM;
760 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
761 ntype = V_0280A0_NUMBER_SRGB;
762 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
763 ntype = V_0280A0_NUMBER_SNORM;
764
765 format = r600_translate_colorformat(surf->base.format);
766 swap = r600_translate_colorswap(surf->base.format);
767 if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
768 endian = ENDIAN_NONE;
769 } else {
770 endian = r600_colorformat_endian_swap(format);
771 }
772
773 /* disable when gallium grows int textures */
774 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
775 ntype = V_0280A0_NUMBER_UINT;
776
777 color_info = S_0280A0_FORMAT(format) |
778 S_0280A0_COMP_SWAP(swap) |
779 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
780 S_0280A0_NUMBER_TYPE(ntype) |
781 S_0280A0_ENDIAN(endian);
782
783 color_info_mask = 0xFFFFFFFF & ~S_0280A0_BLEND_CLAMP(1);
784
785 /* on R600 this can't be set if BLEND_CLAMP isn't set,
786 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */
787 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && desc->channel[i].size < 12) {
788 //TODO: Seems to work on RV710, but i have no idea what to do between R600-RV710
789 if (rctx->family < CHIP_RV710) {
790 color_info |= S_0280A0_BLEND_CLAMP(1);
791 color_info_mask |= S_0280A0_BLEND_CLAMP(1);
792 }
793 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
794 }
795
796 r600_pipe_state_add_reg(rstate,
797 R_028040_CB_COLOR0_BASE + cb * 4,
798 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
799 r600_pipe_state_add_reg(rstate,
800 R_0280A0_CB_COLOR0_INFO + cb * 4,
801 color_info, color_info_mask, NULL);
802 r600_pipe_state_add_reg(rstate,
803 R_028060_CB_COLOR0_SIZE + cb * 4,
804 S_028060_PITCH_TILE_MAX(pitch) |
805 S_028060_SLICE_TILE_MAX(slice),
806 0xFFFFFFFF, NULL);
807 r600_pipe_state_add_reg(rstate,
808 R_028080_CB_COLOR0_VIEW + cb * 4,
809 0x00000000, 0xFFFFFFFF, NULL);
810 r600_pipe_state_add_reg(rstate,
811 R_0280E0_CB_COLOR0_FRAG + cb * 4,
812 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
813 r600_pipe_state_add_reg(rstate,
814 R_0280C0_CB_COLOR0_TILE + cb * 4,
815 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
816 r600_pipe_state_add_reg(rstate,
817 R_028100_CB_COLOR0_MASK + cb * 4,
818 0x00000000, 0xFFFFFFFF, NULL);
819 }
820
821 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
822 const struct pipe_framebuffer_state *state)
823 {
824 struct r600_resource_texture *rtex;
825 struct r600_resource *rbuffer;
826 struct r600_surface *surf;
827 unsigned level;
828 unsigned pitch, slice, format;
829 unsigned offset;
830
831 if (state->zsbuf == NULL)
832 return;
833
834 level = state->zsbuf->u.tex.level;
835
836 surf = (struct r600_surface *)state->zsbuf;
837 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
838
839 rbuffer = &rtex->resource;
840
841 /* XXX quite sure for dx10+ hw don't need any offset hacks */
842 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
843 level, state->zsbuf->u.tex.first_layer);
844 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
845 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
846 format = r600_translate_dbformat(state->zsbuf->texture->format);
847
848 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
849 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
850 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
851 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
852 0xFFFFFFFF, NULL);
853 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
854 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
855 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
856 0xFFFFFFFF, rbuffer->bo);
857 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
858 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
859 }
860
861 static void r600_set_framebuffer_state(struct pipe_context *ctx,
862 const struct pipe_framebuffer_state *state)
863 {
864 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
865 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
866 u32 shader_mask, tl, br, shader_control, target_mask;
867
868 if (rstate == NULL)
869 return;
870
871 r600_context_flush_dest_caches(&rctx->ctx);
872 rctx->ctx.num_dest_buffers = state->nr_cbufs;
873
874 /* unreference old buffer and reference new one */
875 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
876
877 util_copy_framebuffer_state(&rctx->framebuffer, state);
878
879 /* build states */
880 for (int i = 0; i < state->nr_cbufs; i++) {
881 r600_cb(rctx, rstate, state, i);
882 }
883 if (state->zsbuf) {
884 r600_db(rctx, rstate, state);
885 rctx->ctx.num_dest_buffers++;
886 }
887
888 target_mask = 0x00000000;
889 target_mask = 0xFFFFFFFF;
890 shader_mask = 0;
891 shader_control = 0;
892 for (int i = 0; i < state->nr_cbufs; i++) {
893 target_mask ^= 0xf << (i * 4);
894 shader_mask |= 0xf << (i * 4);
895 shader_control |= 1 << i;
896 }
897 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
898 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
899
900 r600_pipe_state_add_reg(rstate,
901 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
902 0xFFFFFFFF, NULL);
903 r600_pipe_state_add_reg(rstate,
904 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
905 0xFFFFFFFF, NULL);
906 r600_pipe_state_add_reg(rstate,
907 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
908 0xFFFFFFFF, NULL);
909 r600_pipe_state_add_reg(rstate,
910 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
911 0xFFFFFFFF, NULL);
912 r600_pipe_state_add_reg(rstate,
913 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
914 0xFFFFFFFF, NULL);
915 r600_pipe_state_add_reg(rstate,
916 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
917 0xFFFFFFFF, NULL);
918 r600_pipe_state_add_reg(rstate,
919 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
920 0xFFFFFFFF, NULL);
921 r600_pipe_state_add_reg(rstate,
922 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
923 0xFFFFFFFF, NULL);
924 r600_pipe_state_add_reg(rstate,
925 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
926 0xFFFFFFFF, NULL);
927 if (rctx->family >= CHIP_RV770) {
928 r600_pipe_state_add_reg(rstate,
929 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
930 0xFFFFFFFF, NULL);
931 }
932
933 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
934 shader_control, 0xFFFFFFFF, NULL);
935 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
936 0x00000000, target_mask, NULL);
937 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
938 shader_mask, 0xFFFFFFFF, NULL);
939 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
940 0x00000000, 0xFFFFFFFF, NULL);
941 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
942 0x00000000, 0xFFFFFFFF, NULL);
943 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
944 0x00000000, 0xFFFFFFFF, NULL);
945 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
946 0x01000000, 0xFFFFFFFF, NULL);
947 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
948 0x00000000, 0xFFFFFFFF, NULL);
949 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
950 0x000000FF, 0xFFFFFFFF, NULL);
951 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
952 0xFFFFFFFF, 0xFFFFFFFF, NULL);
953 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
954 0xFFFFFFFF, 0xFFFFFFFF, NULL);
955
956 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
957 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
958 r600_context_pipe_state_set(&rctx->ctx, rstate);
959
960 if (state->zsbuf) {
961 r600_polygon_offset_update(rctx);
962 }
963 }
964
965 static void r600_texture_barrier(struct pipe_context *ctx)
966 {
967 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
968
969 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
970 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
971 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
972 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
973 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
974 }
975
976 void r600_init_state_functions(struct r600_pipe_context *rctx)
977 {
978 rctx->context.create_blend_state = r600_create_blend_state;
979 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
980 rctx->context.create_fs_state = r600_create_shader_state;
981 rctx->context.create_rasterizer_state = r600_create_rs_state;
982 rctx->context.create_sampler_state = r600_create_sampler_state;
983 rctx->context.create_sampler_view = r600_create_sampler_view;
984 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
985 rctx->context.create_vs_state = r600_create_shader_state;
986 rctx->context.bind_blend_state = r600_bind_blend_state;
987 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
988 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
989 rctx->context.bind_fs_state = r600_bind_ps_shader;
990 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
991 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
992 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
993 rctx->context.bind_vs_state = r600_bind_vs_shader;
994 rctx->context.delete_blend_state = r600_delete_state;
995 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
996 rctx->context.delete_fs_state = r600_delete_ps_shader;
997 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
998 rctx->context.delete_sampler_state = r600_delete_state;
999 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1000 rctx->context.delete_vs_state = r600_delete_vs_shader;
1001 rctx->context.set_blend_color = r600_set_blend_color;
1002 rctx->context.set_clip_state = r600_set_clip_state;
1003 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1004 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1005 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1006 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1007 rctx->context.set_sample_mask = r600_set_sample_mask;
1008 rctx->context.set_scissor_state = r600_set_scissor_state;
1009 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1010 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1011 rctx->context.set_index_buffer = r600_set_index_buffer;
1012 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1013 rctx->context.set_viewport_state = r600_set_viewport_state;
1014 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1015 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1016 rctx->context.texture_barrier = r600_texture_barrier;
1017 }
1018
1019 void r600_init_config(struct r600_pipe_context *rctx)
1020 {
1021 int ps_prio;
1022 int vs_prio;
1023 int gs_prio;
1024 int es_prio;
1025 int num_ps_gprs;
1026 int num_vs_gprs;
1027 int num_gs_gprs;
1028 int num_es_gprs;
1029 int num_temp_gprs;
1030 int num_ps_threads;
1031 int num_vs_threads;
1032 int num_gs_threads;
1033 int num_es_threads;
1034 int num_ps_stack_entries;
1035 int num_vs_stack_entries;
1036 int num_gs_stack_entries;
1037 int num_es_stack_entries;
1038 enum radeon_family family;
1039 struct r600_pipe_state *rstate = &rctx->config;
1040 u32 tmp;
1041
1042 family = r600_get_family(rctx->radeon);
1043 ps_prio = 0;
1044 vs_prio = 1;
1045 gs_prio = 2;
1046 es_prio = 3;
1047 switch (family) {
1048 case CHIP_R600:
1049 num_ps_gprs = 192;
1050 num_vs_gprs = 56;
1051 num_temp_gprs = 4;
1052 num_gs_gprs = 0;
1053 num_es_gprs = 0;
1054 num_ps_threads = 136;
1055 num_vs_threads = 48;
1056 num_gs_threads = 4;
1057 num_es_threads = 4;
1058 num_ps_stack_entries = 128;
1059 num_vs_stack_entries = 128;
1060 num_gs_stack_entries = 0;
1061 num_es_stack_entries = 0;
1062 break;
1063 case CHIP_RV630:
1064 case CHIP_RV635:
1065 num_ps_gprs = 84;
1066 num_vs_gprs = 36;
1067 num_temp_gprs = 4;
1068 num_gs_gprs = 0;
1069 num_es_gprs = 0;
1070 num_ps_threads = 144;
1071 num_vs_threads = 40;
1072 num_gs_threads = 4;
1073 num_es_threads = 4;
1074 num_ps_stack_entries = 40;
1075 num_vs_stack_entries = 40;
1076 num_gs_stack_entries = 32;
1077 num_es_stack_entries = 16;
1078 break;
1079 case CHIP_RV610:
1080 case CHIP_RV620:
1081 case CHIP_RS780:
1082 case CHIP_RS880:
1083 default:
1084 num_ps_gprs = 84;
1085 num_vs_gprs = 36;
1086 num_temp_gprs = 4;
1087 num_gs_gprs = 0;
1088 num_es_gprs = 0;
1089 num_ps_threads = 136;
1090 num_vs_threads = 48;
1091 num_gs_threads = 4;
1092 num_es_threads = 4;
1093 num_ps_stack_entries = 40;
1094 num_vs_stack_entries = 40;
1095 num_gs_stack_entries = 32;
1096 num_es_stack_entries = 16;
1097 break;
1098 case CHIP_RV670:
1099 num_ps_gprs = 144;
1100 num_vs_gprs = 40;
1101 num_temp_gprs = 4;
1102 num_gs_gprs = 0;
1103 num_es_gprs = 0;
1104 num_ps_threads = 136;
1105 num_vs_threads = 48;
1106 num_gs_threads = 4;
1107 num_es_threads = 4;
1108 num_ps_stack_entries = 40;
1109 num_vs_stack_entries = 40;
1110 num_gs_stack_entries = 32;
1111 num_es_stack_entries = 16;
1112 break;
1113 case CHIP_RV770:
1114 num_ps_gprs = 192;
1115 num_vs_gprs = 56;
1116 num_temp_gprs = 4;
1117 num_gs_gprs = 0;
1118 num_es_gprs = 0;
1119 num_ps_threads = 188;
1120 num_vs_threads = 60;
1121 num_gs_threads = 0;
1122 num_es_threads = 0;
1123 num_ps_stack_entries = 256;
1124 num_vs_stack_entries = 256;
1125 num_gs_stack_entries = 0;
1126 num_es_stack_entries = 0;
1127 break;
1128 case CHIP_RV730:
1129 case CHIP_RV740:
1130 num_ps_gprs = 84;
1131 num_vs_gprs = 36;
1132 num_temp_gprs = 4;
1133 num_gs_gprs = 0;
1134 num_es_gprs = 0;
1135 num_ps_threads = 188;
1136 num_vs_threads = 60;
1137 num_gs_threads = 0;
1138 num_es_threads = 0;
1139 num_ps_stack_entries = 128;
1140 num_vs_stack_entries = 128;
1141 num_gs_stack_entries = 0;
1142 num_es_stack_entries = 0;
1143 break;
1144 case CHIP_RV710:
1145 num_ps_gprs = 192;
1146 num_vs_gprs = 56;
1147 num_temp_gprs = 4;
1148 num_gs_gprs = 0;
1149 num_es_gprs = 0;
1150 num_ps_threads = 144;
1151 num_vs_threads = 48;
1152 num_gs_threads = 0;
1153 num_es_threads = 0;
1154 num_ps_stack_entries = 128;
1155 num_vs_stack_entries = 128;
1156 num_gs_stack_entries = 0;
1157 num_es_stack_entries = 0;
1158 break;
1159 }
1160
1161 rstate->id = R600_PIPE_STATE_CONFIG;
1162
1163 /* SQ_CONFIG */
1164 tmp = 0;
1165 switch (family) {
1166 case CHIP_RV610:
1167 case CHIP_RV620:
1168 case CHIP_RS780:
1169 case CHIP_RS880:
1170 case CHIP_RV710:
1171 break;
1172 default:
1173 tmp |= S_008C00_VC_ENABLE(1);
1174 break;
1175 }
1176 tmp |= S_008C00_DX9_CONSTS(0);
1177 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1178 tmp |= S_008C00_PS_PRIO(ps_prio);
1179 tmp |= S_008C00_VS_PRIO(vs_prio);
1180 tmp |= S_008C00_GS_PRIO(gs_prio);
1181 tmp |= S_008C00_ES_PRIO(es_prio);
1182 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1183
1184 /* SQ_GPR_RESOURCE_MGMT_1 */
1185 tmp = 0;
1186 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1187 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1188 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1189 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1190
1191 /* SQ_GPR_RESOURCE_MGMT_2 */
1192 tmp = 0;
1193 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1194 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1195 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1196
1197 /* SQ_THREAD_RESOURCE_MGMT */
1198 tmp = 0;
1199 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1200 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1201 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1202 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1203 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1204
1205 /* SQ_STACK_RESOURCE_MGMT_1 */
1206 tmp = 0;
1207 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1208 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1209 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1210
1211 /* SQ_STACK_RESOURCE_MGMT_2 */
1212 tmp = 0;
1213 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1214 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1215 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1216
1217 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1219
1220 if (family >= CHIP_RV770) {
1221 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1222 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1223 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1224 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1226 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1227 } else {
1228 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1229 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1230 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1232 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1233 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1234 }
1235 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1236 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1237 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1238 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1239 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1240 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1241 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1242 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1243 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1244 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1248 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1250 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1251 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1254 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1256 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1257 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1259 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1260 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1261
1262 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1263 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1267 r600_context_pipe_state_set(&rctx->ctx, rstate);
1268 }
1269
1270 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1271 {
1272 struct r600_pipe_state *rstate = &shader->rstate;
1273 struct r600_shader *rshader = &shader->shader;
1274 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1275 int pos_index = -1, face_index = -1;
1276
1277 rstate->nregs = 0;
1278
1279 for (i = 0; i < rshader->ninput; i++) {
1280 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1281 pos_index = i;
1282 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1283 face_index = i;
1284 }
1285
1286 db_shader_control = 0;
1287 for (i = 0; i < rshader->noutput; i++) {
1288 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1289 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1290 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1291 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1292 }
1293 if (rshader->uses_kill)
1294 db_shader_control |= S_02880C_KILL_ENABLE(1);
1295
1296 exports_ps = 0;
1297 num_cout = 0;
1298 for (i = 0; i < rshader->noutput; i++) {
1299 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1300 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1301 exports_ps |= 1;
1302 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1303 num_cout++;
1304 }
1305 }
1306 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1307 if (!exports_ps) {
1308 /* always at least export 1 component per pixel */
1309 exports_ps = 2;
1310 }
1311
1312 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1313 S_0286CC_PERSP_GRADIENT_ENA(1);
1314 spi_input_z = 0;
1315 if (pos_index != -1) {
1316 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
1317 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1318 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
1319 S_0286CC_BARYC_SAMPLE_CNTL(1));
1320 spi_input_z |= 1;
1321 }
1322
1323 spi_ps_in_control_1 = 0;
1324 if (face_index != -1) {
1325 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1326 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1327 }
1328
1329 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1330 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1331 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1332 r600_pipe_state_add_reg(rstate,
1333 R_028840_SQ_PGM_START_PS,
1334 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1335 r600_pipe_state_add_reg(rstate,
1336 R_028850_SQ_PGM_RESOURCES_PS,
1337 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1338 S_028868_STACK_SIZE(rshader->bc.nstack),
1339 0xFFFFFFFF, NULL);
1340 r600_pipe_state_add_reg(rstate,
1341 R_028854_SQ_PGM_EXPORTS_PS,
1342 exports_ps, 0xFFFFFFFF, NULL);
1343 r600_pipe_state_add_reg(rstate,
1344 R_0288CC_SQ_PGM_CF_OFFSET_PS,
1345 0x00000000, 0xFFFFFFFF, NULL);
1346 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
1347 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
1348 S_028808_MULTIWRITE_ENABLE(1),
1349 NULL);
1350 /* only set some bits here, the other bits are set in the dsa state */
1351 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1352 db_shader_control,
1353 S_02880C_Z_EXPORT_ENABLE(1) |
1354 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
1355 S_02880C_KILL_ENABLE(1),
1356 NULL);
1357
1358 r600_pipe_state_add_reg(rstate,
1359 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
1360 0xFFFFFFFF, NULL);
1361 }
1362
1363 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1364 {
1365 struct r600_pipe_state *rstate = &shader->rstate;
1366 struct r600_shader *rshader = &shader->shader;
1367 unsigned spi_vs_out_id[10];
1368 unsigned i, tmp;
1369
1370 /* clear previous register */
1371 rstate->nregs = 0;
1372
1373 /* so far never got proper semantic id from tgsi */
1374 /* FIXME better to move this in config things so they get emited
1375 * only one time per cs
1376 */
1377 for (i = 0; i < 10; i++) {
1378 spi_vs_out_id[i] = 0;
1379 }
1380 for (i = 0; i < 32; i++) {
1381 tmp = i << ((i & 3) * 8);
1382 spi_vs_out_id[i / 4] |= tmp;
1383 }
1384 for (i = 0; i < 10; i++) {
1385 r600_pipe_state_add_reg(rstate,
1386 R_028614_SPI_VS_OUT_ID_0 + i * 4,
1387 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1388 }
1389
1390 r600_pipe_state_add_reg(rstate,
1391 R_0286C4_SPI_VS_OUT_CONFIG,
1392 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1393 0xFFFFFFFF, NULL);
1394 r600_pipe_state_add_reg(rstate,
1395 R_028868_SQ_PGM_RESOURCES_VS,
1396 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1397 S_028868_STACK_SIZE(rshader->bc.nstack),
1398 0xFFFFFFFF, NULL);
1399 r600_pipe_state_add_reg(rstate,
1400 R_0288D0_SQ_PGM_CF_OFFSET_VS,
1401 0x00000000, 0xFFFFFFFF, NULL);
1402 r600_pipe_state_add_reg(rstate,
1403 R_028858_SQ_PGM_START_VS,
1404 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1405
1406 r600_pipe_state_add_reg(rstate,
1407 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1408 0xFFFFFFFF, NULL);
1409 }
1410
1411 void r600_fetch_shader(struct r600_vertex_element *ve)
1412 {
1413 struct r600_pipe_state *rstate;
1414
1415 rstate = &ve->rstate;
1416 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1417 rstate->nregs = 0;
1418 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1419 0x00000000, 0xFFFFFFFF, NULL);
1420 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1421 0x00000000, 0xFFFFFFFF, NULL);
1422 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1423 r600_bo_offset(ve->fetch_shader) >> 8,
1424 0xFFFFFFFF, ve->fetch_shader);
1425 }
1426
1427 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1428 {
1429 struct pipe_depth_stencil_alpha_state dsa;
1430 struct r600_pipe_state *rstate;
1431 boolean quirk = false;
1432
1433 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1434 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1435 quirk = true;
1436
1437 memset(&dsa, 0, sizeof(dsa));
1438
1439 if (quirk) {
1440 dsa.depth.enabled = 1;
1441 dsa.depth.func = PIPE_FUNC_LEQUAL;
1442 dsa.stencil[0].enabled = 1;
1443 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1444 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1445 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1446 dsa.stencil[0].writemask = 0xff;
1447 }
1448
1449 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1450 r600_pipe_state_add_reg(rstate,
1451 R_02880C_DB_SHADER_CONTROL,
1452 0x0,
1453 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1454 r600_pipe_state_add_reg(rstate,
1455 R_028D0C_DB_RENDER_CONTROL,
1456 S_028D0C_DEPTH_COPY_ENABLE(1) |
1457 S_028D0C_STENCIL_COPY_ENABLE(1) |
1458 S_028D0C_COPY_CENTROID(1),
1459 S_028D0C_DEPTH_COPY_ENABLE(1) |
1460 S_028D0C_STENCIL_COPY_ENABLE(1) |
1461 S_028D0C_COPY_CENTROID(1), NULL);
1462 return rstate;
1463 }
1464
1465 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1466 struct r600_pipe_state *rstate,
1467 struct r600_resource *rbuffer,
1468 unsigned offset, unsigned stride)
1469 {
1470 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1471 offset, 0xFFFFFFFF, rbuffer->bo);
1472 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1473 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1474 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1475 #ifdef PIPE_ARCH_BIG_ENDIAN
1476 S_038008_ENDIAN_SWAP(ENDIAN_8IN32) |
1477 #endif
1478 S_038008_STRIDE(stride), 0xFFFFFFFF, NULL);
1479 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1480 0x00000000, 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1482 0x00000000, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1484 0x00000000, 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1486 0xC0000000, 0xFFFFFFFF, NULL);
1487 }