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r600g: fix binding of same texture to several target slot
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
38 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
39 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
40 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
41 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
42 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
43 const struct pipe_framebuffer_state *state, int cb);
44 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
45 const struct pipe_framebuffer_state *state);
46
47
48 static void *r600_create_blend_state(struct pipe_context *ctx,
49 const struct pipe_blend_state *state)
50 {
51 struct r600_context *rctx = r600_context(ctx);
52
53 return r600_context_state(rctx, pipe_blend_type, state);
54 }
55
56 static void *r600_create_dsa_state(struct pipe_context *ctx,
57 const struct pipe_depth_stencil_alpha_state *state)
58 {
59 struct r600_context *rctx = r600_context(ctx);
60
61 return r600_context_state(rctx, pipe_dsa_type, state);
62 }
63
64 static void *r600_create_rs_state(struct pipe_context *ctx,
65 const struct pipe_rasterizer_state *state)
66 {
67 struct r600_context *rctx = r600_context(ctx);
68
69 return r600_context_state(rctx, pipe_rasterizer_type, state);
70 }
71
72 static void *r600_create_sampler_state(struct pipe_context *ctx,
73 const struct pipe_sampler_state *state)
74 {
75 struct r600_context *rctx = r600_context(ctx);
76
77 return r600_context_state(rctx, pipe_sampler_type, state);
78 }
79
80 static void r600_sampler_view_destroy(struct pipe_context *ctx,
81 struct pipe_sampler_view *state)
82 {
83 struct r600_context_state *rstate = (struct r600_context_state *)state;
84
85 r600_context_state_decref(rstate);
86 }
87
88 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
89 struct pipe_resource *texture,
90 const struct pipe_sampler_view *state)
91 {
92 struct r600_context *rctx = r600_context(ctx);
93 struct r600_context_state *rstate;
94
95 rstate = r600_context_state(rctx, pipe_sampler_view_type, state);
96 pipe_reference(NULL, &texture->reference);
97 rstate->state.sampler_view.texture = texture;
98 rstate->state.sampler_view.reference.count = 1;
99 rstate->state.sampler_view.context = ctx;
100 r600_resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
101 return &rstate->state.sampler_view;
102 }
103
104 static void *r600_create_shader_state(struct pipe_context *ctx,
105 const struct pipe_shader_state *state)
106 {
107 struct r600_context *rctx = r600_context(ctx);
108
109 return r600_context_state(rctx, pipe_shader_type, state);
110 }
111
112 static void *r600_create_vertex_elements(struct pipe_context *ctx,
113 unsigned count,
114 const struct pipe_vertex_element *elements)
115 {
116 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
117
118 assert(count < 32);
119 v->count = count;
120 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
121 v->refcount = 1;
122 return v;
123 }
124
125 static void r600_bind_state(struct pipe_context *ctx, void *state)
126 {
127 struct r600_context *rctx = r600_context(ctx);
128 struct r600_context_state *rstate = (struct r600_context_state *)state;
129
130 if (state == NULL)
131 return;
132 switch (rstate->type) {
133 case pipe_rasterizer_type:
134 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
135 rctx->rasterizer = r600_context_state_incref(rstate);
136 break;
137 case pipe_poly_stipple_type:
138 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
139 rctx->poly_stipple = r600_context_state_incref(rstate);
140 break;
141 case pipe_scissor_type:
142 rctx->scissor = r600_context_state_decref(rctx->scissor);
143 rctx->scissor = r600_context_state_incref(rstate);
144 break;
145 case pipe_clip_type:
146 rctx->clip = r600_context_state_decref(rctx->clip);
147 rctx->clip = r600_context_state_incref(rstate);
148 break;
149 case pipe_depth_type:
150 rctx->depth = r600_context_state_decref(rctx->depth);
151 rctx->depth = r600_context_state_incref(rstate);
152 break;
153 case pipe_stencil_type:
154 rctx->stencil = r600_context_state_decref(rctx->stencil);
155 rctx->stencil = r600_context_state_incref(rstate);
156 break;
157 case pipe_alpha_type:
158 rctx->alpha = r600_context_state_decref(rctx->alpha);
159 rctx->alpha = r600_context_state_incref(rstate);
160 break;
161 case pipe_dsa_type:
162 rctx->dsa = r600_context_state_decref(rctx->dsa);
163 rctx->dsa = r600_context_state_incref(rstate);
164 break;
165 case pipe_blend_type:
166 rctx->blend = r600_context_state_decref(rctx->blend);
167 rctx->blend = r600_context_state_incref(rstate);
168 break;
169 case pipe_framebuffer_type:
170 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
171 rctx->framebuffer = r600_context_state_incref(rstate);
172 break;
173 case pipe_stencil_ref_type:
174 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
175 rctx->stencil_ref = r600_context_state_incref(rstate);
176 break;
177 case pipe_viewport_type:
178 rctx->viewport = r600_context_state_decref(rctx->viewport);
179 rctx->viewport = r600_context_state_incref(rstate);
180 break;
181 case pipe_shader_type:
182 case pipe_sampler_type:
183 case pipe_sampler_view_type:
184 default:
185 R600_ERR("invalid type %d\n", rstate->type);
186 return;
187 }
188 }
189
190 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
191 {
192 struct r600_context *rctx = r600_context(ctx);
193 struct r600_context_state *rstate = (struct r600_context_state *)state;
194
195 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
196 rctx->ps_shader = r600_context_state_incref(rstate);
197 }
198
199 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
200 {
201 struct r600_context *rctx = r600_context(ctx);
202 struct r600_context_state *rstate = (struct r600_context_state *)state;
203
204 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
205 rctx->vs_shader = r600_context_state_incref(rstate);
206 }
207
208 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
209 {
210 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
211
212 if (v == NULL)
213 return;
214 if (--v->refcount)
215 return;
216 free(v);
217 }
218
219 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
220 {
221 struct r600_context *rctx = r600_context(ctx);
222 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
223
224 r600_delete_vertex_element(ctx, rctx->vertex_elements);
225 rctx->vertex_elements = v;
226 if (v) {
227 v->refcount++;
228 }
229 }
230
231 static void r600_bind_ps_sampler(struct pipe_context *ctx,
232 unsigned count, void **states)
233 {
234 struct r600_context *rctx = r600_context(ctx);
235 struct r600_context_state *rstate;
236 unsigned i;
237
238 for (i = 0; i < count; i++) {
239 rstate = (struct r600_context_state *)states[i];
240 if (rstate) {
241 rstate->nrstate = 0;
242 }
243 }
244 for (i = 0; i < count; i++) {
245 rstate = (struct r600_context_state *)states[i];
246 if (rstate) {
247 if (rstate->nrstate >= R600_MAX_RSTATE)
248 continue;
249 if (rstate->nrstate) {
250 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
251 }
252 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_PS);
253 rctx->ps_sampler[i] = &rstate->rstate[rstate->nrstate];
254 rstate->nrstate++;
255 }
256 }
257 rctx->ps_nsampler = count;
258 }
259
260 static void r600_bind_vs_sampler(struct pipe_context *ctx,
261 unsigned count, void **states)
262 {
263 struct r600_context *rctx = r600_context(ctx);
264 struct r600_context_state *rstate;
265 unsigned i;
266
267 for (i = 0; i < count; i++) {
268 rstate = (struct r600_context_state *)states[i];
269 if (rstate) {
270 rstate->nrstate = 0;
271 }
272 }
273 for (i = 0; i < count; i++) {
274 rstate = (struct r600_context_state *)states[i];
275 if (rstate) {
276 if (rstate->nrstate >= R600_MAX_RSTATE)
277 continue;
278 if (rstate->nrstate) {
279 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
280 }
281 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_VS);
282 rctx->vs_sampler[i] = &rstate->rstate[rstate->nrstate];
283 rstate->nrstate++;
284 }
285 }
286 rctx->vs_nsampler = count;
287 }
288
289 static void r600_delete_state(struct pipe_context *ctx, void *state)
290 {
291 struct r600_context_state *rstate = (struct r600_context_state *)state;
292
293 r600_context_state_decref(rstate);
294 }
295
296 static void r600_set_blend_color(struct pipe_context *ctx,
297 const struct pipe_blend_color *color)
298 {
299 struct r600_context *rctx = r600_context(ctx);
300
301 rctx->blend_color = *color;
302 }
303
304 static void r600_set_clip_state(struct pipe_context *ctx,
305 const struct pipe_clip_state *state)
306 {
307 struct r600_context *rctx = r600_context(ctx);
308 struct r600_context_state *rstate;
309
310 rstate = r600_context_state(rctx, pipe_clip_type, state);
311 r600_bind_state(ctx, rstate);
312 /* refcount is taken care of this */
313 r600_delete_state(ctx, rstate);
314 }
315
316 static void r600_set_constant_buffer(struct pipe_context *ctx,
317 uint shader, uint index,
318 struct pipe_resource *buffer)
319 {
320 struct r600_screen *rscreen = r600_screen(ctx->screen);
321 struct r600_context *rctx = r600_context(ctx);
322 unsigned nconstant = 0, i, type, shader_class;
323 struct radeon_state *rstate, *rstates;
324 struct pipe_transfer *transfer;
325 u32 *ptr;
326
327 type = R600_STATE_CONSTANT;
328
329 switch (shader) {
330 case PIPE_SHADER_VERTEX:
331 shader_class = R600_SHADER_VS;
332 rstates = rctx->vs_constant;
333 break;
334 case PIPE_SHADER_FRAGMENT:
335 shader_class = R600_SHADER_PS;
336 rstates = rctx->ps_constant;
337 break;
338 default:
339 R600_ERR("unsupported %d\n", shader);
340 return;
341 }
342 if (buffer && buffer->width0 > 0) {
343 nconstant = buffer->width0 / 16;
344 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
345 if (ptr == NULL)
346 return;
347 for (i = 0; i < nconstant; i++) {
348 rstate = &rstates[i];
349 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
350 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
351 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
352 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
353 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
354 if (radeon_state_pm4(rstate))
355 return;
356 radeon_draw_bind(&rctx->draw, rstate);
357 }
358 pipe_buffer_unmap(ctx, buffer, transfer);
359 }
360 }
361
362 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
363 unsigned count,
364 struct pipe_sampler_view **views)
365 {
366 struct r600_context *rctx = r600_context(ctx);
367 struct r600_context_state *rstate;
368 unsigned i;
369
370 for (i = 0; i < count; i++) {
371 rstate = (struct r600_context_state *)views[i];
372 if (rstate) {
373 rstate->nrstate = 0;
374 }
375 }
376 for (i = 0; i < count; i++) {
377 rstate = (struct r600_context_state *)views[i];
378 if (rstate) {
379 if (rstate->nrstate >= R600_MAX_RSTATE)
380 continue;
381 if (rstate->nrstate) {
382 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
383 }
384 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_PS);
385 rctx->ps_sampler_view[i] = &rstate->rstate[rstate->nrstate];
386 rstate->nrstate++;
387 }
388 }
389 rctx->ps_nsampler_view = count;
390 }
391
392 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
393 unsigned count,
394 struct pipe_sampler_view **views)
395 {
396 struct r600_context *rctx = r600_context(ctx);
397 struct r600_context_state *rstate;
398 unsigned i;
399
400 for (i = 0; i < count; i++) {
401 rstate = (struct r600_context_state *)views[i];
402 if (rstate) {
403 rstate->nrstate = 0;
404 }
405 }
406 for (i = 0; i < count; i++) {
407 rstate = (struct r600_context_state *)views[i];
408 if (rstate) {
409 if (rstate->nrstate >= R600_MAX_RSTATE)
410 continue;
411 if (rstate->nrstate) {
412 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
413 }
414 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_VS);
415 rctx->vs_sampler_view[i] = &rstate->rstate[rstate->nrstate];
416 rstate->nrstate++;
417 }
418 }
419 rctx->vs_nsampler_view = count;
420 }
421
422 static void r600_set_framebuffer_state(struct pipe_context *ctx,
423 const struct pipe_framebuffer_state *state)
424 {
425 struct r600_context *rctx = r600_context(ctx);
426 struct r600_context_state *rstate;
427
428 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
429 r600_bind_state(ctx, rstate);
430 for (int i = 0; i < state->nr_cbufs; i++) {
431 r600_cb(rctx, &rstate->rstate[i+1], state, i);
432 }
433 if (state->zsbuf) {
434 r600_db(rctx, &rstate->rstate[0], state);
435 }
436 }
437
438 static void r600_set_polygon_stipple(struct pipe_context *ctx,
439 const struct pipe_poly_stipple *state)
440 {
441 }
442
443 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
444 {
445 }
446
447 static void r600_set_scissor_state(struct pipe_context *ctx,
448 const struct pipe_scissor_state *state)
449 {
450 struct r600_context *rctx = r600_context(ctx);
451 struct r600_context_state *rstate;
452
453 rstate = r600_context_state(rctx, pipe_scissor_type, state);
454 r600_bind_state(ctx, rstate);
455 /* refcount is taken care of this */
456 r600_delete_state(ctx, rstate);
457 }
458
459 static void r600_set_stencil_ref(struct pipe_context *ctx,
460 const struct pipe_stencil_ref *state)
461 {
462 struct r600_context *rctx = r600_context(ctx);
463 struct r600_context_state *rstate;
464
465 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
466 r600_bind_state(ctx, rstate);
467 /* refcount is taken care of this */
468 r600_delete_state(ctx, rstate);
469 }
470
471 static void r600_set_vertex_buffers(struct pipe_context *ctx,
472 unsigned count,
473 const struct pipe_vertex_buffer *buffers)
474 {
475 struct r600_context *rctx = r600_context(ctx);
476 unsigned i;
477
478 for (i = 0; i < rctx->nvertex_buffer; i++) {
479 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
480 }
481 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
482 for (i = 0; i < count; i++) {
483 rctx->vertex_buffer[i].buffer = NULL;
484 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
485 }
486 rctx->nvertex_buffer = count;
487 }
488
489 static void r600_set_index_buffer(struct pipe_context *ctx,
490 const struct pipe_index_buffer *ib)
491 {
492 struct r600_context *rctx = r600_context(ctx);
493
494 if (ib) {
495 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
496 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
497 } else {
498 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
499 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
500 }
501
502 /* TODO make this more like a state */
503 }
504
505 static void r600_set_viewport_state(struct pipe_context *ctx,
506 const struct pipe_viewport_state *state)
507 {
508 struct r600_context *rctx = r600_context(ctx);
509 struct r600_context_state *rstate;
510
511 rstate = r600_context_state(rctx, pipe_viewport_type, state);
512 r600_bind_state(ctx, rstate);
513 r600_delete_state(ctx, rstate);
514 }
515
516 void r600_init_state_functions(struct r600_context *rctx)
517 {
518 rctx->context.create_blend_state = r600_create_blend_state;
519 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
520 rctx->context.create_fs_state = r600_create_shader_state;
521 rctx->context.create_rasterizer_state = r600_create_rs_state;
522 rctx->context.create_sampler_state = r600_create_sampler_state;
523 rctx->context.create_sampler_view = r600_create_sampler_view;
524 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
525 rctx->context.create_vs_state = r600_create_shader_state;
526 rctx->context.bind_blend_state = r600_bind_state;
527 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
528 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
529 rctx->context.bind_fs_state = r600_bind_ps_shader;
530 rctx->context.bind_rasterizer_state = r600_bind_state;
531 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
532 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
533 rctx->context.bind_vs_state = r600_bind_vs_shader;
534 rctx->context.delete_blend_state = r600_delete_state;
535 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
536 rctx->context.delete_fs_state = r600_delete_state;
537 rctx->context.delete_rasterizer_state = r600_delete_state;
538 rctx->context.delete_sampler_state = r600_delete_state;
539 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
540 rctx->context.delete_vs_state = r600_delete_state;
541 rctx->context.set_blend_color = r600_set_blend_color;
542 rctx->context.set_clip_state = r600_set_clip_state;
543 rctx->context.set_constant_buffer = r600_set_constant_buffer;
544 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
545 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
546 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
547 rctx->context.set_sample_mask = r600_set_sample_mask;
548 rctx->context.set_scissor_state = r600_set_scissor_state;
549 rctx->context.set_stencil_ref = r600_set_stencil_ref;
550 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
551 rctx->context.set_index_buffer = r600_set_index_buffer;
552 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
553 rctx->context.set_viewport_state = r600_set_viewport_state;
554 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
555 }
556
557 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
558 {
559 if (rstate == NULL)
560 return NULL;
561 rstate->refcount++;
562 return rstate;
563 }
564
565 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
566 {
567 unsigned i;
568
569 if (rstate == NULL)
570 return NULL;
571 if (--rstate->refcount)
572 return NULL;
573 switch (rstate->type) {
574 case pipe_sampler_view_type:
575 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
576 break;
577 case pipe_framebuffer_type:
578 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
579 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
580 }
581 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
582 break;
583 case pipe_viewport_type:
584 case pipe_depth_type:
585 case pipe_rasterizer_type:
586 case pipe_poly_stipple_type:
587 case pipe_scissor_type:
588 case pipe_clip_type:
589 case pipe_stencil_type:
590 case pipe_alpha_type:
591 case pipe_dsa_type:
592 case pipe_blend_type:
593 case pipe_stencil_ref_type:
594 case pipe_shader_type:
595 case pipe_sampler_type:
596 break;
597 default:
598 R600_ERR("invalid type %d\n", rstate->type);
599 return NULL;
600 }
601 radeon_state_fini(&rstate->rstate[0]);
602 FREE(rstate);
603 return NULL;
604 }
605
606 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
607 {
608 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
609 const union pipe_states *states = state;
610 unsigned i;
611 int r;
612
613 if (rstate == NULL)
614 return NULL;
615 rstate->type = type;
616 rstate->refcount = 1;
617
618 switch (rstate->type) {
619 case pipe_sampler_view_type:
620 rstate->state.sampler_view = (*states).sampler_view;
621 rstate->state.sampler_view.texture = NULL;
622 break;
623 case pipe_framebuffer_type:
624 rstate->state.framebuffer = (*states).framebuffer;
625 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
626 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
627 (*states).framebuffer.cbufs[i]);
628 }
629 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
630 (*states).framebuffer.zsbuf);
631 break;
632 case pipe_viewport_type:
633 rstate->state.viewport = (*states).viewport;
634 r600_viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
635 break;
636 case pipe_depth_type:
637 rstate->state.depth = (*states).depth;
638 break;
639 case pipe_rasterizer_type:
640 rstate->state.rasterizer = (*states).rasterizer;
641 break;
642 case pipe_poly_stipple_type:
643 rstate->state.poly_stipple = (*states).poly_stipple;
644 break;
645 case pipe_scissor_type:
646 rstate->state.scissor = (*states).scissor;
647 break;
648 case pipe_clip_type:
649 rstate->state.clip = (*states).clip;
650 r600_ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
651 break;
652 case pipe_stencil_type:
653 rstate->state.stencil = (*states).stencil;
654 break;
655 case pipe_alpha_type:
656 rstate->state.alpha = (*states).alpha;
657 break;
658 case pipe_dsa_type:
659 rstate->state.dsa = (*states).dsa;
660 break;
661 case pipe_blend_type:
662 rstate->state.blend = (*states).blend;
663 r600_blend(rctx, &rstate->rstate[0], &rstate->state.blend);
664 break;
665 case pipe_stencil_ref_type:
666 rstate->state.stencil_ref = (*states).stencil_ref;
667 break;
668 case pipe_shader_type:
669 rstate->state.shader = (*states).shader;
670 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
671 if (r) {
672 r600_context_state_decref(rstate);
673 return NULL;
674 }
675 break;
676 case pipe_sampler_type:
677 rstate->state.sampler = (*states).sampler;
678 r600_sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
679 break;
680 default:
681 R600_ERR("invalid type %d\n", rstate->type);
682 FREE(rstate);
683 return NULL;
684 }
685 return rstate;
686 }
687
688 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
689 {
690 struct r600_screen *rscreen = rctx->screen;
691 int i;
692
693 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
694 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
695 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
696 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
697 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
698 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
699 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
700 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
701 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
702 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
703 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
704 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
705 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
706 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
707
708 for (i = 0; i < 8; i++) {
709 unsigned eqRGB = state->rt[i].rgb_func;
710 unsigned srcRGB = state->rt[i].rgb_src_factor;
711 unsigned dstRGB = state->rt[i].rgb_dst_factor;
712
713 unsigned eqA = state->rt[i].alpha_func;
714 unsigned srcA = state->rt[i].alpha_src_factor;
715 unsigned dstA = state->rt[i].alpha_dst_factor;
716 uint32_t bc = 0;
717
718 if (!state->rt[i].blend_enable)
719 continue;
720
721 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
722 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
723 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
724
725 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
726 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
727 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
728 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
729 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
730 }
731
732 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
733 if (i == 0)
734 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
735 }
736
737 radeon_state_pm4(rstate);
738 }
739
740 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
741 const struct pipe_clip_state *state)
742 {
743 struct r600_screen *rscreen = rctx->screen;
744
745 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
746
747 for (int i = 0; i < state->nr; i++) {
748 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
749 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
750 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
751 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
752 }
753 radeon_state_pm4(rstate);
754 }
755
756 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
757 const struct pipe_framebuffer_state *state, int cb)
758 {
759 struct r600_screen *rscreen = rctx->screen;
760 struct r600_resource_texture *rtex;
761 struct r600_resource *rbuffer;
762 unsigned level = state->cbufs[cb]->level;
763 unsigned pitch, slice;
764 unsigned color_info;
765 unsigned format, swap, ntype;
766 const struct util_format_description *desc;
767
768 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
769 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
770 rbuffer = &rtex->resource;
771 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
772 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
773 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
774 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
775 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
776 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
777 rstate->nbo = 3;
778 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
779 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
780
781 ntype = 0;
782 desc = util_format_description(rtex->resource.base.b.format);
783 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
784 ntype = V_0280A0_NUMBER_SRGB;
785
786 format = r600_translate_colorformat(rtex->resource.base.b.format);
787 swap = r600_translate_colorswap(rtex->resource.base.b.format);
788
789 color_info = S_0280A0_FORMAT(format) |
790 S_0280A0_COMP_SWAP(swap) |
791 S_0280A0_BLEND_CLAMP(1) |
792 S_0280A0_SOURCE_FORMAT(1) |
793 S_0280A0_NUMBER_TYPE(ntype);
794
795 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
796 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
797 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
798 S_028060_SLICE_TILE_MAX(slice);
799 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
800 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
801 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
802 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
803 radeon_state_pm4(rstate);
804 }
805
806 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
807 const struct pipe_framebuffer_state *state)
808 {
809 struct r600_screen *rscreen = rctx->screen;
810 struct r600_resource_texture *rtex;
811 struct r600_resource *rbuffer;
812 unsigned level;
813 unsigned pitch, slice, format;
814
815 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
816 if (state->zsbuf == NULL)
817 return;
818
819 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
820 rtex->tilled = 1;
821 rtex->array_mode = 2;
822 rtex->tile_type = 1;
823 rtex->depth = 1;
824 rbuffer = &rtex->resource;
825
826 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
827 rstate->nbo = 1;
828 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
829 level = state->zsbuf->level;
830 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
831 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
832 format = r600_translate_dbformat(state->zsbuf->texture->format);
833 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
834 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
835 S_028010_FORMAT(format);
836 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
837 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
838 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
839 S_028000_SLICE_TILE_MAX(slice);
840 radeon_state_pm4(rstate);
841 }
842
843 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
844 {
845 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
846 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
847 const struct pipe_clip_state *clip = NULL;
848 struct r600_screen *rscreen = rctx->screen;
849 float offset_units = 0, offset_scale = 0;
850 char depth = 0;
851 unsigned offset_db_fmt_cntl = 0;
852 unsigned tmp;
853 unsigned prov_vtx = 1;
854
855 if (rctx->clip)
856 clip = &rctx->clip->state.clip;
857 if (fb->zsbuf) {
858 offset_units = state->offset_units;
859 offset_scale = state->offset_scale * 12.0f;
860 switch (fb->zsbuf->texture->format) {
861 case PIPE_FORMAT_Z24X8_UNORM:
862 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
863 depth = -24;
864 offset_units *= 2.0f;
865 break;
866 case PIPE_FORMAT_Z32_FLOAT:
867 depth = -23;
868 offset_units *= 1.0f;
869 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
870 break;
871 case PIPE_FORMAT_Z16_UNORM:
872 depth = -16;
873 offset_units *= 4.0f;
874 break;
875 default:
876 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
877 return;
878 }
879 }
880 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
881
882 if (state->flatshade_first)
883 prov_vtx = 0;
884
885 rctx->flat_shade = state->flatshade;
886 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
887 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
888 if (state->sprite_coord_enable) {
889 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
890 S_0286D4_PNT_SPRITE_ENA(1) |
891 S_0286D4_PNT_SPRITE_OVRD_X(2) |
892 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
893 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
894 S_0286D4_PNT_SPRITE_OVRD_W(1);
895 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
896 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
897 S_0286D4_PNT_SPRITE_TOP_1(1);
898 }
899 }
900 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
901 if (clip) {
902 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
903 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
904 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
905 }
906 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
907 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
908 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
909 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
910 S_028814_FACE(!state->front_ccw) |
911 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
912 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
913 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
914 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
915 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
916 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
917 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
918 /* point size 12.4 fixed point */
919 tmp = (unsigned)(state->point_size * 8.0);
920 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
921 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
922 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
923 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
924 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
925 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
926 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
927 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
928 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
929 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
930 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
931 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
932 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
933 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
934 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
935 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
936 radeon_state_pm4(rstate);
937 }
938
939 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
940 {
941 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
942 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
943 struct r600_screen *rscreen = rctx->screen;
944 unsigned minx, maxx, miny, maxy;
945 u32 tl, br;
946
947 if (state == NULL) {
948 minx = 0;
949 miny = 0;
950 maxx = fb->cbufs[0]->width;
951 maxy = fb->cbufs[0]->height;
952 } else {
953 minx = state->minx;
954 miny = state->miny;
955 maxx = state->maxx;
956 maxy = state->maxy;
957 }
958 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
959 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
960 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
961 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
962 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
963 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
964 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
965 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
966 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
967 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
968 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
969 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
970 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
971 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
972 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
973 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
974 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
975 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
976 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
977 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
978 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
979 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
980 radeon_state_pm4(rstate);
981 }
982
983 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
984 {
985 struct r600_screen *rscreen = rctx->screen;
986
987 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
988 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
989 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
990 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
991 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
992 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
993 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
994 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
995 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
996 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
997 radeon_state_pm4(rstate);
998 }
999
1000 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
1001 {
1002 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
1003 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
1004 struct r600_screen *rscreen = rctx->screen;
1005 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
1006 unsigned stencil_ref_mask, stencil_ref_mask_bf;
1007 struct r600_shader *rshader;
1008 int i;
1009
1010 if (rctx->ps_shader == NULL) {
1011 return;
1012 }
1013 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
1014
1015 db_shader_control = 0x210;
1016 rshader = &rctx->ps_shader->shader;
1017 if (rshader->uses_kill)
1018 db_shader_control |= (1 << 6);
1019 for (i = 0; i < rshader->noutput; i++) {
1020 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1021 db_shader_control |= 1;
1022 }
1023 stencil_ref_mask = 0;
1024 stencil_ref_mask_bf = 0;
1025 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1026 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1027 S_028800_ZFUNC(state->depth.func);
1028 /* set stencil enable */
1029
1030 if (state->stencil[0].enabled) {
1031 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1032 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
1033 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
1034 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
1035 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1036
1037 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1038 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1039 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
1040 if (state->stencil[1].enabled) {
1041 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1042 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1043 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1044 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1045 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1046 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1047 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1048 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
1049 }
1050 }
1051
1052 alpha_test_control = 0;
1053 alpha_ref = 0;
1054 if (state->alpha.enabled) {
1055 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1056 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1057 alpha_ref = fui(state->alpha.ref_value);
1058 }
1059
1060 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1061 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1062 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1063 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1064 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1065 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1066 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1067 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1068 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1069 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1070 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1071 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
1072 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
1073 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1074 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1075 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1076 radeon_state_pm4(rstate);
1077 }
1078
1079 static inline unsigned r600_tex_wrap(unsigned wrap)
1080 {
1081 switch (wrap) {
1082 default:
1083 case PIPE_TEX_WRAP_REPEAT:
1084 return V_03C000_SQ_TEX_WRAP;
1085 case PIPE_TEX_WRAP_CLAMP:
1086 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1087 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1088 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1089 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1090 return V_03C000_SQ_TEX_CLAMP_BORDER;
1091 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1092 return V_03C000_SQ_TEX_MIRROR;
1093 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1094 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1095 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1096 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1097 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1098 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1099 }
1100 }
1101
1102 static inline unsigned r600_tex_filter(unsigned filter)
1103 {
1104 switch (filter) {
1105 default:
1106 case PIPE_TEX_FILTER_NEAREST:
1107 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1108 case PIPE_TEX_FILTER_LINEAR:
1109 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1110 }
1111 }
1112
1113 static inline unsigned r600_tex_mipfilter(unsigned filter)
1114 {
1115 switch (filter) {
1116 case PIPE_TEX_MIPFILTER_NEAREST:
1117 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1118 case PIPE_TEX_MIPFILTER_LINEAR:
1119 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1120 default:
1121 case PIPE_TEX_MIPFILTER_NONE:
1122 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1123 }
1124 }
1125
1126 static inline unsigned r600_tex_compare(unsigned compare)
1127 {
1128 switch (compare) {
1129 default:
1130 case PIPE_FUNC_NEVER:
1131 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1132 case PIPE_FUNC_LESS:
1133 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1134 case PIPE_FUNC_EQUAL:
1135 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1136 case PIPE_FUNC_LEQUAL:
1137 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1138 case PIPE_FUNC_GREATER:
1139 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1140 case PIPE_FUNC_NOTEQUAL:
1141 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1142 case PIPE_FUNC_GEQUAL:
1143 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1144 case PIPE_FUNC_ALWAYS:
1145 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1146 }
1147 }
1148
1149 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1150 {
1151 return value * (1 << frac_bits);
1152 }
1153
1154 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
1155 const struct pipe_sampler_state *state, unsigned id)
1156 {
1157 struct r600_screen *rscreen = rctx->screen;
1158
1159 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
1160 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1161 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1162 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1163 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1164 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1165 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1166 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1167 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1168 /* FIXME LOD it depends on texture base level ... */
1169 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1170 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1171 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1172 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1173 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1174 radeon_state_pm4(rstate);
1175 }
1176
1177 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1178 {
1179 switch (swizzle) {
1180 case PIPE_SWIZZLE_RED:
1181 return V_038010_SQ_SEL_X;
1182 case PIPE_SWIZZLE_GREEN:
1183 return V_038010_SQ_SEL_Y;
1184 case PIPE_SWIZZLE_BLUE:
1185 return V_038010_SQ_SEL_Z;
1186 case PIPE_SWIZZLE_ALPHA:
1187 return V_038010_SQ_SEL_W;
1188 case PIPE_SWIZZLE_ZERO:
1189 return V_038010_SQ_SEL_0;
1190 default:
1191 case PIPE_SWIZZLE_ONE:
1192 return V_038010_SQ_SEL_1;
1193 }
1194 }
1195
1196 static inline unsigned r600_format_type(unsigned format_type)
1197 {
1198 switch (format_type) {
1199 default:
1200 case UTIL_FORMAT_TYPE_UNSIGNED:
1201 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1202 case UTIL_FORMAT_TYPE_SIGNED:
1203 return V_038010_SQ_FORMAT_COMP_SIGNED;
1204 case UTIL_FORMAT_TYPE_FIXED:
1205 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1206 }
1207 }
1208
1209 static inline unsigned r600_tex_dim(unsigned dim)
1210 {
1211 switch (dim) {
1212 default:
1213 case PIPE_TEXTURE_1D:
1214 return V_038000_SQ_TEX_DIM_1D;
1215 case PIPE_TEXTURE_2D:
1216 case PIPE_TEXTURE_RECT:
1217 return V_038000_SQ_TEX_DIM_2D;
1218 case PIPE_TEXTURE_3D:
1219 return V_038000_SQ_TEX_DIM_3D;
1220 case PIPE_TEXTURE_CUBE:
1221 return V_038000_SQ_TEX_DIM_CUBEMAP;
1222 }
1223 }
1224
1225 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
1226 const struct pipe_sampler_view *view, unsigned id)
1227 {
1228 struct r600_context *rctx = r600_context(ctx);
1229 struct r600_screen *rscreen = rctx->screen;
1230 const struct util_format_description *desc;
1231 struct r600_resource_texture *tmp;
1232 struct r600_resource *rbuffer;
1233 unsigned format;
1234 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1235 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1236 int r;
1237
1238 rstate->cpm4 = 0;
1239 swizzle[0] = view->swizzle_r;
1240 swizzle[1] = view->swizzle_g;
1241 swizzle[2] = view->swizzle_b;
1242 swizzle[3] = view->swizzle_a;
1243 format = r600_translate_texformat(view->texture->format,
1244 swizzle,
1245 &word4, &yuv_format);
1246 if (format == ~0) {
1247 return;
1248 }
1249 desc = util_format_description(view->texture->format);
1250 if (desc == NULL) {
1251 R600_ERR("unknow format %d\n", view->texture->format);
1252 return;
1253 }
1254 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
1255 tmp = (struct r600_resource_texture*)view->texture;
1256 rbuffer = &tmp->resource;
1257 if (tmp->depth) {
1258 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1259 if (r) {
1260 return;
1261 }
1262 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1263 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1264 } else {
1265 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1266 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1267 }
1268 rstate->nbo = 2;
1269 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1270 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1271 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1272 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1273
1274 pitch = (tmp->pitch[0] / tmp->bpt);
1275 pitch = (pitch + 0x7) & ~0x7;
1276
1277 /* FIXME properly handle first level != 0 */
1278 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1279 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1280 S_038000_TILE_MODE(array_mode) |
1281 S_038000_TILE_TYPE(tile_type) |
1282 S_038000_PITCH((pitch / 8) - 1) |
1283 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1284 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1285 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1286 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1287 S_038004_DATA_FORMAT(format);
1288 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1289 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1290 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1291 word4 |
1292 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1293 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1294 S_038010_REQUEST_SIZE(1) |
1295 S_038010_BASE_LEVEL(view->first_level);
1296 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1297 S_038014_LAST_LEVEL(view->last_level) |
1298 S_038014_BASE_ARRAY(0) |
1299 S_038014_LAST_ARRAY(0);
1300 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1301 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1302 radeon_state_pm4(rstate);
1303 }
1304
1305 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
1306 {
1307 struct r600_screen *rscreen = rctx->screen;
1308 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1309 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1310 uint32_t color_control, target_mask, shader_mask;
1311 int i;
1312
1313 target_mask = 0;
1314 shader_mask = 0;
1315 color_control = S_028808_PER_MRT_BLEND(1);
1316
1317 for (i = 0; i < nr_cbufs; i++) {
1318 shader_mask |= 0xf << (i * 4);
1319 }
1320
1321 if (pbs->logicop_enable) {
1322 color_control |= (pbs->logicop_func) << 16;
1323 } else {
1324 color_control |= (0xcc << 16);
1325 }
1326
1327 if (pbs->independent_blend_enable) {
1328 for (i = 0; i < nr_cbufs; i++) {
1329 if (pbs->rt[i].blend_enable) {
1330 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1331 }
1332 target_mask |= (pbs->rt[i].colormask << (4 * i));
1333 }
1334 } else {
1335 for (i = 0; i < nr_cbufs; i++) {
1336 if (pbs->rt[0].blend_enable) {
1337 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1338 }
1339 target_mask |= (pbs->rt[0].colormask << (4 * i));
1340 }
1341 }
1342 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
1343 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1344 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1345 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1346 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1347 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1348 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1349 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1350 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1351 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1352 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1353 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1354 radeon_state_pm4(rstate);
1355 }
1356
1357 int r600_context_hw_states(struct pipe_context *ctx)
1358 {
1359 struct r600_context *rctx = r600_context(ctx);
1360 unsigned i;
1361
1362 /* build new states */
1363 r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
1364 r600_scissor(rctx, &rctx->hw_states.scissor);
1365 r600_dsa(rctx, &rctx->hw_states.dsa);
1366 r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
1367
1368 /* bind states */
1369 radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
1370 radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
1371 radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
1372 radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
1373
1374 radeon_draw_bind(&rctx->draw, &rctx->config);
1375
1376 if (rctx->viewport) {
1377 radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
1378 }
1379 if (rctx->blend) {
1380 radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
1381 }
1382 if (rctx->clip) {
1383 radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
1384 }
1385 for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
1386 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
1387 }
1388 if (rctx->framebuffer->state.framebuffer.zsbuf) {
1389 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
1390 }
1391 for (i = 0; i < rctx->ps_nsampler; i++) {
1392 if (rctx->ps_sampler[i]) {
1393 radeon_draw_bind(&rctx->draw, rctx->ps_sampler[i]);
1394 }
1395 }
1396 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1397 if (rctx->ps_sampler_view[i]) {
1398 radeon_draw_bind(&rctx->draw, rctx->ps_sampler_view[i]);
1399 }
1400 }
1401 return 0;
1402 }