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r600g: kill r600_context_state function
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
38 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
39 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
40 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
41 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
42 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
43 const struct pipe_framebuffer_state *state, int cb);
44 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
45 const struct pipe_framebuffer_state *state);
46
47 static struct r600_context_state *r600_new_context_state(unsigned type)
48 {
49 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
50 if (rstate == NULL)
51 return NULL;
52 rstate->type = type;
53 rstate->refcount = 1;
54 return rstate;
55 }
56
57 static void *r600_create_blend_state(struct pipe_context *ctx,
58 const struct pipe_blend_state *state)
59 {
60 struct r600_context *rctx = r600_context(ctx);
61 struct r600_context_state *rstate;
62
63 rstate = r600_new_context_state(pipe_blend_type);
64 rstate->state.blend = *state;
65 r600_blend(rctx, &rstate->rstate[0], &rstate->state.blend);
66
67 return rstate;
68 }
69
70 static void *r600_create_dsa_state(struct pipe_context *ctx,
71 const struct pipe_depth_stencil_alpha_state *state)
72 {
73 struct r600_context *rctx = r600_context(ctx);
74 struct r600_context_state *rstate;
75
76 rstate = r600_new_context_state(pipe_dsa_type);
77 rstate->state.dsa = *state;
78 return rstate;
79 }
80
81 static void *r600_create_rs_state(struct pipe_context *ctx,
82 const struct pipe_rasterizer_state *state)
83 {
84 struct r600_context *rctx = r600_context(ctx);
85 struct r600_context_state *rstate;
86
87 rstate = r600_new_context_state(pipe_rasterizer_type);
88 rstate->state.rasterizer = *state;
89 return rstate;
90 }
91
92 static void *r600_create_sampler_state(struct pipe_context *ctx,
93 const struct pipe_sampler_state *state)
94 {
95 struct r600_context *rctx = r600_context(ctx);
96 struct r600_context_state *rstate;
97
98 rstate = r600_new_context_state(pipe_sampler_type);
99 rstate->state.sampler = *state;
100 r600_sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
101 return rstate;
102 }
103
104 static void r600_sampler_view_destroy(struct pipe_context *ctx,
105 struct pipe_sampler_view *state)
106 {
107 struct r600_context_state *rstate = (struct r600_context_state *)state;
108
109 r600_context_state_decref(rstate);
110 }
111
112 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
113 struct pipe_resource *texture,
114 const struct pipe_sampler_view *state)
115 {
116 struct r600_context *rctx = r600_context(ctx);
117 struct r600_context_state *rstate;
118
119 rstate = r600_new_context_state(pipe_sampler_view_type);
120 rstate->state.sampler_view = *state;
121 rstate->state.sampler_view.texture = NULL;
122 pipe_reference(NULL, &texture->reference);
123 rstate->state.sampler_view.texture = texture;
124 rstate->state.sampler_view.reference.count = 1;
125 rstate->state.sampler_view.context = ctx;
126 r600_resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
127 return &rstate->state.sampler_view;
128 }
129
130 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
131 unsigned count,
132 struct pipe_sampler_view **views)
133 {
134 struct r600_context *rctx = r600_context(ctx);
135 struct r600_context_state *rstate;
136 unsigned i;
137
138 for (i = 0; i < rctx->ps_nsampler_view; i++) {
139 radeon_draw_unbind(&rctx->draw, rctx->ps_sampler_view[i]);
140 }
141 for (i = 0; i < count; i++) {
142 rstate = (struct r600_context_state *)views[i];
143 if (rstate) {
144 rstate->nrstate = 0;
145 }
146 }
147 for (i = 0; i < count; i++) {
148 rstate = (struct r600_context_state *)views[i];
149 if (rstate) {
150 if (rstate->nrstate >= R600_MAX_RSTATE)
151 continue;
152 if (rstate->nrstate) {
153 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
154 }
155 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_PS);
156 rctx->ps_sampler_view[i] = &rstate->rstate[rstate->nrstate];
157 rstate->nrstate++;
158 }
159 }
160 rctx->ps_nsampler_view = count;
161 }
162
163 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
164 unsigned count,
165 struct pipe_sampler_view **views)
166 {
167 struct r600_context *rctx = r600_context(ctx);
168 struct r600_context_state *rstate;
169 unsigned i;
170
171 for (i = 0; i < rctx->vs_nsampler_view; i++) {
172 radeon_draw_unbind(&rctx->draw, rctx->vs_sampler_view[i]);
173 }
174 for (i = 0; i < count; i++) {
175 rstate = (struct r600_context_state *)views[i];
176 if (rstate) {
177 rstate->nrstate = 0;
178 }
179 }
180 for (i = 0; i < count; i++) {
181 rstate = (struct r600_context_state *)views[i];
182 if (rstate) {
183 if (rstate->nrstate >= R600_MAX_RSTATE)
184 continue;
185 if (rstate->nrstate) {
186 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
187 }
188 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_VS);
189 rctx->vs_sampler_view[i] = &rstate->rstate[rstate->nrstate];
190 rstate->nrstate++;
191 }
192 }
193 rctx->vs_nsampler_view = count;
194 }
195
196 static void *r600_create_shader_state(struct pipe_context *ctx,
197 const struct pipe_shader_state *state)
198 {
199 struct r600_context *rctx = r600_context(ctx);
200 struct r600_context_state *rstate;
201 int r;
202
203 rstate = r600_new_context_state(pipe_shader_type);
204 rstate->state.shader = *state;
205 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
206 if (r) {
207 r600_context_state_decref(rstate);
208 return NULL;
209 }
210 return rstate;
211 }
212
213 static void *r600_create_vertex_elements(struct pipe_context *ctx,
214 unsigned count,
215 const struct pipe_vertex_element *elements)
216 {
217 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
218
219 assert(count < 32);
220 v->count = count;
221 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
222 v->refcount = 1;
223 return v;
224 }
225
226 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
227 {
228 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
229
230 if (v == NULL)
231 return;
232 if (--v->refcount)
233 return;
234 free(v);
235 }
236
237 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
238 {
239 struct r600_context *rctx = r600_context(ctx);
240 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
241
242 r600_delete_vertex_element(ctx, rctx->vertex_elements);
243 rctx->vertex_elements = v;
244 if (v) {
245 v->refcount++;
246 }
247 }
248
249 static void r600_bind_state(struct pipe_context *ctx, void *state)
250 {
251 struct r600_context *rctx = r600_context(ctx);
252 struct r600_context_state *rstate = (struct r600_context_state *)state;
253
254 if (state == NULL)
255 return;
256 switch (rstate->type) {
257 case pipe_rasterizer_type:
258 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
259 rctx->rasterizer = r600_context_state_incref(rstate);
260 break;
261 case pipe_poly_stipple_type:
262 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
263 rctx->poly_stipple = r600_context_state_incref(rstate);
264 break;
265 case pipe_scissor_type:
266 rctx->scissor = r600_context_state_decref(rctx->scissor);
267 rctx->scissor = r600_context_state_incref(rstate);
268 break;
269 case pipe_clip_type:
270 rctx->clip = r600_context_state_decref(rctx->clip);
271 rctx->clip = r600_context_state_incref(rstate);
272 break;
273 case pipe_depth_type:
274 rctx->depth = r600_context_state_decref(rctx->depth);
275 rctx->depth = r600_context_state_incref(rstate);
276 break;
277 case pipe_stencil_type:
278 rctx->stencil = r600_context_state_decref(rctx->stencil);
279 rctx->stencil = r600_context_state_incref(rstate);
280 break;
281 case pipe_alpha_type:
282 rctx->alpha = r600_context_state_decref(rctx->alpha);
283 rctx->alpha = r600_context_state_incref(rstate);
284 break;
285 case pipe_dsa_type:
286 rctx->dsa = r600_context_state_decref(rctx->dsa);
287 rctx->dsa = r600_context_state_incref(rstate);
288 break;
289 case pipe_blend_type:
290 rctx->blend = r600_context_state_decref(rctx->blend);
291 rctx->blend = r600_context_state_incref(rstate);
292 break;
293 case pipe_framebuffer_type:
294 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
295 rctx->framebuffer = r600_context_state_incref(rstate);
296 break;
297 case pipe_stencil_ref_type:
298 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
299 rctx->stencil_ref = r600_context_state_incref(rstate);
300 break;
301 case pipe_viewport_type:
302 rctx->viewport = r600_context_state_decref(rctx->viewport);
303 rctx->viewport = r600_context_state_incref(rstate);
304 break;
305 case pipe_shader_type:
306 case pipe_sampler_type:
307 case pipe_sampler_view_type:
308 default:
309 R600_ERR("invalid type %d\n", rstate->type);
310 return;
311 }
312 }
313
314 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
315 {
316 struct r600_context *rctx = r600_context(ctx);
317 struct r600_context_state *rstate = (struct r600_context_state *)state;
318
319 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
320 rctx->ps_shader = r600_context_state_incref(rstate);
321 }
322
323 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
324 {
325 struct r600_context *rctx = r600_context(ctx);
326 struct r600_context_state *rstate = (struct r600_context_state *)state;
327
328 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
329 rctx->vs_shader = r600_context_state_incref(rstate);
330 }
331
332 static void r600_bind_ps_sampler(struct pipe_context *ctx,
333 unsigned count, void **states)
334 {
335 struct r600_context *rctx = r600_context(ctx);
336 struct r600_context_state *rstate;
337 unsigned i;
338
339 for (i = 0; i < rctx->ps_nsampler; i++) {
340 radeon_draw_unbind(&rctx->draw, rctx->ps_sampler[i]);
341 }
342 for (i = 0; i < count; i++) {
343 rstate = (struct r600_context_state *)states[i];
344 if (rstate) {
345 rstate->nrstate = 0;
346 }
347 }
348 for (i = 0; i < count; i++) {
349 rstate = (struct r600_context_state *)states[i];
350 if (rstate) {
351 if (rstate->nrstate >= R600_MAX_RSTATE)
352 continue;
353 if (rstate->nrstate) {
354 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
355 }
356 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_PS);
357 rctx->ps_sampler[i] = &rstate->rstate[rstate->nrstate];
358 rstate->nrstate++;
359 }
360 }
361 rctx->ps_nsampler = count;
362 }
363
364 static void r600_bind_vs_sampler(struct pipe_context *ctx,
365 unsigned count, void **states)
366 {
367 struct r600_context *rctx = r600_context(ctx);
368 struct r600_context_state *rstate;
369 unsigned i;
370
371 for (i = 0; i < rctx->vs_nsampler; i++) {
372 radeon_draw_unbind(&rctx->draw, rctx->vs_sampler[i]);
373 }
374 for (i = 0; i < count; i++) {
375 rstate = (struct r600_context_state *)states[i];
376 if (rstate) {
377 rstate->nrstate = 0;
378 }
379 }
380 for (i = 0; i < count; i++) {
381 rstate = (struct r600_context_state *)states[i];
382 if (rstate) {
383 if (rstate->nrstate >= R600_MAX_RSTATE)
384 continue;
385 if (rstate->nrstate) {
386 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
387 }
388 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_VS);
389 rctx->vs_sampler[i] = &rstate->rstate[rstate->nrstate];
390 rstate->nrstate++;
391 }
392 }
393 rctx->vs_nsampler = count;
394 }
395
396 static void r600_delete_state(struct pipe_context *ctx, void *state)
397 {
398 struct r600_context_state *rstate = (struct r600_context_state *)state;
399
400 r600_context_state_decref(rstate);
401 }
402
403 static void r600_set_blend_color(struct pipe_context *ctx,
404 const struct pipe_blend_color *color)
405 {
406 struct r600_context *rctx = r600_context(ctx);
407
408 rctx->blend_color = *color;
409 }
410
411 static void r600_set_clip_state(struct pipe_context *ctx,
412 const struct pipe_clip_state *state)
413 {
414 struct r600_context *rctx = r600_context(ctx);
415 struct r600_context_state *rstate;
416
417 rstate = r600_new_context_state(pipe_clip_type);
418 rstate->state.clip = *state;
419 r600_ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
420 r600_bind_state(ctx, rstate);
421 /* refcount is taken care of this */
422 r600_delete_state(ctx, rstate);
423 }
424
425 static void r600_set_constant_buffer(struct pipe_context *ctx,
426 uint shader, uint index,
427 struct pipe_resource *buffer)
428 {
429 struct r600_screen *rscreen = r600_screen(ctx->screen);
430 struct r600_context *rctx = r600_context(ctx);
431 unsigned nconstant = 0, i, type, shader_class;
432 struct radeon_state *rstate, *rstates;
433 struct pipe_transfer *transfer;
434 u32 *ptr;
435
436 type = R600_STATE_CONSTANT;
437
438 switch (shader) {
439 case PIPE_SHADER_VERTEX:
440 shader_class = R600_SHADER_VS;
441 rstates = rctx->vs_constant;
442 break;
443 case PIPE_SHADER_FRAGMENT:
444 shader_class = R600_SHADER_PS;
445 rstates = rctx->ps_constant;
446 break;
447 default:
448 R600_ERR("unsupported %d\n", shader);
449 return;
450 }
451 if (buffer && buffer->width0 > 0) {
452 nconstant = buffer->width0 / 16;
453 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
454 if (ptr == NULL)
455 return;
456 for (i = 0; i < nconstant; i++) {
457 rstate = &rstates[i];
458 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
459 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
460 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
461 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
462 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
463 if (radeon_state_pm4(rstate))
464 return;
465 radeon_draw_bind(&rctx->draw, rstate);
466 }
467 pipe_buffer_unmap(ctx, buffer, transfer);
468 }
469 }
470
471 static void r600_set_framebuffer_state(struct pipe_context *ctx,
472 const struct pipe_framebuffer_state *state)
473 {
474 struct r600_context *rctx = r600_context(ctx);
475 struct r600_context_state *rstate;
476 int i;
477
478 rstate = r600_new_context_state(pipe_framebuffer_type);
479 rstate->state.framebuffer = *state;
480 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
481 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
482 state->cbufs[i]);
483 }
484 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
485 state->zsbuf);
486 r600_bind_state(ctx, rstate);
487 for (i = 0; i < state->nr_cbufs; i++) {
488 r600_cb(rctx, &rstate->rstate[i+1], state, i);
489 }
490 if (state->zsbuf) {
491 r600_db(rctx, &rstate->rstate[0], state);
492 }
493 return rstate;
494 }
495
496 static void r600_set_polygon_stipple(struct pipe_context *ctx,
497 const struct pipe_poly_stipple *state)
498 {
499 }
500
501 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
502 {
503 }
504
505 static void r600_set_scissor_state(struct pipe_context *ctx,
506 const struct pipe_scissor_state *state)
507 {
508 struct r600_context *rctx = r600_context(ctx);
509 struct r600_context_state *rstate;
510
511 rstate = r600_new_context_state(pipe_scissor_type);
512 rstate->state.scissor = *state;
513 r600_bind_state(ctx, rstate);
514 /* refcount is taken care of this */
515 r600_delete_state(ctx, rstate);
516 }
517
518 static void r600_set_stencil_ref(struct pipe_context *ctx,
519 const struct pipe_stencil_ref *state)
520 {
521 struct r600_context *rctx = r600_context(ctx);
522 struct r600_context_state *rstate;
523
524 rstate = r600_new_context_state(pipe_stencil_ref_type);
525 rstate->state.stencil_ref = *state;
526 r600_bind_state(ctx, rstate);
527 /* refcount is taken care of this */
528 r600_delete_state(ctx, rstate);
529 }
530
531 static void r600_set_vertex_buffers(struct pipe_context *ctx,
532 unsigned count,
533 const struct pipe_vertex_buffer *buffers)
534 {
535 struct r600_context *rctx = r600_context(ctx);
536 unsigned i;
537
538 for (i = 0; i < rctx->nvertex_buffer; i++) {
539 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
540 }
541 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
542 for (i = 0; i < count; i++) {
543 rctx->vertex_buffer[i].buffer = NULL;
544 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
545 }
546 rctx->nvertex_buffer = count;
547 }
548
549 static void r600_set_index_buffer(struct pipe_context *ctx,
550 const struct pipe_index_buffer *ib)
551 {
552 struct r600_context *rctx = r600_context(ctx);
553
554 if (ib) {
555 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
556 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
557 } else {
558 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
559 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
560 }
561
562 /* TODO make this more like a state */
563 }
564
565 static void r600_set_viewport_state(struct pipe_context *ctx,
566 const struct pipe_viewport_state *state)
567 {
568 struct r600_context *rctx = r600_context(ctx);
569 struct r600_context_state *rstate;
570
571 rstate = r600_new_context_state(pipe_viewport_type);
572 rstate->state.viewport = *state;
573 r600_viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
574 r600_bind_state(ctx, rstate);
575 r600_delete_state(ctx, rstate);
576 }
577
578 void r600_init_state_functions(struct r600_context *rctx)
579 {
580 rctx->context.create_blend_state = r600_create_blend_state;
581 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
582 rctx->context.create_fs_state = r600_create_shader_state;
583 rctx->context.create_rasterizer_state = r600_create_rs_state;
584 rctx->context.create_sampler_state = r600_create_sampler_state;
585 rctx->context.create_sampler_view = r600_create_sampler_view;
586 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
587 rctx->context.create_vs_state = r600_create_shader_state;
588 rctx->context.bind_blend_state = r600_bind_state;
589 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
590 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
591 rctx->context.bind_fs_state = r600_bind_ps_shader;
592 rctx->context.bind_rasterizer_state = r600_bind_state;
593 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
594 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
595 rctx->context.bind_vs_state = r600_bind_vs_shader;
596 rctx->context.delete_blend_state = r600_delete_state;
597 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
598 rctx->context.delete_fs_state = r600_delete_state;
599 rctx->context.delete_rasterizer_state = r600_delete_state;
600 rctx->context.delete_sampler_state = r600_delete_state;
601 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
602 rctx->context.delete_vs_state = r600_delete_state;
603 rctx->context.set_blend_color = r600_set_blend_color;
604 rctx->context.set_clip_state = r600_set_clip_state;
605 rctx->context.set_constant_buffer = r600_set_constant_buffer;
606 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
607 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
608 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
609 rctx->context.set_sample_mask = r600_set_sample_mask;
610 rctx->context.set_scissor_state = r600_set_scissor_state;
611 rctx->context.set_stencil_ref = r600_set_stencil_ref;
612 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
613 rctx->context.set_index_buffer = r600_set_index_buffer;
614 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
615 rctx->context.set_viewport_state = r600_set_viewport_state;
616 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
617 }
618
619 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
620 {
621 if (rstate == NULL)
622 return NULL;
623 rstate->refcount++;
624 return rstate;
625 }
626
627 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
628 {
629 unsigned i;
630
631 if (rstate == NULL)
632 return NULL;
633 if (--rstate->refcount)
634 return NULL;
635 switch (rstate->type) {
636 case pipe_sampler_view_type:
637 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
638 break;
639 case pipe_framebuffer_type:
640 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
641 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
642 }
643 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
644 break;
645 case pipe_viewport_type:
646 case pipe_depth_type:
647 case pipe_rasterizer_type:
648 case pipe_poly_stipple_type:
649 case pipe_scissor_type:
650 case pipe_clip_type:
651 case pipe_stencil_type:
652 case pipe_alpha_type:
653 case pipe_dsa_type:
654 case pipe_blend_type:
655 case pipe_stencil_ref_type:
656 case pipe_shader_type:
657 case pipe_sampler_type:
658 break;
659 default:
660 R600_ERR("invalid type %d\n", rstate->type);
661 return NULL;
662 }
663 radeon_state_fini(&rstate->rstate[0]);
664 FREE(rstate);
665 return NULL;
666 }
667
668 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
669 {
670 struct r600_screen *rscreen = rctx->screen;
671 int i;
672
673 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
674 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
675 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
676 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
677 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
678 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
679 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
680 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
681 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
682 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
683 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
684 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
685 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
686 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
687
688 for (i = 0; i < 8; i++) {
689 unsigned eqRGB = state->rt[i].rgb_func;
690 unsigned srcRGB = state->rt[i].rgb_src_factor;
691 unsigned dstRGB = state->rt[i].rgb_dst_factor;
692
693 unsigned eqA = state->rt[i].alpha_func;
694 unsigned srcA = state->rt[i].alpha_src_factor;
695 unsigned dstA = state->rt[i].alpha_dst_factor;
696 uint32_t bc = 0;
697
698 if (!state->rt[i].blend_enable)
699 continue;
700
701 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
702 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
703 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
704
705 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
706 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
707 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
708 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
709 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
710 }
711
712 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
713 if (i == 0)
714 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
715 }
716
717 radeon_state_pm4(rstate);
718 }
719
720 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
721 const struct pipe_clip_state *state)
722 {
723 struct r600_screen *rscreen = rctx->screen;
724
725 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
726
727 for (int i = 0; i < state->nr; i++) {
728 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
729 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
730 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
731 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
732 }
733 radeon_state_pm4(rstate);
734 }
735
736 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
737 const struct pipe_framebuffer_state *state, int cb)
738 {
739 struct r600_screen *rscreen = rctx->screen;
740 struct r600_resource_texture *rtex;
741 struct r600_resource *rbuffer;
742 unsigned level = state->cbufs[cb]->level;
743 unsigned pitch, slice;
744 unsigned color_info;
745 unsigned format, swap, ntype;
746 const struct util_format_description *desc;
747
748 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
749 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
750 rbuffer = &rtex->resource;
751 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
752 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
753 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
754 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
755 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
756 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
757 rstate->nbo = 3;
758 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
759 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
760
761 ntype = 0;
762 desc = util_format_description(rtex->resource.base.b.format);
763 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
764 ntype = V_0280A0_NUMBER_SRGB;
765
766 format = r600_translate_colorformat(rtex->resource.base.b.format);
767 swap = r600_translate_colorswap(rtex->resource.base.b.format);
768
769 color_info = S_0280A0_FORMAT(format) |
770 S_0280A0_COMP_SWAP(swap) |
771 S_0280A0_BLEND_CLAMP(1) |
772 S_0280A0_SOURCE_FORMAT(1) |
773 S_0280A0_NUMBER_TYPE(ntype);
774
775 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
776 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
777 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
778 S_028060_SLICE_TILE_MAX(slice);
779 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
780 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
781 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
782 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
783 radeon_state_pm4(rstate);
784 }
785
786 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
787 const struct pipe_framebuffer_state *state)
788 {
789 struct r600_screen *rscreen = rctx->screen;
790 struct r600_resource_texture *rtex;
791 struct r600_resource *rbuffer;
792 unsigned level;
793 unsigned pitch, slice, format;
794
795 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
796 if (state->zsbuf == NULL)
797 return;
798
799 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
800 rtex->tilled = 1;
801 rtex->array_mode = 2;
802 rtex->tile_type = 1;
803 rtex->depth = 1;
804 rbuffer = &rtex->resource;
805
806 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
807 rstate->nbo = 1;
808 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
809 level = state->zsbuf->level;
810 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
811 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
812 format = r600_translate_dbformat(state->zsbuf->texture->format);
813 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
814 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
815 S_028010_FORMAT(format);
816 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
817 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
818 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
819 S_028000_SLICE_TILE_MAX(slice);
820 radeon_state_pm4(rstate);
821 }
822
823 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
824 {
825 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
826 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
827 const struct pipe_clip_state *clip = NULL;
828 struct r600_screen *rscreen = rctx->screen;
829 float offset_units = 0, offset_scale = 0;
830 char depth = 0;
831 unsigned offset_db_fmt_cntl = 0;
832 unsigned tmp;
833 unsigned prov_vtx = 1;
834
835 if (rctx->clip)
836 clip = &rctx->clip->state.clip;
837 if (fb->zsbuf) {
838 offset_units = state->offset_units;
839 offset_scale = state->offset_scale * 12.0f;
840 switch (fb->zsbuf->texture->format) {
841 case PIPE_FORMAT_Z24X8_UNORM:
842 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
843 depth = -24;
844 offset_units *= 2.0f;
845 break;
846 case PIPE_FORMAT_Z32_FLOAT:
847 depth = -23;
848 offset_units *= 1.0f;
849 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
850 break;
851 case PIPE_FORMAT_Z16_UNORM:
852 depth = -16;
853 offset_units *= 4.0f;
854 break;
855 default:
856 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
857 return;
858 }
859 }
860 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
861
862 if (state->flatshade_first)
863 prov_vtx = 0;
864
865 rctx->flat_shade = state->flatshade;
866 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
867 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
868 if (state->sprite_coord_enable) {
869 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
870 S_0286D4_PNT_SPRITE_ENA(1) |
871 S_0286D4_PNT_SPRITE_OVRD_X(2) |
872 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
873 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
874 S_0286D4_PNT_SPRITE_OVRD_W(1);
875 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
876 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
877 S_0286D4_PNT_SPRITE_TOP_1(1);
878 }
879 }
880 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
881 if (clip) {
882 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
883 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
884 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
885 }
886 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
887 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
888 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
889 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
890 S_028814_FACE(!state->front_ccw) |
891 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
892 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
893 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
894 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
895 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
896 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
897 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
898 /* point size 12.4 fixed point */
899 tmp = (unsigned)(state->point_size * 8.0);
900 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
901 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
902 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
903 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
904 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
905 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
906 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
907 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
908 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
909 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
910 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
911 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
912 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
913 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
914 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
915 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
916 radeon_state_pm4(rstate);
917 }
918
919 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
920 {
921 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
922 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
923 struct r600_screen *rscreen = rctx->screen;
924 unsigned minx, maxx, miny, maxy;
925 u32 tl, br;
926
927 if (state == NULL) {
928 minx = 0;
929 miny = 0;
930 maxx = fb->cbufs[0]->width;
931 maxy = fb->cbufs[0]->height;
932 } else {
933 minx = state->minx;
934 miny = state->miny;
935 maxx = state->maxx;
936 maxy = state->maxy;
937 }
938 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
939 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
940 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
941 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
942 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
943 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
944 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
945 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
946 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
947 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
948 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
949 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
950 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
951 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
952 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
953 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
954 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
955 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
956 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
957 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
958 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
959 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
960 radeon_state_pm4(rstate);
961 }
962
963 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
964 {
965 struct r600_screen *rscreen = rctx->screen;
966
967 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
968 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
969 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
970 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
971 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
972 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
973 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
974 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
975 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
976 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
977 radeon_state_pm4(rstate);
978 }
979
980 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
981 {
982 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
983 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
984 struct r600_screen *rscreen = rctx->screen;
985 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
986 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
987 struct r600_shader *rshader;
988 struct r600_query *rquery;
989 boolean query_running;
990 int i;
991
992 if (rctx->ps_shader == NULL) {
993 return;
994 }
995 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
996
997 db_shader_control = 0x210;
998 rshader = &rctx->ps_shader->shader;
999 if (rshader->uses_kill)
1000 db_shader_control |= (1 << 6);
1001 for (i = 0; i < rshader->noutput; i++) {
1002 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1003 db_shader_control |= 1;
1004 }
1005 stencil_ref_mask = 0;
1006 stencil_ref_mask_bf = 0;
1007 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1008 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1009 S_028800_ZFUNC(state->depth.func);
1010 /* set stencil enable */
1011
1012 if (state->stencil[0].enabled) {
1013 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1014 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
1015 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
1016 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
1017 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1018
1019 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1020 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1021 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
1022 if (state->stencil[1].enabled) {
1023 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1024 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1025 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1026 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1027 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1028 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1029 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1030 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
1031 }
1032 }
1033
1034 alpha_test_control = 0;
1035 alpha_ref = 0;
1036 if (state->alpha.enabled) {
1037 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1038 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1039 alpha_ref = fui(state->alpha.ref_value);
1040 }
1041
1042 db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
1043 S_028D0C_DEPTH_COMPRESS_DISABLE(1);
1044 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1045 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1046 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1047
1048 query_running = false;
1049
1050 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
1051 if (rquery->state & R600_QUERY_STATE_STARTED) {
1052 query_running = true;
1053 }
1054 }
1055
1056 if (query_running) {
1057 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1058 if (rscreen->chip_class == R700)
1059 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1060 }
1061
1062 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1063 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1064 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1065 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1066 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1067 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1068 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1069 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1070 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1071 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1072 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1073 rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control;
1074 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
1075
1076 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1077 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1078 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1079 radeon_state_pm4(rstate);
1080 }
1081
1082
1083 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1084 {
1085 return value * (1 << frac_bits);
1086 }
1087
1088 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
1089 const struct pipe_sampler_state *state, unsigned id)
1090 {
1091 struct r600_screen *rscreen = rctx->screen;
1092
1093 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
1094 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1095 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1096 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1097 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1098 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1099 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1100 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1101 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1102 /* FIXME LOD it depends on texture base level ... */
1103 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1104 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1105 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1106 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1107 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1108 radeon_state_pm4(rstate);
1109
1110 }
1111
1112
1113 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
1114 const struct pipe_sampler_view *view, unsigned id)
1115 {
1116 struct r600_context *rctx = r600_context(ctx);
1117 struct r600_screen *rscreen = rctx->screen;
1118 const struct util_format_description *desc;
1119 struct r600_resource_texture *tmp;
1120 struct r600_resource *rbuffer;
1121 unsigned format;
1122 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1123 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1124 int r;
1125
1126 rstate->cpm4 = 0;
1127 swizzle[0] = view->swizzle_r;
1128 swizzle[1] = view->swizzle_g;
1129 swizzle[2] = view->swizzle_b;
1130 swizzle[3] = view->swizzle_a;
1131 format = r600_translate_texformat(view->texture->format,
1132 swizzle,
1133 &word4, &yuv_format);
1134 if (format == ~0) {
1135 return;
1136 }
1137 desc = util_format_description(view->texture->format);
1138 if (desc == NULL) {
1139 R600_ERR("unknow format %d\n", view->texture->format);
1140 return;
1141 }
1142 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
1143 tmp = (struct r600_resource_texture*)view->texture;
1144 rbuffer = &tmp->resource;
1145 if (tmp->depth) {
1146 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1147 if (r) {
1148 return;
1149 }
1150 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1151 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1152 } else {
1153 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1154 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1155 }
1156 rstate->nbo = 2;
1157 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1158 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1159 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1160 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1161
1162 pitch = (tmp->pitch[0] / tmp->bpt);
1163 pitch = (pitch + 0x7) & ~0x7;
1164
1165 /* FIXME properly handle first level != 0 */
1166 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1167 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1168 S_038000_TILE_MODE(array_mode) |
1169 S_038000_TILE_TYPE(tile_type) |
1170 S_038000_PITCH((pitch / 8) - 1) |
1171 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1172 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1173 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1174 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1175 S_038004_DATA_FORMAT(format);
1176 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1177 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1178 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1179 word4 |
1180 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1181 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1182 S_038010_REQUEST_SIZE(1) |
1183 S_038010_BASE_LEVEL(view->first_level);
1184 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1185 S_038014_LAST_LEVEL(view->last_level) |
1186 S_038014_BASE_ARRAY(0) |
1187 S_038014_LAST_ARRAY(0);
1188 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1189 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1190 radeon_state_pm4(rstate);
1191 }
1192
1193 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
1194 {
1195 struct r600_screen *rscreen = rctx->screen;
1196 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1197 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1198 uint32_t color_control, target_mask, shader_mask;
1199 int i;
1200
1201 target_mask = 0;
1202 shader_mask = 0;
1203 color_control = S_028808_PER_MRT_BLEND(1);
1204
1205 for (i = 0; i < nr_cbufs; i++) {
1206 shader_mask |= 0xf << (i * 4);
1207 }
1208
1209 if (pbs->logicop_enable) {
1210 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
1211 } else {
1212 color_control |= (0xcc << 16);
1213 }
1214
1215 if (pbs->independent_blend_enable) {
1216 for (i = 0; i < nr_cbufs; i++) {
1217 if (pbs->rt[i].blend_enable) {
1218 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1219 }
1220 target_mask |= (pbs->rt[i].colormask << (4 * i));
1221 }
1222 } else {
1223 for (i = 0; i < nr_cbufs; i++) {
1224 if (pbs->rt[0].blend_enable) {
1225 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1226 }
1227 target_mask |= (pbs->rt[0].colormask << (4 * i));
1228 }
1229 }
1230 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
1231 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1232 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1233 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1234 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1235 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1236 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1237 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1238 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1239 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1240 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1241 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1242 radeon_state_pm4(rstate);
1243 }
1244
1245 int r600_context_hw_states(struct pipe_context *ctx)
1246 {
1247 struct r600_context *rctx = r600_context(ctx);
1248 unsigned i;
1249
1250 /* build new states */
1251 r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
1252 r600_scissor(rctx, &rctx->hw_states.scissor);
1253 r600_dsa(rctx, &rctx->hw_states.dsa);
1254 r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
1255
1256 /* bind states */
1257 radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
1258 radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
1259 radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
1260 radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
1261
1262 radeon_draw_bind(&rctx->draw, &rctx->config);
1263
1264 if (rctx->viewport) {
1265 radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
1266 }
1267 if (rctx->blend) {
1268 radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
1269 }
1270 if (rctx->clip) {
1271 radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
1272 }
1273 for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
1274 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
1275 }
1276 if (rctx->framebuffer->state.framebuffer.zsbuf) {
1277 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
1278 }
1279 for (i = 0; i < rctx->ps_nsampler; i++) {
1280 if (rctx->ps_sampler[i]) {
1281 radeon_draw_bind(&rctx->draw, rctx->ps_sampler[i]);
1282 }
1283 }
1284 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1285 if (rctx->ps_sampler_view[i]) {
1286 radeon_draw_bind(&rctx->draw, rctx->ps_sampler_view[i]);
1287 }
1288 }
1289 return 0;
1290 }