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r600g: fix segfault in state after rework
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "r600_screen.h"
33 #include "r600_context.h"
34 #include "r600_resource.h"
35 #include "r600d.h"
36 #include "r600_state_inlines.h"
37
38 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
39 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
40 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
41 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
42 static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
43 const struct pipe_sampler_state *state, unsigned id);
44 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
45 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
46 const struct pipe_framebuffer_state *state, int cb);
47 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
48 const struct pipe_framebuffer_state *state);
49
50 static struct r600_context_state *r600_new_context_state(unsigned type)
51 {
52 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
53 if (rstate == NULL)
54 return NULL;
55 rstate->type = type;
56 rstate->refcount = 1;
57 return rstate;
58 }
59
60 static void *r600_create_blend_state(struct pipe_context *ctx,
61 const struct pipe_blend_state *state)
62 {
63 struct r600_context *rctx = r600_context(ctx);
64 struct r600_context_state *rstate;
65
66 rstate = r600_new_context_state(pipe_blend_type);
67 rstate->state.blend = *state;
68 r600_blend(rctx, &rstate->rstate[0], &rstate->state.blend);
69
70 return rstate;
71 }
72
73 static void *r600_create_dsa_state(struct pipe_context *ctx,
74 const struct pipe_depth_stencil_alpha_state *state)
75 {
76 struct r600_context_state *rstate;
77
78 rstate = r600_new_context_state(pipe_dsa_type);
79 rstate->state.dsa = *state;
80 return rstate;
81 }
82
83 static void *r600_create_rs_state(struct pipe_context *ctx,
84 const struct pipe_rasterizer_state *state)
85 {
86 struct r600_context_state *rstate;
87
88 rstate = r600_new_context_state(pipe_rasterizer_type);
89 rstate->state.rasterizer = *state;
90 return rstate;
91 }
92
93 static void *r600_create_sampler_state(struct pipe_context *ctx,
94 const struct pipe_sampler_state *state)
95 {
96 struct r600_context *rctx = r600_context(ctx);
97 struct r600_context_state *rstate;
98
99 rstate = r600_new_context_state(pipe_sampler_type);
100 rstate->state.sampler = *state;
101 r600_sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
102 r600_sampler_border(rctx, &rstate->rstate[1], &rstate->state.sampler, 0);
103 return rstate;
104 }
105
106 static void r600_sampler_view_destroy(struct pipe_context *ctx,
107 struct pipe_sampler_view *state)
108 {
109 struct r600_context_state *rstate = (struct r600_context_state *)state;
110
111 r600_context_state_decref(rstate);
112 }
113
114 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
115 struct pipe_resource *texture,
116 const struct pipe_sampler_view *state)
117 {
118 struct r600_context_state *rstate;
119
120 rstate = r600_new_context_state(pipe_sampler_view_type);
121 rstate->state.sampler_view = *state;
122 rstate->state.sampler_view.texture = NULL;
123 pipe_reference(NULL, &texture->reference);
124 rstate->state.sampler_view.texture = texture;
125 rstate->state.sampler_view.reference.count = 1;
126 rstate->state.sampler_view.context = ctx;
127 r600_resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
128 return &rstate->state.sampler_view;
129 }
130
131 static void r600_set_sampler_view(struct pipe_context *ctx,
132 unsigned count,
133 struct pipe_sampler_view **views,
134 struct r600_shader_sampler_states *sampler,
135 unsigned shader_id)
136 {
137 struct r600_context *rctx = r600_context(ctx);
138 struct r600_context_state *rstate;
139 unsigned i;
140
141 for (i = 0; i < sampler->nview; i++) {
142 radeon_draw_unbind(&rctx->draw, sampler->view[i]);
143 }
144
145 for (i = 0; i < count; i++) {
146 rstate = (struct r600_context_state *)views[i];
147 if (rstate) {
148 rstate->nrstate = 0;
149 }
150 }
151 for (i = 0; i < count; i++) {
152 rstate = (struct r600_context_state *)views[i];
153 if (rstate) {
154 if (rstate->nrstate >= R600_MAX_RSTATE)
155 continue;
156 if (rstate->nrstate) {
157 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
158 }
159 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, shader_id);
160 sampler->view[i] = &rstate->rstate[rstate->nrstate];
161 rstate->nrstate++;
162 }
163 }
164 sampler->nview = count;
165 }
166
167 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
168 unsigned count,
169 struct pipe_sampler_view **views)
170 {
171 struct r600_context *rctx = r600_context(ctx);
172 r600_set_sampler_view(ctx, count, views, &rctx->ps_sampler, R600_SHADER_PS);
173 }
174
175 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
176 unsigned count,
177 struct pipe_sampler_view **views)
178 {
179 struct r600_context *rctx = r600_context(ctx);
180 r600_set_sampler_view(ctx, count, views, &rctx->vs_sampler, R600_SHADER_VS);
181 }
182
183 static void *r600_create_shader_state(struct pipe_context *ctx,
184 const struct pipe_shader_state *state)
185 {
186 struct r600_context *rctx = r600_context(ctx);
187 struct r600_context_state *rstate;
188 int r;
189
190 rstate = r600_new_context_state(pipe_shader_type);
191 rstate->state.shader = *state;
192 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
193 if (r) {
194 r600_context_state_decref(rstate);
195 return NULL;
196 }
197 return rstate;
198 }
199
200 static void *r600_create_vertex_elements(struct pipe_context *ctx,
201 unsigned count,
202 const struct pipe_vertex_element *elements)
203 {
204 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
205
206 assert(count < 32);
207 v->count = count;
208 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
209 v->refcount = 1;
210 return v;
211 }
212
213 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
214 {
215 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
216
217 if (v == NULL)
218 return;
219 if (--v->refcount)
220 return;
221 free(v);
222 }
223
224 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
225 {
226 struct r600_context *rctx = r600_context(ctx);
227 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
228
229 r600_delete_vertex_element(ctx, rctx->vertex_elements);
230 rctx->vertex_elements = v;
231 if (v) {
232 v->refcount++;
233 }
234 }
235
236 static void r600_bind_rasterizer_state(struct pipe_context *ctx, void *state)
237 {
238 struct r600_context *rctx = r600_context(ctx);
239 struct r600_context_state *rstate = (struct r600_context_state *)state;
240
241 if (state == NULL)
242 return;
243 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
244 rctx->rasterizer = r600_context_state_incref(rstate);
245 }
246
247 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
248 {
249 struct r600_context *rctx = r600_context(ctx);
250 struct r600_context_state *rstate = (struct r600_context_state *)state;
251
252 if (state == NULL)
253 return;
254 rctx->blend = r600_context_state_decref(rctx->blend);
255 rctx->blend = r600_context_state_incref(rstate);
256
257 }
258
259 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
260 {
261 struct r600_context *rctx = r600_context(ctx);
262 struct r600_context_state *rstate = (struct r600_context_state *)state;
263
264 if (state == NULL)
265 return;
266 rctx->dsa = r600_context_state_decref(rctx->dsa);
267 rctx->dsa = r600_context_state_incref(rstate);
268 }
269
270 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
271 {
272 struct r600_context *rctx = r600_context(ctx);
273 struct r600_context_state *rstate = (struct r600_context_state *)state;
274
275 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
276 rctx->ps_shader = r600_context_state_incref(rstate);
277 }
278
279 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
280 {
281 struct r600_context *rctx = r600_context(ctx);
282 struct r600_context_state *rstate = (struct r600_context_state *)state;
283
284 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
285 rctx->vs_shader = r600_context_state_incref(rstate);
286 }
287
288 static void r600_bind_sampler_shader(struct pipe_context *ctx,
289 unsigned count, void **states,
290 struct r600_shader_sampler_states *sampler, unsigned shader_id)
291 {
292 struct r600_context *rctx = r600_context(ctx);
293 struct r600_context_state *rstate;
294 unsigned i;
295
296 for (i = 0; i < sampler->nsampler; i++) {
297 radeon_draw_unbind(&rctx->draw, sampler->sampler[i]);
298 }
299 for (i = 0; i < sampler->nborder; i++) {
300 radeon_draw_unbind(&rctx->draw, sampler->border[i]);
301 }
302 for (i = 0; i < count; i++) {
303 rstate = (struct r600_context_state *)states[i];
304 if (rstate) {
305 rstate->nrstate = 0;
306 }
307 }
308 for (i = 0; i < count; i++) {
309 rstate = (struct r600_context_state *)states[i];
310 if (rstate) {
311 if (rstate->nrstate >= R600_MAX_RSTATE)
312 continue;
313 if (rstate->nrstate) {
314 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
315 memcpy(&rstate->rstate[rstate->nrstate+1], &rstate->rstate[1], sizeof(struct radeon_state));
316 }
317 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, shader_id);
318 radeon_state_convert(&rstate->rstate[rstate->nrstate + 1], R600_STATE_SAMPLER_BORDER, i, shader_id);
319 sampler->sampler[i] = &rstate->rstate[rstate->nrstate];
320 sampler->border[i] = &rstate->rstate[rstate->nrstate + 1];
321 rstate->nrstate += 2;
322 }
323 }
324 sampler->nsampler = count;
325 sampler->nborder = count;
326 }
327
328 static void r600_bind_ps_sampler(struct pipe_context *ctx,
329 unsigned count, void **states)
330 {
331 struct r600_context *rctx = r600_context(ctx);
332 r600_bind_sampler_shader(ctx, count, states, &rctx->ps_sampler, R600_SHADER_PS);
333 }
334
335 static void r600_bind_vs_sampler(struct pipe_context *ctx,
336 unsigned count, void **states)
337 {
338 struct r600_context *rctx = r600_context(ctx);
339 r600_bind_sampler_shader(ctx, count, states, &rctx->vs_sampler, R600_SHADER_VS);
340 }
341
342 static void r600_delete_state(struct pipe_context *ctx, void *state)
343 {
344 struct r600_context_state *rstate = (struct r600_context_state *)state;
345
346 r600_context_state_decref(rstate);
347 }
348
349 static void r600_set_blend_color(struct pipe_context *ctx,
350 const struct pipe_blend_color *color)
351 {
352 struct r600_context *rctx = r600_context(ctx);
353
354 rctx->blend_color = *color;
355 }
356
357 static void r600_set_clip_state(struct pipe_context *ctx,
358 const struct pipe_clip_state *state)
359 {
360 struct r600_context *rctx = r600_context(ctx);
361 struct r600_context_state *rstate;
362
363 r600_context_state_decref(rctx->clip);
364
365 rstate = r600_new_context_state(pipe_clip_type);
366 rstate->state.clip = *state;
367 r600_ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
368 rctx->clip = rstate;
369 }
370
371 static void r600_set_constant_buffer(struct pipe_context *ctx,
372 uint shader, uint index,
373 struct pipe_resource *buffer)
374 {
375 struct r600_screen *rscreen = r600_screen(ctx->screen);
376 struct r600_context *rctx = r600_context(ctx);
377 unsigned nconstant = 0, i, type, shader_class;
378 struct radeon_state *rstate, *rstates;
379 struct pipe_transfer *transfer;
380 u32 *ptr;
381
382 type = R600_STATE_CONSTANT;
383
384 switch (shader) {
385 case PIPE_SHADER_VERTEX:
386 shader_class = R600_SHADER_VS;
387 rstates = rctx->vs_constant;
388 break;
389 case PIPE_SHADER_FRAGMENT:
390 shader_class = R600_SHADER_PS;
391 rstates = rctx->ps_constant;
392 break;
393 default:
394 R600_ERR("unsupported %d\n", shader);
395 return;
396 }
397 if (buffer && buffer->width0 > 0) {
398 nconstant = buffer->width0 / 16;
399 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
400 if (ptr == NULL)
401 return;
402 for (i = 0; i < nconstant; i++) {
403 rstate = &rstates[i];
404 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
405 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
406 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
407 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
408 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
409 if (radeon_state_pm4(rstate))
410 return;
411 radeon_draw_bind(&rctx->draw, rstate);
412 }
413 pipe_buffer_unmap(ctx, buffer, transfer);
414 }
415 }
416
417 static void r600_set_framebuffer_state(struct pipe_context *ctx,
418 const struct pipe_framebuffer_state *state)
419 {
420 struct r600_context *rctx = r600_context(ctx);
421 struct r600_context_state *rstate;
422 int i;
423
424 r600_context_state_decref(rctx->framebuffer);
425
426 rstate = r600_new_context_state(pipe_framebuffer_type);
427 rstate->state.framebuffer = *state;
428 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
429 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
430 state->cbufs[i]);
431 }
432 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
433 state->zsbuf);
434 rctx->framebuffer = rstate;
435 for (i = 0; i < state->nr_cbufs; i++) {
436 r600_cb(rctx, &rstate->rstate[i+1], state, i);
437 }
438 if (state->zsbuf) {
439 r600_db(rctx, &rstate->rstate[0], state);
440 }
441 return;
442 }
443
444 static void r600_set_polygon_stipple(struct pipe_context *ctx,
445 const struct pipe_poly_stipple *state)
446 {
447 }
448
449 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
450 {
451 }
452
453 static void r600_set_scissor_state(struct pipe_context *ctx,
454 const struct pipe_scissor_state *state)
455 {
456 struct r600_context *rctx = r600_context(ctx);
457 struct r600_context_state *rstate;
458
459 r600_context_state_decref(rctx->scissor);
460
461 rstate = r600_new_context_state(pipe_scissor_type);
462 rstate->state.scissor = *state;
463 rctx->scissor = rstate;
464 }
465
466 static void r600_set_stencil_ref(struct pipe_context *ctx,
467 const struct pipe_stencil_ref *state)
468 {
469 struct r600_context *rctx = r600_context(ctx);
470 struct r600_context_state *rstate;
471
472 r600_context_state_decref(rctx->stencil_ref);
473
474 rstate = r600_new_context_state(pipe_stencil_ref_type);
475 rstate->state.stencil_ref = *state;
476 rctx->stencil_ref = rstate;
477 }
478
479 static void r600_set_vertex_buffers(struct pipe_context *ctx,
480 unsigned count,
481 const struct pipe_vertex_buffer *buffers)
482 {
483 struct r600_context *rctx = r600_context(ctx);
484 unsigned i;
485
486 for (i = 0; i < rctx->nvertex_buffer; i++) {
487 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
488 }
489 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
490 for (i = 0; i < count; i++) {
491 rctx->vertex_buffer[i].buffer = NULL;
492 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
493 }
494 rctx->nvertex_buffer = count;
495 }
496
497 static void r600_set_index_buffer(struct pipe_context *ctx,
498 const struct pipe_index_buffer *ib)
499 {
500 struct r600_context *rctx = r600_context(ctx);
501
502 if (ib) {
503 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
504 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
505 } else {
506 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
507 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
508 }
509
510 /* TODO make this more like a state */
511 }
512
513 static void r600_set_viewport_state(struct pipe_context *ctx,
514 const struct pipe_viewport_state *state)
515 {
516 struct r600_context *rctx = r600_context(ctx);
517 struct r600_context_state *rstate;
518
519 r600_context_state_decref(rctx->viewport);
520
521 rstate = r600_new_context_state(pipe_viewport_type);
522 rstate->state.viewport = *state;
523 r600_viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
524 rctx->viewport = rstate;
525 }
526
527 void r600_init_state_functions(struct r600_context *rctx)
528 {
529 rctx->context.create_blend_state = r600_create_blend_state;
530 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
531 rctx->context.create_fs_state = r600_create_shader_state;
532 rctx->context.create_rasterizer_state = r600_create_rs_state;
533 rctx->context.create_sampler_state = r600_create_sampler_state;
534 rctx->context.create_sampler_view = r600_create_sampler_view;
535 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
536 rctx->context.create_vs_state = r600_create_shader_state;
537 rctx->context.bind_blend_state = r600_bind_blend_state;
538 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
539 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
540 rctx->context.bind_fs_state = r600_bind_ps_shader;
541 rctx->context.bind_rasterizer_state = r600_bind_rasterizer_state;
542 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
543 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
544 rctx->context.bind_vs_state = r600_bind_vs_shader;
545 rctx->context.delete_blend_state = r600_delete_state;
546 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
547 rctx->context.delete_fs_state = r600_delete_state;
548 rctx->context.delete_rasterizer_state = r600_delete_state;
549 rctx->context.delete_sampler_state = r600_delete_state;
550 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
551 rctx->context.delete_vs_state = r600_delete_state;
552 rctx->context.set_blend_color = r600_set_blend_color;
553 rctx->context.set_clip_state = r600_set_clip_state;
554 rctx->context.set_constant_buffer = r600_set_constant_buffer;
555 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
556 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
557 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
558 rctx->context.set_sample_mask = r600_set_sample_mask;
559 rctx->context.set_scissor_state = r600_set_scissor_state;
560 rctx->context.set_stencil_ref = r600_set_stencil_ref;
561 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
562 rctx->context.set_index_buffer = r600_set_index_buffer;
563 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
564 rctx->context.set_viewport_state = r600_set_viewport_state;
565 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
566 }
567
568 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
569 {
570 if (rstate == NULL)
571 return NULL;
572 rstate->refcount++;
573 return rstate;
574 }
575
576 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
577 {
578 unsigned i;
579
580 if (rstate == NULL)
581 return NULL;
582 if (--rstate->refcount)
583 return NULL;
584 switch (rstate->type) {
585 case pipe_sampler_view_type:
586 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
587 break;
588 case pipe_framebuffer_type:
589 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
590 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
591 }
592 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
593 break;
594 case pipe_viewport_type:
595 case pipe_depth_type:
596 case pipe_rasterizer_type:
597 case pipe_poly_stipple_type:
598 case pipe_scissor_type:
599 case pipe_clip_type:
600 case pipe_stencil_type:
601 case pipe_alpha_type:
602 case pipe_dsa_type:
603 case pipe_blend_type:
604 case pipe_stencil_ref_type:
605 case pipe_shader_type:
606 case pipe_sampler_type:
607 break;
608 default:
609 R600_ERR("invalid type %d\n", rstate->type);
610 return NULL;
611 }
612 radeon_state_fini(&rstate->rstate[0]);
613 FREE(rstate);
614 return NULL;
615 }
616
617 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
618 {
619 struct r600_screen *rscreen = rctx->screen;
620 int i;
621
622 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
623 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
624 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
625 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
626 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
627 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
628 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
629 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
630 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
631 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
632 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
633 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
634 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
635 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
636
637 for (i = 0; i < 8; i++) {
638 unsigned eqRGB = state->rt[i].rgb_func;
639 unsigned srcRGB = state->rt[i].rgb_src_factor;
640 unsigned dstRGB = state->rt[i].rgb_dst_factor;
641
642 unsigned eqA = state->rt[i].alpha_func;
643 unsigned srcA = state->rt[i].alpha_src_factor;
644 unsigned dstA = state->rt[i].alpha_dst_factor;
645 uint32_t bc = 0;
646
647 if (!state->rt[i].blend_enable)
648 continue;
649
650 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
651 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
652 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
653
654 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
655 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
656 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
657 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
658 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
659 }
660
661 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
662 if (i == 0)
663 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
664 }
665
666 radeon_state_pm4(rstate);
667 }
668
669 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
670 const struct pipe_clip_state *state)
671 {
672 struct r600_screen *rscreen = rctx->screen;
673
674 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
675
676 for (int i = 0; i < state->nr; i++) {
677 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
678 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
679 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
680 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
681 }
682 radeon_state_pm4(rstate);
683 }
684
685 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
686 const struct pipe_framebuffer_state *state, int cb)
687 {
688 struct r600_screen *rscreen = rctx->screen;
689 struct r600_resource_texture *rtex;
690 struct r600_resource *rbuffer;
691 unsigned level = state->cbufs[cb]->level;
692 unsigned pitch, slice;
693 unsigned color_info;
694 unsigned format, swap, ntype;
695 const struct util_format_description *desc;
696
697 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
698 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
699 rbuffer = &rtex->resource;
700 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
701 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
702 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
703 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
704 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
705 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
706 rstate->nbo = 3;
707 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
708 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
709
710 ntype = 0;
711 desc = util_format_description(rtex->resource.base.b.format);
712 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
713 ntype = V_0280A0_NUMBER_SRGB;
714
715 format = r600_translate_colorformat(rtex->resource.base.b.format);
716 swap = r600_translate_colorswap(rtex->resource.base.b.format);
717
718 color_info = S_0280A0_FORMAT(format) |
719 S_0280A0_COMP_SWAP(swap) |
720 S_0280A0_BLEND_CLAMP(1) |
721 S_0280A0_SOURCE_FORMAT(1) |
722 S_0280A0_NUMBER_TYPE(ntype);
723
724 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
725 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
726 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
727 S_028060_SLICE_TILE_MAX(slice);
728 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
729 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
730 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
731 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
732 radeon_state_pm4(rstate);
733 }
734
735 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
736 const struct pipe_framebuffer_state *state)
737 {
738 struct r600_screen *rscreen = rctx->screen;
739 struct r600_resource_texture *rtex;
740 struct r600_resource *rbuffer;
741 unsigned level;
742 unsigned pitch, slice, format;
743
744 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
745 if (state->zsbuf == NULL)
746 return;
747
748 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
749 rtex->tilled = 1;
750 rtex->array_mode = 2;
751 rtex->tile_type = 1;
752 rtex->depth = 1;
753 rbuffer = &rtex->resource;
754
755 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
756 rstate->nbo = 1;
757 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
758 level = state->zsbuf->level;
759 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
760 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
761 format = r600_translate_dbformat(state->zsbuf->texture->format);
762 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
763 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
764 S_028010_FORMAT(format);
765 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
766 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
767 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
768 S_028000_SLICE_TILE_MAX(slice);
769 radeon_state_pm4(rstate);
770 }
771
772 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
773 {
774 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
775 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
776 const struct pipe_clip_state *clip = NULL;
777 struct r600_screen *rscreen = rctx->screen;
778 float offset_units = 0, offset_scale = 0;
779 char depth = 0;
780 unsigned offset_db_fmt_cntl = 0;
781 unsigned tmp;
782 unsigned prov_vtx = 1;
783
784 if (rctx->clip)
785 clip = &rctx->clip->state.clip;
786 if (fb->zsbuf) {
787 offset_units = state->offset_units;
788 offset_scale = state->offset_scale * 12.0f;
789 switch (fb->zsbuf->texture->format) {
790 case PIPE_FORMAT_Z24X8_UNORM:
791 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
792 depth = -24;
793 offset_units *= 2.0f;
794 break;
795 case PIPE_FORMAT_Z32_FLOAT:
796 depth = -23;
797 offset_units *= 1.0f;
798 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
799 break;
800 case PIPE_FORMAT_Z16_UNORM:
801 depth = -16;
802 offset_units *= 4.0f;
803 break;
804 default:
805 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
806 return;
807 }
808 }
809 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
810
811 if (state->flatshade_first)
812 prov_vtx = 0;
813
814 rctx->flat_shade = state->flatshade;
815 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
816 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
817 if (state->sprite_coord_enable) {
818 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
819 S_0286D4_PNT_SPRITE_ENA(1) |
820 S_0286D4_PNT_SPRITE_OVRD_X(2) |
821 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
822 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
823 S_0286D4_PNT_SPRITE_OVRD_W(1);
824 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
825 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
826 S_0286D4_PNT_SPRITE_TOP_1(1);
827 }
828 }
829 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
830 if (clip) {
831 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
832 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
833 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
834 }
835 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
836 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
837 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
838 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
839 S_028814_FACE(!state->front_ccw) |
840 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
841 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
842 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
843 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
844 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
845 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
846 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
847 /* point size 12.4 fixed point */
848 tmp = (unsigned)(state->point_size * 8.0);
849 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
850 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
851 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
852 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
853 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
854 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
855 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
856 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
857 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
858 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
859 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
860 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
861 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
862 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
863 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
864 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
865 radeon_state_pm4(rstate);
866 }
867
868 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
869 {
870 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
871 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
872 struct r600_screen *rscreen = rctx->screen;
873 unsigned minx, maxx, miny, maxy;
874 u32 tl, br;
875
876 if (state == NULL) {
877 minx = 0;
878 miny = 0;
879 maxx = fb->cbufs[0]->width;
880 maxy = fb->cbufs[0]->height;
881 } else {
882 minx = state->minx;
883 miny = state->miny;
884 maxx = state->maxx;
885 maxy = state->maxy;
886 }
887 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
888 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
889 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
890 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
891 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
892 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
893 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
894 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
895 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
896 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
897 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
898 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
899 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
900 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
901 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
902 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
903 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
904 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
905 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
906 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
907 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
908 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
909 radeon_state_pm4(rstate);
910 }
911
912 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
913 {
914 struct r600_screen *rscreen = rctx->screen;
915
916 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
917 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
918 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
919 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
920 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
921 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
922 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
923 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
924 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
925 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
926 radeon_state_pm4(rstate);
927 }
928
929 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
930 {
931 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
932 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
933 struct r600_screen *rscreen = rctx->screen;
934 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
935 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
936 struct r600_shader *rshader;
937 struct r600_query *rquery;
938 boolean query_running;
939 int i;
940
941 if (rctx->ps_shader == NULL) {
942 return;
943 }
944 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
945
946 db_shader_control = 0x210;
947 rshader = &rctx->ps_shader->shader;
948 if (rshader->uses_kill)
949 db_shader_control |= (1 << 6);
950 for (i = 0; i < rshader->noutput; i++) {
951 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
952 db_shader_control |= 1;
953 }
954 stencil_ref_mask = 0;
955 stencil_ref_mask_bf = 0;
956 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
957 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
958 S_028800_ZFUNC(state->depth.func);
959 /* set stencil enable */
960
961 if (state->stencil[0].enabled) {
962 db_depth_control |= S_028800_STENCIL_ENABLE(1);
963 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
964 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
965 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
966 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
967
968 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
969 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
970 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
971 if (state->stencil[1].enabled) {
972 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
973 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
974 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
975 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
976 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
977 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
978 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
979 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
980 }
981 }
982
983 alpha_test_control = 0;
984 alpha_ref = 0;
985 if (state->alpha.enabled) {
986 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
987 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
988 alpha_ref = fui(state->alpha.ref_value);
989 }
990
991 db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
992 S_028D0C_DEPTH_COMPRESS_DISABLE(1);
993 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
994 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
995 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
996
997 query_running = false;
998
999 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
1000 if (rquery->state & R600_QUERY_STATE_STARTED) {
1001 query_running = true;
1002 }
1003 }
1004
1005 if (query_running) {
1006 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1007 if (rscreen->chip_class == R700)
1008 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1009 }
1010
1011 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1012 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1013 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1014 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1015 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1016 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1017 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1018 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1019 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1020 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1021 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1022 rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control;
1023 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
1024
1025 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1026 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1027 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1028 radeon_state_pm4(rstate);
1029 }
1030
1031
1032 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1033 {
1034 return value * (1 << frac_bits);
1035 }
1036
1037 static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
1038 const struct pipe_sampler_state *state, unsigned id)
1039 {
1040 struct r600_screen *rscreen = rctx->screen;
1041 union util_color uc;
1042
1043 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1044
1045 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
1046 if (uc.ui) {
1047 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
1048 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
1049 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
1050 rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
1051 }
1052 radeon_state_pm4(rstate);
1053 }
1054
1055 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
1056 const struct pipe_sampler_state *state, unsigned id)
1057 {
1058 struct r600_screen *rscreen = rctx->screen;
1059 union util_color uc;
1060
1061 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1062
1063 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
1064 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1065 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1066 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1067 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1068 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1069 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1070 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1071 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1072 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1073 /* FIXME LOD it depends on texture base level ... */
1074 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1075 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1076 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1077 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1078 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1079 radeon_state_pm4(rstate);
1080
1081 }
1082
1083
1084 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
1085 const struct pipe_sampler_view *view, unsigned id)
1086 {
1087 struct r600_context *rctx = r600_context(ctx);
1088 struct r600_screen *rscreen = rctx->screen;
1089 const struct util_format_description *desc;
1090 struct r600_resource_texture *tmp;
1091 struct r600_resource *rbuffer;
1092 unsigned format;
1093 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1094 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1095 int r;
1096
1097 rstate->cpm4 = 0;
1098 swizzle[0] = view->swizzle_r;
1099 swizzle[1] = view->swizzle_g;
1100 swizzle[2] = view->swizzle_b;
1101 swizzle[3] = view->swizzle_a;
1102 format = r600_translate_texformat(view->texture->format,
1103 swizzle,
1104 &word4, &yuv_format);
1105 if (format == ~0) {
1106 return;
1107 }
1108 desc = util_format_description(view->texture->format);
1109 if (desc == NULL) {
1110 R600_ERR("unknow format %d\n", view->texture->format);
1111 return;
1112 }
1113 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
1114 tmp = (struct r600_resource_texture*)view->texture;
1115 rbuffer = &tmp->resource;
1116 if (tmp->depth) {
1117 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1118 if (r) {
1119 return;
1120 }
1121 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1122 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1123 } else {
1124 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1125 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1126 }
1127 rstate->nbo = 2;
1128 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1129 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1130 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1131 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1132
1133 pitch = (tmp->pitch[0] / tmp->bpt);
1134 pitch = (pitch + 0x7) & ~0x7;
1135
1136 /* FIXME properly handle first level != 0 */
1137 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1138 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1139 S_038000_TILE_MODE(array_mode) |
1140 S_038000_TILE_TYPE(tile_type) |
1141 S_038000_PITCH((pitch / 8) - 1) |
1142 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1143 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1144 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1145 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1146 S_038004_DATA_FORMAT(format);
1147 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1148 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1149 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1150 word4 |
1151 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1152 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1153 S_038010_REQUEST_SIZE(1) |
1154 S_038010_BASE_LEVEL(view->first_level);
1155 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1156 S_038014_LAST_LEVEL(view->last_level) |
1157 S_038014_BASE_ARRAY(0) |
1158 S_038014_LAST_ARRAY(0);
1159 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1160 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1161 radeon_state_pm4(rstate);
1162 }
1163
1164 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
1165 {
1166 struct r600_screen *rscreen = rctx->screen;
1167 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1168 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1169 uint32_t color_control, target_mask, shader_mask;
1170 int i;
1171
1172 target_mask = 0;
1173 shader_mask = 0;
1174 color_control = S_028808_PER_MRT_BLEND(1);
1175
1176 for (i = 0; i < nr_cbufs; i++) {
1177 shader_mask |= 0xf << (i * 4);
1178 }
1179
1180 if (pbs->logicop_enable) {
1181 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
1182 } else {
1183 color_control |= (0xcc << 16);
1184 }
1185
1186 if (pbs->independent_blend_enable) {
1187 for (i = 0; i < nr_cbufs; i++) {
1188 if (pbs->rt[i].blend_enable) {
1189 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1190 }
1191 target_mask |= (pbs->rt[i].colormask << (4 * i));
1192 }
1193 } else {
1194 for (i = 0; i < nr_cbufs; i++) {
1195 if (pbs->rt[0].blend_enable) {
1196 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1197 }
1198 target_mask |= (pbs->rt[0].colormask << (4 * i));
1199 }
1200 }
1201 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
1202 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1203 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1204 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1205 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1206 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1207 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1208 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1209 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1210 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1211 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1212 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1213 radeon_state_pm4(rstate);
1214 }
1215
1216 static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shader_sampler_states *sampler)
1217 {
1218 int i;
1219
1220 for (i = 0; i < sampler->nsampler; i++) {
1221 if (sampler->sampler[i])
1222 radeon_draw_bind(&rctx->draw, sampler->sampler[i]);
1223 }
1224
1225 for (i = 0; i < sampler->nborder; i++) {
1226 if (sampler->border[i])
1227 radeon_draw_bind(&rctx->draw, sampler->border[i]);
1228 }
1229
1230 for (i = 0; i < sampler->nview; i++) {
1231 if (sampler->view[i])
1232 radeon_draw_bind(&rctx->draw, sampler->view[i]);
1233 }
1234 }
1235
1236 int r600_context_hw_states(struct pipe_context *ctx)
1237 {
1238 struct r600_context *rctx = r600_context(ctx);
1239 unsigned i;
1240
1241 /* build new states */
1242 r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
1243 r600_scissor(rctx, &rctx->hw_states.scissor);
1244 r600_dsa(rctx, &rctx->hw_states.dsa);
1245 r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
1246
1247 /* bind states */
1248 radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
1249 radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
1250 radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
1251 radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
1252
1253 radeon_draw_bind(&rctx->draw, &rctx->config);
1254
1255 if (rctx->viewport) {
1256 radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
1257 }
1258 if (rctx->blend) {
1259 radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
1260 }
1261 if (rctx->clip) {
1262 radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
1263 }
1264 for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
1265 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
1266 }
1267 if (rctx->framebuffer->state.framebuffer.zsbuf) {
1268 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
1269 }
1270
1271 r600_bind_shader_sampler(rctx, &rctx->vs_sampler);
1272 r600_bind_shader_sampler(rctx, &rctx->ps_sampler);
1273
1274 return 0;
1275 }