src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include <pipe/p_defines.h>
  30 #include <pipe/p_state.h>
  31 #include <pipe/p_context.h>
  32 #include <tgsi/tgsi_scan.h>
  33 #include <tgsi/tgsi_parse.h>
  34 #include <tgsi/tgsi_util.h>
  35 #include <util/u_double_list.h>
  36 #include <util/u_pack_color.h>
  37 #include <util/u_memory.h>
  38 #include <util/u_inlines.h>
  39 #include <util/u_upload_mgr.h>
  40 #include <util/u_index_modify.h>
  41 #include <pipebuffer/pb_buffer.h>
  42 #include "r600.h"
  43 #include "r600d.h"
  44 #include "r600_resource.h"
  45 #include "r600_shader.h"
  46 #include "r600_pipe.h"
  47 #include "r600_state_inlines.h"
  48
  49 static void r600_draw_common(struct r600_drawl *draw)
  50 {
  51         struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
  52         struct r600_pipe_state *rstate;
  53         struct r600_resource *rbuffer;
  54         unsigned i, j, offset, prim;
  55         u32 vgt_dma_index_type, vgt_draw_initiator, mask;
  56         struct pipe_vertex_buffer *vertex_buffer;
  57         struct r600_draw rdraw;
  58         struct r600_pipe_state vgt;
  59
  60         switch (draw->index_size) {
  61         case 2:
  62                 vgt_draw_initiator = 0;
  63                 vgt_dma_index_type = 0;
  64                 break;
  65         case 4:
  66                 vgt_draw_initiator = 0;
  67                 vgt_dma_index_type = 1;
  68                 break;
  69         case 0:
  70                 vgt_draw_initiator = 2;
  71                 vgt_dma_index_type = 0;
  72                 break;
  73         default:
  74                 R600_ERR("unsupported index size %d\n", draw->index_size);
  75                 return;
  76         }
  77         if (r600_conv_pipe_prim(draw->mode, &prim))
  78                 return;
  79
  80
  81         /* rebuild vertex shader if input format changed */
  82         if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
  83                 return;
  84         if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
  85                 return;
  86
  87         for (i = 0 ; i < rctx->vertex_elements->count; i++) {
  88                 uint32_t word2, format;
  89
  90                 rstate = &rctx->vs_resource[i];
  91                 rstate->id = R600_PIPE_STATE_RESOURCE;
  92                 rstate->nregs = 0;
  93
  94                 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
  95                 vertex_buffer = &rctx->vertex_buffer[j];
  96                 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
  97                 offset = rctx->vertex_elements->elements[i].src_offset +
  98                         vertex_buffer->buffer_offset +
  99                         r600_bo_offset(rbuffer->bo);
 100
 101                 format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
 102
 103                 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
 104
 105                 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
 106                 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
 107                 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
 108                 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
 109                 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
 110                 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
 111                 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
 112                 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
 113         }
 114
 115         mask = 0;
 116         for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
 117                 mask |= (0xF << (i * 4));
 118         }
 119
 120         vgt.id = R600_PIPE_STATE_VGT;
 121         vgt.nregs = 0;
 122         r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
 123         r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
 124         r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
 125         r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
 126         r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
 127         r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
 128         r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
 129         /* build late state */
 130         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 131                 float offset_units = rctx->rasterizer->offset_units;
 132                 unsigned offset_db_fmt_cntl = 0, depth;
 133
 134                 switch (rctx->framebuffer.zsbuf->texture->format) {
 135                 case PIPE_FORMAT_Z24X8_UNORM:
 136                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 137                         depth = -24;
 138                         offset_units *= 2.0f;
 139                         break;
 140                 case PIPE_FORMAT_Z32_FLOAT:
 141                         depth = -23;
 142                         offset_units *= 1.0f;
 143                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 144                         break;
 145                 case PIPE_FORMAT_Z16_UNORM:
 146                         depth = -16;
 147                         offset_units *= 4.0f;
 148                         break;
 149                 default:
 150                         return;
 151                 }
 152                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 153                 r600_pipe_state_add_reg(&vgt,
 154                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 155                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
 156                 r600_pipe_state_add_reg(&vgt,
 157                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 158                                 fui(offset_units), 0xFFFFFFFF, NULL);
 159                 r600_pipe_state_add_reg(&vgt,
 160                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 161                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
 162                 r600_pipe_state_add_reg(&vgt,
 163                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 164                                 fui(offset_units), 0xFFFFFFFF, NULL);
 165                 r600_pipe_state_add_reg(&vgt,
 166                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 167                                 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
 168         }
 169         r600_context_pipe_state_set(&rctx->ctx, &vgt);
 170
 171         rdraw.vgt_num_indices = draw->count;
 172         rdraw.vgt_num_instances = 1;
 173         rdraw.vgt_index_type = vgt_dma_index_type;
 174         rdraw.vgt_draw_initiator = vgt_draw_initiator;
 175         rdraw.indices = NULL;
 176         if (draw->index_buffer) {
 177                 rbuffer = (struct r600_resource*)draw->index_buffer;
 178                 rdraw.indices = rbuffer->bo;
 179                 rdraw.indices_bo_offset = draw->index_buffer_offset;
 180         }
 181         r600_context_draw(&rctx->ctx, &rdraw);
 182 }
 183
 184 void r600_translate_index_buffer(struct r600_pipe_context *r600,
 185                                         struct pipe_resource **index_buffer,
 186                                         unsigned *index_size,
 187                                         unsigned *start, unsigned count)
 188 {
 189         switch (*index_size) {
 190         case 1:
 191                 util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
 192                 *index_size = 2;
 193                 *start = 0;
 194                 break;
 195
 196         case 2:
 197                 if (*start % 2 != 0) {
 198                         util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
 199                         *start = 0;
 200                 }
 201                 break;
 202
 203         case 4:
 204                 break;
 205         }
 206 }
 207
 208 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 209 {
 210         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 211         struct r600_drawl draw;
 212
 213         if (rctx->any_user_vbs) {
 214                 r600_upload_user_buffers(rctx);
 215                 rctx->any_user_vbs = FALSE;
 216         }
 217
 218         memset(&draw, 0, sizeof(struct r600_drawl));
 219         draw.ctx = ctx;
 220         draw.mode = info->mode;
 221         draw.start = info->start;
 222         draw.count = info->count;
 223         if (info->indexed && rctx->index_buffer.buffer) {
 224                 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
 225                 draw.min_index = info->min_index;
 226                 draw.max_index = info->max_index;
 227                 draw.index_bias = info->index_bias;
 228
 229                 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
 230                                             &rctx->index_buffer.index_size,
 231                                             &draw.start,
 232                                             info->count);
 233
 234                 draw.index_size = rctx->index_buffer.index_size;
 235                 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
 236                 draw.index_buffer_offset = draw.start * draw.index_size;
 237                 draw.start = 0;
 238                 r600_upload_index_buffer(rctx, &draw);
 239         } else {
 240                 draw.index_size = 0;
 241                 draw.index_buffer = NULL;
 242                 draw.min_index = info->min_index;
 243                 draw.max_index = info->max_index;
 244                 draw.index_bias = info->start;
 245         }
 246         r600_draw_common(&draw);
 247
 248         pipe_resource_reference(&draw.index_buffer, NULL);
 249 }
 250
 251 static void r600_set_blend_color(struct pipe_context *ctx,
 252                                         const struct pipe_blend_color *state)
 253 {
 254         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 255         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 256
 257         if (rstate == NULL)
 258                 return;
 259
 260         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 261         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
 262         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
 263         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
 264         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
 265         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 266         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 267         r600_context_pipe_state_set(&rctx->ctx, rstate);
 268 }
 269
 270 static void *r600_create_blend_state(struct pipe_context *ctx,
 271                                         const struct pipe_blend_state *state)
 272 {
 273         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 274         struct r600_pipe_state *rstate;
 275         u32 color_control, target_mask;
 276
 277         if (blend == NULL) {
 278                 return NULL;
 279         }
 280         rstate = &blend->rstate;
 281
 282         rstate->id = R600_PIPE_STATE_BLEND;
 283
 284         target_mask = 0;
 285         color_control = S_028808_PER_MRT_BLEND(1);
 286         if (state->logicop_enable) {
 287                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 288         } else {
 289                 color_control |= (0xcc << 16);
 290         }
 291         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 292         if (state->independent_blend_enable) {
 293                 for (int i = 0; i < 8; i++) {
 294                         if (state->rt[i].blend_enable) {
 295                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 296                         }
 297                         target_mask |= (state->rt[i].colormask << (4 * i));
 298                 }
 299         } else {
 300                 for (int i = 0; i < 8; i++) {
 301                         if (state->rt[0].blend_enable) {
 302                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 303                         }
 304                         target_mask |= (state->rt[0].colormask << (4 * i));
 305                 }
 306         }
 307         blend->cb_target_mask = target_mask;
 308         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 309                                 color_control, 0xFFFFFFFF, NULL);
 310
 311         for (int i = 0; i < 8; i++) {
 312                 unsigned eqRGB = state->rt[i].rgb_func;
 313                 unsigned srcRGB = state->rt[i].rgb_src_factor;
 314                 unsigned dstRGB = state->rt[i].rgb_dst_factor;
 315
 316                 unsigned eqA = state->rt[i].alpha_func;
 317                 unsigned srcA = state->rt[i].alpha_src_factor;
 318                 unsigned dstA = state->rt[i].alpha_dst_factor;
 319                 uint32_t bc = 0;
 320
 321                 if (!state->rt[i].blend_enable)
 322                         continue;
 323
 324                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 325                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 326                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 327
 328                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 329                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 330                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 331                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 332                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 333                 }
 334
 335                 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
 336                 if (i == 0) {
 337                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
 338                 }
 339         }
 340         return rstate;
 341 }
 342
 343 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 344 {
 345         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 346         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 347         struct r600_pipe_state *rstate;
 348
 349         if (state == NULL)
 350                 return;
 351         rstate = &blend->rstate;
 352         rctx->states[rstate->id] = rstate;
 353         rctx->cb_target_mask = blend->cb_target_mask;
 354         r600_context_pipe_state_set(&rctx->ctx, rstate);
 355 }
 356
 357 static void *r600_create_dsa_state(struct pipe_context *ctx,
 358                                    const struct pipe_depth_stencil_alpha_state *state)
 359 {
 360         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 361         unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 362         unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 363
 364         if (rstate == NULL) {
 365                 return NULL;
 366         }
 367
 368         rstate->id = R600_PIPE_STATE_DSA;
 369         /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
 370         /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
 371          * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
 372          * be set if shader use texkill instruction
 373          */
 374         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 375         stencil_ref_mask = 0;
 376         stencil_ref_mask_bf = 0;
 377         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 378                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 379                 S_028800_ZFUNC(state->depth.func);
 380
 381         /* stencil */
 382         if (state->stencil[0].enabled) {
 383                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 384                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 385                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 386                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 387                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 388
 389
 390                 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 391                         S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 392                 if (state->stencil[1].enabled) {
 393                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 394                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 395                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 396                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 397                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 398                         stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 399                                 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 400                 }
 401         }
 402
 403         /* alpha */
 404         alpha_test_control = 0;
 405         alpha_ref = 0;
 406         if (state->alpha.enabled) {
 407                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 408                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 409                 alpha_ref = fui(state->alpha.ref_value);
 410         }
 411
 412         /* misc */
 413         db_render_control = 0;
 414         db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
 415                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
 416                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
 417         /* TODO db_render_override depends on query */
 418         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
 419         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
 420         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
 421         r600_pipe_state_add_reg(rstate,
 422                                 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
 423                                 0xFFFFFFFF & C_028430_STENCILREF, NULL);
 424         r600_pipe_state_add_reg(rstate,
 425                                 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
 426                                 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
 427         r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
 428         r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
 429         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
 430         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 431         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
 432         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
 433         r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
 434         r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
 435         r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
 436         r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
 437         r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
 438
 439         return rstate;
 440 }
 441
 442 static void *r600_create_rs_state(struct pipe_context *ctx,
 443                                         const struct pipe_rasterizer_state *state)
 444 {
 445         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 446         struct r600_pipe_state *rstate;
 447         unsigned tmp;
 448         unsigned prov_vtx = 1, polygon_dual_mode;
 449
 450         if (rs == NULL) {
 451                 return NULL;
 452         }
 453
 454         rstate = &rs->rstate;
 455         rs->flatshade = state->flatshade;
 456         rs->sprite_coord_enable = state->sprite_coord_enable;
 457
 458         /* offset */
 459         rs->offset_units = state->offset_units;
 460         rs->offset_scale = state->offset_scale * 12.0f;
 461
 462         rstate->id = R600_PIPE_STATE_RASTERIZER;
 463         if (state->flatshade_first)
 464                 prov_vtx = 0;
 465         tmp = 0x00000001;
 466         if (state->sprite_coord_enable) {
 467                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 468                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 469                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 470                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 471                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 472                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 473                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 474                 }
 475         }
 476         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
 477
 478         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 479                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 480         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 481                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 482                 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 483                 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 484                 S_028814_FACE(!state->front_ccw) |
 485                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 486                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 487                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 488                 S_028814_POLY_MODE(polygon_dual_mode) |
 489                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 490                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
 491         r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
 492                         S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 493                         S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
 494         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 495         /* point size 12.4 fixed point */
 496         tmp = (unsigned)(state->point_size * 8.0);
 497         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
 498         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
 499         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
 500         r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
 501         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 502         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
 503         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 504         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 505         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 506         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 507         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
 508         return rstate;
 509 }
 510
 511 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 512 {
 513         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 514         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 515
 516         if (state == NULL)
 517                 return;
 518
 519         rctx->flatshade = rs->flatshade;
 520         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 521         rctx->rasterizer = rs;
 522
 523         rctx->states[rs->rstate.id] = &rs->rstate;
 524         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 525 }
 526
 527 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 528 {
 529         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 530         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 531
 532         if (rctx->rasterizer == rs) {
 533                 rctx->rasterizer = NULL;
 534         }
 535         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 536                 rctx->states[rs->rstate.id] = NULL;
 537         }
 538         free(rs);
 539 }
 540
 541 static void *r600_create_sampler_state(struct pipe_context *ctx,
 542                                         const struct pipe_sampler_state *state)
 543 {
 544         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 545         union util_color uc;
 546
 547         if (rstate == NULL) {
 548                 return NULL;
 549         }
 550
 551         rstate->id = R600_PIPE_STATE_SAMPLER;
 552         util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 553         r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
 554                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 555                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 556                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 557                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
 558                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
 559                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 560                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 561                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
 562         /* FIXME LOD it depends on texture base level ... */
 563         r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
 564                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
 565                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 566                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
 567         r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
 568         if (uc.ui) {
 569                 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
 570                 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
 571                 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
 572                 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
 573         }
 574         return rstate;
 575 }
 576
 577 static void *r600_create_vertex_elements(struct pipe_context *ctx,
 578                                 unsigned count,
 579                                 const struct pipe_vertex_element *elements)
 580 {
 581         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 582
 583         assert(count < 32);
 584         v->count = count;
 585         v->refcount = 1;
 586         memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
 587         return v;
 588 }
 589
 590 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 591                                       struct pipe_sampler_view *state)
 592 {
 593         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 594
 595         pipe_resource_reference(&state->texture, NULL);
 596         FREE(resource);
 597 }
 598
 599 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
 600                                                         struct pipe_resource *texture,
 601                                                         const struct pipe_sampler_view *state)
 602 {
 603         struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
 604         struct r600_pipe_state *rstate;
 605         const struct util_format_description *desc;
 606         struct r600_resource_texture *tmp;
 607         struct r600_resource *rbuffer;
 608         unsigned format;
 609         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 610         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
 611         struct r600_bo *bo[2];
 612
 613         if (resource == NULL)
 614                 return NULL;
 615         rstate = &resource->state;
 616
 617         /* initialize base object */
 618         resource->base = *state;
 619         resource->base.texture = NULL;
 620         pipe_reference(NULL, &texture->reference);
 621         resource->base.texture = texture;
 622         resource->base.reference.count = 1;
 623         resource->base.context = ctx;
 624
 625         swizzle[0] = state->swizzle_r;
 626         swizzle[1] = state->swizzle_g;
 627         swizzle[2] = state->swizzle_b;
 628         swizzle[3] = state->swizzle_a;
 629         format = r600_translate_texformat(state->format,
 630                                           swizzle,
 631                                           &word4, &yuv_format);
 632         if (format == ~0) {
 633                 format = 0;
 634         }
 635         desc = util_format_description(state->format);
 636         if (desc == NULL) {
 637                 R600_ERR("unknow format %d\n", state->format);
 638         }
 639         tmp = (struct r600_resource_texture*)texture;
 640         rbuffer = &tmp->resource;
 641         bo[0] = rbuffer->bo;
 642         bo[1] = rbuffer->bo;
 643         /* FIXME depth texture decompression */
 644         if (tmp->depth) {
 645                 r600_texture_depth_flush(ctx, texture);
 646                 tmp = (struct r600_resource_texture*)texture;
 647                 rbuffer = &tmp->flushed_depth_texture->resource;
 648                 bo[0] = rbuffer->bo;
 649                 bo[1] = rbuffer->bo;
 650         }
 651         pitch = align(tmp->pitch[0] / tmp->bpt, 8);
 652
 653         /* FIXME properly handle first level != 0 */
 654         r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
 655                                 S_038000_DIM(r600_tex_dim(texture->target)) |
 656                                 S_038000_TILE_MODE(array_mode) |
 657                                 S_038000_TILE_TYPE(tile_type) |
 658                                 S_038000_PITCH((pitch / 8) - 1) |
 659                                 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
 660         r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
 661                                 S_038004_TEX_HEIGHT(texture->height0 - 1) |
 662                                 S_038004_TEX_DEPTH(texture->depth0 - 1) |
 663                                 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
 664         r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
 665                                 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
 666         r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
 667                                 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
 668         r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
 669                                 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
 670                                 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
 671                                 S_038010_REQUEST_SIZE(1) |
 672                                 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
 673         r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
 674                                 S_038014_LAST_LEVEL(state->last_level) |
 675                                 S_038014_BASE_ARRAY(0) |
 676                                 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
 677         r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
 678                                 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
 679
 680         return &resource->base;
 681 }
 682
 683 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
 684                                         struct pipe_sampler_view **views)
 685 {
 686         /* TODO */
 687         assert(1);
 688 }
 689
 690 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
 691                                         struct pipe_sampler_view **views)
 692 {
 693         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 694         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 695
 696         for (int i = 0; i < count; i++) {
 697                 if (resource[i]) {
 698                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
 699                 }
 700         }
 701 }
 702
 703 static void r600_bind_state(struct pipe_context *ctx, void *state)
 704 {
 705         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 706         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 707
 708         if (state == NULL)
 709                 return;
 710         rctx->states[rstate->id] = rstate;
 711         r600_context_pipe_state_set(&rctx->ctx, rstate);
 712 }
 713
 714 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
 715 {
 716         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 717         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 718
 719         for (int i = 0; i < count; i++) {
 720                 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
 721         }
 722 }
 723
 724 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
 725 {
 726         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 727         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 728
 729         /* TODO implement */
 730         for (int i = 0; i < count; i++) {
 731                 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
 732         }
 733 }
 734
 735 static void r600_delete_state(struct pipe_context *ctx, void *state)
 736 {
 737         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 738         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 739
 740         if (rctx->states[rstate->id] == rstate) {
 741                 rctx->states[rstate->id] = NULL;
 742         }
 743         for (int i = 0; i < rstate->nregs; i++) {
 744                 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
 745         }
 746         free(rstate);
 747 }
 748
 749 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 750 {
 751         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 752
 753         if (v == NULL)
 754                 return;
 755         if (--v->refcount)
 756                 return;
 757         free(v);
 758 }
 759
 760 static void r600_set_clip_state(struct pipe_context *ctx,
 761                                 const struct pipe_clip_state *state)
 762 {
 763         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 764         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 765
 766         if (rstate == NULL)
 767                 return;
 768
 769         rctx->clip = *state;
 770         rstate->id = R600_PIPE_STATE_CLIP;
 771         for (int i = 0; i < state->nr; i++) {
 772                 r600_pipe_state_add_reg(rstate,
 773                                         R_028E20_PA_CL_UCP0_X + i * 4,
 774                                         fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
 775                 r600_pipe_state_add_reg(rstate,
 776                                         R_028E24_PA_CL_UCP0_Y + i * 4,
 777                                         fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
 778                 r600_pipe_state_add_reg(rstate,
 779                                         R_028E28_PA_CL_UCP0_Z + i * 4,
 780                                         fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
 781                 r600_pipe_state_add_reg(rstate,
 782                                         R_028E2C_PA_CL_UCP0_W + i * 4,
 783                                         fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
 784         }
 785         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
 786                         S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
 787                         S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
 788                         S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
 789
 790         free(rctx->states[R600_PIPE_STATE_CLIP]);
 791         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
 792         r600_context_pipe_state_set(&rctx->ctx, rstate);
 793 }
 794
 795 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 796 {
 797         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 798         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 799
 800         r600_delete_vertex_element(ctx, rctx->vertex_elements);
 801         rctx->vertex_elements = v;
 802         if (v) {
 803                 v->refcount++;
 804 //              rctx->vs_rebuild = TRUE;
 805         }
 806 }
 807
 808 static void r600_set_polygon_stipple(struct pipe_context *ctx,
 809                                          const struct pipe_poly_stipple *state)
 810 {
 811 }
 812
 813 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 814 {
 815 }
 816
 817 static void r600_set_scissor_state(struct pipe_context *ctx,
 818                                         const struct pipe_scissor_state *state)
 819 {
 820         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 821         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 822         u32 tl, br;
 823
 824         if (rstate == NULL)
 825                 return;
 826
 827         rstate->id = R600_PIPE_STATE_SCISSOR;
 828         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 829         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 830         r600_pipe_state_add_reg(rstate,
 831                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
 832                                 0xFFFFFFFF, NULL);
 833         r600_pipe_state_add_reg(rstate,
 834                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
 835                                 0xFFFFFFFF, NULL);
 836         r600_pipe_state_add_reg(rstate,
 837                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
 838                                 0xFFFFFFFF, NULL);
 839         r600_pipe_state_add_reg(rstate,
 840                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
 841                                 0xFFFFFFFF, NULL);
 842         r600_pipe_state_add_reg(rstate,
 843                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
 844                                 0xFFFFFFFF, NULL);
 845         r600_pipe_state_add_reg(rstate,
 846                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
 847                                 0xFFFFFFFF, NULL);
 848         r600_pipe_state_add_reg(rstate,
 849                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
 850                                 0xFFFFFFFF, NULL);
 851         r600_pipe_state_add_reg(rstate,
 852                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
 853                                 0xFFFFFFFF, NULL);
 854         r600_pipe_state_add_reg(rstate,
 855                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
 856                                 0xFFFFFFFF, NULL);
 857         r600_pipe_state_add_reg(rstate,
 858                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
 859                                 0xFFFFFFFF, NULL);
 860         r600_pipe_state_add_reg(rstate,
 861                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
 862                                 0xFFFFFFFF, NULL);
 863         r600_pipe_state_add_reg(rstate,
 864                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
 865                                 0xFFFFFFFF, NULL);
 866         r600_pipe_state_add_reg(rstate,
 867                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
 868                                 0xFFFFFFFF, NULL);
 869         r600_pipe_state_add_reg(rstate,
 870                                 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
 871                                 0xFFFFFFFF, NULL);
 872         if (rctx->family >= CHIP_RV770) {
 873                 r600_pipe_state_add_reg(rstate,
 874                                         R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
 875                                         0xFFFFFFFF, NULL);
 876         }
 877
 878         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
 879         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
 880         r600_context_pipe_state_set(&rctx->ctx, rstate);
 881 }
 882
 883 static void r600_set_stencil_ref(struct pipe_context *ctx,
 884                                 const struct pipe_stencil_ref *state)
 885 {
 886         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 887         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 888         u32 tmp;
 889
 890         if (rstate == NULL)
 891                 return;
 892
 893         rctx->stencil_ref = *state;
 894         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 895         tmp = S_028430_STENCILREF(state->ref_value[0]);
 896         r600_pipe_state_add_reg(rstate,
 897                                 R_028430_DB_STENCILREFMASK, tmp,
 898                                 ~C_028430_STENCILREF, NULL);
 899         tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
 900         r600_pipe_state_add_reg(rstate,
 901                                 R_028434_DB_STENCILREFMASK_BF, tmp,
 902                                 ~C_028434_STENCILREF_BF, NULL);
 903
 904         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 905         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 906         r600_context_pipe_state_set(&rctx->ctx, rstate);
 907 }
 908
 909 static void r600_set_viewport_state(struct pipe_context *ctx,
 910                                         const struct pipe_viewport_state *state)
 911 {
 912         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 913         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 914
 915         if (rstate == NULL)
 916                 return;
 917
 918         rctx->viewport = *state;
 919         rstate->id = R600_PIPE_STATE_VIEWPORT;
 920         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
 921         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
 922         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
 923         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
 924         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
 925         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
 926         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
 927         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
 928         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
 929
 930         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
 931         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
 932         r600_context_pipe_state_set(&rctx->ctx, rstate);
 933 }
 934
 935 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 936                         const struct pipe_framebuffer_state *state, int cb)
 937 {
 938         struct r600_resource_texture *rtex;
 939         struct r600_resource *rbuffer;
 940         unsigned level = state->cbufs[cb]->level;
 941         unsigned pitch, slice;
 942         unsigned color_info;
 943         unsigned format, swap, ntype;
 944         const struct util_format_description *desc;
 945         struct r600_bo *bo[3];
 946
 947         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
 948         rbuffer = &rtex->resource;
 949         bo[0] = rbuffer->bo;
 950         bo[1] = rbuffer->bo;
 951         bo[2] = rbuffer->bo;
 952
 953         pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 954         slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
 955         ntype = 0;
 956         desc = util_format_description(rtex->resource.base.b.format);
 957         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 958                 ntype = V_0280A0_NUMBER_SRGB;
 959
 960         format = r600_translate_colorformat(rtex->resource.base.b.format);
 961         swap = r600_translate_colorswap(rtex->resource.base.b.format);
 962         color_info = S_0280A0_FORMAT(format) |
 963                 S_0280A0_COMP_SWAP(swap) |
 964                 S_0280A0_BLEND_CLAMP(1) |
 965                 S_0280A0_NUMBER_TYPE(ntype);
 966         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 967                 color_info |= S_0280A0_SOURCE_FORMAT(1);
 968
 969         r600_pipe_state_add_reg(rstate,
 970                                 R_028040_CB_COLOR0_BASE + cb * 4,
 971                                 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
 972         r600_pipe_state_add_reg(rstate,
 973                                 R_0280A0_CB_COLOR0_INFO + cb * 4,
 974                                 color_info, 0xFFFFFFFF, bo[0]);
 975         r600_pipe_state_add_reg(rstate,
 976                                 R_028060_CB_COLOR0_SIZE + cb * 4,
 977                                 S_028060_PITCH_TILE_MAX(pitch) |
 978                                 S_028060_SLICE_TILE_MAX(slice),
 979                                 0xFFFFFFFF, NULL);
 980         r600_pipe_state_add_reg(rstate,
 981                                 R_028080_CB_COLOR0_VIEW + cb * 4,
 982                                 0x00000000, 0xFFFFFFFF, NULL);
 983         r600_pipe_state_add_reg(rstate,
 984                                 R_0280E0_CB_COLOR0_FRAG + cb * 4,
 985                                 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
 986         r600_pipe_state_add_reg(rstate,
 987                                 R_0280C0_CB_COLOR0_TILE + cb * 4,
 988                                 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
 989         r600_pipe_state_add_reg(rstate,
 990                                 R_028100_CB_COLOR0_MASK + cb * 4,
 991                                 0x00000000, 0xFFFFFFFF, NULL);
 992 }
 993
 994 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 995                         const struct pipe_framebuffer_state *state)
 996 {
 997         struct r600_resource_texture *rtex;
 998         struct r600_resource *rbuffer;
 999         unsigned level;
1000         unsigned pitch, slice, format;
1001
1002         if (state->zsbuf == NULL)
1003                 return;
1004
1005         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1006         rtex->tiled = 1;
1007         rtex->array_mode = 2;
1008         rtex->tile_type = 1;
1009         rtex->depth = 1;
1010         rbuffer = &rtex->resource;
1011
1012         level = state->zsbuf->level;
1013         pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1014         slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
1015         format = r600_translate_dbformat(state->zsbuf->texture->format);
1016
1017         r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1018                                 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1019         r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1020                                 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1021                                 0xFFFFFFFF, NULL);
1022         r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1023         r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1024                                 S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
1025                                 0xFFFFFFFF, rbuffer->bo);
1026         r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1027                                 (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
1028 }
1029
1030 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1031                                         const struct pipe_framebuffer_state *state)
1032 {
1033         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1034         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1035         u32 shader_mask, tl, br, shader_control, target_mask;
1036
1037         if (rstate == NULL)
1038                 return;
1039
1040         /* unreference old buffer and reference new one */
1041         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1042         for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1043                 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
1044         }
1045         for (int i = 0; i < state->nr_cbufs; i++) {
1046                 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
1047         }
1048         pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
1049         rctx->framebuffer = *state;
1050         rctx->pframebuffer = &rctx->framebuffer;
1051
1052         /* build states */
1053         for (int i = 0; i < state->nr_cbufs; i++) {
1054                 r600_cb(rctx, rstate, state, i);
1055         }
1056         if (state->zsbuf) {
1057                 r600_db(rctx, rstate, state);
1058         }
1059
1060         target_mask = 0x00000000;
1061         target_mask = 0xFFFFFFFF;
1062         shader_mask = 0;
1063         shader_control = 0;
1064         for (int i = 0; i < state->nr_cbufs; i++) {
1065                 target_mask ^= 0xf << (i * 4);
1066                 shader_mask |= 0xf << (i * 4);
1067                 shader_control |= 1 << i;
1068         }
1069         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1070         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1071
1072         r600_pipe_state_add_reg(rstate,
1073                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1074                                 0xFFFFFFFF, NULL);
1075         r600_pipe_state_add_reg(rstate,
1076                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1077                                 0xFFFFFFFF, NULL);
1078         r600_pipe_state_add_reg(rstate,
1079                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1080                                 0xFFFFFFFF, NULL);
1081         r600_pipe_state_add_reg(rstate,
1082                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1083                                 0xFFFFFFFF, NULL);
1084
1085         r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1086                                 shader_control, 0xFFFFFFFF, NULL);
1087         r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1088                                 0x00000000, target_mask, NULL);
1089         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1090                                 shader_mask, 0xFFFFFFFF, NULL);
1091         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1092                                 0x00000000, 0xFFFFFFFF, NULL);
1093         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1094                                 0x00000000, 0xFFFFFFFF, NULL);
1095         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1096                                 0x00000000, 0xFFFFFFFF, NULL);
1097         r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1098                                 0x01000000, 0xFFFFFFFF, NULL);
1099         r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1100                                 0x00000000, 0xFFFFFFFF, NULL);
1101         r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1102                                 0x000000FF, 0xFFFFFFFF, NULL);
1103         r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1104                                 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1105         r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1106                                 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1107
1108         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1109         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1110         r600_context_pipe_state_set(&rctx->ctx, rstate);
1111 }
1112
1113 static void r600_set_index_buffer(struct pipe_context *ctx,
1114                                   const struct pipe_index_buffer *ib)
1115 {
1116         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1117
1118         if (ib) {
1119                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1120                 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1121         } else {
1122                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1123                 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1124         }
1125
1126         /* TODO make this more like a state */
1127 }
1128
1129 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1130                                         const struct pipe_vertex_buffer *buffers)
1131 {
1132         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1133
1134         for (int i = 0; i < rctx->nvertex_buffer; i++) {
1135                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1136         }
1137         memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1138         for (int i = 0; i < count; i++) {
1139                 rctx->vertex_buffer[i].buffer = NULL;
1140                 if (r600_buffer_is_user_buffer(buffers[i].buffer))
1141                         rctx->any_user_vbs = TRUE;
1142                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1143         }
1144         rctx->nvertex_buffer = count;
1145 }
1146
1147 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1148                                         struct pipe_resource *buffer)
1149 {
1150         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1151         struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1152
1153         switch (shader) {
1154         case PIPE_SHADER_VERTEX:
1155                 rctx->vs_const_buffer.nregs = 0;
1156                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1157                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1158                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
1159                                         0xFFFFFFFF, NULL);
1160                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1161                                         R_028980_ALU_CONST_CACHE_VS_0,
1162                                         r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1163                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1164                 break;
1165         case PIPE_SHADER_FRAGMENT:
1166                 rctx->ps_const_buffer.nregs = 0;
1167                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1168                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1169                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
1170                                         0xFFFFFFFF, NULL);
1171                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1172                                         R_028940_ALU_CONST_CACHE_PS_0,
1173                                         r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1174                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1175                 break;
1176         default:
1177                 R600_ERR("unsupported %d\n", shader);
1178                 return;
1179         }
1180 }
1181
1182 static void *r600_create_shader_state(struct pipe_context *ctx,
1183                                         const struct pipe_shader_state *state)
1184 {
1185         struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
1186         int r;
1187
1188         r =  r600_pipe_shader_create(ctx, shader, state->tokens);
1189         if (r) {
1190                 return NULL;
1191         }
1192         return shader;
1193 }
1194
1195 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1196 {
1197         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1198
1199         /* TODO delete old shader */
1200         rctx->ps_shader = (struct r600_pipe_shader *)state;
1201 }
1202
1203 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1204 {
1205         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1206
1207         /* TODO delete old shader */
1208         rctx->vs_shader = (struct r600_pipe_shader *)state;
1209 }
1210
1211 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1212 {
1213         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1214         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1215
1216         if (rctx->ps_shader == shader) {
1217                 rctx->ps_shader = NULL;
1218         }
1219         /* TODO proper delete */
1220         free(shader);
1221 }
1222
1223 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1224 {
1225         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1226         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1227
1228         if (rctx->vs_shader == shader) {
1229                 rctx->vs_shader = NULL;
1230         }
1231         /* TODO proper delete */
1232         free(shader);
1233 }
1234
1235 void r600_init_state_functions(struct r600_pipe_context *rctx)
1236 {
1237         rctx->context.create_blend_state = r600_create_blend_state;
1238         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1239         rctx->context.create_fs_state = r600_create_shader_state;
1240         rctx->context.create_rasterizer_state = r600_create_rs_state;
1241         rctx->context.create_sampler_state = r600_create_sampler_state;
1242         rctx->context.create_sampler_view = r600_create_sampler_view;
1243         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1244         rctx->context.create_vs_state = r600_create_shader_state;
1245         rctx->context.bind_blend_state = r600_bind_blend_state;
1246         rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1247         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1248         rctx->context.bind_fs_state = r600_bind_ps_shader;
1249         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1250         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1251         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1252         rctx->context.bind_vs_state = r600_bind_vs_shader;
1253         rctx->context.delete_blend_state = r600_delete_state;
1254         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1255         rctx->context.delete_fs_state = r600_delete_ps_shader;
1256         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1257         rctx->context.delete_sampler_state = r600_delete_state;
1258         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1259         rctx->context.delete_vs_state = r600_delete_vs_shader;
1260         rctx->context.set_blend_color = r600_set_blend_color;
1261         rctx->context.set_clip_state = r600_set_clip_state;
1262         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1263         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1264         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1265         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1266         rctx->context.set_sample_mask = r600_set_sample_mask;
1267         rctx->context.set_scissor_state = r600_set_scissor_state;
1268         rctx->context.set_stencil_ref = r600_set_stencil_ref;
1269         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1270         rctx->context.set_index_buffer = r600_set_index_buffer;
1271         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1272         rctx->context.set_viewport_state = r600_set_viewport_state;
1273         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1274 }
1275
1276 void r600_init_config(struct r600_pipe_context *rctx)
1277 {
1278         int ps_prio;
1279         int vs_prio;
1280         int gs_prio;
1281         int es_prio;
1282         int num_ps_gprs;
1283         int num_vs_gprs;
1284         int num_gs_gprs;
1285         int num_es_gprs;
1286         int num_temp_gprs;
1287         int num_ps_threads;
1288         int num_vs_threads;
1289         int num_gs_threads;
1290         int num_es_threads;
1291         int num_ps_stack_entries;
1292         int num_vs_stack_entries;
1293         int num_gs_stack_entries;
1294         int num_es_stack_entries;
1295         enum radeon_family family;
1296         struct r600_pipe_state *rstate = &rctx->config;
1297         u32 tmp;
1298
1299         family = r600_get_family(rctx->radeon);
1300         ps_prio = 0;
1301         vs_prio = 1;
1302         gs_prio = 2;
1303         es_prio = 3;
1304         switch (family) {
1305         case CHIP_R600:
1306                 num_ps_gprs = 192;
1307                 num_vs_gprs = 56;
1308                 num_temp_gprs = 4;
1309                 num_gs_gprs = 0;
1310                 num_es_gprs = 0;
1311                 num_ps_threads = 136;
1312                 num_vs_threads = 48;
1313                 num_gs_threads = 4;
1314                 num_es_threads = 4;
1315                 num_ps_stack_entries = 128;
1316                 num_vs_stack_entries = 128;
1317                 num_gs_stack_entries = 0;
1318                 num_es_stack_entries = 0;
1319                 break;
1320         case CHIP_RV630:
1321         case CHIP_RV635:
1322                 num_ps_gprs = 84;
1323                 num_vs_gprs = 36;
1324                 num_temp_gprs = 4;
1325                 num_gs_gprs = 0;
1326                 num_es_gprs = 0;
1327                 num_ps_threads = 144;
1328                 num_vs_threads = 40;
1329                 num_gs_threads = 4;
1330                 num_es_threads = 4;
1331                 num_ps_stack_entries = 40;
1332                 num_vs_stack_entries = 40;
1333                 num_gs_stack_entries = 32;
1334                 num_es_stack_entries = 16;
1335                 break;
1336         case CHIP_RV610:
1337         case CHIP_RV620:
1338         case CHIP_RS780:
1339         case CHIP_RS880:
1340         default:
1341                 num_ps_gprs = 84;
1342                 num_vs_gprs = 36;
1343                 num_temp_gprs = 4;
1344                 num_gs_gprs = 0;
1345                 num_es_gprs = 0;
1346                 num_ps_threads = 136;
1347                 num_vs_threads = 48;
1348                 num_gs_threads = 4;
1349                 num_es_threads = 4;
1350                 num_ps_stack_entries = 40;
1351                 num_vs_stack_entries = 40;
1352                 num_gs_stack_entries = 32;
1353                 num_es_stack_entries = 16;
1354                 break;
1355         case CHIP_RV670:
1356                 num_ps_gprs = 144;
1357                 num_vs_gprs = 40;
1358                 num_temp_gprs = 4;
1359                 num_gs_gprs = 0;
1360                 num_es_gprs = 0;
1361                 num_ps_threads = 136;
1362                 num_vs_threads = 48;
1363                 num_gs_threads = 4;
1364                 num_es_threads = 4;
1365                 num_ps_stack_entries = 40;
1366                 num_vs_stack_entries = 40;
1367                 num_gs_stack_entries = 32;
1368                 num_es_stack_entries = 16;
1369                 break;
1370         case CHIP_RV770:
1371                 num_ps_gprs = 192;
1372                 num_vs_gprs = 56;
1373                 num_temp_gprs = 4;
1374                 num_gs_gprs = 0;
1375                 num_es_gprs = 0;
1376                 num_ps_threads = 188;
1377                 num_vs_threads = 60;
1378                 num_gs_threads = 0;
1379                 num_es_threads = 0;
1380                 num_ps_stack_entries = 256;
1381                 num_vs_stack_entries = 256;
1382                 num_gs_stack_entries = 0;
1383                 num_es_stack_entries = 0;
1384                 break;
1385         case CHIP_RV730:
1386         case CHIP_RV740:
1387                 num_ps_gprs = 84;
1388                 num_vs_gprs = 36;
1389                 num_temp_gprs = 4;
1390                 num_gs_gprs = 0;
1391                 num_es_gprs = 0;
1392                 num_ps_threads = 188;
1393                 num_vs_threads = 60;
1394                 num_gs_threads = 0;
1395                 num_es_threads = 0;
1396                 num_ps_stack_entries = 128;
1397                 num_vs_stack_entries = 128;
1398                 num_gs_stack_entries = 0;
1399                 num_es_stack_entries = 0;
1400                 break;
1401         case CHIP_RV710:
1402                 num_ps_gprs = 192;
1403                 num_vs_gprs = 56;
1404                 num_temp_gprs = 4;
1405                 num_gs_gprs = 0;
1406                 num_es_gprs = 0;
1407                 num_ps_threads = 144;
1408                 num_vs_threads = 48;
1409                 num_gs_threads = 0;
1410                 num_es_threads = 0;
1411                 num_ps_stack_entries = 128;
1412                 num_vs_stack_entries = 128;
1413                 num_gs_stack_entries = 0;
1414                 num_es_stack_entries = 0;
1415                 break;
1416         }
1417
1418         rstate->id = R600_PIPE_STATE_CONFIG;
1419
1420         /* SQ_CONFIG */
1421         tmp = 0;
1422         switch (family) {
1423         case CHIP_RV610:
1424         case CHIP_RV620:
1425         case CHIP_RS780:
1426         case CHIP_RS880:
1427         case CHIP_RV710:
1428                 break;
1429         default:
1430                 tmp |= S_008C00_VC_ENABLE(1);
1431                 break;
1432         }
1433         tmp |= S_008C00_DX9_CONSTS(0);
1434         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1435         tmp |= S_008C00_PS_PRIO(ps_prio);
1436         tmp |= S_008C00_VS_PRIO(vs_prio);
1437         tmp |= S_008C00_GS_PRIO(gs_prio);
1438         tmp |= S_008C00_ES_PRIO(es_prio);
1439         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1440
1441         /* SQ_GPR_RESOURCE_MGMT_1 */
1442         tmp = 0;
1443         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1444         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1445         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1446         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1447
1448         /* SQ_GPR_RESOURCE_MGMT_2 */
1449         tmp = 0;
1450         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1451         tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1452         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1453
1454         /* SQ_THREAD_RESOURCE_MGMT */
1455         tmp = 0;
1456         tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1457         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1458         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1459         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1460         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1461
1462         /* SQ_STACK_RESOURCE_MGMT_1 */
1463         tmp = 0;
1464         tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1465         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1466         r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1467
1468         /* SQ_STACK_RESOURCE_MGMT_2 */
1469         tmp = 0;
1470         tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1471         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1472         r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1473
1474         r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1475         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1476
1477         if (family >= CHIP_RV770) {
1478                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1479                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1480                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1481                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1482                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1483                 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
1484         } else {
1485                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1486                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1487                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1488                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1489                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1490                 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
1491         }
1492         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1493         r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1494         r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1495         r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1496         r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1497         r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1498         r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1499         r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1500         r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1501         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1502         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1503         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1504         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1505         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1506         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1507         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1508         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1509         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1510         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1511         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1512         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1513         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1514         r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1515         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1516         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1517         r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1518
1519         r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1520         r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1521         r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1522         r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1523         r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1524         r600_context_pipe_state_set(&rctx->ctx, rstate);
1525 }
1526
1527 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1528 {
1529         struct pipe_depth_stencil_alpha_state dsa;
1530         struct r600_pipe_state *rstate;
1531         boolean quirk = false;
1532
1533         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1534                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1535                 quirk = true;
1536
1537         memset(&dsa, 0, sizeof(dsa));
1538
1539         if (quirk) {
1540                 dsa.depth.enabled = 1;
1541                 dsa.depth.func = PIPE_FUNC_LEQUAL;
1542                 dsa.stencil[0].enabled = 1;
1543                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1544                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1545                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1546                 dsa.stencil[0].writemask = 0xff;
1547         }
1548
1549         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1550         r600_pipe_state_add_reg(rstate,
1551                                 R_02880C_DB_SHADER_CONTROL,
1552                                 0x0,
1553                                 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1554         r600_pipe_state_add_reg(rstate,
1555                                 R_028D0C_DB_RENDER_CONTROL,
1556                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
1557                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
1558                                 S_028D0C_COPY_CENTROID(1),
1559                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
1560                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
1561                                 S_028D0C_COPY_CENTROID(1), NULL);
1562         return rstate;
1563 }