2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
35 #include "r600_state_inlines.h"
37 static void *r600_create_blend_state(struct pipe_context
*ctx
,
38 const struct pipe_blend_state
*state
)
40 struct r600_context
*rctx
= r600_context(ctx
);
42 return r600_context_state(rctx
, pipe_blend_type
, state
);
45 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
46 const struct pipe_depth_stencil_alpha_state
*state
)
48 struct r600_context
*rctx
= r600_context(ctx
);
50 return r600_context_state(rctx
, pipe_dsa_type
, state
);
53 static void *r600_create_rs_state(struct pipe_context
*ctx
,
54 const struct pipe_rasterizer_state
*state
)
56 struct r600_context
*rctx
= r600_context(ctx
);
58 return r600_context_state(rctx
, pipe_rasterizer_type
, state
);
61 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
62 const struct pipe_sampler_state
*state
)
64 struct r600_context
*rctx
= r600_context(ctx
);
66 return r600_context_state(rctx
, pipe_sampler_type
, state
);
69 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
70 struct pipe_sampler_view
*state
)
72 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
74 r600_context_state_decref(rstate
);
77 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
78 struct pipe_resource
*texture
,
79 const struct pipe_sampler_view
*state
)
81 struct r600_context
*rctx
= r600_context(ctx
);
82 struct r600_context_state
*rstate
;
84 rstate
= r600_context_state(rctx
, pipe_sampler_type
, state
);
85 pipe_reference(NULL
, &texture
->reference
);
86 rstate
->state
.sampler_view
.texture
= texture
;
87 rstate
->state
.sampler_view
.reference
.count
= 1;
88 rstate
->state
.sampler_view
.context
= ctx
;
89 return &rstate
->state
.sampler_view
;
92 static void *r600_create_shader_state(struct pipe_context
*ctx
,
93 const struct pipe_shader_state
*state
)
95 struct r600_context
*rctx
= r600_context(ctx
);
97 return r600_context_state(rctx
, pipe_shader_type
, state
);
100 static void *r600_create_vertex_elements(struct pipe_context
*ctx
,
102 const struct pipe_vertex_element
*elements
)
104 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
108 memcpy(v
->elements
, elements
, count
* sizeof(struct pipe_vertex_element
));
113 static void r600_bind_state(struct pipe_context
*ctx
, void *state
)
115 struct r600_context
*rctx
= r600_context(ctx
);
116 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
120 switch (rstate
->type
) {
121 case pipe_rasterizer_type
:
122 rctx
->rasterizer
= r600_context_state_decref(rctx
->rasterizer
);
123 rctx
->rasterizer
= r600_context_state_incref(rstate
);
125 case pipe_poly_stipple_type
:
126 rctx
->poly_stipple
= r600_context_state_decref(rctx
->poly_stipple
);
127 rctx
->poly_stipple
= r600_context_state_incref(rstate
);
129 case pipe_scissor_type
:
130 rctx
->scissor
= r600_context_state_decref(rctx
->scissor
);
131 rctx
->scissor
= r600_context_state_incref(rstate
);
134 rctx
->clip
= r600_context_state_decref(rctx
->clip
);
135 rctx
->clip
= r600_context_state_incref(rstate
);
137 case pipe_depth_type
:
138 rctx
->depth
= r600_context_state_decref(rctx
->depth
);
139 rctx
->depth
= r600_context_state_incref(rstate
);
141 case pipe_stencil_type
:
142 rctx
->stencil
= r600_context_state_decref(rctx
->stencil
);
143 rctx
->stencil
= r600_context_state_incref(rstate
);
145 case pipe_alpha_type
:
146 rctx
->alpha
= r600_context_state_decref(rctx
->alpha
);
147 rctx
->alpha
= r600_context_state_incref(rstate
);
150 rctx
->dsa
= r600_context_state_decref(rctx
->dsa
);
151 rctx
->dsa
= r600_context_state_incref(rstate
);
153 case pipe_blend_type
:
154 rctx
->blend
= r600_context_state_decref(rctx
->blend
);
155 rctx
->blend
= r600_context_state_incref(rstate
);
157 case pipe_framebuffer_type
:
158 rctx
->framebuffer
= r600_context_state_decref(rctx
->framebuffer
);
159 rctx
->framebuffer
= r600_context_state_incref(rstate
);
161 case pipe_stencil_ref_type
:
162 rctx
->stencil_ref
= r600_context_state_decref(rctx
->stencil_ref
);
163 rctx
->stencil_ref
= r600_context_state_incref(rstate
);
165 case pipe_viewport_type
:
166 rctx
->viewport
= r600_context_state_decref(rctx
->viewport
);
167 rctx
->viewport
= r600_context_state_incref(rstate
);
169 case pipe_shader_type
:
170 case pipe_sampler_type
:
171 case pipe_sampler_view_type
:
173 R600_ERR("invalid type %d\n", rstate
->type
);
178 static void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
180 struct r600_context
*rctx
= r600_context(ctx
);
181 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
183 rctx
->ps_shader
= r600_context_state_decref(rctx
->ps_shader
);
184 rctx
->ps_shader
= r600_context_state_incref(rstate
);
187 static void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
189 struct r600_context
*rctx
= r600_context(ctx
);
190 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
192 rctx
->vs_shader
= r600_context_state_decref(rctx
->vs_shader
);
193 rctx
->vs_shader
= r600_context_state_incref(rstate
);
196 static void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
198 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
207 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
209 struct r600_context
*rctx
= r600_context(ctx
);
210 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
212 r600_delete_vertex_element(ctx
, rctx
->vertex_elements
);
213 rctx
->vertex_elements
= v
;
219 static void r600_bind_ps_sampler(struct pipe_context
*ctx
,
220 unsigned count
, void **states
)
222 struct r600_context
*rctx
= r600_context(ctx
);
223 struct r600_context_state
*rstate
;
226 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
227 rctx
->ps_sampler
[i
] = r600_context_state_decref(rctx
->ps_sampler
[i
]);
229 for (i
= 0; i
< count
; i
++) {
230 rstate
= (struct r600_context_state
*)states
[i
];
231 rctx
->ps_sampler
[i
] = r600_context_state_incref(rstate
);
233 rctx
->ps_nsampler
= count
;
236 static void r600_bind_vs_sampler(struct pipe_context
*ctx
,
237 unsigned count
, void **states
)
239 struct r600_context
*rctx
= r600_context(ctx
);
240 struct r600_context_state
*rstate
;
243 for (i
= 0; i
< rctx
->vs_nsampler
; i
++) {
244 rctx
->vs_sampler
[i
] = r600_context_state_decref(rctx
->vs_sampler
[i
]);
246 for (i
= 0; i
< count
; i
++) {
247 rstate
= (struct r600_context_state
*)states
[i
];
248 rctx
->vs_sampler
[i
] = r600_context_state_incref(rstate
);
250 rctx
->vs_nsampler
= count
;
253 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
255 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
257 r600_context_state_decref(rstate
);
260 static void r600_set_blend_color(struct pipe_context
*ctx
,
261 const struct pipe_blend_color
*color
)
263 struct r600_context
*rctx
= r600_context(ctx
);
265 rctx
->blend_color
= *color
;
268 static void r600_set_clip_state(struct pipe_context
*ctx
,
269 const struct pipe_clip_state
*state
)
271 struct r600_context
*rctx
= r600_context(ctx
);
272 struct r600_context_state
*rstate
;
274 rstate
= r600_context_state(rctx
, pipe_clip_type
, state
);
275 r600_bind_state(ctx
, rstate
);
276 /* refcount is taken care of this */
277 r600_delete_state(ctx
, rstate
);
280 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
281 uint shader
, uint index
,
282 struct pipe_resource
*buffer
)
284 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
285 struct r600_context
*rctx
= r600_context(ctx
);
286 unsigned nconstant
= 0, i
, type
, shader_class
;
287 struct radeon_state
*rstate
;
288 struct pipe_transfer
*transfer
;
291 type
= R600_STATE_CONSTANT
;
294 case PIPE_SHADER_VERTEX
:
295 shader_class
= R600_SHADER_VS
;
297 case PIPE_SHADER_FRAGMENT
:
298 shader_class
= R600_SHADER_PS
;
301 R600_ERR("unsupported %d\n", shader
);
304 if (buffer
&& buffer
->width0
> 0) {
305 nconstant
= buffer
->width0
/ 16;
306 ptr
= pipe_buffer_map(ctx
, buffer
, PIPE_TRANSFER_READ
, &transfer
);
309 for (i
= 0; i
< nconstant
; i
++) {
310 rstate
= radeon_state_shader(rscreen
->rw
, type
, i
, shader_class
);
313 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0
] = ptr
[i
* 4 + 0];
314 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0
] = ptr
[i
* 4 + 1];
315 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0
] = ptr
[i
* 4 + 2];
316 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0
] = ptr
[i
* 4 + 3];
317 if (radeon_state_pm4(rstate
))
319 if (radeon_draw_set_new(rctx
->draw
, rstate
))
322 pipe_buffer_unmap(ctx
, buffer
, transfer
);
326 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
,
328 struct pipe_sampler_view
**views
)
330 struct r600_context
*rctx
= r600_context(ctx
);
331 struct r600_context_state
*rstate
;
334 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
335 rctx
->ps_sampler_view
[i
] = r600_context_state_decref(rctx
->ps_sampler_view
[i
]);
337 for (i
= 0; i
< count
; i
++) {
338 rstate
= (struct r600_context_state
*)views
[i
];
339 rctx
->ps_sampler_view
[i
] = r600_context_state_incref(rstate
);
341 rctx
->ps_nsampler_view
= count
;
344 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
,
346 struct pipe_sampler_view
**views
)
348 struct r600_context
*rctx
= r600_context(ctx
);
349 struct r600_context_state
*rstate
;
352 for (i
= 0; i
< rctx
->vs_nsampler_view
; i
++) {
353 rctx
->vs_sampler_view
[i
] = r600_context_state_decref(rctx
->vs_sampler_view
[i
]);
355 for (i
= 0; i
< count
; i
++) {
356 rstate
= (struct r600_context_state
*)views
[i
];
357 rctx
->vs_sampler_view
[i
] = r600_context_state_incref(rstate
);
359 rctx
->vs_nsampler_view
= count
;
362 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
363 const struct pipe_framebuffer_state
*state
)
365 struct r600_context
*rctx
= r600_context(ctx
);
366 struct r600_context_state
*rstate
;
368 rstate
= r600_context_state(rctx
, pipe_framebuffer_type
, state
);
369 r600_bind_state(ctx
, rstate
);
372 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
373 const struct pipe_poly_stipple
*state
)
377 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
381 static void r600_set_scissor_state(struct pipe_context
*ctx
,
382 const struct pipe_scissor_state
*state
)
384 struct r600_context
*rctx
= r600_context(ctx
);
385 struct r600_context_state
*rstate
;
387 rstate
= r600_context_state(rctx
, pipe_scissor_type
, state
);
388 r600_bind_state(ctx
, rstate
);
389 /* refcount is taken care of this */
390 r600_delete_state(ctx
, rstate
);
393 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
394 const struct pipe_stencil_ref
*state
)
396 struct r600_context
*rctx
= r600_context(ctx
);
397 struct r600_context_state
*rstate
;
399 rstate
= r600_context_state(rctx
, pipe_stencil_ref_type
, state
);
400 r600_bind_state(ctx
, rstate
);
401 /* refcount is taken care of this */
402 r600_delete_state(ctx
, rstate
);
405 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
407 const struct pipe_vertex_buffer
*buffers
)
409 struct r600_context
*rctx
= r600_context(ctx
);
412 for (i
= 0; i
< rctx
->nvertex_buffer
; i
++) {
413 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, NULL
);
415 memcpy(rctx
->vertex_buffer
, buffers
, sizeof(struct pipe_vertex_buffer
) * count
);
416 for (i
= 0; i
< count
; i
++) {
417 rctx
->vertex_buffer
[i
].buffer
= NULL
;
418 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, buffers
[i
].buffer
);
420 rctx
->nvertex_buffer
= count
;
423 static void r600_set_index_buffer(struct pipe_context
*ctx
,
424 const struct pipe_index_buffer
*ib
)
426 struct r600_context
*rctx
= r600_context(ctx
);
429 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
430 memcpy(&rctx
->index_buffer
, ib
, sizeof(rctx
->index_buffer
));
432 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
433 memset(&rctx
->index_buffer
, 0, sizeof(rctx
->index_buffer
));
436 /* TODO make this more like a state */
439 static void r600_set_viewport_state(struct pipe_context
*ctx
,
440 const struct pipe_viewport_state
*state
)
442 struct r600_context
*rctx
= r600_context(ctx
);
443 struct r600_context_state
*rstate
;
445 rstate
= r600_context_state(rctx
, pipe_viewport_type
, state
);
446 r600_bind_state(ctx
, rstate
);
447 r600_delete_state(ctx
, rstate
);
450 void r600_init_state_functions(struct r600_context
*rctx
)
452 rctx
->context
.create_blend_state
= r600_create_blend_state
;
453 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
454 rctx
->context
.create_fs_state
= r600_create_shader_state
;
455 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
456 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
457 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
458 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
459 rctx
->context
.create_vs_state
= r600_create_shader_state
;
460 rctx
->context
.bind_blend_state
= r600_bind_state
;
461 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
462 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
463 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
464 rctx
->context
.bind_rasterizer_state
= r600_bind_state
;
465 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
466 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
467 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
468 rctx
->context
.delete_blend_state
= r600_delete_state
;
469 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
470 rctx
->context
.delete_fs_state
= r600_delete_state
;
471 rctx
->context
.delete_rasterizer_state
= r600_delete_state
;
472 rctx
->context
.delete_sampler_state
= r600_delete_state
;
473 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
474 rctx
->context
.delete_vs_state
= r600_delete_state
;
475 rctx
->context
.set_blend_color
= r600_set_blend_color
;
476 rctx
->context
.set_clip_state
= r600_set_clip_state
;
477 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
478 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
479 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
480 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
481 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
482 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
483 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
484 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
485 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
486 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
487 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
488 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
491 struct r600_context_state
*r600_context_state_incref(struct r600_context_state
*rstate
)
499 struct r600_context_state
*r600_context_state_decref(struct r600_context_state
*rstate
)
505 if (--rstate
->refcount
)
507 switch (rstate
->type
) {
508 case pipe_sampler_view_type
:
509 pipe_resource_reference(&rstate
->state
.sampler_view
.texture
, NULL
);
511 case pipe_framebuffer_type
:
512 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
513 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
], NULL
);
515 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
, NULL
);
517 case pipe_viewport_type
:
518 case pipe_depth_type
:
519 case pipe_rasterizer_type
:
520 case pipe_poly_stipple_type
:
521 case pipe_scissor_type
:
523 case pipe_stencil_type
:
524 case pipe_alpha_type
:
526 case pipe_blend_type
:
527 case pipe_stencil_ref_type
:
528 case pipe_shader_type
:
529 case pipe_sampler_type
:
532 R600_ERR("invalid type %d\n", rstate
->type
);
535 radeon_state_decref(rstate
->rstate
);
540 struct r600_context_state
*r600_context_state(struct r600_context
*rctx
, unsigned type
, const void *state
)
542 struct r600_context_state
*rstate
= CALLOC_STRUCT(r600_context_state
);
543 const union pipe_states
*states
= state
;
550 rstate
->refcount
= 1;
552 switch (rstate
->type
) {
553 case pipe_sampler_view_type
:
554 rstate
->state
.sampler_view
= (*states
).sampler_view
;
555 rstate
->state
.sampler_view
.texture
= NULL
;
557 case pipe_framebuffer_type
:
558 rstate
->state
.framebuffer
= (*states
).framebuffer
;
559 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
560 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
],
561 (*states
).framebuffer
.cbufs
[i
]);
563 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
,
564 (*states
).framebuffer
.zsbuf
);
566 case pipe_viewport_type
:
567 rstate
->state
.viewport
= (*states
).viewport
;
569 case pipe_depth_type
:
570 rstate
->state
.depth
= (*states
).depth
;
572 case pipe_rasterizer_type
:
573 rstate
->state
.rasterizer
= (*states
).rasterizer
;
575 case pipe_poly_stipple_type
:
576 rstate
->state
.poly_stipple
= (*states
).poly_stipple
;
578 case pipe_scissor_type
:
579 rstate
->state
.scissor
= (*states
).scissor
;
582 rstate
->state
.clip
= (*states
).clip
;
584 case pipe_stencil_type
:
585 rstate
->state
.stencil
= (*states
).stencil
;
587 case pipe_alpha_type
:
588 rstate
->state
.alpha
= (*states
).alpha
;
591 rstate
->state
.dsa
= (*states
).dsa
;
593 case pipe_blend_type
:
594 rstate
->state
.blend
= (*states
).blend
;
596 case pipe_stencil_ref_type
:
597 rstate
->state
.stencil_ref
= (*states
).stencil_ref
;
599 case pipe_shader_type
:
600 rstate
->state
.shader
= (*states
).shader
;
601 r
= r600_pipe_shader_create(&rctx
->context
, rstate
, rstate
->state
.shader
.tokens
);
603 r600_context_state_decref(rstate
);
607 case pipe_sampler_type
:
608 rstate
->state
.sampler
= (*states
).sampler
;
611 R600_ERR("invalid type %d\n", rstate
->type
);
618 static struct radeon_state
*r600_blend(struct r600_context
*rctx
)
620 struct r600_screen
*rscreen
= rctx
->screen
;
621 struct radeon_state
*rstate
;
622 const struct pipe_blend_state
*state
= &rctx
->blend
->state
.blend
;
625 rstate
= radeon_state(rscreen
->rw
, R600_STATE_BLEND
, 0);
628 rstate
->states
[R600_BLEND__CB_BLEND_RED
] = fui(rctx
->blend_color
.color
[0]);
629 rstate
->states
[R600_BLEND__CB_BLEND_GREEN
] = fui(rctx
->blend_color
.color
[1]);
630 rstate
->states
[R600_BLEND__CB_BLEND_BLUE
] = fui(rctx
->blend_color
.color
[2]);
631 rstate
->states
[R600_BLEND__CB_BLEND_ALPHA
] = fui(rctx
->blend_color
.color
[3]);
632 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
] = 0x00000000;
633 rstate
->states
[R600_BLEND__CB_BLEND1_CONTROL
] = 0x00000000;
634 rstate
->states
[R600_BLEND__CB_BLEND2_CONTROL
] = 0x00000000;
635 rstate
->states
[R600_BLEND__CB_BLEND3_CONTROL
] = 0x00000000;
636 rstate
->states
[R600_BLEND__CB_BLEND4_CONTROL
] = 0x00000000;
637 rstate
->states
[R600_BLEND__CB_BLEND5_CONTROL
] = 0x00000000;
638 rstate
->states
[R600_BLEND__CB_BLEND6_CONTROL
] = 0x00000000;
639 rstate
->states
[R600_BLEND__CB_BLEND7_CONTROL
] = 0x00000000;
640 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = 0x00000000;
642 for (i
= 0; i
< 8; i
++) {
643 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
644 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
645 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
647 unsigned eqA
= state
->rt
[i
].alpha_func
;
648 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
649 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
652 if (!state
->rt
[i
].blend_enable
)
655 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
656 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
657 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
659 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
660 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
661 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
662 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
663 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
666 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
+ i
] = bc
;
668 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = bc
;
671 if (radeon_state_pm4(rstate
)) {
672 radeon_state_decref(rstate
);
678 static struct radeon_state
*r600_ucp(struct r600_context
*rctx
, int clip
)
680 struct r600_screen
*rscreen
= rctx
->screen
;
681 struct radeon_state
*rstate
;
682 const struct pipe_clip_state
*state
= &rctx
->clip
->state
.clip
;
684 rstate
= radeon_state(rscreen
->rw
, R600_STATE_CLIP
, clip
);
688 rstate
->states
[R600_CLIP__PA_CL_UCP_X_0
] = fui(state
->ucp
[clip
][0]);
689 rstate
->states
[R600_CLIP__PA_CL_UCP_Y_0
] = fui(state
->ucp
[clip
][1]);
690 rstate
->states
[R600_CLIP__PA_CL_UCP_Z_0
] = fui(state
->ucp
[clip
][2]);
691 rstate
->states
[R600_CLIP__PA_CL_UCP_W_0
] = fui(state
->ucp
[clip
][3]);
693 if (radeon_state_pm4(rstate
)) {
694 radeon_state_decref(rstate
);
701 static struct radeon_state
*r600_cb(struct r600_context
*rctx
, int cb
)
703 struct r600_screen
*rscreen
= rctx
->screen
;
704 struct r600_resource_texture
*rtex
;
705 struct r600_resource
*rbuffer
;
706 struct radeon_state
*rstate
;
707 const struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
->state
.framebuffer
;
708 unsigned level
= state
->cbufs
[cb
]->level
;
709 unsigned pitch
, slice
;
711 unsigned format
, swap
, ntype
;
712 const struct util_format_description
*desc
;
714 rstate
= radeon_state(rscreen
->rw
, R600_STATE_CB0
+ cb
, 0);
717 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
718 rbuffer
= &rtex
->resource
;
719 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
720 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
721 rstate
->bo
[2] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
722 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
723 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
724 rstate
->placement
[4] = RADEON_GEM_DOMAIN_GTT
;
726 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
727 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->cbufs
[cb
]->height
/ 64 - 1;
730 desc
= util_format_description(rtex
->resource
.base
.b
.format
);
731 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
732 ntype
= V_0280A0_NUMBER_SRGB
;
734 format
= r600_translate_colorformat(rtex
->resource
.base
.b
.format
);
735 swap
= r600_translate_colorswap(rtex
->resource
.base
.b
.format
);
737 color_info
= S_0280A0_FORMAT(format
) |
738 S_0280A0_COMP_SWAP(swap
) |
739 S_0280A0_BLEND_CLAMP(1) |
740 S_0280A0_SOURCE_FORMAT(1) |
741 S_0280A0_NUMBER_TYPE(ntype
);
743 rstate
->states
[R600_CB0__CB_COLOR0_BASE
] = rtex
->offset
[level
] >> 8;
744 rstate
->states
[R600_CB0__CB_COLOR0_INFO
] = color_info
;
745 rstate
->states
[R600_CB0__CB_COLOR0_SIZE
] = S_028060_PITCH_TILE_MAX(pitch
) |
746 S_028060_SLICE_TILE_MAX(slice
);
747 rstate
->states
[R600_CB0__CB_COLOR0_VIEW
] = 0x00000000;
748 rstate
->states
[R600_CB0__CB_COLOR0_FRAG
] = 0x00000000;
749 rstate
->states
[R600_CB0__CB_COLOR0_TILE
] = 0x00000000;
750 rstate
->states
[R600_CB0__CB_COLOR0_MASK
] = 0x00000000;
751 if (radeon_state_pm4(rstate
)) {
752 radeon_state_decref(rstate
);
758 static struct radeon_state
*r600_db(struct r600_context
*rctx
)
760 struct r600_screen
*rscreen
= rctx
->screen
;
761 struct r600_resource_texture
*rtex
;
762 struct r600_resource
*rbuffer
;
763 struct radeon_state
*rstate
;
764 const struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
->state
.framebuffer
;
766 unsigned pitch
, slice
, format
;
768 if (state
->zsbuf
== NULL
)
771 rstate
= radeon_state(rscreen
->rw
, R600_STATE_DB
, 0);
775 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
777 rtex
->array_mode
= 2;
780 rbuffer
= &rtex
->resource
;
782 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
784 rstate
->placement
[0] = RADEON_GEM_DOMAIN_VRAM
;
785 level
= state
->zsbuf
->level
;
786 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
787 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->zsbuf
->height
/ 64 - 1;
788 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
789 rstate
->states
[R600_DB__DB_DEPTH_BASE
] = rtex
->offset
[level
] >> 8;
790 rstate
->states
[R600_DB__DB_DEPTH_INFO
] = S_028010_ARRAY_MODE(rtex
->array_mode
) |
791 S_028010_FORMAT(format
);
792 rstate
->states
[R600_DB__DB_DEPTH_VIEW
] = 0x00000000;
793 rstate
->states
[R600_DB__DB_PREFETCH_LIMIT
] = (state
->zsbuf
->height
/ 8) -1;
794 rstate
->states
[R600_DB__DB_DEPTH_SIZE
] = S_028000_PITCH_TILE_MAX(pitch
) |
795 S_028000_SLICE_TILE_MAX(slice
);
796 if (radeon_state_pm4(rstate
)) {
797 radeon_state_decref(rstate
);
803 static struct radeon_state
*r600_rasterizer(struct r600_context
*rctx
)
805 const struct pipe_rasterizer_state
*state
= &rctx
->rasterizer
->state
.rasterizer
;
806 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
807 const struct pipe_clip_state
*clip
= NULL
;
808 struct r600_screen
*rscreen
= rctx
->screen
;
809 struct radeon_state
*rstate
;
810 float offset_units
= 0, offset_scale
= 0;
812 unsigned offset_db_fmt_cntl
= 0;
814 unsigned prov_vtx
= 1;
817 clip
= &rctx
->clip
->state
.clip
;
819 offset_units
= state
->offset_units
;
820 offset_scale
= state
->offset_scale
* 12.0f
;
821 switch (fb
->zsbuf
->texture
->format
) {
822 case PIPE_FORMAT_Z24X8_UNORM
:
823 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
825 offset_units
*= 2.0f
;
827 case PIPE_FORMAT_Z32_FLOAT
:
829 offset_units
*= 1.0f
;
830 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
832 case PIPE_FORMAT_Z16_UNORM
:
834 offset_units
*= 4.0f
;
837 R600_ERR("unsupported %d\n", fb
->zsbuf
->texture
->format
);
841 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
843 if (state
->flatshade_first
)
846 rctx
->flat_shade
= state
->flatshade
;
847 rstate
= radeon_state(rscreen
->rw
, R600_STATE_RASTERIZER
, 0);
850 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] = 0x00000001;
851 if (state
->sprite_coord_enable
) {
852 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
853 S_0286D4_PNT_SPRITE_ENA(1) |
854 S_0286D4_PNT_SPRITE_OVRD_X(2) |
855 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
856 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
857 S_0286D4_PNT_SPRITE_OVRD_W(1);
858 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
859 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
860 S_0286D4_PNT_SPRITE_TOP_1(1);
863 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = 0;
865 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = S_028810_PS_UCP_MODE(3) | ((1 << clip
->nr
) - 1);
866 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] |= S_028810_ZCLIP_NEAR_DISABLE(clip
->depth_clamp
);
867 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] |= S_028810_ZCLIP_FAR_DISABLE(clip
->depth_clamp
);
869 rstate
->states
[R600_RASTERIZER__PA_SU_SC_MODE_CNTL
] =
870 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
871 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
872 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
873 S_028814_FACE(!state
->front_ccw
) |
874 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
875 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
876 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
);
877 rstate
->states
[R600_RASTERIZER__PA_CL_VS_OUT_CNTL
] =
878 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
879 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
);
880 rstate
->states
[R600_RASTERIZER__PA_CL_NANINF_CNTL
] = 0x00000000;
881 /* point size 12.4 fixed point */
882 tmp
= (unsigned)(state
->point_size
* 8.0);
883 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_SIZE
] = S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
);
884 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_MINMAX
] = 0x80000000;
885 rstate
->states
[R600_RASTERIZER__PA_SU_LINE_CNTL
] = 0x00000008;
886 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_STIPPLE
] = 0x00000005;
887 rstate
->states
[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL
] = 0x00000000;
888 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_CNTL
] = 0x00000400;
889 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ
] = 0x3F800000;
890 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ
] = 0x3F800000;
891 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ
] = 0x3F800000;
892 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ
] = 0x3F800000;
893 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL
] = offset_db_fmt_cntl
;
894 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP
] = 0x00000000;
895 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE
] = fui(offset_scale
);
896 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET
] = fui(offset_units
);
897 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE
] = fui(offset_scale
);
898 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET
] = fui(offset_units
);
899 if (radeon_state_pm4(rstate
)) {
900 radeon_state_decref(rstate
);
906 static struct radeon_state
*r600_scissor(struct r600_context
*rctx
)
908 const struct pipe_scissor_state
*state
= &rctx
->scissor
->state
.scissor
;
909 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
910 struct r600_screen
*rscreen
= rctx
->screen
;
911 struct radeon_state
*rstate
;
912 unsigned minx
, maxx
, miny
, maxy
;
918 maxx
= fb
->cbufs
[0]->width
;
919 maxy
= fb
->cbufs
[0]->height
;
926 tl
= S_028240_TL_X(minx
) | S_028240_TL_Y(miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
927 br
= S_028244_BR_X(maxx
) | S_028244_BR_Y(maxy
);
928 rstate
= radeon_state(rscreen
->rw
, R600_STATE_SCISSOR
, 0);
931 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL
] = tl
;
932 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR
] = br
;
933 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_OFFSET
] = 0x00000000;
934 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL
] = tl
;
935 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR
] = br
;
936 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_RULE
] = 0x0000FFFF;
937 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_TL
] = tl
;
938 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_BR
] = br
;
939 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_TL
] = tl
;
940 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_BR
] = br
;
941 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_TL
] = tl
;
942 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_BR
] = br
;
943 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_TL
] = tl
;
944 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_BR
] = br
;
945 rstate
->states
[R600_SCISSOR__PA_SC_EDGERULE
] = 0xAAAAAAAA;
946 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL
] = tl
;
947 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR
] = br
;
948 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL
] = tl
;
949 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR
] = br
;
950 if (radeon_state_pm4(rstate
)) {
951 radeon_state_decref(rstate
);
957 static struct radeon_state
*r600_viewport(struct r600_context
*rctx
)
959 const struct pipe_viewport_state
*state
= &rctx
->viewport
->state
.viewport
;
960 struct r600_screen
*rscreen
= rctx
->screen
;
961 struct radeon_state
*rstate
;
963 rstate
= radeon_state(rscreen
->rw
, R600_STATE_VIEWPORT
, 0);
966 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0
] = 0x00000000;
967 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0
] = 0x3F800000;
968 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0
] = fui(state
->scale
[0]);
969 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0
] = fui(state
->scale
[1]);
970 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0
] = fui(state
->scale
[2]);
971 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0
] = fui(state
->translate
[0]);
972 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0
] = fui(state
->translate
[1]);
973 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0
] = fui(state
->translate
[2]);
974 rstate
->states
[R600_VIEWPORT__PA_CL_VTE_CNTL
] = 0x0000043F;
975 if (radeon_state_pm4(rstate
)) {
976 radeon_state_decref(rstate
);
982 static struct radeon_state
*r600_dsa(struct r600_context
*rctx
)
984 const struct pipe_depth_stencil_alpha_state
*state
= &rctx
->dsa
->state
.dsa
;
985 const struct pipe_stencil_ref
*stencil_ref
= &rctx
->stencil_ref
->state
.stencil_ref
;
986 struct r600_screen
*rscreen
= rctx
->screen
;
987 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
988 unsigned stencil_ref_mask
, stencil_ref_mask_bf
;
989 struct r600_shader
*rshader
;
990 struct radeon_state
*rstate
;
993 if (rctx
->ps_shader
== NULL
) {
996 rstate
= radeon_state(rscreen
->rw
, R600_STATE_DSA
, 0);
1000 db_shader_control
= 0x210;
1001 rshader
= &rctx
->ps_shader
->shader
;
1002 if (rshader
->uses_kill
)
1003 db_shader_control
|= (1 << 6);
1004 for (i
= 0; i
< rshader
->noutput
; i
++) {
1005 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
1006 db_shader_control
|= 1;
1008 stencil_ref_mask
= 0;
1009 stencil_ref_mask_bf
= 0;
1010 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1011 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1012 S_028800_ZFUNC(state
->depth
.func
);
1013 /* set stencil enable */
1015 if (state
->stencil
[0].enabled
) {
1016 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1017 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
1018 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
1019 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
1020 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
1022 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
1023 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
1024 stencil_ref_mask
|= S_028430_STENCILREF(stencil_ref
->ref_value
[0]);
1025 if (state
->stencil
[1].enabled
) {
1026 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1027 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
1028 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
1029 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
1030 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
1031 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
1032 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
1033 stencil_ref_mask_bf
|= S_028430_STENCILREF(stencil_ref
->ref_value
[1]);
1037 alpha_test_control
= 0;
1039 if (state
->alpha
.enabled
) {
1040 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
1041 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
1042 alpha_ref
= fui(state
->alpha
.ref_value
);
1045 rstate
->states
[R600_DSA__DB_STENCIL_CLEAR
] = 0x00000000;
1046 rstate
->states
[R600_DSA__DB_DEPTH_CLEAR
] = 0x3F800000;
1047 rstate
->states
[R600_DSA__SX_ALPHA_TEST_CONTROL
] = alpha_test_control
;
1048 rstate
->states
[R600_DSA__DB_STENCILREFMASK
] = stencil_ref_mask
;
1049 rstate
->states
[R600_DSA__DB_STENCILREFMASK_BF
] = stencil_ref_mask_bf
;
1050 rstate
->states
[R600_DSA__SX_ALPHA_REF
] = alpha_ref
;
1051 rstate
->states
[R600_DSA__SPI_FOG_FUNC_SCALE
] = 0x00000000;
1052 rstate
->states
[R600_DSA__SPI_FOG_FUNC_BIAS
] = 0x00000000;
1053 rstate
->states
[R600_DSA__SPI_FOG_CNTL
] = 0x00000000;
1054 rstate
->states
[R600_DSA__DB_DEPTH_CONTROL
] = db_depth_control
;
1055 rstate
->states
[R600_DSA__DB_SHADER_CONTROL
] = db_shader_control
;
1056 rstate
->states
[R600_DSA__DB_RENDER_CONTROL
] = 0x00000060;
1057 rstate
->states
[R600_DSA__DB_RENDER_OVERRIDE
] = 0x0000002A;
1058 rstate
->states
[R600_DSA__DB_SRESULTS_COMPARE_STATE1
] = 0x00000000;
1059 rstate
->states
[R600_DSA__DB_PRELOAD_CONTROL
] = 0x00000000;
1060 rstate
->states
[R600_DSA__DB_ALPHA_TO_MASK
] = 0x0000AA00;
1061 if (radeon_state_pm4(rstate
)) {
1062 radeon_state_decref(rstate
);
1068 static inline unsigned r600_tex_wrap(unsigned wrap
)
1072 case PIPE_TEX_WRAP_REPEAT
:
1073 return V_03C000_SQ_TEX_WRAP
;
1074 case PIPE_TEX_WRAP_CLAMP
:
1075 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1076 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1077 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1078 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1079 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1080 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1081 return V_03C000_SQ_TEX_MIRROR
;
1082 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1083 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1084 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1085 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1086 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1087 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1091 static inline unsigned r600_tex_filter(unsigned filter
)
1095 case PIPE_TEX_FILTER_NEAREST
:
1096 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1097 case PIPE_TEX_FILTER_LINEAR
:
1098 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1102 static inline unsigned r600_tex_mipfilter(unsigned filter
)
1105 case PIPE_TEX_MIPFILTER_NEAREST
:
1106 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1107 case PIPE_TEX_MIPFILTER_LINEAR
:
1108 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1110 case PIPE_TEX_MIPFILTER_NONE
:
1111 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1115 static inline unsigned r600_tex_compare(unsigned compare
)
1119 case PIPE_FUNC_NEVER
:
1120 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1121 case PIPE_FUNC_LESS
:
1122 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1123 case PIPE_FUNC_EQUAL
:
1124 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1125 case PIPE_FUNC_LEQUAL
:
1126 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1127 case PIPE_FUNC_GREATER
:
1128 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1129 case PIPE_FUNC_NOTEQUAL
:
1130 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1131 case PIPE_FUNC_GEQUAL
:
1132 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1133 case PIPE_FUNC_ALWAYS
:
1134 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1138 static INLINE u32
S_FIXED(float value
, u32 frac_bits
)
1140 return value
* (1 << frac_bits
);
1143 static struct radeon_state
*r600_sampler(struct r600_context
*rctx
,
1144 const struct pipe_sampler_state
*state
,
1147 struct r600_screen
*rscreen
= rctx
->screen
;
1148 struct radeon_state
*rstate
;
1150 rstate
= radeon_state_shader(rscreen
->rw
, R600_STATE_SAMPLER
, id
, R600_SHADER_PS
);
1153 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0
] =
1154 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
1155 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
1156 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1157 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
1158 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
1159 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1160 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
));
1161 /* FIXME LOD it depends on texture base level ... */
1162 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0
] =
1163 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
1164 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
1165 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
1166 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0
] = S_03C008_TYPE(1);
1167 if (radeon_state_pm4(rstate
)) {
1168 radeon_state_decref(rstate
);
1174 static inline unsigned r600_tex_swizzle(unsigned swizzle
)
1177 case PIPE_SWIZZLE_RED
:
1178 return V_038010_SQ_SEL_X
;
1179 case PIPE_SWIZZLE_GREEN
:
1180 return V_038010_SQ_SEL_Y
;
1181 case PIPE_SWIZZLE_BLUE
:
1182 return V_038010_SQ_SEL_Z
;
1183 case PIPE_SWIZZLE_ALPHA
:
1184 return V_038010_SQ_SEL_W
;
1185 case PIPE_SWIZZLE_ZERO
:
1186 return V_038010_SQ_SEL_0
;
1188 case PIPE_SWIZZLE_ONE
:
1189 return V_038010_SQ_SEL_1
;
1193 static inline unsigned r600_format_type(unsigned format_type
)
1195 switch (format_type
) {
1197 case UTIL_FORMAT_TYPE_UNSIGNED
:
1198 return V_038010_SQ_FORMAT_COMP_UNSIGNED
;
1199 case UTIL_FORMAT_TYPE_SIGNED
:
1200 return V_038010_SQ_FORMAT_COMP_SIGNED
;
1201 case UTIL_FORMAT_TYPE_FIXED
:
1202 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED
;
1206 static inline unsigned r600_tex_dim(unsigned dim
)
1210 case PIPE_TEXTURE_1D
:
1211 return V_038000_SQ_TEX_DIM_1D
;
1212 case PIPE_TEXTURE_2D
:
1213 case PIPE_TEXTURE_RECT
:
1214 return V_038000_SQ_TEX_DIM_2D
;
1215 case PIPE_TEXTURE_3D
:
1216 return V_038000_SQ_TEX_DIM_3D
;
1217 case PIPE_TEXTURE_CUBE
:
1218 return V_038000_SQ_TEX_DIM_CUBEMAP
;
1222 static struct radeon_state
*r600_resource(struct pipe_context
*ctx
,
1223 const struct pipe_sampler_view
*view
,
1226 struct r600_context
*rctx
= r600_context(ctx
);
1227 struct r600_screen
*rscreen
= rctx
->screen
;
1228 const struct util_format_description
*desc
;
1229 struct r600_resource_texture
*tmp
;
1230 struct r600_resource
*rbuffer
;
1231 struct radeon_state
*rstate
;
1233 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1234 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
1237 swizzle
[0] = view
->swizzle_r
;
1238 swizzle
[1] = view
->swizzle_g
;
1239 swizzle
[2] = view
->swizzle_b
;
1240 swizzle
[3] = view
->swizzle_a
;
1241 format
= r600_translate_texformat(view
->texture
->format
,
1243 &word4
, &yuv_format
);
1246 desc
= util_format_description(view
->texture
->format
);
1248 R600_ERR("unknow format %d\n", view
->texture
->format
);
1251 rstate
= radeon_state_shader(rscreen
->rw
, R600_STATE_RESOURCE
, id
, R600_SHADER_PS
);
1252 if (rstate
== NULL
) {
1255 tmp
= (struct r600_resource_texture
*)view
->texture
;
1256 rbuffer
= &tmp
->resource
;
1258 r
= r600_texture_from_depth(ctx
, tmp
, view
->first_level
);
1262 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, tmp
->uncompressed
);
1263 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, tmp
->uncompressed
);
1265 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1266 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1269 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
1270 rstate
->placement
[1] = RADEON_GEM_DOMAIN_GTT
;
1271 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
1272 rstate
->placement
[3] = RADEON_GEM_DOMAIN_GTT
;
1274 pitch
= (tmp
->pitch
[0] / tmp
->bpt
);
1275 pitch
= (pitch
+ 0x7) & ~0x7;
1277 /* FIXME properly handle first level != 0 */
1278 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD0
] =
1279 S_038000_DIM(r600_tex_dim(view
->texture
->target
)) |
1280 S_038000_TILE_MODE(array_mode
) |
1281 S_038000_TILE_TYPE(tile_type
) |
1282 S_038000_PITCH((pitch
/ 8) - 1) |
1283 S_038000_TEX_WIDTH(view
->texture
->width0
- 1);
1284 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD1
] =
1285 S_038004_TEX_HEIGHT(view
->texture
->height0
- 1) |
1286 S_038004_TEX_DEPTH(view
->texture
->depth0
- 1) |
1287 S_038004_DATA_FORMAT(format
);
1288 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD2
] = tmp
->offset
[0] >> 8;
1289 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD3
] = tmp
->offset
[1] >> 8;
1290 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD4
] =
1292 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM
) |
1293 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO
) |
1294 S_038010_REQUEST_SIZE(1) |
1295 S_038010_BASE_LEVEL(view
->first_level
);
1296 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD5
] =
1297 S_038014_LAST_LEVEL(view
->last_level
) |
1298 S_038014_BASE_ARRAY(0) |
1299 S_038014_LAST_ARRAY(0);
1300 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD6
] =
1301 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
);
1302 if (radeon_state_pm4(rstate
)) {
1303 radeon_state_decref(rstate
);
1309 static struct radeon_state
*r600_cb_cntl(struct r600_context
*rctx
)
1311 struct r600_screen
*rscreen
= rctx
->screen
;
1312 struct radeon_state
*rstate
;
1313 const struct pipe_blend_state
*pbs
= &rctx
->blend
->state
.blend
;
1314 int nr_cbufs
= rctx
->framebuffer
->state
.framebuffer
.nr_cbufs
;
1315 uint32_t color_control
, target_mask
, shader_mask
;
1320 color_control
= S_028808_PER_MRT_BLEND(1);
1322 for (i
= 0; i
< nr_cbufs
; i
++) {
1323 shader_mask
|= 0xf << (i
* 4);
1326 if (pbs
->logicop_enable
) {
1327 color_control
|= (pbs
->logicop_func
) << 16;
1329 color_control
|= (0xcc << 16);
1332 if (pbs
->independent_blend_enable
) {
1333 for (i
= 0; i
< nr_cbufs
; i
++) {
1334 if (pbs
->rt
[i
].blend_enable
) {
1335 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
1337 target_mask
|= (pbs
->rt
[i
].colormask
<< (4 * i
));
1340 for (i
= 0; i
< nr_cbufs
; i
++) {
1341 if (pbs
->rt
[0].blend_enable
) {
1342 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
1344 target_mask
|= (pbs
->rt
[0].colormask
<< (4 * i
));
1347 rstate
= radeon_state(rscreen
->rw
, R600_STATE_CB_CNTL
, 0);
1348 rstate
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = shader_mask
;
1349 rstate
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = target_mask
;
1350 rstate
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = color_control
;
1351 rstate
->states
[R600_CB_CNTL__PA_SC_AA_CONFIG
] = 0x00000000;
1352 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX
] = 0x00000000;
1353 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
] = 0x00000000;
1354 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
1355 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_SRC
] = 0x00000000;
1356 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
1357 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
1358 rstate
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
1359 if (radeon_state_pm4(rstate
)) {
1360 radeon_state_decref(rstate
);
1366 int r600_context_hw_states(struct pipe_context
*ctx
)
1368 struct r600_context
*rctx
= r600_context(ctx
);
1371 int nr_cbufs
= rctx
->framebuffer
->state
.framebuffer
.nr_cbufs
;
1375 ucp_nclip
= rctx
->clip
->state
.clip
.nr
;
1377 /* free previous TODO determine what need to be updated, what
1380 //radeon_state_decref(rctx->hw_states.config);
1381 rctx
->hw_states
.cb_cntl
= radeon_state_decref(rctx
->hw_states
.cb_cntl
);
1382 rctx
->hw_states
.db
= radeon_state_decref(rctx
->hw_states
.db
);
1383 rctx
->hw_states
.rasterizer
= radeon_state_decref(rctx
->hw_states
.rasterizer
);
1384 rctx
->hw_states
.scissor
= radeon_state_decref(rctx
->hw_states
.scissor
);
1385 rctx
->hw_states
.dsa
= radeon_state_decref(rctx
->hw_states
.dsa
);
1386 rctx
->hw_states
.blend
= radeon_state_decref(rctx
->hw_states
.blend
);
1387 rctx
->hw_states
.viewport
= radeon_state_decref(rctx
->hw_states
.viewport
);
1388 for (i
= 0; i
< 8; i
++) {
1389 rctx
->hw_states
.cb
[i
] = radeon_state_decref(rctx
->hw_states
.cb
[i
]);
1391 for (i
= 0; i
< 6; i
++) {
1392 rctx
->hw_states
.ucp
[i
] = radeon_state_decref(rctx
->hw_states
.ucp
[i
]);
1394 for (i
= 0; i
< rctx
->hw_states
.ps_nresource
; i
++) {
1395 radeon_state_decref(rctx
->hw_states
.ps_resource
[i
]);
1396 rctx
->hw_states
.ps_resource
[i
] = NULL
;
1398 rctx
->hw_states
.ps_nresource
= 0;
1399 for (i
= 0; i
< rctx
->hw_states
.ps_nsampler
; i
++) {
1400 radeon_state_decref(rctx
->hw_states
.ps_sampler
[i
]);
1401 rctx
->hw_states
.ps_sampler
[i
] = NULL
;
1403 rctx
->hw_states
.ps_nsampler
= 0;
1405 /* build new states */
1406 rctx
->hw_states
.rasterizer
= r600_rasterizer(rctx
);
1407 rctx
->hw_states
.scissor
= r600_scissor(rctx
);
1408 rctx
->hw_states
.dsa
= r600_dsa(rctx
);
1409 rctx
->hw_states
.blend
= r600_blend(rctx
);
1410 rctx
->hw_states
.viewport
= r600_viewport(rctx
);
1411 for (i
= 0; i
< nr_cbufs
; i
++) {
1412 rctx
->hw_states
.cb
[i
] = r600_cb(rctx
, i
);
1414 for (i
= 0; i
< ucp_nclip
; i
++) {
1415 rctx
->hw_states
.ucp
[i
] = r600_ucp(rctx
, i
);
1417 rctx
->hw_states
.db
= r600_db(rctx
);
1418 rctx
->hw_states
.cb_cntl
= r600_cb_cntl(rctx
);
1420 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
1421 if (rctx
->ps_sampler
[i
]) {
1422 rctx
->hw_states
.ps_sampler
[i
] = r600_sampler(rctx
,
1423 &rctx
->ps_sampler
[i
]->state
.sampler
,
1427 rctx
->hw_states
.ps_nsampler
= rctx
->ps_nsampler
;
1428 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
1429 if (rctx
->ps_sampler_view
[i
]) {
1430 rctx
->hw_states
.ps_resource
[i
] = r600_resource(ctx
,
1431 &rctx
->ps_sampler_view
[i
]->state
.sampler_view
,
1435 rctx
->hw_states
.ps_nresource
= rctx
->ps_nsampler_view
;
1438 for (i
= 0; i
< ucp_nclip
; i
++) {
1439 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.ucp
[i
]);
1443 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.db
);
1446 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.rasterizer
);
1449 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.scissor
);
1452 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.dsa
);
1455 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.blend
);
1458 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.viewport
);
1461 for (i
= 0; i
< nr_cbufs
; i
++) {
1462 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.cb
[i
]);
1466 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.config
);
1469 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.cb_cntl
);
1472 for (i
= 0; i
< rctx
->hw_states
.ps_nresource
; i
++) {
1473 if (rctx
->hw_states
.ps_resource
[i
]) {
1474 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.ps_resource
[i
]);
1479 for (i
= 0; i
< rctx
->hw_states
.ps_nsampler
; i
++) {
1480 if (rctx
->hw_states
.ps_sampler
[i
]) {
1481 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.ps_sampler
[i
]);