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Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include <pipebuffer/pb_buffer.h>
41 #include "r600.h"
42 #include "r600d.h"
43 #include "r600_resource.h"
44 #include "r600_shader.h"
45 #include "r600_pipe.h"
46 #include "r600_state_inlines.h"
47
48 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
49 {
50 struct r600_pipe_state state;
51
52 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
53 state.nregs = 0;
54 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
55 float offset_units = rctx->rasterizer->offset_units;
56 unsigned offset_db_fmt_cntl = 0, depth;
57
58 switch (rctx->framebuffer.zsbuf->texture->format) {
59 case PIPE_FORMAT_Z24X8_UNORM:
60 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
61 depth = -24;
62 offset_units *= 2.0f;
63 break;
64 case PIPE_FORMAT_Z32_FLOAT:
65 depth = -23;
66 offset_units *= 1.0f;
67 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
68 break;
69 case PIPE_FORMAT_Z16_UNORM:
70 depth = -16;
71 offset_units *= 4.0f;
72 break;
73 default:
74 return;
75 }
76 /* FIXME some of those reg can be computed with cso */
77 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
78 r600_pipe_state_add_reg(&state,
79 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
80 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
81 r600_pipe_state_add_reg(&state,
82 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
83 fui(offset_units), 0xFFFFFFFF, NULL);
84 r600_pipe_state_add_reg(&state,
85 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
86 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
87 r600_pipe_state_add_reg(&state,
88 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
89 fui(offset_units), 0xFFFFFFFF, NULL);
90 r600_pipe_state_add_reg(&state,
91 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
92 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
93 r600_context_pipe_state_set(&rctx->ctx, &state);
94 }
95 }
96
97 /* FIXME optimize away spi update when it's not needed */
98 static void r600_spi_update(struct r600_pipe_context *rctx)
99 {
100 struct r600_pipe_shader *shader = rctx->ps_shader;
101 struct r600_pipe_state rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, tmp;
104
105 rstate.nregs = 0;
106 for (i = 0; i < rshader->ninput; i++) {
107 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
108 if (rshader->input[i].centroid)
109 tmp |= S_028644_SEL_CENTROID(1);
110 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
111 tmp |= S_028644_SEL_LINEAR(1);
112
113 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
114 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
115 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
116 tmp |= S_028644_FLAT_SHADE(rctx->flatshade);
117 }
118 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
119 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
120 tmp |= S_028644_PT_SPRITE_TEX(1);
121 }
122 r600_pipe_state_add_reg(&rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
123 }
124 r600_context_pipe_state_set(&rctx->ctx, &rstate);
125 }
126
127 void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
128 {
129 struct r600_pipe_state *rstate;
130 struct r600_resource *rbuffer;
131 struct pipe_vertex_buffer *vertex_buffer;
132 unsigned i, offset;
133
134 /* we don't update until we know vertex elements */
135 if (rctx->vertex_elements == NULL || !rctx->nvertex_buffer)
136 return;
137
138 /* delete previous translated vertex elements */
139 if (rctx->tran.new_velems) {
140 r600_end_vertex_translate(rctx);
141 }
142
143 if (rctx->vertex_elements->incompatible_layout) {
144 /* translate rebind new vertex elements so
145 * return once translated
146 */
147 r600_begin_vertex_translate(rctx);
148 return;
149 }
150
151 if (rctx->any_user_vbs) {
152 r600_upload_user_buffers(rctx);
153 rctx->any_user_vbs = FALSE;
154 }
155
156 if (rctx->vertex_elements->vbuffer_need_offset) {
157 /* one resource per vertex elements */
158 rctx->nvs_resource = rctx->vertex_elements->count;
159 } else {
160 /* bind vertex buffer once */
161 rctx->nvs_resource = rctx->nvertex_buffer;
162 }
163
164 for (i = 0 ; i < rctx->nvs_resource; i++) {
165 rstate = &rctx->vs_resource[i];
166 rstate->id = R600_PIPE_STATE_RESOURCE;
167 rstate->nregs = 0;
168
169 if (rctx->vertex_elements->vbuffer_need_offset) {
170 /* one resource per vertex elements */
171 unsigned vbuffer_index;
172 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
173 vertex_buffer = &rctx->vertex_buffer[vbuffer_index];
174 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
175 offset = rctx->vertex_elements->vbuffer_offset[i] +
176 vertex_buffer->buffer_offset +
177 r600_bo_offset(rbuffer->bo);
178 } else {
179 /* bind vertex buffer once */
180 vertex_buffer = &rctx->vertex_buffer[i];
181 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
182 offset = vertex_buffer->buffer_offset +
183 r600_bo_offset(rbuffer->bo);
184 }
185
186 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
187 offset, 0xFFFFFFFF, rbuffer->bo);
188 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
189 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
190 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
191 S_038008_STRIDE(vertex_buffer->stride),
192 0xFFFFFFFF, NULL);
193 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
194 0x00000000, 0xFFFFFFFF, NULL);
195 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
196 0x00000000, 0xFFFFFFFF, NULL);
197 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
198 0x00000000, 0xFFFFFFFF, NULL);
199 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
200 0xC0000000, 0xFFFFFFFF, NULL);
201 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
202 }
203 }
204
205 static void r600_draw_common(struct r600_drawl *draw)
206 {
207 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
208 struct r600_resource *rbuffer;
209 unsigned prim;
210 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
211 struct r600_draw rdraw;
212 struct r600_pipe_state vgt;
213
214 switch (draw->index_size) {
215 case 2:
216 vgt_draw_initiator = 0;
217 vgt_dma_index_type = 0;
218 break;
219 case 4:
220 vgt_draw_initiator = 0;
221 vgt_dma_index_type = 1;
222 break;
223 case 0:
224 vgt_draw_initiator = 2;
225 vgt_dma_index_type = 0;
226 break;
227 default:
228 R600_ERR("unsupported index size %d\n", draw->index_size);
229 return;
230 }
231 if (r600_conv_pipe_prim(draw->mode, &prim))
232 return;
233 if (unlikely(rctx->ps_shader == NULL)) {
234 R600_ERR("missing vertex shader\n");
235 return;
236 }
237 if (unlikely(rctx->vs_shader == NULL)) {
238 R600_ERR("missing vertex shader\n");
239 return;
240 }
241 /* there should be enough input */
242 if (rctx->vertex_elements->count < rctx->vs_shader->shader.bc.nresource) {
243 R600_ERR("%d resources provided, expecting %d\n",
244 rctx->vertex_elements->count, rctx->vs_shader->shader.bc.nresource);
245 return;
246 }
247
248 r600_spi_update(rctx);
249
250 mask = 0;
251 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
252 mask |= (0xF << (i * 4));
253 }
254
255 vgt.id = R600_PIPE_STATE_VGT;
256 vgt.nregs = 0;
257 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
258 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
259 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
260 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
261 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
262 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
264 r600_context_pipe_state_set(&rctx->ctx, &vgt);
265
266 rdraw.vgt_num_indices = draw->count;
267 rdraw.vgt_num_instances = 1;
268 rdraw.vgt_index_type = vgt_dma_index_type;
269 rdraw.vgt_draw_initiator = vgt_draw_initiator;
270 rdraw.indices = NULL;
271 if (draw->index_buffer) {
272 rbuffer = (struct r600_resource*)draw->index_buffer;
273 rdraw.indices = rbuffer->bo;
274 rdraw.indices_bo_offset = draw->index_buffer_offset;
275 }
276 r600_context_draw(&rctx->ctx, &rdraw);
277 }
278
279 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
280 {
281 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
282 struct r600_drawl draw;
283 boolean translate = FALSE;
284
285 memset(&draw, 0, sizeof(struct r600_drawl));
286 draw.ctx = ctx;
287 draw.mode = info->mode;
288 draw.start = info->start;
289 draw.count = info->count;
290 if (info->indexed && rctx->index_buffer.buffer) {
291 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
292 draw.min_index = info->min_index;
293 draw.max_index = info->max_index;
294 draw.index_bias = info->index_bias;
295
296 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
297 &rctx->index_buffer.index_size,
298 &draw.start,
299 info->count);
300
301 draw.index_size = rctx->index_buffer.index_size;
302 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
303 draw.index_buffer_offset = draw.start * draw.index_size;
304 draw.start = 0;
305 r600_upload_index_buffer(rctx, &draw);
306 } else {
307 draw.index_size = 0;
308 draw.index_buffer = NULL;
309 draw.min_index = info->min_index;
310 draw.max_index = info->max_index;
311 draw.index_bias = info->start;
312 }
313 r600_draw_common(&draw);
314
315 if (translate)
316 r600_end_vertex_translate(rctx);
317
318 pipe_resource_reference(&draw.index_buffer, NULL);
319 }
320
321 static void r600_set_blend_color(struct pipe_context *ctx,
322 const struct pipe_blend_color *state)
323 {
324 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
325 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
326
327 if (rstate == NULL)
328 return;
329
330 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
331 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
332 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
333 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
334 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
335 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
336 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
337 r600_context_pipe_state_set(&rctx->ctx, rstate);
338 }
339
340 static void *r600_create_blend_state(struct pipe_context *ctx,
341 const struct pipe_blend_state *state)
342 {
343 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
344 struct r600_pipe_state *rstate;
345 u32 color_control, target_mask;
346
347 if (blend == NULL) {
348 return NULL;
349 }
350 rstate = &blend->rstate;
351
352 rstate->id = R600_PIPE_STATE_BLEND;
353
354 target_mask = 0;
355 color_control = S_028808_PER_MRT_BLEND(1);
356 if (state->logicop_enable) {
357 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
358 } else {
359 color_control |= (0xcc << 16);
360 }
361 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
362 if (state->independent_blend_enable) {
363 for (int i = 0; i < 8; i++) {
364 if (state->rt[i].blend_enable) {
365 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
366 }
367 target_mask |= (state->rt[i].colormask << (4 * i));
368 }
369 } else {
370 for (int i = 0; i < 8; i++) {
371 if (state->rt[0].blend_enable) {
372 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
373 }
374 target_mask |= (state->rt[0].colormask << (4 * i));
375 }
376 }
377 blend->cb_target_mask = target_mask;
378 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
379 color_control, 0xFFFFFFFF, NULL);
380
381 for (int i = 0; i < 8; i++) {
382 unsigned eqRGB = state->rt[i].rgb_func;
383 unsigned srcRGB = state->rt[i].rgb_src_factor;
384 unsigned dstRGB = state->rt[i].rgb_dst_factor;
385
386 unsigned eqA = state->rt[i].alpha_func;
387 unsigned srcA = state->rt[i].alpha_src_factor;
388 unsigned dstA = state->rt[i].alpha_dst_factor;
389 uint32_t bc = 0;
390
391 if (!state->rt[i].blend_enable)
392 continue;
393
394 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
395 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
396 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
397
398 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
399 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
400 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
401 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
402 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
403 }
404
405 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
406 if (i == 0) {
407 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
408 }
409 }
410 return rstate;
411 }
412
413 static void *r600_create_dsa_state(struct pipe_context *ctx,
414 const struct pipe_depth_stencil_alpha_state *state)
415 {
416 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
417 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
418 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
419
420 if (rstate == NULL) {
421 return NULL;
422 }
423
424 rstate->id = R600_PIPE_STATE_DSA;
425 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
426 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
427 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
428 * be set if shader use texkill instruction
429 */
430 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
431 stencil_ref_mask = 0;
432 stencil_ref_mask_bf = 0;
433 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
434 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
435 S_028800_ZFUNC(state->depth.func);
436
437 /* stencil */
438 if (state->stencil[0].enabled) {
439 db_depth_control |= S_028800_STENCIL_ENABLE(1);
440 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
441 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
442 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
443 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
444
445
446 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
447 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
448 if (state->stencil[1].enabled) {
449 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
450 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
451 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
452 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
453 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
454 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
455 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
456 }
457 }
458
459 /* alpha */
460 alpha_test_control = 0;
461 alpha_ref = 0;
462 if (state->alpha.enabled) {
463 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
464 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
465 alpha_ref = fui(state->alpha.ref_value);
466 }
467
468 /* misc */
469 db_render_control = 0;
470 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
471 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
472 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
473 /* TODO db_render_override depends on query */
474 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
475 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
476 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
477 r600_pipe_state_add_reg(rstate,
478 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
479 0xFFFFFFFF & C_028430_STENCILREF, NULL);
480 r600_pipe_state_add_reg(rstate,
481 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
482 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
483 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
484 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
485 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
486 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
487 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
488 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
489 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
490 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
491 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
492 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
493 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
494
495 return rstate;
496 }
497
498 static void *r600_create_rs_state(struct pipe_context *ctx,
499 const struct pipe_rasterizer_state *state)
500 {
501 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
502 struct r600_pipe_state *rstate;
503 unsigned tmp;
504 unsigned prov_vtx = 1, polygon_dual_mode;
505 unsigned clip_rule;
506
507 if (rs == NULL) {
508 return NULL;
509 }
510
511 rstate = &rs->rstate;
512 rs->flatshade = state->flatshade;
513 rs->sprite_coord_enable = state->sprite_coord_enable;
514
515 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
516 /* offset */
517 rs->offset_units = state->offset_units;
518 rs->offset_scale = state->offset_scale * 12.0f;
519
520 rstate->id = R600_PIPE_STATE_RASTERIZER;
521 if (state->flatshade_first)
522 prov_vtx = 0;
523 tmp = S_0286D4_FLAT_SHADE_ENA(1);
524 if (state->sprite_coord_enable) {
525 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
526 S_0286D4_PNT_SPRITE_OVRD_X(2) |
527 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
528 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
529 S_0286D4_PNT_SPRITE_OVRD_W(1);
530 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
531 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
532 }
533 }
534 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
535
536 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
537 state->fill_back != PIPE_POLYGON_MODE_FILL);
538 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
539 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
540 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
541 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
542 S_028814_FACE(!state->front_ccw) |
543 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
544 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
545 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
546 S_028814_POLY_MODE(polygon_dual_mode) |
547 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
548 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
549 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
550 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
551 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
552 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
553 /* point size 12.4 fixed point */
554 tmp = (unsigned)(state->point_size * 8.0);
555 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
556 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
557
558 tmp = (unsigned)state->line_width * 8;
559 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
560
561 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
562 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
563 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
564
565 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
566 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
567 0xFFFFFFFF, NULL);
568
569 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
570 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
571 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
572 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
573 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
574 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
575
576 return rstate;
577 }
578
579 static void *r600_create_sampler_state(struct pipe_context *ctx,
580 const struct pipe_sampler_state *state)
581 {
582 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
583 union util_color uc;
584
585 if (rstate == NULL) {
586 return NULL;
587 }
588
589 rstate->id = R600_PIPE_STATE_SAMPLER;
590 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
591 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
592 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
593 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
594 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
595 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
596 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
597 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
598 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
599 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
600 /* FIXME LOD it depends on texture base level ... */
601 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
602 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
603 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
604 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
605 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
606 if (uc.ui) {
607 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
608 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
609 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
610 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
611 }
612 return rstate;
613 }
614
615 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
616 struct pipe_resource *texture,
617 const struct pipe_sampler_view *state)
618 {
619 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
620 struct r600_pipe_state *rstate;
621 const struct util_format_description *desc;
622 struct r600_resource_texture *tmp;
623 struct r600_resource *rbuffer;
624 unsigned format;
625 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
626 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
627 struct r600_bo *bo[2];
628
629 if (resource == NULL)
630 return NULL;
631 rstate = &resource->state;
632
633 /* initialize base object */
634 resource->base = *state;
635 resource->base.texture = NULL;
636 pipe_reference(NULL, &texture->reference);
637 resource->base.texture = texture;
638 resource->base.reference.count = 1;
639 resource->base.context = ctx;
640
641 swizzle[0] = state->swizzle_r;
642 swizzle[1] = state->swizzle_g;
643 swizzle[2] = state->swizzle_b;
644 swizzle[3] = state->swizzle_a;
645 format = r600_translate_texformat(state->format,
646 swizzle,
647 &word4, &yuv_format);
648 if (format == ~0) {
649 format = 0;
650 }
651 desc = util_format_description(state->format);
652 if (desc == NULL) {
653 R600_ERR("unknow format %d\n", state->format);
654 }
655 tmp = (struct r600_resource_texture*)texture;
656 rbuffer = &tmp->resource;
657 bo[0] = rbuffer->bo;
658 bo[1] = rbuffer->bo;
659 /* FIXME depth texture decompression */
660 if (tmp->depth) {
661 r600_texture_depth_flush(ctx, texture);
662 tmp = (struct r600_resource_texture*)texture;
663 rbuffer = &tmp->flushed_depth_texture->resource;
664 bo[0] = rbuffer->bo;
665 bo[1] = rbuffer->bo;
666 }
667 pitch = align(tmp->pitch_in_pixels[0], 8);
668 if (tmp->tiled) {
669 array_mode = tmp->array_mode[0];
670 tile_type = tmp->tile_type;
671 }
672
673 /* FIXME properly handle first level != 0 */
674 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
675 S_038000_DIM(r600_tex_dim(texture->target)) |
676 S_038000_TILE_MODE(array_mode) |
677 S_038000_TILE_TYPE(tile_type) |
678 S_038000_PITCH((pitch / 8) - 1) |
679 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
680 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
681 S_038004_TEX_HEIGHT(texture->height0 - 1) |
682 S_038004_TEX_DEPTH(texture->depth0 - 1) |
683 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
684 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
685 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
686 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
687 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
688 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
689 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
690 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
691 S_038010_REQUEST_SIZE(1) |
692 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
693 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
694 S_038014_LAST_LEVEL(state->u.tex.last_level) |
695 S_038014_BASE_ARRAY(0) |
696 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
697 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
698 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
699
700 return &resource->base;
701 }
702
703 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
704 struct pipe_sampler_view **views)
705 {
706 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
707 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
708
709 for (int i = 0; i < count; i++) {
710 if (resource[i]) {
711 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
712 }
713 }
714 }
715
716 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
717 struct pipe_sampler_view **views)
718 {
719 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
720 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
721 int i;
722
723 for (i = 0; i < count; i++) {
724 if (&rctx->ps_samplers.views[i]->base != views[i]) {
725 if (resource[i])
726 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
727 else
728 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
729
730 pipe_sampler_view_reference(
731 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
732 views[i]);
733
734 }
735 }
736 for (i = count; i < NUM_TEX_UNITS; i++) {
737 if (rctx->ps_samplers.views[i]) {
738 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
739 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
740 }
741 }
742 rctx->ps_samplers.n_views = count;
743 }
744
745 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
746 {
747 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
748 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
749
750 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
751 rctx->ps_samplers.n_samplers = count;
752
753 for (int i = 0; i < count; i++) {
754 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
755 }
756 }
757
758 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
759 {
760 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
761 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
762
763 for (int i = 0; i < count; i++) {
764 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
765 }
766 }
767
768 static void r600_set_clip_state(struct pipe_context *ctx,
769 const struct pipe_clip_state *state)
770 {
771 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
772 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
773
774 if (rstate == NULL)
775 return;
776
777 rctx->clip = *state;
778 rstate->id = R600_PIPE_STATE_CLIP;
779 for (int i = 0; i < state->nr; i++) {
780 r600_pipe_state_add_reg(rstate,
781 R_028E20_PA_CL_UCP0_X + i * 16,
782 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
783 r600_pipe_state_add_reg(rstate,
784 R_028E24_PA_CL_UCP0_Y + i * 16,
785 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate,
787 R_028E28_PA_CL_UCP0_Z + i * 16,
788 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
789 r600_pipe_state_add_reg(rstate,
790 R_028E2C_PA_CL_UCP0_W + i * 16,
791 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
792 }
793 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
794 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
795 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
796 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
797
798 free(rctx->states[R600_PIPE_STATE_CLIP]);
799 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
800 r600_context_pipe_state_set(&rctx->ctx, rstate);
801 }
802
803 static void r600_set_polygon_stipple(struct pipe_context *ctx,
804 const struct pipe_poly_stipple *state)
805 {
806 }
807
808 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
809 {
810 }
811
812 static void r600_set_scissor_state(struct pipe_context *ctx,
813 const struct pipe_scissor_state *state)
814 {
815 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
816 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
817 u32 tl, br;
818
819 if (rstate == NULL)
820 return;
821
822 rstate->id = R600_PIPE_STATE_SCISSOR;
823 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
824 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
825 r600_pipe_state_add_reg(rstate,
826 R_028210_PA_SC_CLIPRECT_0_TL, tl,
827 0xFFFFFFFF, NULL);
828 r600_pipe_state_add_reg(rstate,
829 R_028214_PA_SC_CLIPRECT_0_BR, br,
830 0xFFFFFFFF, NULL);
831 r600_pipe_state_add_reg(rstate,
832 R_028218_PA_SC_CLIPRECT_1_TL, tl,
833 0xFFFFFFFF, NULL);
834 r600_pipe_state_add_reg(rstate,
835 R_02821C_PA_SC_CLIPRECT_1_BR, br,
836 0xFFFFFFFF, NULL);
837 r600_pipe_state_add_reg(rstate,
838 R_028220_PA_SC_CLIPRECT_2_TL, tl,
839 0xFFFFFFFF, NULL);
840 r600_pipe_state_add_reg(rstate,
841 R_028224_PA_SC_CLIPRECT_2_BR, br,
842 0xFFFFFFFF, NULL);
843 r600_pipe_state_add_reg(rstate,
844 R_028228_PA_SC_CLIPRECT_3_TL, tl,
845 0xFFFFFFFF, NULL);
846 r600_pipe_state_add_reg(rstate,
847 R_02822C_PA_SC_CLIPRECT_3_BR, br,
848 0xFFFFFFFF, NULL);
849
850 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
851 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
852 r600_context_pipe_state_set(&rctx->ctx, rstate);
853 }
854
855 static void r600_set_stencil_ref(struct pipe_context *ctx,
856 const struct pipe_stencil_ref *state)
857 {
858 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
859 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
860 u32 tmp;
861
862 if (rstate == NULL)
863 return;
864
865 rctx->stencil_ref = *state;
866 rstate->id = R600_PIPE_STATE_STENCIL_REF;
867 tmp = S_028430_STENCILREF(state->ref_value[0]);
868 r600_pipe_state_add_reg(rstate,
869 R_028430_DB_STENCILREFMASK, tmp,
870 ~C_028430_STENCILREF, NULL);
871 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
872 r600_pipe_state_add_reg(rstate,
873 R_028434_DB_STENCILREFMASK_BF, tmp,
874 ~C_028434_STENCILREF_BF, NULL);
875
876 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
877 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
878 r600_context_pipe_state_set(&rctx->ctx, rstate);
879 }
880
881 static void r600_set_viewport_state(struct pipe_context *ctx,
882 const struct pipe_viewport_state *state)
883 {
884 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
885 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
886
887 if (rstate == NULL)
888 return;
889
890 rctx->viewport = *state;
891 rstate->id = R600_PIPE_STATE_VIEWPORT;
892 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
894 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
895 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
896 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
897 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
898 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
899 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
900 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
901
902 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
903 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
904 r600_context_pipe_state_set(&rctx->ctx, rstate);
905 }
906
907 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
908 const struct pipe_framebuffer_state *state, int cb)
909 {
910 struct r600_resource_texture *rtex;
911 struct r600_resource *rbuffer;
912 struct r600_surface *surf;
913 unsigned level = state->cbufs[cb]->u.tex.level;
914 unsigned pitch, slice;
915 unsigned color_info;
916 unsigned format, swap, ntype;
917 unsigned offset;
918 const struct util_format_description *desc;
919 struct r600_bo *bo[3];
920
921 surf = (struct r600_surface *)state->cbufs[cb];
922 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
923 rbuffer = &rtex->resource;
924 bo[0] = rbuffer->bo;
925 bo[1] = rbuffer->bo;
926 bo[2] = rbuffer->bo;
927
928 /* XXX quite sure for dx10+ hw don't need any offset hacks */
929 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
930 level, state->cbufs[cb]->u.tex.first_layer);
931 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
932 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
933 ntype = 0;
934 desc = util_format_description(rtex->resource.base.b.format);
935 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
936 ntype = V_0280A0_NUMBER_SRGB;
937 else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
938 switch(desc->channel[0].type) {
939 case UTIL_FORMAT_TYPE_UNSIGNED:
940 ntype = V_0280A0_NUMBER_UNORM;
941 break;
942
943 case UTIL_FORMAT_TYPE_SIGNED:
944 ntype = V_0280A0_NUMBER_SNORM;
945 break;
946 }
947 }
948
949 format = r600_translate_colorformat(rtex->resource.base.b.format);
950 swap = r600_translate_colorswap(rtex->resource.base.b.format);
951 color_info = S_0280A0_FORMAT(format) |
952 S_0280A0_COMP_SWAP(swap) |
953 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
954 S_0280A0_BLEND_CLAMP(1) |
955 S_0280A0_NUMBER_TYPE(ntype);
956 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
957 color_info |= S_0280A0_SOURCE_FORMAT(1);
958
959 r600_pipe_state_add_reg(rstate,
960 R_028040_CB_COLOR0_BASE + cb * 4,
961 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
962 r600_pipe_state_add_reg(rstate,
963 R_0280A0_CB_COLOR0_INFO + cb * 4,
964 color_info, 0xFFFFFFFF, bo[0]);
965 r600_pipe_state_add_reg(rstate,
966 R_028060_CB_COLOR0_SIZE + cb * 4,
967 S_028060_PITCH_TILE_MAX(pitch) |
968 S_028060_SLICE_TILE_MAX(slice),
969 0xFFFFFFFF, NULL);
970 r600_pipe_state_add_reg(rstate,
971 R_028080_CB_COLOR0_VIEW + cb * 4,
972 0x00000000, 0xFFFFFFFF, NULL);
973 r600_pipe_state_add_reg(rstate,
974 R_0280E0_CB_COLOR0_FRAG + cb * 4,
975 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
976 r600_pipe_state_add_reg(rstate,
977 R_0280C0_CB_COLOR0_TILE + cb * 4,
978 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
979 r600_pipe_state_add_reg(rstate,
980 R_028100_CB_COLOR0_MASK + cb * 4,
981 0x00000000, 0xFFFFFFFF, NULL);
982 }
983
984 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
985 const struct pipe_framebuffer_state *state)
986 {
987 struct r600_resource_texture *rtex;
988 struct r600_resource *rbuffer;
989 struct r600_surface *surf;
990 unsigned level;
991 unsigned pitch, slice, format;
992 unsigned offset;
993
994 if (state->zsbuf == NULL)
995 return;
996
997 level = state->zsbuf->u.tex.level;
998
999 surf = (struct r600_surface *)state->zsbuf;
1000 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1001 rtex->tiled = 1;
1002 rtex->array_mode[level] = 2;
1003 rtex->tile_type = 1;
1004 rtex->depth = 1;
1005 rbuffer = &rtex->resource;
1006
1007 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1008 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1009 level, state->zsbuf->u.tex.first_layer);
1010 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
1011 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
1012 format = r600_translate_dbformat(state->zsbuf->texture->format);
1013
1014 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1015 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1016 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1017 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1018 0xFFFFFFFF, NULL);
1019 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1020 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1021 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1022 0xFFFFFFFF, rbuffer->bo);
1023 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1024 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1025 }
1026
1027 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1028 const struct pipe_framebuffer_state *state)
1029 {
1030 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1031 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1032 u32 shader_mask, tl, br, shader_control, target_mask;
1033
1034 if (rstate == NULL)
1035 return;
1036
1037 /* unreference old buffer and reference new one */
1038 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1039
1040 util_copy_framebuffer_state(&rctx->framebuffer, state);
1041
1042 rctx->pframebuffer = &rctx->framebuffer;
1043
1044 /* build states */
1045 for (int i = 0; i < state->nr_cbufs; i++) {
1046 r600_cb(rctx, rstate, state, i);
1047 }
1048 if (state->zsbuf) {
1049 r600_db(rctx, rstate, state);
1050 }
1051
1052 target_mask = 0x00000000;
1053 target_mask = 0xFFFFFFFF;
1054 shader_mask = 0;
1055 shader_control = 0;
1056 for (int i = 0; i < state->nr_cbufs; i++) {
1057 target_mask ^= 0xf << (i * 4);
1058 shader_mask |= 0xf << (i * 4);
1059 shader_control |= 1 << i;
1060 }
1061 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1062 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1063
1064 r600_pipe_state_add_reg(rstate,
1065 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1066 0xFFFFFFFF, NULL);
1067 r600_pipe_state_add_reg(rstate,
1068 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1069 0xFFFFFFFF, NULL);
1070 r600_pipe_state_add_reg(rstate,
1071 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1072 0xFFFFFFFF, NULL);
1073 r600_pipe_state_add_reg(rstate,
1074 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1075 0xFFFFFFFF, NULL);
1076 r600_pipe_state_add_reg(rstate,
1077 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1078 0xFFFFFFFF, NULL);
1079 r600_pipe_state_add_reg(rstate,
1080 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1081 0xFFFFFFFF, NULL);
1082 r600_pipe_state_add_reg(rstate,
1083 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1084 0xFFFFFFFF, NULL);
1085 r600_pipe_state_add_reg(rstate,
1086 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1087 0xFFFFFFFF, NULL);
1088 r600_pipe_state_add_reg(rstate,
1089 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1090 0xFFFFFFFF, NULL);
1091 if (rctx->family >= CHIP_RV770) {
1092 r600_pipe_state_add_reg(rstate,
1093 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1094 0xFFFFFFFF, NULL);
1095 }
1096
1097 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1098 shader_control, 0xFFFFFFFF, NULL);
1099 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1100 0x00000000, target_mask, NULL);
1101 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1102 shader_mask, 0xFFFFFFFF, NULL);
1103 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1104 0x00000000, 0xFFFFFFFF, NULL);
1105 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1106 0x00000000, 0xFFFFFFFF, NULL);
1107 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1108 0x00000000, 0xFFFFFFFF, NULL);
1109 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1110 0x01000000, 0xFFFFFFFF, NULL);
1111 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1112 0x00000000, 0xFFFFFFFF, NULL);
1113 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1114 0x000000FF, 0xFFFFFFFF, NULL);
1115 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1116 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1117 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1118 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1119
1120 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1121 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1122 r600_context_pipe_state_set(&rctx->ctx, rstate);
1123
1124 if (state->zsbuf) {
1125 r600_polygon_offset_update(rctx);
1126 }
1127 }
1128
1129 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1130 struct pipe_resource *buffer)
1131 {
1132 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1133 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1134
1135 /* Note that the state tracker can unbind constant buffers by
1136 * passing NULL here.
1137 */
1138 if (buffer == NULL) {
1139 return;
1140 }
1141
1142 switch (shader) {
1143 case PIPE_SHADER_VERTEX:
1144 rctx->vs_const_buffer.nregs = 0;
1145 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1146 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1147 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1148 0xFFFFFFFF, NULL);
1149 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1150 R_028980_ALU_CONST_CACHE_VS_0,
1151 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1152 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1153 break;
1154 case PIPE_SHADER_FRAGMENT:
1155 rctx->ps_const_buffer.nregs = 0;
1156 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1157 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1158 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1159 0xFFFFFFFF, NULL);
1160 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1161 R_028940_ALU_CONST_CACHE_PS_0,
1162 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1163 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1164 break;
1165 default:
1166 R600_ERR("unsupported %d\n", shader);
1167 return;
1168 }
1169 }
1170
1171 void r600_init_state_functions(struct r600_pipe_context *rctx)
1172 {
1173 rctx->context.create_blend_state = r600_create_blend_state;
1174 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1175 rctx->context.create_fs_state = r600_create_shader_state;
1176 rctx->context.create_rasterizer_state = r600_create_rs_state;
1177 rctx->context.create_sampler_state = r600_create_sampler_state;
1178 rctx->context.create_sampler_view = r600_create_sampler_view;
1179 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1180 rctx->context.create_vs_state = r600_create_shader_state;
1181 rctx->context.bind_blend_state = r600_bind_blend_state;
1182 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1183 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1184 rctx->context.bind_fs_state = r600_bind_ps_shader;
1185 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1186 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1187 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1188 rctx->context.bind_vs_state = r600_bind_vs_shader;
1189 rctx->context.delete_blend_state = r600_delete_state;
1190 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1191 rctx->context.delete_fs_state = r600_delete_ps_shader;
1192 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1193 rctx->context.delete_sampler_state = r600_delete_state;
1194 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1195 rctx->context.delete_vs_state = r600_delete_vs_shader;
1196 rctx->context.set_blend_color = r600_set_blend_color;
1197 rctx->context.set_clip_state = r600_set_clip_state;
1198 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1199 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1200 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1201 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1202 rctx->context.set_sample_mask = r600_set_sample_mask;
1203 rctx->context.set_scissor_state = r600_set_scissor_state;
1204 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1205 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1206 rctx->context.set_index_buffer = r600_set_index_buffer;
1207 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1208 rctx->context.set_viewport_state = r600_set_viewport_state;
1209 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1210 }
1211
1212 void r600_init_config(struct r600_pipe_context *rctx)
1213 {
1214 int ps_prio;
1215 int vs_prio;
1216 int gs_prio;
1217 int es_prio;
1218 int num_ps_gprs;
1219 int num_vs_gprs;
1220 int num_gs_gprs;
1221 int num_es_gprs;
1222 int num_temp_gprs;
1223 int num_ps_threads;
1224 int num_vs_threads;
1225 int num_gs_threads;
1226 int num_es_threads;
1227 int num_ps_stack_entries;
1228 int num_vs_stack_entries;
1229 int num_gs_stack_entries;
1230 int num_es_stack_entries;
1231 enum radeon_family family;
1232 struct r600_pipe_state *rstate = &rctx->config;
1233 u32 tmp;
1234
1235 family = r600_get_family(rctx->radeon);
1236 ps_prio = 0;
1237 vs_prio = 1;
1238 gs_prio = 2;
1239 es_prio = 3;
1240 switch (family) {
1241 case CHIP_R600:
1242 num_ps_gprs = 192;
1243 num_vs_gprs = 56;
1244 num_temp_gprs = 4;
1245 num_gs_gprs = 0;
1246 num_es_gprs = 0;
1247 num_ps_threads = 136;
1248 num_vs_threads = 48;
1249 num_gs_threads = 4;
1250 num_es_threads = 4;
1251 num_ps_stack_entries = 128;
1252 num_vs_stack_entries = 128;
1253 num_gs_stack_entries = 0;
1254 num_es_stack_entries = 0;
1255 break;
1256 case CHIP_RV630:
1257 case CHIP_RV635:
1258 num_ps_gprs = 84;
1259 num_vs_gprs = 36;
1260 num_temp_gprs = 4;
1261 num_gs_gprs = 0;
1262 num_es_gprs = 0;
1263 num_ps_threads = 144;
1264 num_vs_threads = 40;
1265 num_gs_threads = 4;
1266 num_es_threads = 4;
1267 num_ps_stack_entries = 40;
1268 num_vs_stack_entries = 40;
1269 num_gs_stack_entries = 32;
1270 num_es_stack_entries = 16;
1271 break;
1272 case CHIP_RV610:
1273 case CHIP_RV620:
1274 case CHIP_RS780:
1275 case CHIP_RS880:
1276 default:
1277 num_ps_gprs = 84;
1278 num_vs_gprs = 36;
1279 num_temp_gprs = 4;
1280 num_gs_gprs = 0;
1281 num_es_gprs = 0;
1282 num_ps_threads = 136;
1283 num_vs_threads = 48;
1284 num_gs_threads = 4;
1285 num_es_threads = 4;
1286 num_ps_stack_entries = 40;
1287 num_vs_stack_entries = 40;
1288 num_gs_stack_entries = 32;
1289 num_es_stack_entries = 16;
1290 break;
1291 case CHIP_RV670:
1292 num_ps_gprs = 144;
1293 num_vs_gprs = 40;
1294 num_temp_gprs = 4;
1295 num_gs_gprs = 0;
1296 num_es_gprs = 0;
1297 num_ps_threads = 136;
1298 num_vs_threads = 48;
1299 num_gs_threads = 4;
1300 num_es_threads = 4;
1301 num_ps_stack_entries = 40;
1302 num_vs_stack_entries = 40;
1303 num_gs_stack_entries = 32;
1304 num_es_stack_entries = 16;
1305 break;
1306 case CHIP_RV770:
1307 num_ps_gprs = 192;
1308 num_vs_gprs = 56;
1309 num_temp_gprs = 4;
1310 num_gs_gprs = 0;
1311 num_es_gprs = 0;
1312 num_ps_threads = 188;
1313 num_vs_threads = 60;
1314 num_gs_threads = 0;
1315 num_es_threads = 0;
1316 num_ps_stack_entries = 256;
1317 num_vs_stack_entries = 256;
1318 num_gs_stack_entries = 0;
1319 num_es_stack_entries = 0;
1320 break;
1321 case CHIP_RV730:
1322 case CHIP_RV740:
1323 num_ps_gprs = 84;
1324 num_vs_gprs = 36;
1325 num_temp_gprs = 4;
1326 num_gs_gprs = 0;
1327 num_es_gprs = 0;
1328 num_ps_threads = 188;
1329 num_vs_threads = 60;
1330 num_gs_threads = 0;
1331 num_es_threads = 0;
1332 num_ps_stack_entries = 128;
1333 num_vs_stack_entries = 128;
1334 num_gs_stack_entries = 0;
1335 num_es_stack_entries = 0;
1336 break;
1337 case CHIP_RV710:
1338 num_ps_gprs = 192;
1339 num_vs_gprs = 56;
1340 num_temp_gprs = 4;
1341 num_gs_gprs = 0;
1342 num_es_gprs = 0;
1343 num_ps_threads = 144;
1344 num_vs_threads = 48;
1345 num_gs_threads = 0;
1346 num_es_threads = 0;
1347 num_ps_stack_entries = 128;
1348 num_vs_stack_entries = 128;
1349 num_gs_stack_entries = 0;
1350 num_es_stack_entries = 0;
1351 break;
1352 }
1353
1354 rstate->id = R600_PIPE_STATE_CONFIG;
1355
1356 /* SQ_CONFIG */
1357 tmp = 0;
1358 switch (family) {
1359 case CHIP_RV610:
1360 case CHIP_RV620:
1361 case CHIP_RS780:
1362 case CHIP_RS880:
1363 case CHIP_RV710:
1364 break;
1365 default:
1366 tmp |= S_008C00_VC_ENABLE(1);
1367 break;
1368 }
1369 tmp |= S_008C00_DX9_CONSTS(0);
1370 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1371 tmp |= S_008C00_PS_PRIO(ps_prio);
1372 tmp |= S_008C00_VS_PRIO(vs_prio);
1373 tmp |= S_008C00_GS_PRIO(gs_prio);
1374 tmp |= S_008C00_ES_PRIO(es_prio);
1375 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1376
1377 /* SQ_GPR_RESOURCE_MGMT_1 */
1378 tmp = 0;
1379 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1380 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1381 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1382 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1383
1384 /* SQ_GPR_RESOURCE_MGMT_2 */
1385 tmp = 0;
1386 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1387 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1388 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1389
1390 /* SQ_THREAD_RESOURCE_MGMT */
1391 tmp = 0;
1392 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1393 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1394 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1395 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1396 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1397
1398 /* SQ_STACK_RESOURCE_MGMT_1 */
1399 tmp = 0;
1400 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1401 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1402 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1403
1404 /* SQ_STACK_RESOURCE_MGMT_2 */
1405 tmp = 0;
1406 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1407 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1408 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1409
1410 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1411 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1412
1413 if (family >= CHIP_RV770) {
1414 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1415 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1416 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1417 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1418 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1419 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1420 } else {
1421 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1422 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1423 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1426 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1427 }
1428 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1429 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1430 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1431 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1432 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1433 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1435 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1437 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1438 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1439 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1440 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1443 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1447 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1448 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1452 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1453 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1454
1455 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1456 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1459 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1460 r600_context_pipe_state_set(&rctx->ctx, rstate);
1461 }
1462
1463 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1464 {
1465 struct pipe_depth_stencil_alpha_state dsa;
1466 struct r600_pipe_state *rstate;
1467 boolean quirk = false;
1468
1469 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1470 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1471 quirk = true;
1472
1473 memset(&dsa, 0, sizeof(dsa));
1474
1475 if (quirk) {
1476 dsa.depth.enabled = 1;
1477 dsa.depth.func = PIPE_FUNC_LEQUAL;
1478 dsa.stencil[0].enabled = 1;
1479 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1480 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1481 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1482 dsa.stencil[0].writemask = 0xff;
1483 }
1484
1485 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1486 r600_pipe_state_add_reg(rstate,
1487 R_02880C_DB_SHADER_CONTROL,
1488 0x0,
1489 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1490 r600_pipe_state_add_reg(rstate,
1491 R_028D0C_DB_RENDER_CONTROL,
1492 S_028D0C_DEPTH_COPY_ENABLE(1) |
1493 S_028D0C_STENCIL_COPY_ENABLE(1) |
1494 S_028D0C_COPY_CENTROID(1),
1495 S_028D0C_DEPTH_COPY_ENABLE(1) |
1496 S_028D0C_STENCIL_COPY_ENABLE(1) |
1497 S_028D0C_COPY_CENTROID(1), NULL);
1498 return rstate;
1499 }