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r600g: rename pitch in texture to pitch_in_bytes
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_index_modify.h>
41 #include <util/u_framebuffer.h>
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "r600d.h"
45 #include "r600_resource.h"
46 #include "r600_shader.h"
47 #include "r600_pipe.h"
48 #include "r600_state_inlines.h"
49
50 static void r600_draw_common(struct r600_drawl *draw)
51 {
52 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
53 struct r600_pipe_state *rstate;
54 struct r600_resource *rbuffer;
55 unsigned i, j, offset, prim;
56 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
57 struct pipe_vertex_buffer *vertex_buffer;
58 struct r600_draw rdraw;
59 struct r600_pipe_state vgt;
60
61 switch (draw->index_size) {
62 case 2:
63 vgt_draw_initiator = 0;
64 vgt_dma_index_type = 0;
65 break;
66 case 4:
67 vgt_draw_initiator = 0;
68 vgt_dma_index_type = 1;
69 break;
70 case 0:
71 vgt_draw_initiator = 2;
72 vgt_dma_index_type = 0;
73 break;
74 default:
75 R600_ERR("unsupported index size %d\n", draw->index_size);
76 return;
77 }
78 if (r600_conv_pipe_prim(draw->mode, &prim))
79 return;
80
81
82 /* rebuild vertex shader if input format changed */
83 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
84 return;
85 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
86 return;
87
88 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
89 uint32_t word2, format;
90
91 rstate = &rctx->vs_resource[i];
92 rstate->id = R600_PIPE_STATE_RESOURCE;
93 rstate->nregs = 0;
94
95 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
96 vertex_buffer = &rctx->vertex_buffer[j];
97 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
98 offset = rctx->vertex_elements->elements[i].src_offset +
99 vertex_buffer->buffer_offset +
100 r600_bo_offset(rbuffer->bo);
101
102 format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
103
104 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
105
106 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
107 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
108 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
112 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
113 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
114 }
115
116 mask = 0;
117 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
118 mask |= (0xF << (i * 4));
119 }
120
121 vgt.id = R600_PIPE_STATE_VGT;
122 vgt.nregs = 0;
123 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
124 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
125 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
126 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
127 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
128 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
129 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
130 /* build late state */
131 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
132 float offset_units = rctx->rasterizer->offset_units;
133 unsigned offset_db_fmt_cntl = 0, depth;
134
135 switch (rctx->framebuffer.zsbuf->texture->format) {
136 case PIPE_FORMAT_Z24X8_UNORM:
137 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
138 depth = -24;
139 offset_units *= 2.0f;
140 break;
141 case PIPE_FORMAT_Z32_FLOAT:
142 depth = -23;
143 offset_units *= 1.0f;
144 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
145 break;
146 case PIPE_FORMAT_Z16_UNORM:
147 depth = -16;
148 offset_units *= 4.0f;
149 break;
150 default:
151 return;
152 }
153 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
154 r600_pipe_state_add_reg(&vgt,
155 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
156 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
157 r600_pipe_state_add_reg(&vgt,
158 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
159 fui(offset_units), 0xFFFFFFFF, NULL);
160 r600_pipe_state_add_reg(&vgt,
161 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
162 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(&vgt,
164 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
165 fui(offset_units), 0xFFFFFFFF, NULL);
166 r600_pipe_state_add_reg(&vgt,
167 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
168 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
169 }
170 r600_context_pipe_state_set(&rctx->ctx, &vgt);
171
172 rdraw.vgt_num_indices = draw->count;
173 rdraw.vgt_num_instances = 1;
174 rdraw.vgt_index_type = vgt_dma_index_type;
175 rdraw.vgt_draw_initiator = vgt_draw_initiator;
176 rdraw.indices = NULL;
177 if (draw->index_buffer) {
178 rbuffer = (struct r600_resource*)draw->index_buffer;
179 rdraw.indices = rbuffer->bo;
180 rdraw.indices_bo_offset = draw->index_buffer_offset;
181 }
182 r600_context_draw(&rctx->ctx, &rdraw);
183 }
184
185 void r600_translate_index_buffer(struct r600_pipe_context *r600,
186 struct pipe_resource **index_buffer,
187 unsigned *index_size,
188 unsigned *start, unsigned count)
189 {
190 switch (*index_size) {
191 case 1:
192 util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
193 *index_size = 2;
194 *start = 0;
195 break;
196
197 case 2:
198 if (*start % 2 != 0) {
199 util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
200 *start = 0;
201 }
202 break;
203
204 case 4:
205 break;
206 }
207 }
208
209 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
210 {
211 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
212 struct r600_drawl draw;
213
214 if (rctx->any_user_vbs) {
215 r600_upload_user_buffers(rctx);
216 rctx->any_user_vbs = FALSE;
217 }
218
219 memset(&draw, 0, sizeof(struct r600_drawl));
220 draw.ctx = ctx;
221 draw.mode = info->mode;
222 draw.start = info->start;
223 draw.count = info->count;
224 if (info->indexed && rctx->index_buffer.buffer) {
225 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
226 draw.min_index = info->min_index;
227 draw.max_index = info->max_index;
228 draw.index_bias = info->index_bias;
229
230 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
231 &rctx->index_buffer.index_size,
232 &draw.start,
233 info->count);
234
235 draw.index_size = rctx->index_buffer.index_size;
236 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
237 draw.index_buffer_offset = draw.start * draw.index_size;
238 draw.start = 0;
239 r600_upload_index_buffer(rctx, &draw);
240 } else {
241 draw.index_size = 0;
242 draw.index_buffer = NULL;
243 draw.min_index = info->min_index;
244 draw.max_index = info->max_index;
245 draw.index_bias = info->start;
246 }
247 r600_draw_common(&draw);
248
249 pipe_resource_reference(&draw.index_buffer, NULL);
250 }
251
252 static void r600_set_blend_color(struct pipe_context *ctx,
253 const struct pipe_blend_color *state)
254 {
255 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
256 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
257
258 if (rstate == NULL)
259 return;
260
261 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
262 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
264 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
265 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
266 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
267 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
268 r600_context_pipe_state_set(&rctx->ctx, rstate);
269 }
270
271 static void *r600_create_blend_state(struct pipe_context *ctx,
272 const struct pipe_blend_state *state)
273 {
274 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
275 struct r600_pipe_state *rstate;
276 u32 color_control, target_mask;
277
278 if (blend == NULL) {
279 return NULL;
280 }
281 rstate = &blend->rstate;
282
283 rstate->id = R600_PIPE_STATE_BLEND;
284
285 target_mask = 0;
286 color_control = S_028808_PER_MRT_BLEND(1);
287 if (state->logicop_enable) {
288 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
289 } else {
290 color_control |= (0xcc << 16);
291 }
292 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
293 if (state->independent_blend_enable) {
294 for (int i = 0; i < 8; i++) {
295 if (state->rt[i].blend_enable) {
296 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
297 }
298 target_mask |= (state->rt[i].colormask << (4 * i));
299 }
300 } else {
301 for (int i = 0; i < 8; i++) {
302 if (state->rt[0].blend_enable) {
303 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
304 }
305 target_mask |= (state->rt[0].colormask << (4 * i));
306 }
307 }
308 blend->cb_target_mask = target_mask;
309 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
310 color_control, 0xFFFFFFFF, NULL);
311
312 for (int i = 0; i < 8; i++) {
313 unsigned eqRGB = state->rt[i].rgb_func;
314 unsigned srcRGB = state->rt[i].rgb_src_factor;
315 unsigned dstRGB = state->rt[i].rgb_dst_factor;
316
317 unsigned eqA = state->rt[i].alpha_func;
318 unsigned srcA = state->rt[i].alpha_src_factor;
319 unsigned dstA = state->rt[i].alpha_dst_factor;
320 uint32_t bc = 0;
321
322 if (!state->rt[i].blend_enable)
323 continue;
324
325 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
326 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
327 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
328
329 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
330 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
331 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
332 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
333 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
334 }
335
336 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
337 if (i == 0) {
338 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
339 }
340 }
341 return rstate;
342 }
343
344 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
345 {
346 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
347 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
348 struct r600_pipe_state *rstate;
349
350 if (state == NULL)
351 return;
352 rstate = &blend->rstate;
353 rctx->states[rstate->id] = rstate;
354 rctx->cb_target_mask = blend->cb_target_mask;
355 r600_context_pipe_state_set(&rctx->ctx, rstate);
356 }
357
358 static void *r600_create_dsa_state(struct pipe_context *ctx,
359 const struct pipe_depth_stencil_alpha_state *state)
360 {
361 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
362 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
363 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
364
365 if (rstate == NULL) {
366 return NULL;
367 }
368
369 rstate->id = R600_PIPE_STATE_DSA;
370 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
371 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
372 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
373 * be set if shader use texkill instruction
374 */
375 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
376 stencil_ref_mask = 0;
377 stencil_ref_mask_bf = 0;
378 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
379 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
380 S_028800_ZFUNC(state->depth.func);
381
382 /* stencil */
383 if (state->stencil[0].enabled) {
384 db_depth_control |= S_028800_STENCIL_ENABLE(1);
385 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
386 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
387 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
388 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
389
390
391 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
392 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
393 if (state->stencil[1].enabled) {
394 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
395 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
396 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
397 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
398 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
399 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
400 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
401 }
402 }
403
404 /* alpha */
405 alpha_test_control = 0;
406 alpha_ref = 0;
407 if (state->alpha.enabled) {
408 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
409 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
410 alpha_ref = fui(state->alpha.ref_value);
411 }
412
413 /* misc */
414 db_render_control = 0;
415 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
416 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
417 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
418 /* TODO db_render_override depends on query */
419 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
420 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
421 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
422 r600_pipe_state_add_reg(rstate,
423 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
424 0xFFFFFFFF & C_028430_STENCILREF, NULL);
425 r600_pipe_state_add_reg(rstate,
426 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
427 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
428 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
429 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
430 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
431 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
432 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
433 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
434 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
435 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
436 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
437 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
438 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
439
440 return rstate;
441 }
442
443 static void *r600_create_rs_state(struct pipe_context *ctx,
444 const struct pipe_rasterizer_state *state)
445 {
446 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
447 struct r600_pipe_state *rstate;
448 unsigned tmp;
449 unsigned prov_vtx = 1, polygon_dual_mode;
450 unsigned clip_rule;
451
452 if (rs == NULL) {
453 return NULL;
454 }
455
456 rstate = &rs->rstate;
457 rs->flatshade = state->flatshade;
458 rs->sprite_coord_enable = state->sprite_coord_enable;
459
460 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
461 /* offset */
462 rs->offset_units = state->offset_units;
463 rs->offset_scale = state->offset_scale * 12.0f;
464
465 rstate->id = R600_PIPE_STATE_RASTERIZER;
466 if (state->flatshade_first)
467 prov_vtx = 0;
468 tmp = 0x00000001;
469 if (state->sprite_coord_enable) {
470 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
471 S_0286D4_PNT_SPRITE_OVRD_X(2) |
472 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
473 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
474 S_0286D4_PNT_SPRITE_OVRD_W(1);
475 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
476 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
477 }
478 }
479 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
480
481 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
482 state->fill_back != PIPE_POLYGON_MODE_FILL);
483 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
484 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
485 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
486 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
487 S_028814_FACE(!state->front_ccw) |
488 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
489 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
490 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
491 S_028814_POLY_MODE(polygon_dual_mode) |
492 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
493 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
494 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
495 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
496 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
497 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
498 /* point size 12.4 fixed point */
499 tmp = (unsigned)(state->point_size * 8.0);
500 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
501 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
502 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
503 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
504 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
505 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
506 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
507 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
508 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
509 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
510 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
511 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
512
513 return rstate;
514 }
515
516 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
517 {
518 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
519 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
520
521 if (state == NULL)
522 return;
523
524 rctx->flatshade = rs->flatshade;
525 rctx->sprite_coord_enable = rs->sprite_coord_enable;
526 rctx->rasterizer = rs;
527
528 rctx->states[rs->rstate.id] = &rs->rstate;
529 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
530 }
531
532 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
533 {
534 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
535 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
536
537 if (rctx->rasterizer == rs) {
538 rctx->rasterizer = NULL;
539 }
540 if (rctx->states[rs->rstate.id] == &rs->rstate) {
541 rctx->states[rs->rstate.id] = NULL;
542 }
543 free(rs);
544 }
545
546 static void *r600_create_sampler_state(struct pipe_context *ctx,
547 const struct pipe_sampler_state *state)
548 {
549 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
550 union util_color uc;
551
552 if (rstate == NULL) {
553 return NULL;
554 }
555
556 rstate->id = R600_PIPE_STATE_SAMPLER;
557 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
558 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
559 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
560 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
561 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
562 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
563 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
564 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
565 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
566 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
567 /* FIXME LOD it depends on texture base level ... */
568 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
569 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
570 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
571 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
572 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
573 if (uc.ui) {
574 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
575 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
576 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
577 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
578 }
579 return rstate;
580 }
581
582 static void *r600_create_vertex_elements(struct pipe_context *ctx,
583 unsigned count,
584 const struct pipe_vertex_element *elements)
585 {
586 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
587
588 assert(count < 32);
589 v->count = count;
590 v->refcount = 1;
591 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
592 return v;
593 }
594
595 static void r600_sampler_view_destroy(struct pipe_context *ctx,
596 struct pipe_sampler_view *state)
597 {
598 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
599
600 pipe_resource_reference(&state->texture, NULL);
601 FREE(resource);
602 }
603
604 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
605 struct pipe_resource *texture,
606 const struct pipe_sampler_view *state)
607 {
608 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
609 struct r600_pipe_state *rstate;
610 const struct util_format_description *desc;
611 struct r600_resource_texture *tmp;
612 struct r600_resource *rbuffer;
613 unsigned format;
614 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
615 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
616 struct r600_bo *bo[2];
617
618 if (resource == NULL)
619 return NULL;
620 rstate = &resource->state;
621
622 /* initialize base object */
623 resource->base = *state;
624 resource->base.texture = NULL;
625 pipe_reference(NULL, &texture->reference);
626 resource->base.texture = texture;
627 resource->base.reference.count = 1;
628 resource->base.context = ctx;
629
630 swizzle[0] = state->swizzle_r;
631 swizzle[1] = state->swizzle_g;
632 swizzle[2] = state->swizzle_b;
633 swizzle[3] = state->swizzle_a;
634 format = r600_translate_texformat(state->format,
635 swizzle,
636 &word4, &yuv_format);
637 if (format == ~0) {
638 format = 0;
639 }
640 desc = util_format_description(state->format);
641 if (desc == NULL) {
642 R600_ERR("unknow format %d\n", state->format);
643 }
644 tmp = (struct r600_resource_texture*)texture;
645 rbuffer = &tmp->resource;
646 bo[0] = rbuffer->bo;
647 bo[1] = rbuffer->bo;
648 /* FIXME depth texture decompression */
649 if (tmp->depth) {
650 r600_texture_depth_flush(ctx, texture);
651 tmp = (struct r600_resource_texture*)texture;
652 rbuffer = &tmp->flushed_depth_texture->resource;
653 bo[0] = rbuffer->bo;
654 bo[1] = rbuffer->bo;
655 }
656 pitch = align(tmp->pitch_in_bytes[0] / tmp->bpt, 8);
657
658 /* FIXME properly handle first level != 0 */
659 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
660 S_038000_DIM(r600_tex_dim(texture->target)) |
661 S_038000_TILE_MODE(array_mode) |
662 S_038000_TILE_TYPE(tile_type) |
663 S_038000_PITCH((pitch / 8) - 1) |
664 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
665 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
666 S_038004_TEX_HEIGHT(texture->height0 - 1) |
667 S_038004_TEX_DEPTH(texture->depth0 - 1) |
668 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
669 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
670 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
671 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
672 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
673 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
674 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
675 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
676 S_038010_REQUEST_SIZE(1) |
677 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
678 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
679 S_038014_LAST_LEVEL(state->last_level) |
680 S_038014_BASE_ARRAY(0) |
681 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
682 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
683 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
684
685 return &resource->base;
686 }
687
688 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
689 struct pipe_sampler_view **views)
690 {
691 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
692 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
693
694 for (int i = 0; i < count; i++) {
695 if (resource[i]) {
696 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
697 }
698 }
699 }
700
701 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
702 struct pipe_sampler_view **views)
703 {
704 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
705 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
706
707 rctx->ps_samplers.views = resource;
708 rctx->ps_samplers.n_views = count;
709
710 for (int i = 0; i < count; i++) {
711 if (resource[i]) {
712 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
713 }
714 }
715 }
716
717 static void r600_bind_state(struct pipe_context *ctx, void *state)
718 {
719 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
720 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
721
722 if (state == NULL)
723 return;
724 rctx->states[rstate->id] = rstate;
725 r600_context_pipe_state_set(&rctx->ctx, rstate);
726 }
727
728 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
729 {
730 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
731 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
732
733 rctx->ps_samplers.samplers = states;
734 rctx->ps_samplers.n_samplers = count;
735
736 for (int i = 0; i < count; i++) {
737 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
738 }
739 }
740
741 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
742 {
743 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
744 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
745
746 for (int i = 0; i < count; i++) {
747 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
748 }
749 }
750
751 static void r600_delete_state(struct pipe_context *ctx, void *state)
752 {
753 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
754 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
755
756 if (rctx->states[rstate->id] == rstate) {
757 rctx->states[rstate->id] = NULL;
758 }
759 for (int i = 0; i < rstate->nregs; i++) {
760 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
761 }
762 free(rstate);
763 }
764
765 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
766 {
767 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
768
769 if (v == NULL)
770 return;
771 if (--v->refcount)
772 return;
773 free(v);
774 }
775
776 static void r600_set_clip_state(struct pipe_context *ctx,
777 const struct pipe_clip_state *state)
778 {
779 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
780 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
781
782 if (rstate == NULL)
783 return;
784
785 rctx->clip = *state;
786 rstate->id = R600_PIPE_STATE_CLIP;
787 for (int i = 0; i < state->nr; i++) {
788 r600_pipe_state_add_reg(rstate,
789 R_028E20_PA_CL_UCP0_X + i * 4,
790 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
791 r600_pipe_state_add_reg(rstate,
792 R_028E24_PA_CL_UCP0_Y + i * 4,
793 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
794 r600_pipe_state_add_reg(rstate,
795 R_028E28_PA_CL_UCP0_Z + i * 4,
796 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
797 r600_pipe_state_add_reg(rstate,
798 R_028E2C_PA_CL_UCP0_W + i * 4,
799 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
800 }
801 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
802 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
803 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
804 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
805
806 free(rctx->states[R600_PIPE_STATE_CLIP]);
807 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
808 r600_context_pipe_state_set(&rctx->ctx, rstate);
809 }
810
811 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
812 {
813 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
814 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
815
816 r600_delete_vertex_element(ctx, rctx->vertex_elements);
817 rctx->vertex_elements = v;
818 if (v) {
819 v->refcount++;
820 // rctx->vs_rebuild = TRUE;
821 }
822 }
823
824 static void r600_set_polygon_stipple(struct pipe_context *ctx,
825 const struct pipe_poly_stipple *state)
826 {
827 }
828
829 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
830 {
831 }
832
833 static void r600_set_scissor_state(struct pipe_context *ctx,
834 const struct pipe_scissor_state *state)
835 {
836 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
837 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
838 u32 tl, br;
839
840 if (rstate == NULL)
841 return;
842
843 rstate->id = R600_PIPE_STATE_SCISSOR;
844 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
845 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
846 r600_pipe_state_add_reg(rstate,
847 R_028210_PA_SC_CLIPRECT_0_TL, tl,
848 0xFFFFFFFF, NULL);
849 r600_pipe_state_add_reg(rstate,
850 R_028214_PA_SC_CLIPRECT_0_BR, br,
851 0xFFFFFFFF, NULL);
852 r600_pipe_state_add_reg(rstate,
853 R_028218_PA_SC_CLIPRECT_1_TL, tl,
854 0xFFFFFFFF, NULL);
855 r600_pipe_state_add_reg(rstate,
856 R_02821C_PA_SC_CLIPRECT_1_BR, br,
857 0xFFFFFFFF, NULL);
858 r600_pipe_state_add_reg(rstate,
859 R_028220_PA_SC_CLIPRECT_2_TL, tl,
860 0xFFFFFFFF, NULL);
861 r600_pipe_state_add_reg(rstate,
862 R_028224_PA_SC_CLIPRECT_2_BR, br,
863 0xFFFFFFFF, NULL);
864 r600_pipe_state_add_reg(rstate,
865 R_028228_PA_SC_CLIPRECT_3_TL, tl,
866 0xFFFFFFFF, NULL);
867 r600_pipe_state_add_reg(rstate,
868 R_02822C_PA_SC_CLIPRECT_3_BR, br,
869 0xFFFFFFFF, NULL);
870
871 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
872 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
873 r600_context_pipe_state_set(&rctx->ctx, rstate);
874 }
875
876 static void r600_set_stencil_ref(struct pipe_context *ctx,
877 const struct pipe_stencil_ref *state)
878 {
879 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
880 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
881 u32 tmp;
882
883 if (rstate == NULL)
884 return;
885
886 rctx->stencil_ref = *state;
887 rstate->id = R600_PIPE_STATE_STENCIL_REF;
888 tmp = S_028430_STENCILREF(state->ref_value[0]);
889 r600_pipe_state_add_reg(rstate,
890 R_028430_DB_STENCILREFMASK, tmp,
891 ~C_028430_STENCILREF, NULL);
892 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
893 r600_pipe_state_add_reg(rstate,
894 R_028434_DB_STENCILREFMASK_BF, tmp,
895 ~C_028434_STENCILREF_BF, NULL);
896
897 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
898 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
899 r600_context_pipe_state_set(&rctx->ctx, rstate);
900 }
901
902 static void r600_set_viewport_state(struct pipe_context *ctx,
903 const struct pipe_viewport_state *state)
904 {
905 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
906 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
907
908 if (rstate == NULL)
909 return;
910
911 rctx->viewport = *state;
912 rstate->id = R600_PIPE_STATE_VIEWPORT;
913 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
914 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
915 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
916 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
918 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
919 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
921 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
922
923 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
924 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
925 r600_context_pipe_state_set(&rctx->ctx, rstate);
926 }
927
928 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
929 const struct pipe_framebuffer_state *state, int cb)
930 {
931 struct r600_resource_texture *rtex;
932 struct r600_resource *rbuffer;
933 unsigned level = state->cbufs[cb]->level;
934 unsigned pitch, slice;
935 unsigned color_info;
936 unsigned format, swap, ntype;
937 const struct util_format_description *desc;
938 struct r600_bo *bo[3];
939
940 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
941 rbuffer = &rtex->resource;
942 bo[0] = rbuffer->bo;
943 bo[1] = rbuffer->bo;
944 bo[2] = rbuffer->bo;
945
946 pitch = (rtex->pitch_in_bytes[level] / rtex->bpt) / 8 - 1;
947 slice = (rtex->pitch_in_bytes[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
948 ntype = 0;
949 desc = util_format_description(rtex->resource.base.b.format);
950 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
951 ntype = V_0280A0_NUMBER_SRGB;
952
953 format = r600_translate_colorformat(rtex->resource.base.b.format);
954 swap = r600_translate_colorswap(rtex->resource.base.b.format);
955 color_info = S_0280A0_FORMAT(format) |
956 S_0280A0_COMP_SWAP(swap) |
957 S_0280A0_BLEND_CLAMP(1) |
958 S_0280A0_NUMBER_TYPE(ntype);
959 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
960 color_info |= S_0280A0_SOURCE_FORMAT(1);
961
962 r600_pipe_state_add_reg(rstate,
963 R_028040_CB_COLOR0_BASE + cb * 4,
964 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
965 r600_pipe_state_add_reg(rstate,
966 R_0280A0_CB_COLOR0_INFO + cb * 4,
967 color_info, 0xFFFFFFFF, bo[0]);
968 r600_pipe_state_add_reg(rstate,
969 R_028060_CB_COLOR0_SIZE + cb * 4,
970 S_028060_PITCH_TILE_MAX(pitch) |
971 S_028060_SLICE_TILE_MAX(slice),
972 0xFFFFFFFF, NULL);
973 r600_pipe_state_add_reg(rstate,
974 R_028080_CB_COLOR0_VIEW + cb * 4,
975 0x00000000, 0xFFFFFFFF, NULL);
976 r600_pipe_state_add_reg(rstate,
977 R_0280E0_CB_COLOR0_FRAG + cb * 4,
978 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
979 r600_pipe_state_add_reg(rstate,
980 R_0280C0_CB_COLOR0_TILE + cb * 4,
981 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
982 r600_pipe_state_add_reg(rstate,
983 R_028100_CB_COLOR0_MASK + cb * 4,
984 0x00000000, 0xFFFFFFFF, NULL);
985 }
986
987 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
988 const struct pipe_framebuffer_state *state)
989 {
990 struct r600_resource_texture *rtex;
991 struct r600_resource *rbuffer;
992 unsigned level;
993 unsigned pitch, slice, format;
994
995 if (state->zsbuf == NULL)
996 return;
997
998 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
999 rtex->tiled = 1;
1000 rtex->array_mode = 2;
1001 rtex->tile_type = 1;
1002 rtex->depth = 1;
1003 rbuffer = &rtex->resource;
1004
1005 level = state->zsbuf->level;
1006 pitch = (rtex->pitch_in_bytes[level] / rtex->bpt) / 8 - 1;
1007 slice = (rtex->pitch_in_bytes[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
1008 format = r600_translate_dbformat(state->zsbuf->texture->format);
1009
1010 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1011 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1012 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1013 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1014 0xFFFFFFFF, NULL);
1015 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1016 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1017 S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
1018 0xFFFFFFFF, rbuffer->bo);
1019 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1020 (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
1021 }
1022
1023 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1024 const struct pipe_framebuffer_state *state)
1025 {
1026 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1027 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1028 u32 shader_mask, tl, br, shader_control, target_mask;
1029
1030 if (rstate == NULL)
1031 return;
1032
1033 /* unreference old buffer and reference new one */
1034 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1035
1036 util_copy_framebuffer_state(&rctx->framebuffer, state);
1037
1038 rctx->pframebuffer = &rctx->framebuffer;
1039
1040 /* build states */
1041 for (int i = 0; i < state->nr_cbufs; i++) {
1042 r600_cb(rctx, rstate, state, i);
1043 }
1044 if (state->zsbuf) {
1045 r600_db(rctx, rstate, state);
1046 }
1047
1048 target_mask = 0x00000000;
1049 target_mask = 0xFFFFFFFF;
1050 shader_mask = 0;
1051 shader_control = 0;
1052 for (int i = 0; i < state->nr_cbufs; i++) {
1053 target_mask ^= 0xf << (i * 4);
1054 shader_mask |= 0xf << (i * 4);
1055 shader_control |= 1 << i;
1056 }
1057 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1058 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1059
1060 r600_pipe_state_add_reg(rstate,
1061 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1062 0xFFFFFFFF, NULL);
1063 r600_pipe_state_add_reg(rstate,
1064 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1065 0xFFFFFFFF, NULL);
1066 r600_pipe_state_add_reg(rstate,
1067 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1068 0xFFFFFFFF, NULL);
1069 r600_pipe_state_add_reg(rstate,
1070 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1071 0xFFFFFFFF, NULL);
1072 r600_pipe_state_add_reg(rstate,
1073 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1074 0xFFFFFFFF, NULL);
1075 r600_pipe_state_add_reg(rstate,
1076 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1077 0xFFFFFFFF, NULL);
1078 r600_pipe_state_add_reg(rstate,
1079 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1080 0xFFFFFFFF, NULL);
1081 r600_pipe_state_add_reg(rstate,
1082 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1083 0xFFFFFFFF, NULL);
1084 r600_pipe_state_add_reg(rstate,
1085 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1086 0xFFFFFFFF, NULL);
1087 if (rctx->family >= CHIP_RV770) {
1088 r600_pipe_state_add_reg(rstate,
1089 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1090 0xFFFFFFFF, NULL);
1091 }
1092
1093 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1094 shader_control, 0xFFFFFFFF, NULL);
1095 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1096 0x00000000, target_mask, NULL);
1097 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1098 shader_mask, 0xFFFFFFFF, NULL);
1099 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1100 0x00000000, 0xFFFFFFFF, NULL);
1101 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1102 0x00000000, 0xFFFFFFFF, NULL);
1103 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1104 0x00000000, 0xFFFFFFFF, NULL);
1105 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1106 0x01000000, 0xFFFFFFFF, NULL);
1107 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1108 0x00000000, 0xFFFFFFFF, NULL);
1109 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1110 0x000000FF, 0xFFFFFFFF, NULL);
1111 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1112 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1113 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1114 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1115
1116 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1117 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1118 r600_context_pipe_state_set(&rctx->ctx, rstate);
1119 }
1120
1121 static void r600_set_index_buffer(struct pipe_context *ctx,
1122 const struct pipe_index_buffer *ib)
1123 {
1124 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1125
1126 if (ib) {
1127 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1128 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1129 } else {
1130 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1131 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1132 }
1133
1134 /* TODO make this more like a state */
1135 }
1136
1137 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1138 const struct pipe_vertex_buffer *buffers)
1139 {
1140 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1141
1142 for (int i = 0; i < rctx->nvertex_buffer; i++) {
1143 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1144 }
1145 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1146 for (int i = 0; i < count; i++) {
1147 rctx->vertex_buffer[i].buffer = NULL;
1148 if (r600_buffer_is_user_buffer(buffers[i].buffer))
1149 rctx->any_user_vbs = TRUE;
1150 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1151 }
1152 rctx->nvertex_buffer = count;
1153 }
1154
1155 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1156 struct pipe_resource *buffer)
1157 {
1158 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1159 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1160
1161 switch (shader) {
1162 case PIPE_SHADER_VERTEX:
1163 rctx->vs_const_buffer.nregs = 0;
1164 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1165 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1166 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1167 0xFFFFFFFF, NULL);
1168 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1169 R_028980_ALU_CONST_CACHE_VS_0,
1170 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1171 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1172 break;
1173 case PIPE_SHADER_FRAGMENT:
1174 rctx->ps_const_buffer.nregs = 0;
1175 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1176 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1177 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1178 0xFFFFFFFF, NULL);
1179 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1180 R_028940_ALU_CONST_CACHE_PS_0,
1181 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1182 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1183 break;
1184 default:
1185 R600_ERR("unsupported %d\n", shader);
1186 return;
1187 }
1188 }
1189
1190 static void *r600_create_shader_state(struct pipe_context *ctx,
1191 const struct pipe_shader_state *state)
1192 {
1193 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1194 int r;
1195
1196 r = r600_pipe_shader_create(ctx, shader, state->tokens);
1197 if (r) {
1198 return NULL;
1199 }
1200 return shader;
1201 }
1202
1203 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1204 {
1205 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1206
1207 /* TODO delete old shader */
1208 rctx->ps_shader = (struct r600_pipe_shader *)state;
1209 }
1210
1211 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1212 {
1213 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1214
1215 /* TODO delete old shader */
1216 rctx->vs_shader = (struct r600_pipe_shader *)state;
1217 }
1218
1219 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1220 {
1221 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1222 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1223
1224 if (rctx->ps_shader == shader) {
1225 rctx->ps_shader = NULL;
1226 }
1227 /* TODO proper delete */
1228 free(shader);
1229 }
1230
1231 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1232 {
1233 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1234 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1235
1236 if (rctx->vs_shader == shader) {
1237 rctx->vs_shader = NULL;
1238 }
1239 /* TODO proper delete */
1240 free(shader);
1241 }
1242
1243 void r600_init_state_functions(struct r600_pipe_context *rctx)
1244 {
1245 rctx->context.create_blend_state = r600_create_blend_state;
1246 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1247 rctx->context.create_fs_state = r600_create_shader_state;
1248 rctx->context.create_rasterizer_state = r600_create_rs_state;
1249 rctx->context.create_sampler_state = r600_create_sampler_state;
1250 rctx->context.create_sampler_view = r600_create_sampler_view;
1251 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1252 rctx->context.create_vs_state = r600_create_shader_state;
1253 rctx->context.bind_blend_state = r600_bind_blend_state;
1254 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1255 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1256 rctx->context.bind_fs_state = r600_bind_ps_shader;
1257 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1258 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1259 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1260 rctx->context.bind_vs_state = r600_bind_vs_shader;
1261 rctx->context.delete_blend_state = r600_delete_state;
1262 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1263 rctx->context.delete_fs_state = r600_delete_ps_shader;
1264 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1265 rctx->context.delete_sampler_state = r600_delete_state;
1266 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1267 rctx->context.delete_vs_state = r600_delete_vs_shader;
1268 rctx->context.set_blend_color = r600_set_blend_color;
1269 rctx->context.set_clip_state = r600_set_clip_state;
1270 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1271 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1272 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1273 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1274 rctx->context.set_sample_mask = r600_set_sample_mask;
1275 rctx->context.set_scissor_state = r600_set_scissor_state;
1276 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1277 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1278 rctx->context.set_index_buffer = r600_set_index_buffer;
1279 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1280 rctx->context.set_viewport_state = r600_set_viewport_state;
1281 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1282 }
1283
1284 void r600_init_config(struct r600_pipe_context *rctx)
1285 {
1286 int ps_prio;
1287 int vs_prio;
1288 int gs_prio;
1289 int es_prio;
1290 int num_ps_gprs;
1291 int num_vs_gprs;
1292 int num_gs_gprs;
1293 int num_es_gprs;
1294 int num_temp_gprs;
1295 int num_ps_threads;
1296 int num_vs_threads;
1297 int num_gs_threads;
1298 int num_es_threads;
1299 int num_ps_stack_entries;
1300 int num_vs_stack_entries;
1301 int num_gs_stack_entries;
1302 int num_es_stack_entries;
1303 enum radeon_family family;
1304 struct r600_pipe_state *rstate = &rctx->config;
1305 u32 tmp;
1306
1307 family = r600_get_family(rctx->radeon);
1308 ps_prio = 0;
1309 vs_prio = 1;
1310 gs_prio = 2;
1311 es_prio = 3;
1312 switch (family) {
1313 case CHIP_R600:
1314 num_ps_gprs = 192;
1315 num_vs_gprs = 56;
1316 num_temp_gprs = 4;
1317 num_gs_gprs = 0;
1318 num_es_gprs = 0;
1319 num_ps_threads = 136;
1320 num_vs_threads = 48;
1321 num_gs_threads = 4;
1322 num_es_threads = 4;
1323 num_ps_stack_entries = 128;
1324 num_vs_stack_entries = 128;
1325 num_gs_stack_entries = 0;
1326 num_es_stack_entries = 0;
1327 break;
1328 case CHIP_RV630:
1329 case CHIP_RV635:
1330 num_ps_gprs = 84;
1331 num_vs_gprs = 36;
1332 num_temp_gprs = 4;
1333 num_gs_gprs = 0;
1334 num_es_gprs = 0;
1335 num_ps_threads = 144;
1336 num_vs_threads = 40;
1337 num_gs_threads = 4;
1338 num_es_threads = 4;
1339 num_ps_stack_entries = 40;
1340 num_vs_stack_entries = 40;
1341 num_gs_stack_entries = 32;
1342 num_es_stack_entries = 16;
1343 break;
1344 case CHIP_RV610:
1345 case CHIP_RV620:
1346 case CHIP_RS780:
1347 case CHIP_RS880:
1348 default:
1349 num_ps_gprs = 84;
1350 num_vs_gprs = 36;
1351 num_temp_gprs = 4;
1352 num_gs_gprs = 0;
1353 num_es_gprs = 0;
1354 num_ps_threads = 136;
1355 num_vs_threads = 48;
1356 num_gs_threads = 4;
1357 num_es_threads = 4;
1358 num_ps_stack_entries = 40;
1359 num_vs_stack_entries = 40;
1360 num_gs_stack_entries = 32;
1361 num_es_stack_entries = 16;
1362 break;
1363 case CHIP_RV670:
1364 num_ps_gprs = 144;
1365 num_vs_gprs = 40;
1366 num_temp_gprs = 4;
1367 num_gs_gprs = 0;
1368 num_es_gprs = 0;
1369 num_ps_threads = 136;
1370 num_vs_threads = 48;
1371 num_gs_threads = 4;
1372 num_es_threads = 4;
1373 num_ps_stack_entries = 40;
1374 num_vs_stack_entries = 40;
1375 num_gs_stack_entries = 32;
1376 num_es_stack_entries = 16;
1377 break;
1378 case CHIP_RV770:
1379 num_ps_gprs = 192;
1380 num_vs_gprs = 56;
1381 num_temp_gprs = 4;
1382 num_gs_gprs = 0;
1383 num_es_gprs = 0;
1384 num_ps_threads = 188;
1385 num_vs_threads = 60;
1386 num_gs_threads = 0;
1387 num_es_threads = 0;
1388 num_ps_stack_entries = 256;
1389 num_vs_stack_entries = 256;
1390 num_gs_stack_entries = 0;
1391 num_es_stack_entries = 0;
1392 break;
1393 case CHIP_RV730:
1394 case CHIP_RV740:
1395 num_ps_gprs = 84;
1396 num_vs_gprs = 36;
1397 num_temp_gprs = 4;
1398 num_gs_gprs = 0;
1399 num_es_gprs = 0;
1400 num_ps_threads = 188;
1401 num_vs_threads = 60;
1402 num_gs_threads = 0;
1403 num_es_threads = 0;
1404 num_ps_stack_entries = 128;
1405 num_vs_stack_entries = 128;
1406 num_gs_stack_entries = 0;
1407 num_es_stack_entries = 0;
1408 break;
1409 case CHIP_RV710:
1410 num_ps_gprs = 192;
1411 num_vs_gprs = 56;
1412 num_temp_gprs = 4;
1413 num_gs_gprs = 0;
1414 num_es_gprs = 0;
1415 num_ps_threads = 144;
1416 num_vs_threads = 48;
1417 num_gs_threads = 0;
1418 num_es_threads = 0;
1419 num_ps_stack_entries = 128;
1420 num_vs_stack_entries = 128;
1421 num_gs_stack_entries = 0;
1422 num_es_stack_entries = 0;
1423 break;
1424 }
1425
1426 rstate->id = R600_PIPE_STATE_CONFIG;
1427
1428 /* SQ_CONFIG */
1429 tmp = 0;
1430 switch (family) {
1431 case CHIP_RV610:
1432 case CHIP_RV620:
1433 case CHIP_RS780:
1434 case CHIP_RS880:
1435 case CHIP_RV710:
1436 break;
1437 default:
1438 tmp |= S_008C00_VC_ENABLE(1);
1439 break;
1440 }
1441 tmp |= S_008C00_DX9_CONSTS(0);
1442 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1443 tmp |= S_008C00_PS_PRIO(ps_prio);
1444 tmp |= S_008C00_VS_PRIO(vs_prio);
1445 tmp |= S_008C00_GS_PRIO(gs_prio);
1446 tmp |= S_008C00_ES_PRIO(es_prio);
1447 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1448
1449 /* SQ_GPR_RESOURCE_MGMT_1 */
1450 tmp = 0;
1451 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1452 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1453 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1454 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1455
1456 /* SQ_GPR_RESOURCE_MGMT_2 */
1457 tmp = 0;
1458 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1459 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1460 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1461
1462 /* SQ_THREAD_RESOURCE_MGMT */
1463 tmp = 0;
1464 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1465 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1466 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1467 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1468 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1469
1470 /* SQ_STACK_RESOURCE_MGMT_1 */
1471 tmp = 0;
1472 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1473 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1474 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1475
1476 /* SQ_STACK_RESOURCE_MGMT_2 */
1477 tmp = 0;
1478 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1479 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1480 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1481
1482 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1484
1485 if (family >= CHIP_RV770) {
1486 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1490 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1492 } else {
1493 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1495 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1496 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1497 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1498 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1499 }
1500 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1501 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1502 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1503 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1504 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1505 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1506 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1507 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1508 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1509 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1510 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1511 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1512 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1513 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1514 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1515 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1516 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1517 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1518 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1519 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1520 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1521 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1522 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1523 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1524 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1525 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1526
1527 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1528 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1529 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1530 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1531 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1532 r600_context_pipe_state_set(&rctx->ctx, rstate);
1533 }
1534
1535 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1536 {
1537 struct pipe_depth_stencil_alpha_state dsa;
1538 struct r600_pipe_state *rstate;
1539 boolean quirk = false;
1540
1541 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1542 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1543 quirk = true;
1544
1545 memset(&dsa, 0, sizeof(dsa));
1546
1547 if (quirk) {
1548 dsa.depth.enabled = 1;
1549 dsa.depth.func = PIPE_FUNC_LEQUAL;
1550 dsa.stencil[0].enabled = 1;
1551 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1552 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1553 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1554 dsa.stencil[0].writemask = 0xff;
1555 }
1556
1557 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1558 r600_pipe_state_add_reg(rstate,
1559 R_02880C_DB_SHADER_CONTROL,
1560 0x0,
1561 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1562 r600_pipe_state_add_reg(rstate,
1563 R_028D0C_DB_RENDER_CONTROL,
1564 S_028D0C_DEPTH_COPY_ENABLE(1) |
1565 S_028D0C_STENCIL_COPY_ENABLE(1) |
1566 S_028D0C_COPY_CENTROID(1),
1567 S_028D0C_DEPTH_COPY_ENABLE(1) |
1568 S_028D0C_STENCIL_COPY_ENABLE(1) |
1569 S_028D0C_COPY_CENTROID(1), NULL);
1570 return rstate;
1571 }