src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 extern struct u_resource_vtbl r600_texture_vtbl;
  42
  43 /* Copy from a full GPU texture to a transfer's staging one. */
  44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  45 {
  46         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  47         struct pipe_resource *texture = transfer->resource;
  48         struct pipe_subresource subdst;
  49
  50         subdst.face = 0;
  51         subdst.level = 0;
  52         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  53                                 subdst, 0, 0, 0, texture, transfer->sr,
  54                                 transfer->box.x, transfer->box.y, transfer->box.z,
  55                                 transfer->box.width, transfer->box.height);
  56 }
  57
  58
  59 /* Copy from a transfer's staging texture to a full GPU one. */
  60 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  61 {
  62         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  63         struct pipe_resource *texture = transfer->resource;
  64         struct pipe_subresource subsrc;
  65
  66         subsrc.face = 0;
  67         subsrc.level = 0;
  68         ctx->resource_copy_region(ctx, texture, transfer->sr,
  69                                   transfer->box.x, transfer->box.y, transfer->box.z,
  70                                   rtransfer->staging_texture, subsrc,
  71                                   0, 0, 0,
  72                                   transfer->box.width, transfer->box.height);
  73
  74         ctx->flush(ctx, 0, NULL);
  75 }
  76
  77 static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  78                                         unsigned level, unsigned zslice,
  79                                         unsigned face)
  80 {
  81         unsigned offset = rtex->offset[level];
  82
  83         switch (rtex->resource.base.b.target) {
  84         case PIPE_TEXTURE_3D:
  85                 assert(face == 0);
  86                 return offset + zslice * rtex->layer_size[level];
  87         case PIPE_TEXTURE_CUBE:
  88                 assert(zslice == 0);
  89                 return offset + face * rtex->layer_size[level];
  90         default:
  91                 assert(zslice == 0 && face == 0);
  92                 return offset;
  93         }
  94 }
  95
  96 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  97                                          enum pipe_format format,
  98                                          unsigned array_mode)
  99 {
 100         struct r600_screen* rscreen = (struct r600_screen *)screen;
 101         unsigned pixsize = util_format_get_blocksize(format);
 102         int p_align;
 103
 104         switch(array_mode) {
 105         case V_038000_ARRAY_1D_TILED_THIN1:
 106                 p_align = MAX2(8,
 107                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 108                 break;
 109         case V_038000_ARRAY_2D_TILED_THIN1:
 110                 p_align = MAX2(rscreen->tiling_info->num_banks,
 111                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 112                                 rscreen->tiling_info->num_banks));
 113                 break;
 114         case 0:
 115         default:
 116                 p_align = 64;
 117                 break;
 118         }
 119         return p_align;
 120 }
 121
 122 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 123                                           unsigned array_mode)
 124 {
 125         struct r600_screen* rscreen = (struct r600_screen *)screen;
 126         int h_align;
 127
 128         switch (array_mode) {
 129         case V_038000_ARRAY_2D_TILED_THIN1:
 130                 h_align = rscreen->tiling_info->num_channels * 8;
 131                 break;
 132         case V_038000_ARRAY_1D_TILED_THIN1:
 133                 h_align = 8;
 134                 break;
 135         default:
 136                 h_align = 1;
 137                 break;
 138         }
 139         return h_align;
 140 }
 141
 142 static unsigned mip_minify(unsigned size, unsigned level)
 143 {
 144         unsigned val;
 145         val = u_minify(size, level);
 146         if (level > 0)
 147                 val = util_next_power_of_two(val);
 148         return val;
 149 }
 150
 151 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 152                                         struct r600_resource_texture *rtex,
 153                                         unsigned level)
 154 {
 155         struct pipe_resource *ptex = &rtex->resource.base.b;
 156         struct radeon *radeon = (struct radeon *)screen->winsys;
 157         enum chip_class chipc = r600_get_family_class(radeon);
 158         unsigned width, stride, tile_width;
 159
 160         if (rtex->pitch_override)
 161                 return rtex->pitch_override;
 162
 163         width = mip_minify(ptex->width0, level);
 164         if (util_format_is_plain(ptex->format)) {
 165                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 166                                                       rtex->array_mode[level]);
 167                 width = align(width, tile_width);
 168         }
 169         stride = util_format_get_stride(ptex->format, width);
 170         if (chipc == EVERGREEN)
 171                 stride = align(stride, 512);
 172
 173         if (ptex->bind & PIPE_BIND_RENDER_TARGET)
 174                 stride = align(stride, 512);
 175
 176         return stride;
 177 }
 178
 179 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 180                                           struct r600_resource_texture *rtex,
 181                                           unsigned level)
 182 {
 183         struct pipe_resource *ptex = &rtex->resource.base.b;
 184         unsigned height, tile_height;
 185
 186         height = mip_minify(ptex->height0, level);
 187         if (util_format_is_plain(ptex->format)) {
 188                 tile_height = r600_get_height_alignment(screen,
 189                                                         rtex->array_mode[level]);
 190                 height = align(height, tile_height);
 191         }
 192         return util_format_get_nblocksy(ptex->format, height);
 193 }
 194
 195 /* Get a width in pixels from a stride in bytes. */
 196 static unsigned pitch_to_width(enum pipe_format format,
 197                                 unsigned pitch_in_bytes)
 198 {
 199     return (pitch_in_bytes / util_format_get_blocksize(format)) *
 200             util_format_get_blockwidth(format);
 201 }
 202
 203 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 204                                         struct r600_resource_texture *rtex,
 205                                         unsigned level, unsigned array_mode)
 206 {
 207         struct pipe_resource *ptex = &rtex->resource.base.b;
 208
 209         switch (array_mode) {
 210         case V_0280A0_ARRAY_LINEAR_GENERAL:
 211         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 212         case V_0280A0_ARRAY_1D_TILED_THIN1:
 213         default:
 214                 rtex->array_mode[level] = array_mode;
 215                 break;
 216         case V_0280A0_ARRAY_2D_TILED_THIN1:
 217         {
 218                 unsigned w, h, tile_height, tile_width;
 219
 220                 tile_height = r600_get_height_alignment(screen, array_mode);
 221                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 222
 223                 w = mip_minify(ptex->width0, level);
 224                 h = mip_minify(ptex->height0, level);
 225                 if (w < tile_width || h < tile_height)
 226                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 227                 else
 228                         rtex->array_mode[level] = array_mode;
 229         }
 230         break;
 231         }
 232 }
 233
 234 static void r600_setup_miptree(struct pipe_screen *screen,
 235                                struct r600_resource_texture *rtex,
 236                                unsigned array_mode)
 237 {
 238         struct pipe_resource *ptex = &rtex->resource.base.b;
 239         struct radeon *radeon = (struct radeon *)screen->winsys;
 240         enum chip_class chipc = r600_get_family_class(radeon);
 241         unsigned pitch, size, layer_size, i, offset;
 242         unsigned nblocksy;
 243
 244         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 245                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 246
 247                 pitch = r600_texture_get_stride(screen, rtex, i);
 248                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 249
 250                 layer_size = pitch * nblocksy;
 251
 252                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 253                         if (chipc >= R700)
 254                                 size = layer_size * 8;
 255                         else
 256                                 size = layer_size * 6;
 257                 }
 258                 else
 259                         size = layer_size * u_minify(ptex->depth0, i);
 260                 rtex->offset[i] = offset;
 261                 rtex->layer_size[i] = layer_size;
 262                 rtex->pitch_in_bytes[i] = pitch;
 263                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 264                 offset += size;
 265         }
 266         rtex->size = offset;
 267 }
 268
 269 static struct r600_resource_texture *
 270 r600_texture_create_object(struct pipe_screen *screen,
 271                            const struct pipe_resource *base,
 272                            unsigned array_mode,
 273                            unsigned pitch_in_bytes_override,
 274                            unsigned max_buffer_size,
 275                            struct r600_bo *bo)
 276 {
 277         struct r600_resource_texture *rtex;
 278         struct r600_resource *resource;
 279         struct radeon *radeon = (struct radeon *)screen->winsys;
 280
 281         rtex = CALLOC_STRUCT(r600_resource_texture);
 282         if (rtex == NULL)
 283                 return NULL;
 284
 285         resource = &rtex->resource;
 286         resource->base.b = *base;
 287         resource->base.vtbl = &r600_texture_vtbl;
 288         pipe_reference_init(&resource->base.b.reference, 1);
 289         resource->base.b.screen = screen;
 290         resource->bo = bo;
 291         rtex->pitch_override = pitch_in_bytes_override;
 292
 293         if (array_mode)
 294                 rtex->tiled = 1;
 295         r600_setup_miptree(screen, rtex, array_mode);
 296
 297         resource->size = rtex->size;
 298
 299         if (!resource->bo) {
 300                 resource->bo = r600_bo(radeon, rtex->size, 4096, base->bind, base->usage);
 301                 if (!resource->bo) {
 302                         FREE(rtex);
 303                         return NULL;
 304                 }
 305         }
 306         return rtex;
 307 }
 308
 309 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 310                                                 const struct pipe_resource *templ)
 311 {
 312         unsigned array_mode = 0;
 313         static int force_tiling = -1;
 314
 315         /* Would like some magic "get_bool_option_once" routine.
 316          */
 317         if (force_tiling == -1)
 318                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 319
 320         if (force_tiling) {
 321                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 322                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 323                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 324                 }
 325         }
 326
 327         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 328                                                                   0, 0, NULL);
 329
 330 }
 331
 332 static void r600_texture_destroy(struct pipe_screen *screen,
 333                                  struct pipe_resource *ptex)
 334 {
 335         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 336         struct r600_resource *resource = &rtex->resource;
 337         struct radeon *radeon = (struct radeon *)screen->winsys;
 338
 339         if (rtex->flushed_depth_texture)
 340                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 341
 342         if (resource->bo) {
 343                 r600_bo_reference(radeon, &resource->bo, NULL);
 344         }
 345         FREE(rtex);
 346 }
 347
 348 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 349                                        struct pipe_resource *ptex,
 350                                        struct winsys_handle *whandle)
 351 {
 352         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 353         struct r600_resource *resource = &rtex->resource;
 354         struct radeon *radeon = (struct radeon *)screen->winsys;
 355
 356         return r600_bo_get_winsys_handle(radeon, resource->bo,
 357                         rtex->pitch_in_bytes[0], whandle);
 358 }
 359
 360 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 361                                                 struct pipe_resource *texture,
 362                                                 unsigned face, unsigned level,
 363                                                 unsigned zslice, unsigned flags)
 364 {
 365         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 366         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 367         unsigned offset, tile_height;
 368
 369         if (surface == NULL)
 370                 return NULL;
 371         offset = r600_texture_get_offset(rtex, level, zslice, face);
 372         pipe_reference_init(&surface->base.reference, 1);
 373         pipe_resource_reference(&surface->base.texture, texture);
 374         surface->base.format = texture->format;
 375         surface->base.width = mip_minify(texture->width0, level);
 376         surface->base.height = mip_minify(texture->height0, level);
 377         surface->base.offset = offset;
 378         surface->base.usage = flags;
 379         surface->base.zslice = zslice;
 380         surface->base.texture = texture;
 381         surface->base.face = face;
 382         surface->base.level = level;
 383
 384         tile_height = r600_get_height_alignment(screen, rtex->array_mode[level]);
 385         surface->aligned_height = align(surface->base.height, tile_height);
 386         return &surface->base;
 387 }
 388
 389 static void r600_tex_surface_destroy(struct pipe_surface *surface)
 390 {
 391         pipe_resource_reference(&surface->texture, NULL);
 392         FREE(surface);
 393 }
 394
 395
 396 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 397                                                const struct pipe_resource *templ,
 398                                                struct winsys_handle *whandle)
 399 {
 400         struct radeon *rw = (struct radeon*)screen->winsys;
 401         struct r600_bo *bo = NULL;
 402         unsigned array_mode = 0;
 403
 404         /* Support only 2D textures without mipmaps */
 405         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 406               templ->depth0 != 1 || templ->last_level != 0)
 407                 return NULL;
 408
 409         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 410         if (bo == NULL) {
 411                 return NULL;
 412         }
 413
 414         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 415                                                                   whandle->stride,
 416                                                                   0,
 417                                                                   bo);
 418 }
 419
 420 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 421                                                 struct pipe_resource *texture,
 422                                                 unsigned face, unsigned level)
 423 {
 424         /* FIXME */
 425         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 426 }
 427
 428 int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
 429
 430 int r600_texture_depth_flush(struct pipe_context *ctx,
 431                              struct pipe_resource *texture)
 432 {
 433         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 434         struct pipe_resource resource;
 435
 436         if (rtex->flushed_depth_texture)
 437                 goto out;
 438
 439         resource.target = PIPE_TEXTURE_2D;
 440         resource.format = texture->format;
 441         resource.width0 = texture->width0;
 442         resource.height0 = texture->height0;
 443         resource.depth0 = 1;
 444         resource.last_level = 0;
 445         resource.nr_samples = 0;
 446         resource.usage = PIPE_USAGE_DYNAMIC;
 447         resource.bind = 0;
 448         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 449
 450         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 451
 452         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 453         if (rtex->flushed_depth_texture == NULL) {
 454                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 455                 return -ENOMEM;
 456         }
 457
 458 out:
 459         /* XXX: only do this if the depth texture has actually changed:
 460          */
 461         r600_blit_uncompress_depth_ptr(ctx, rtex);
 462         return 0;
 463 }
 464
 465 /* Needs adjustment for pixelformat:
 466  */
 467 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 468 {
 469         return box->width * box->depth * box->height;
 470 };
 471
 472
 473 /* Figure out whether u_blitter will fallback to a transfer operation.
 474  * If so, don't use a staging resource.
 475  */
 476 static boolean permit_hardware_blit(struct pipe_screen *screen,
 477                                     struct pipe_resource *res)
 478 {
 479         unsigned bind;
 480
 481         if (util_format_is_depth_or_stencil(res->format))
 482                 bind = PIPE_BIND_DEPTH_STENCIL;
 483         else
 484                 bind = PIPE_BIND_RENDER_TARGET;
 485
 486         /* See r600_resource_copy_region: there is something wrong
 487          * with depth resource copies at the moment so avoid them for
 488          * now.
 489          */
 490         if (util_format_get_component_bits(res->format,
 491                                            UTIL_FORMAT_COLORSPACE_ZS,
 492                                            0) != 0)
 493                 return FALSE;
 494
 495         if (!screen->is_format_supported(screen,
 496                                          res->format,
 497                                          res->target,
 498                                          res->nr_samples,
 499                                          bind, 0))
 500                 return FALSE;
 501
 502         if (!screen->is_format_supported(screen,
 503                                          res->format,
 504                                          res->target,
 505                                          res->nr_samples,
 506                                          PIPE_BIND_SAMPLER_VIEW, 0))
 507                 return FALSE;
 508
 509         return TRUE;
 510 }
 511
 512 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 513                                                 struct pipe_resource *texture,
 514                                                 struct pipe_subresource sr,
 515                                                 unsigned usage,
 516                                                 const struct pipe_box *box)
 517 {
 518         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 519         struct pipe_resource resource;
 520         struct r600_transfer *trans;
 521         int r;
 522         boolean use_staging_texture = FALSE;
 523
 524         /* We cannot map a tiled texture directly because the data is
 525          * in a different order, therefore we do detiling using a blit.
 526          *
 527          * Also, use a temporary in GTT memory for read transfers, as
 528          * the CPU is much happier reading out of cached system memory
 529          * than uncached VRAM.
 530          */
 531         if (rtex->tiled)
 532                 use_staging_texture = TRUE;
 533
 534         if ((usage & PIPE_TRANSFER_READ) &&
 535             u_box_volume(box) > 1024)
 536                 use_staging_texture = TRUE;
 537
 538         /* XXX: Use a staging texture for uploads if the underlying BO
 539          * is busy.  No interface for checking that currently? so do
 540          * it eagerly whenever the transfer doesn't require a readback
 541          * and might block.
 542          */
 543         if ((usage & PIPE_TRANSFER_WRITE) &&
 544             !(usage & (PIPE_TRANSFER_READ |
 545                        PIPE_TRANSFER_DONTBLOCK |
 546                        PIPE_TRANSFER_UNSYNCHRONIZED)))
 547                 use_staging_texture = TRUE;
 548
 549         if (!permit_hardware_blit(ctx->screen, texture) ||
 550             (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 551                 use_staging_texture = FALSE;
 552
 553         trans = CALLOC_STRUCT(r600_transfer);
 554         if (trans == NULL)
 555                 return NULL;
 556         pipe_resource_reference(&trans->transfer.resource, texture);
 557         trans->transfer.sr = sr;
 558         trans->transfer.usage = usage;
 559         trans->transfer.box = *box;
 560         if (rtex->depth) {
 561                 /* XXX: only readback the rectangle which is being mapped?
 562                  */
 563                 /* XXX: when discard is true, no need to read back from depth texture
 564                  */
 565                 r = r600_texture_depth_flush(ctx, texture);
 566                 if (r < 0) {
 567                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 568                         pipe_resource_reference(&trans->transfer.resource, NULL);
 569                         FREE(trans);
 570                         return NULL;
 571                 }
 572         } else if (use_staging_texture) {
 573                 resource.target = PIPE_TEXTURE_2D;
 574                 resource.format = texture->format;
 575                 resource.width0 = box->width;
 576                 resource.height0 = box->height;
 577                 resource.depth0 = 1;
 578                 resource.last_level = 0;
 579                 resource.nr_samples = 0;
 580                 resource.usage = PIPE_USAGE_STAGING;
 581                 resource.bind = 0;
 582                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 583                 /* For texture reading, the temporary (detiled) texture is used as
 584                  * a render target when blitting from a tiled texture. */
 585                 if (usage & PIPE_TRANSFER_READ) {
 586                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 587                 }
 588                 /* For texture writing, the temporary texture is used as a sampler
 589                  * when blitting into a tiled texture. */
 590                 if (usage & PIPE_TRANSFER_WRITE) {
 591                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 592                 }
 593                 /* Create the temporary texture. */
 594                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 595                 if (trans->staging_texture == NULL) {
 596                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 597                         pipe_resource_reference(&trans->transfer.resource, NULL);
 598                         FREE(trans);
 599                         return NULL;
 600                 }
 601
 602                 trans->transfer.stride =
 603                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 604                 if (usage & PIPE_TRANSFER_READ) {
 605                         r600_copy_to_staging_texture(ctx, trans);
 606                         /* Always referenced in the blit. */
 607                         ctx->flush(ctx, 0, NULL);
 608                 }
 609                 return &trans->transfer;
 610         }
 611         trans->transfer.stride = rtex->pitch_in_bytes[sr.level];
 612         trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
 613         return &trans->transfer;
 614 }
 615
 616 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 617                                    struct pipe_transfer *transfer)
 618 {
 619         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 620         struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 621
 622         if (rtransfer->staging_texture) {
 623                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 624                         r600_copy_from_staging_texture(ctx, rtransfer);
 625                 }
 626                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 627         }
 628         if (rtex->flushed_depth_texture) {
 629                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 630         }
 631         pipe_resource_reference(&transfer->resource, NULL);
 632         FREE(transfer);
 633 }
 634
 635 void* r600_texture_transfer_map(struct pipe_context *ctx,
 636                                 struct pipe_transfer* transfer)
 637 {
 638         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 639         struct r600_bo *bo;
 640         enum pipe_format format = transfer->resource->format;
 641         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 642         unsigned offset = 0;
 643         unsigned usage = 0;
 644         char *map;
 645
 646         if (rtransfer->staging_texture) {
 647                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 648         } else {
 649                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 650
 651                 if (rtex->flushed_depth_texture)
 652                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 653                 else
 654                         bo = ((struct r600_resource *)transfer->resource)->bo;
 655
 656                 offset = rtransfer->offset +
 657                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 658                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 659         }
 660
 661         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 662                 usage |= PB_USAGE_CPU_WRITE;
 663
 664                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 665                 }
 666
 667                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 668                 }
 669         }
 670
 671         if (transfer->usage & PIPE_TRANSFER_READ) {
 672                 usage |= PB_USAGE_CPU_READ;
 673         }
 674
 675         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 676                 usage |= PB_USAGE_DONTBLOCK;
 677         }
 678
 679         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 680                 usage |= PB_USAGE_UNSYNCHRONIZED;
 681         }
 682
 683         map = r600_bo_map(radeon, bo, usage, ctx);
 684         if (!map) {
 685                 return NULL;
 686         }
 687
 688         return map + offset;
 689 }
 690
 691 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 692                                  struct pipe_transfer* transfer)
 693 {
 694         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 695         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 696         struct r600_bo *bo;
 697
 698         if (rtransfer->staging_texture) {
 699                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 700         } else {
 701                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 702
 703                 if (rtex->flushed_depth_texture) {
 704                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 705                 } else {
 706                         bo = ((struct r600_resource *)transfer->resource)->bo;
 707                 }
 708         }
 709         r600_bo_unmap(radeon, bo);
 710 }
 711
 712 struct u_resource_vtbl r600_texture_vtbl =
 713 {
 714         r600_texture_get_handle,        /* get_handle */
 715         r600_texture_destroy,           /* resource_destroy */
 716         r600_texture_is_referenced,     /* is_resource_referenced */
 717         r600_texture_get_transfer,      /* get_transfer */
 718         r600_texture_transfer_destroy,  /* transfer_destroy */
 719         r600_texture_transfer_map,      /* transfer_map */
 720         u_default_transfer_flush_region,/* transfer_flush_region */
 721         r600_texture_transfer_unmap,    /* transfer_unmap */
 722         u_default_transfer_inline_write /* transfer_inline_write */
 723 };
 724
 725 void r600_init_screen_texture_functions(struct pipe_screen *screen)
 726 {
 727         screen->get_tex_surface = r600_get_tex_surface;
 728         screen->tex_surface_destroy = r600_tex_surface_destroy;
 729 }
 730
 731 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 732                 const unsigned char *swizzle_view)
 733 {
 734         unsigned i;
 735         unsigned char swizzle[4];
 736         unsigned result = 0;
 737         const uint32_t swizzle_shift[4] = {
 738                 16, 19, 22, 25,
 739         };
 740         const uint32_t swizzle_bit[4] = {
 741                 0, 1, 2, 3,
 742         };
 743
 744         if (swizzle_view) {
 745                 /* Combine two sets of swizzles. */
 746                 for (i = 0; i < 4; i++) {
 747                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 748                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 749                 }
 750         } else {
 751                 memcpy(swizzle, swizzle_format, 4);
 752         }
 753
 754         /* Get swizzle. */
 755         for (i = 0; i < 4; i++) {
 756                 switch (swizzle[i]) {
 757                 case UTIL_FORMAT_SWIZZLE_Y:
 758                         result |= swizzle_bit[1] << swizzle_shift[i];
 759                         break;
 760                 case UTIL_FORMAT_SWIZZLE_Z:
 761                         result |= swizzle_bit[2] << swizzle_shift[i];
 762                         break;
 763                 case UTIL_FORMAT_SWIZZLE_W:
 764                         result |= swizzle_bit[3] << swizzle_shift[i];
 765                         break;
 766                 case UTIL_FORMAT_SWIZZLE_0:
 767                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 768                         break;
 769                 case UTIL_FORMAT_SWIZZLE_1:
 770                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 771                         break;
 772                 default: /* UTIL_FORMAT_SWIZZLE_X */
 773                         result |= swizzle_bit[0] << swizzle_shift[i];
 774                 }
 775         }
 776         return result;
 777 }
 778
 779 /* texture format translate */
 780 uint32_t r600_translate_texformat(enum pipe_format format,
 781                                   const unsigned char *swizzle_view,
 782                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 783 {
 784         uint32_t result = 0, word4 = 0, yuv_format = 0;
 785         const struct util_format_description *desc;
 786         boolean uniform = TRUE;
 787         int i;
 788         const uint32_t sign_bit[4] = {
 789                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 790                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 791                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 792                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 793         };
 794         desc = util_format_description(format);
 795
 796         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 797
 798         /* Colorspace (return non-RGB formats directly). */
 799         switch (desc->colorspace) {
 800                 /* Depth stencil formats */
 801         case UTIL_FORMAT_COLORSPACE_ZS:
 802                 switch (format) {
 803                 case PIPE_FORMAT_Z16_UNORM:
 804                         result = FMT_16;
 805                         goto out_word4;
 806                 case PIPE_FORMAT_X24S8_USCALED:
 807                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 808                 case PIPE_FORMAT_Z24X8_UNORM:
 809                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 810                         result = FMT_8_24;
 811                         goto out_word4;
 812                 case PIPE_FORMAT_S8X24_USCALED:
 813                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 814                 case PIPE_FORMAT_X8Z24_UNORM:
 815                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 816                         result = FMT_24_8;
 817                         goto out_word4;
 818                 case PIPE_FORMAT_S8_USCALED:
 819                         result = FMT_8;
 820                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 821                         goto out_word4;
 822                 default:
 823                         goto out_unknown;
 824                 }
 825
 826         case UTIL_FORMAT_COLORSPACE_YUV:
 827                 yuv_format |= (1 << 30);
 828                 switch (format) {
 829                 case PIPE_FORMAT_UYVY:
 830                 case PIPE_FORMAT_YUYV:
 831                 default:
 832                         break;
 833                 }
 834                 goto out_unknown; /* TODO */
 835
 836         case UTIL_FORMAT_COLORSPACE_SRGB:
 837                 word4 |= S_038010_FORCE_DEGAMMA(1);
 838                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 839                         goto out_unknown; /* fails for some reason - TODO */
 840                 break;
 841
 842         default:
 843                 break;
 844         }
 845
 846         /* S3TC formats. TODO */
 847         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 848                 static int r600_enable_s3tc = -1;
 849
 850                 if (r600_enable_s3tc == -1)
 851                         r600_enable_s3tc =
 852                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 853
 854                 if (!r600_enable_s3tc)
 855                         goto out_unknown;
 856
 857                 switch (format) {
 858                 case PIPE_FORMAT_DXT1_RGB:
 859                 case PIPE_FORMAT_DXT1_RGBA:
 860                         result = FMT_BC1;
 861                         goto out_word4;
 862                 case PIPE_FORMAT_DXT3_RGBA:
 863                         result = FMT_BC2;
 864                         goto out_word4;
 865                 case PIPE_FORMAT_DXT5_RGBA:
 866                         result = FMT_BC3;
 867                         goto out_word4;
 868                 default:
 869                         goto out_unknown;
 870                 }
 871         }
 872
 873
 874         for (i = 0; i < desc->nr_channels; i++) {
 875                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 876                         word4 |= sign_bit[i];
 877                 }
 878         }
 879
 880         /* R8G8Bx_SNORM - TODO CxV8U8 */
 881
 882         /* RGTC - TODO */
 883
 884         /* See whether the components are of the same size. */
 885         for (i = 1; i < desc->nr_channels; i++) {
 886                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 887         }
 888
 889         /* Non-uniform formats. */
 890         if (!uniform) {
 891                 switch(desc->nr_channels) {
 892                 case 3:
 893                         if (desc->channel[0].size == 5 &&
 894                             desc->channel[1].size == 6 &&
 895                             desc->channel[2].size == 5) {
 896                                 result = FMT_5_6_5;
 897                                 goto out_word4;
 898                         }
 899                         goto out_unknown;
 900                 case 4:
 901                         if (desc->channel[0].size == 5 &&
 902                             desc->channel[1].size == 5 &&
 903                             desc->channel[2].size == 5 &&
 904                             desc->channel[3].size == 1) {
 905                                 result = FMT_1_5_5_5;
 906                                 goto out_word4;
 907                         }
 908                         if (desc->channel[0].size == 10 &&
 909                             desc->channel[1].size == 10 &&
 910                             desc->channel[2].size == 10 &&
 911                             desc->channel[3].size == 2) {
 912                                 result = FMT_10_10_10_2;
 913                                 goto out_word4;
 914                         }
 915                         goto out_unknown;
 916                 }
 917                 goto out_unknown;
 918         }
 919
 920         /* Find the first non-VOID channel. */
 921         for (i = 0; i < 4; i++) {
 922                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 923                         break;
 924                 }
 925         }
 926
 927         if (i == 4)
 928                 goto out_unknown;
 929
 930         /* uniform formats */
 931         switch (desc->channel[i].type) {
 932         case UTIL_FORMAT_TYPE_UNSIGNED:
 933         case UTIL_FORMAT_TYPE_SIGNED:
 934                 if (!desc->channel[i].normalized &&
 935                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 936                         goto out_unknown;
 937                 }
 938
 939                 switch (desc->channel[i].size) {
 940                 case 4:
 941                         switch (desc->nr_channels) {
 942                         case 2:
 943                                 result = FMT_4_4;
 944                                 goto out_word4;
 945                         case 4:
 946                                 result = FMT_4_4_4_4;
 947                                 goto out_word4;
 948                         }
 949                         goto out_unknown;
 950                 case 8:
 951                         switch (desc->nr_channels) {
 952                         case 1:
 953                                 result = FMT_8;
 954                                 goto out_word4;
 955                         case 2:
 956                                 result = FMT_8_8;
 957                                 goto out_word4;
 958                         case 4:
 959                                 result = FMT_8_8_8_8;
 960                                 goto out_word4;
 961                         }
 962                         goto out_unknown;
 963                 case 16:
 964                         switch (desc->nr_channels) {
 965                         case 1:
 966                                 result = FMT_16;
 967                                 goto out_word4;
 968                         case 2:
 969                                 result = FMT_16_16;
 970                                 goto out_word4;
 971                         case 4:
 972                                 result = FMT_16_16_16_16;
 973                                 goto out_word4;
 974                         }
 975                 }
 976                 goto out_unknown;
 977
 978         case UTIL_FORMAT_TYPE_FLOAT:
 979                 switch (desc->channel[i].size) {
 980                 case 16:
 981                         switch (desc->nr_channels) {
 982                         case 1:
 983                                 result = FMT_16_FLOAT;
 984                                 goto out_word4;
 985                         case 2:
 986                                 result = FMT_16_16_FLOAT;
 987                                 goto out_word4;
 988                         case 4:
 989                                 result = FMT_16_16_16_16_FLOAT;
 990                                 goto out_word4;
 991                         }
 992                         goto out_unknown;
 993                 case 32:
 994                         switch (desc->nr_channels) {
 995                         case 1:
 996                                 result = FMT_32_FLOAT;
 997                                 goto out_word4;
 998                         case 2:
 999                                 result = FMT_32_32_FLOAT;
1000                                 goto out_word4;
1001                         case 4:
1002                                 result = FMT_32_32_32_32_FLOAT;
1003                                 goto out_word4;
1004                         }
1005                 }
1006
1007         }
1008 out_word4:
1009         if (word4_p)
1010                 *word4_p = word4;
1011         if (yuv_format_p)
1012                 *yuv_format_p = yuv_format;
1013         return result;
1014 out_unknown:
1015 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1016         return ~0;
1017 }