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amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbuf
[mesa.git] / src / gallium / drivers / r600 / radeon_vce.h
1 /**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #ifndef RADEON_VCE_H
35 #define RADEON_VCE_H
36
37 #include "util/list.h"
38
39 #define RVCE_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
40 #define RVCE_BEGIN(cmd) { \
41 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
42 RVCE_CS(cmd)
43 #define RVCE_READ(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
44 #define RVCE_WRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
45 #define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
46 #define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
47
48 #define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
49 #define RVCE_MAX_AUX_BUFFER_NUM 4
50
51 struct r600_common_screen;
52
53 /* driver dependent callback */
54 typedef void (*rvce_get_buffer)(struct pipe_resource *resource,
55 struct pb_buffer **handle,
56 struct radeon_surf **surface);
57
58 /* Coded picture buffer slot */
59 struct rvce_cpb_slot {
60 struct list_head list;
61
62 unsigned index;
63 enum pipe_h264_enc_picture_type picture_type;
64 unsigned frame_num;
65 unsigned pic_order_cnt;
66 };
67
68 struct rvce_rate_control {
69 uint32_t rc_method;
70 uint32_t target_bitrate;
71 uint32_t peak_bitrate;
72 uint32_t frame_rate_num;
73 uint32_t gop_size;
74 uint32_t quant_i_frames;
75 uint32_t quant_p_frames;
76 uint32_t quant_b_frames;
77 uint32_t vbv_buffer_size;
78 uint32_t frame_rate_den;
79 uint32_t vbv_buf_lv;
80 uint32_t max_au_size;
81 uint32_t qp_initial_mode;
82 uint32_t target_bits_picture;
83 uint32_t peak_bits_picture_integer;
84 uint32_t peak_bits_picture_fraction;
85 uint32_t min_qp;
86 uint32_t max_qp;
87 uint32_t skip_frame_enable;
88 uint32_t fill_data_enable;
89 uint32_t enforce_hrd;
90 uint32_t b_pics_delta_qp;
91 uint32_t ref_b_pics_delta_qp;
92 uint32_t rc_reinit_disable;
93 uint32_t enc_lcvbr_init_qp_flag;
94 uint32_t lcvbrsatd_based_nonlinear_bit_budget_flag;
95 };
96
97 struct rvce_motion_estimation {
98 uint32_t enc_ime_decimation_search;
99 uint32_t motion_est_half_pixel;
100 uint32_t motion_est_quarter_pixel;
101 uint32_t disable_favor_pmv_point;
102 uint32_t force_zero_point_center;
103 uint32_t lsmvert;
104 uint32_t enc_search_range_x;
105 uint32_t enc_search_range_y;
106 uint32_t enc_search1_range_x;
107 uint32_t enc_search1_range_y;
108 uint32_t disable_16x16_frame1;
109 uint32_t disable_satd;
110 uint32_t enable_amd;
111 uint32_t enc_disable_sub_mode;
112 uint32_t enc_ime_skip_x;
113 uint32_t enc_ime_skip_y;
114 uint32_t enc_en_ime_overw_dis_subm;
115 uint32_t enc_ime_overw_dis_subm_no;
116 uint32_t enc_ime2_search_range_x;
117 uint32_t enc_ime2_search_range_y;
118 uint32_t parallel_mode_speedup_enable;
119 uint32_t fme0_enc_disable_sub_mode;
120 uint32_t fme1_enc_disable_sub_mode;
121 uint32_t ime_sw_speedup_enable;
122 };
123
124 struct rvce_pic_control {
125 uint32_t enc_use_constrained_intra_pred;
126 uint32_t enc_cabac_enable;
127 uint32_t enc_cabac_idc;
128 uint32_t enc_loop_filter_disable;
129 int32_t enc_lf_beta_offset;
130 int32_t enc_lf_alpha_c0_offset;
131 uint32_t enc_crop_left_offset;
132 uint32_t enc_crop_right_offset;
133 uint32_t enc_crop_top_offset;
134 uint32_t enc_crop_bottom_offset;
135 uint32_t enc_num_mbs_per_slice;
136 uint32_t enc_intra_refresh_num_mbs_per_slot;
137 uint32_t enc_force_intra_refresh;
138 uint32_t enc_force_imb_period;
139 uint32_t enc_pic_order_cnt_type;
140 uint32_t log2_max_pic_order_cnt_lsb_minus4;
141 uint32_t enc_sps_id;
142 uint32_t enc_pps_id;
143 uint32_t enc_constraint_set_flags;
144 uint32_t enc_b_pic_pattern;
145 uint32_t weight_pred_mode_b_picture;
146 uint32_t enc_number_of_reference_frames;
147 uint32_t enc_max_num_ref_frames;
148 uint32_t enc_num_default_active_ref_l0;
149 uint32_t enc_num_default_active_ref_l1;
150 uint32_t enc_slice_mode;
151 uint32_t enc_max_slice_size;
152 };
153
154 struct rvce_task_info {
155 uint32_t offset_of_next_task_info;
156 uint32_t task_operation;
157 uint32_t reference_picture_dependency;
158 uint32_t collocate_flag_dependency;
159 uint32_t feedback_index;
160 uint32_t video_bitstream_ring_index;
161 };
162
163 struct rvce_feedback_buf_pkg {
164 uint32_t feedback_ring_address_hi;
165 uint32_t feedback_ring_address_lo;
166 uint32_t feedback_ring_size;
167 };
168
169 struct rvce_rdo {
170 uint32_t enc_disable_tbe_pred_i_frame;
171 uint32_t enc_disable_tbe_pred_p_frame;
172 uint32_t use_fme_interpol_y;
173 uint32_t use_fme_interpol_uv;
174 uint32_t use_fme_intrapol_y;
175 uint32_t use_fme_intrapol_uv;
176 uint32_t use_fme_interpol_y_1;
177 uint32_t use_fme_interpol_uv_1;
178 uint32_t use_fme_intrapol_y_1;
179 uint32_t use_fme_intrapol_uv_1;
180 uint32_t enc_16x16_cost_adj;
181 uint32_t enc_skip_cost_adj;
182 uint32_t enc_force_16x16_skip;
183 uint32_t enc_disable_threshold_calc_a;
184 uint32_t enc_luma_coeff_cost;
185 uint32_t enc_luma_mb_coeff_cost;
186 uint32_t enc_chroma_coeff_cost;
187 };
188
189 struct rvce_vui {
190 uint32_t aspect_ratio_info_present_flag;
191 uint32_t aspect_ratio_idc;
192 uint32_t sar_width;
193 uint32_t sar_height;
194 uint32_t overscan_info_present_flag;
195 uint32_t overscan_Approp_flag;
196 uint32_t video_signal_type_present_flag;
197 uint32_t video_format;
198 uint32_t video_full_range_flag;
199 uint32_t color_description_present_flag;
200 uint32_t color_prim;
201 uint32_t transfer_char;
202 uint32_t matrix_coef;
203 uint32_t chroma_loc_info_present_flag;
204 uint32_t chroma_loc_top;
205 uint32_t chroma_loc_bottom;
206 uint32_t timing_info_present_flag;
207 uint32_t num_units_in_tick;
208 uint32_t time_scale;
209 uint32_t fixed_frame_rate_flag;
210 uint32_t nal_hrd_parameters_present_flag;
211 uint32_t cpb_cnt_minus1;
212 uint32_t bit_rate_scale;
213 uint32_t cpb_size_scale;
214 uint32_t bit_rate_value_minus;
215 uint32_t cpb_size_value_minus;
216 uint32_t cbr_flag;
217 uint32_t initial_cpb_removal_delay_length_minus1;
218 uint32_t cpb_removal_delay_length_minus1;
219 uint32_t dpb_output_delay_length_minus1;
220 uint32_t time_offset_length;
221 uint32_t low_delay_hrd_flag;
222 uint32_t pic_struct_present_flag;
223 uint32_t bitstream_restriction_present_flag;
224 uint32_t motion_vectors_over_pic_boundaries_flag;
225 uint32_t max_bytes_per_pic_denom;
226 uint32_t max_bits_per_mb_denom;
227 uint32_t log2_max_mv_length_hori;
228 uint32_t log2_max_mv_length_vert;
229 uint32_t num_reorder_frames;
230 uint32_t max_dec_frame_buffering;
231 };
232
233 struct rvce_enc_operation {
234 uint32_t insert_headers;
235 uint32_t picture_structure;
236 uint32_t allowed_max_bitstream_size;
237 uint32_t force_refresh_map;
238 uint32_t insert_aud;
239 uint32_t end_of_sequence;
240 uint32_t end_of_stream;
241 uint32_t input_picture_luma_address_hi;
242 uint32_t input_picture_luma_address_lo;
243 uint32_t input_picture_chroma_address_hi;
244 uint32_t input_picture_chroma_address_lo;
245 uint32_t enc_input_frame_y_pitch;
246 uint32_t enc_input_pic_luma_pitch;
247 uint32_t enc_input_pic_chroma_pitch;;
248 uint32_t enc_input_pic_addr_array;
249 uint32_t enc_input_pic_addr_array_disable2pipe_disablemboffload;
250 uint32_t enc_input_pic_tile_config;
251 uint32_t enc_pic_type;
252 uint32_t enc_idr_flag;
253 uint32_t enc_idr_pic_id;
254 uint32_t enc_mgs_key_pic;
255 uint32_t enc_reference_flag;
256 uint32_t enc_temporal_layer_index;
257 uint32_t num_ref_idx_active_override_flag;
258 uint32_t num_ref_idx_l0_active_minus1;
259 uint32_t num_ref_idx_l1_active_minus1;
260 uint32_t enc_ref_list_modification_op;
261 uint32_t enc_ref_list_modification_num;
262 uint32_t enc_decoded_picture_marking_op;
263 uint32_t enc_decoded_picture_marking_num;
264 uint32_t enc_decoded_picture_marking_idx;
265 uint32_t enc_decoded_ref_base_picture_marking_op;
266 uint32_t enc_decoded_ref_base_picture_marking_num;
267 uint32_t l0_picture_structure;
268 uint32_t l0_enc_pic_type;
269 uint32_t l0_frame_number;
270 uint32_t l0_picture_order_count;
271 uint32_t l0_luma_offset;
272 uint32_t l0_chroma_offset;
273 uint32_t l1_picture_structure;
274 uint32_t l1_enc_pic_type;
275 uint32_t l1_frame_number;
276 uint32_t l1_picture_order_count;
277 uint32_t l1_luma_offset;
278 uint32_t l1_chroma_offset;
279 uint32_t enc_reconstructed_luma_offset;
280 uint32_t enc_reconstructed_chroma_offset;;
281 uint32_t enc_coloc_buffer_offset;
282 uint32_t enc_reconstructed_ref_base_picture_luma_offset;
283 uint32_t enc_reconstructed_ref_base_picture_chroma_offset;
284 uint32_t enc_reference_ref_base_picture_luma_offset;
285 uint32_t enc_reference_ref_base_picture_chroma_offset;
286 uint32_t picture_count;
287 uint32_t frame_number;
288 uint32_t picture_order_count;
289 uint32_t num_i_pic_remain_in_rcgop;
290 uint32_t num_p_pic_remain_in_rcgop;
291 uint32_t num_b_pic_remain_in_rcgop;
292 uint32_t num_ir_pic_remain_in_rcgop;
293 uint32_t enable_intra_refresh;
294 uint32_t aq_variance_en;
295 uint32_t aq_block_size;
296 uint32_t aq_mb_variance_sel;
297 uint32_t aq_frame_variance_sel;
298 uint32_t aq_param_a;
299 uint32_t aq_param_b;
300 uint32_t aq_param_c;
301 uint32_t aq_param_d;
302 uint32_t aq_param_e;
303 uint32_t context_in_sfb;
304 };
305
306 struct rvce_enc_create {
307 uint32_t enc_use_circular_buffer;
308 uint32_t enc_profile;
309 uint32_t enc_level;
310 uint32_t enc_pic_struct_restriction;
311 uint32_t enc_image_width;
312 uint32_t enc_image_height;
313 uint32_t enc_ref_pic_luma_pitch;
314 uint32_t enc_ref_pic_chroma_pitch;
315 uint32_t enc_ref_y_height_in_qw;
316 uint32_t enc_ref_pic_addr_array_enc_pic_struct_restriction_disable_rdo;
317 uint32_t enc_pre_encode_context_buffer_offset;
318 uint32_t enc_pre_encode_input_luma_buffer_offset;
319 uint32_t enc_pre_encode_input_chroma_buffer_offset;
320 uint32_t enc_pre_encode_mode_chromaflag_vbaqmode_scenechangesensitivity;
321 };
322
323 struct rvce_config_ext {
324 uint32_t enc_enable_perf_logging;
325 };
326
327 struct rvce_h264_enc_pic {
328 struct rvce_rate_control rc;
329 struct rvce_motion_estimation me;
330 struct rvce_pic_control pc;
331 struct rvce_task_info ti;
332 struct rvce_feedback_buf_pkg fb;
333 struct rvce_rdo rdo;
334 struct rvce_vui vui;
335 struct rvce_enc_operation eo;
336 struct rvce_enc_create ec;
337 struct rvce_config_ext ce;
338
339 unsigned quant_i_frames;
340 unsigned quant_p_frames;
341 unsigned quant_b_frames;
342
343 enum pipe_h264_enc_picture_type picture_type;
344 unsigned frame_num;
345 unsigned frame_num_cnt;
346 unsigned p_remain;
347 unsigned i_remain;
348 unsigned idr_pic_id;
349 unsigned gop_cnt;
350 unsigned gop_size;
351 unsigned pic_order_cnt;
352 unsigned ref_idx_l0;
353 unsigned ref_idx_l1;
354 unsigned addrmode_arraymode_disrdo_distwoinstants;
355
356 bool not_referenced;
357 bool is_idr;
358 bool has_ref_pic_list;
359 bool enable_vui;
360 unsigned int ref_pic_list_0[32];
361 unsigned int ref_pic_list_1[32];
362 unsigned int frame_idx[32];
363 };
364
365 /* VCE encoder representation */
366 struct rvce_encoder {
367 struct pipe_video_codec base;
368
369 /* version specific packets */
370 void (*session)(struct rvce_encoder *enc);
371 void (*create)(struct rvce_encoder *enc);
372 void (*feedback)(struct rvce_encoder *enc);
373 void (*rate_control)(struct rvce_encoder *enc);
374 void (*config_extension)(struct rvce_encoder *enc);
375 void (*pic_control)(struct rvce_encoder *enc);
376 void (*motion_estimation)(struct rvce_encoder *enc);
377 void (*rdo)(struct rvce_encoder *enc);
378 void (*vui)(struct rvce_encoder *enc);
379 void (*config)(struct rvce_encoder *enc);
380 void (*encode)(struct rvce_encoder *enc);
381 void (*destroy)(struct rvce_encoder *enc);
382 void (*task_info)(struct rvce_encoder *enc, uint32_t op,
383 uint32_t dep, uint32_t fb_idx,
384 uint32_t ring_idx);
385
386 unsigned stream_handle;
387
388 struct pipe_screen *screen;
389 struct radeon_winsys* ws;
390 struct radeon_cmdbuf* cs;
391
392 rvce_get_buffer get_buffer;
393
394 struct pb_buffer* handle;
395 struct radeon_surf* luma;
396 struct radeon_surf* chroma;
397
398 struct pb_buffer* bs_handle;
399 unsigned bs_size;
400
401 struct rvce_cpb_slot *cpb_array;
402 struct list_head cpb_slots;
403 unsigned cpb_num;
404
405 struct rvid_buffer *fb;
406 struct rvid_buffer cpb;
407 struct pipe_h264_enc_picture_desc pic;
408 struct rvce_h264_enc_pic enc_pic;
409
410 unsigned task_info_idx;
411 unsigned bs_idx;
412
413 bool use_vm;
414 bool use_vui;
415 bool dual_pipe;
416 bool dual_inst;
417 };
418
419 /* CPB handling functions */
420 struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc);
421 struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc);
422 struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc);
423 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
424 signed *luma_offset, signed *chroma_offset);
425
426 struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
427 const struct pipe_video_codec *templat,
428 struct radeon_winsys* ws,
429 rvce_get_buffer get_buffer);
430
431 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen);
432
433 void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
434 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
435 signed offset);
436
437 /* init vce fw 40.2.2 specific callbacks */
438 void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
439
440 /* init vce fw 50 specific callbacks */
441 void radeon_vce_50_init(struct rvce_encoder *enc);
442
443 /* init vce fw 52 specific callbacks */
444 void radeon_vce_52_init(struct rvce_encoder *enc);
445
446 /* version specific function for getting parameters */
447 void (*get_pic_param)(struct rvce_encoder *enc,
448 struct pipe_h264_enc_picture_desc *pic);
449
450 /* get parameters for vce 40.2.2 */
451 void radeon_vce_40_2_2_get_param(struct rvce_encoder *enc,
452 struct pipe_h264_enc_picture_desc *pic);
453
454 /* get parameters for vce 50 */
455 void radeon_vce_50_get_param(struct rvce_encoder *enc,
456 struct pipe_h264_enc_picture_desc *pic);
457
458 /* get parameters for vce 52 */
459 void radeon_vce_52_get_param(struct rvce_encoder *enc,
460 struct pipe_h264_enc_picture_desc *pic);
461
462 #endif