0314598d6e3a7592d4ba2e96082c29108c2526eb
[mesa.git] / src / gallium / drivers / radeon / AMDILInstrPatterns.td
1 //===- AMDILInstrPatterns.td - AMDIL Target ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //===--------------------------------------------------------------------===//
10 // This file holds all the custom patterns that are used by the amdil backend
11 //
12 //===--------------------------------------------------------------------===//
13 //===--------------------------------------------------------------------===//
14 // Custom patterns for conversion operations
15 //===--------------------------------------------------------------------===////
16 // Pattern to remap integer or to IL_or
17 def : Pat<(i32 (or GPRI32:$src0, GPRI32:$src1)),
18 (i32 (BINARY_OR_i32 GPRI32:$src0, GPRI32:$src1))>;
19 // float ==> long patterns
20 // unsigned: f32 -> i64
21 def FTOUL : Pat<(i64 (fp_to_uint GPRF32:$src)),
22 (LCREATE (FTOU GPRF32:$src), (LOADCONST_i32 0))>;
23 // signed: f32 -> i64
24 def FTOL : Pat<(i64 (fp_to_sint GPRF32:$src)),
25 (LCREATE (FTOI GPRF32:$src), (LOADCONST_i32 0))>;
26 // unsigned: i64 -> f32
27 def ULTOF : Pat<(f32 (uint_to_fp GPRI64:$src)),
28 (UTOF (LLO GPRI64:$src))>;
29 // signed: i64 -> f32
30 def LTOF : Pat<(f32 (sint_to_fp GPRI64:$src)),
31 (ITOF (LLO GPRI64:$src))>;
32
33 // LLVM isn't lowering this correctly, so writing a pattern that
34 // matches it isntead.
35 def : Pat<(build_vector (i32 imm:$src)),
36 (VCREATE_v4i32 (LOADCONST_i32 imm:$src))>;
37
38 // Calls:
39 def : Pat<(IL_call tglobaladdr:$dst),
40 (CALL tglobaladdr:$dst)>;
41 def : Pat<(IL_call texternalsym:$dst),
42 (CALL texternalsym:$dst)>;
43 def : Pat<(IL_call tconstpool:$dst),
44 (CALL tconstpool:$dst)>;
45
46 include "AMDILConversions.td"