2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "radeonsi/si_pipe.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
31 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
32 struct pb_buffer
*buf
,
33 enum radeon_bo_usage usage
)
35 if (ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx_cs
, buf
, usage
)) {
38 if (radeon_emitted(ctx
->dma_cs
, 0) &&
39 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma_cs
, buf
, usage
)) {
45 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
46 struct r600_resource
*resource
,
49 enum radeon_bo_usage rusage
= RADEON_USAGE_READWRITE
;
52 assert(!(resource
->flags
& RADEON_FLAG_SPARSE
));
54 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
55 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
58 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
59 /* have to wait for the last write */
60 rusage
= RADEON_USAGE_WRITE
;
63 if (radeon_emitted(ctx
->gfx_cs
, ctx
->initial_gfx_cs_size
) &&
64 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx_cs
,
65 resource
->buf
, rusage
)) {
66 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
67 si_flush_gfx_cs(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
70 si_flush_gfx_cs(ctx
, 0, NULL
);
74 if (radeon_emitted(ctx
->dma_cs
, 0) &&
75 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma_cs
,
76 resource
->buf
, rusage
)) {
77 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
78 si_flush_dma_cs(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
81 si_flush_dma_cs(ctx
, 0, NULL
);
86 if (busy
|| !ctx
->ws
->buffer_wait(resource
->buf
, 0, rusage
)) {
87 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
90 /* We will be wait for the GPU. Wait for any offloaded
91 * CS flush to complete to avoid busy-waiting in the winsys. */
92 ctx
->ws
->cs_sync_flush(ctx
->gfx_cs
);
94 ctx
->ws
->cs_sync_flush(ctx
->dma_cs
);
98 /* Setting the CS to NULL will prevent doing checks we have done already. */
99 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
102 void si_init_resource_fields(struct si_screen
*sscreen
,
103 struct r600_resource
*res
,
104 uint64_t size
, unsigned alignment
)
106 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
109 res
->bo_alignment
= alignment
;
111 res
->texture_handle_allocated
= false;
112 res
->image_handle_allocated
= false;
114 switch (res
->b
.b
.usage
) {
115 case PIPE_USAGE_STREAM
:
116 res
->flags
= RADEON_FLAG_GTT_WC
;
118 case PIPE_USAGE_STAGING
:
119 /* Transfers are likely to occur more often with these
121 res
->domains
= RADEON_DOMAIN_GTT
;
123 case PIPE_USAGE_DYNAMIC
:
124 /* Older kernels didn't always flush the HDP cache before
127 if (sscreen
->info
.drm_major
== 2 &&
128 sscreen
->info
.drm_minor
< 40) {
129 res
->domains
= RADEON_DOMAIN_GTT
;
130 res
->flags
|= RADEON_FLAG_GTT_WC
;
134 case PIPE_USAGE_DEFAULT
:
135 case PIPE_USAGE_IMMUTABLE
:
137 /* Not listing GTT here improves performance in some
139 res
->domains
= RADEON_DOMAIN_VRAM
;
140 res
->flags
|= RADEON_FLAG_GTT_WC
;
144 if (res
->b
.b
.target
== PIPE_BUFFER
&&
145 res
->b
.b
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
146 PIPE_RESOURCE_FLAG_MAP_COHERENT
)) {
147 /* Use GTT for all persistent mappings with older
148 * kernels, because they didn't always flush the HDP
149 * cache before CS execution.
151 * Write-combined CPU mappings are fine, the kernel
152 * ensures all CPU writes finish before the GPU
153 * executes a command stream.
155 if (sscreen
->info
.drm_major
== 2 &&
156 sscreen
->info
.drm_minor
< 40)
157 res
->domains
= RADEON_DOMAIN_GTT
;
160 /* Tiled textures are unmappable. Always put them in VRAM. */
161 if ((res
->b
.b
.target
!= PIPE_BUFFER
&& !rtex
->surface
.is_linear
) ||
162 res
->b
.b
.flags
& R600_RESOURCE_FLAG_UNMAPPABLE
) {
163 res
->domains
= RADEON_DOMAIN_VRAM
;
164 res
->flags
|= RADEON_FLAG_NO_CPU_ACCESS
|
168 /* Displayable and shareable surfaces are not suballocated. */
169 if (res
->b
.b
.bind
& (PIPE_BIND_SHARED
| PIPE_BIND_SCANOUT
))
170 res
->flags
|= RADEON_FLAG_NO_SUBALLOC
; /* shareable */
172 res
->flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
174 if (sscreen
->debug_flags
& DBG(NO_WC
))
175 res
->flags
&= ~RADEON_FLAG_GTT_WC
;
177 if (res
->b
.b
.flags
& R600_RESOURCE_FLAG_READ_ONLY
)
178 res
->flags
|= RADEON_FLAG_READ_ONLY
;
180 if (res
->b
.b
.flags
& R600_RESOURCE_FLAG_32BIT
)
181 res
->flags
|= RADEON_FLAG_32BIT
;
183 /* Set expected VRAM and GART usage for the buffer. */
186 res
->max_forced_staging_uploads
= 0;
187 res
->b
.max_forced_staging_uploads
= 0;
189 if (res
->domains
& RADEON_DOMAIN_VRAM
) {
190 res
->vram_usage
= size
;
192 res
->max_forced_staging_uploads
=
193 res
->b
.max_forced_staging_uploads
=
194 sscreen
->info
.has_dedicated_vram
&&
195 size
>= sscreen
->info
.vram_vis_size
/ 4 ? 1 : 0;
196 } else if (res
->domains
& RADEON_DOMAIN_GTT
) {
197 res
->gart_usage
= size
;
201 bool si_alloc_resource(struct si_screen
*sscreen
,
202 struct r600_resource
*res
)
204 struct pb_buffer
*old_buf
, *new_buf
;
206 /* Allocate a new resource. */
207 new_buf
= sscreen
->ws
->buffer_create(sscreen
->ws
, res
->bo_size
,
209 res
->domains
, res
->flags
);
214 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
215 * NULL. This should prevent crashes with multiple contexts using
216 * the same buffer where one of the contexts invalidates it while
217 * the others are using it. */
219 res
->buf
= new_buf
; /* should be atomic */
220 res
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(res
->buf
);
222 if (res
->flags
& RADEON_FLAG_32BIT
) {
223 uint64_t start
= res
->gpu_address
;
224 uint64_t last
= start
+ res
->bo_size
- 1;
228 assert((start
>> 32) == sscreen
->info
.address32_hi
);
229 assert((last
>> 32) == sscreen
->info
.address32_hi
);
232 pb_reference(&old_buf
, NULL
);
234 util_range_set_empty(&res
->valid_buffer_range
);
235 res
->TC_L2_dirty
= false;
237 /* Print debug information. */
238 if (sscreen
->debug_flags
& DBG(VM
) && res
->b
.b
.target
== PIPE_BUFFER
) {
239 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Buffer %"PRIu64
" bytes\n",
240 res
->gpu_address
, res
->gpu_address
+ res
->buf
->size
,
246 static void r600_buffer_destroy(struct pipe_screen
*screen
,
247 struct pipe_resource
*buf
)
249 struct r600_resource
*rbuffer
= r600_resource(buf
);
251 threaded_resource_deinit(buf
);
252 util_range_destroy(&rbuffer
->valid_buffer_range
);
253 pb_reference(&rbuffer
->buf
, NULL
);
257 /* Reallocate the buffer a update all resource bindings where the buffer is
260 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
261 * idle by discarding its contents.
264 r600_invalidate_buffer(struct r600_common_context
*rctx
,
265 struct r600_resource
*rbuffer
)
267 /* Shared buffers can't be reallocated. */
268 if (rbuffer
->b
.is_shared
)
271 /* Sparse buffers can't be reallocated. */
272 if (rbuffer
->flags
& RADEON_FLAG_SPARSE
)
275 /* In AMD_pinned_memory, the user pointer association only gets
276 * broken when the buffer is explicitly re-allocated.
278 if (rbuffer
->b
.is_user_ptr
)
281 /* Check if mapping this buffer would cause waiting for the GPU. */
282 if (si_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
283 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
284 uint64_t old_va
= rbuffer
->gpu_address
;
286 /* Reallocate the buffer in the same pipe_resource. */
287 si_alloc_resource(rctx
->screen
, rbuffer
);
288 si_rebind_buffer(&rctx
->b
, &rbuffer
->b
.b
, old_va
);
290 util_range_set_empty(&rbuffer
->valid_buffer_range
);
296 /* Replace the storage of dst with src. */
297 void si_replace_buffer_storage(struct pipe_context
*ctx
,
298 struct pipe_resource
*dst
,
299 struct pipe_resource
*src
)
301 struct r600_resource
*rdst
= r600_resource(dst
);
302 struct r600_resource
*rsrc
= r600_resource(src
);
303 uint64_t old_gpu_address
= rdst
->gpu_address
;
305 pb_reference(&rdst
->buf
, rsrc
->buf
);
306 rdst
->gpu_address
= rsrc
->gpu_address
;
307 rdst
->b
.b
.bind
= rsrc
->b
.b
.bind
;
308 rdst
->b
.max_forced_staging_uploads
= rsrc
->b
.max_forced_staging_uploads
;
309 rdst
->max_forced_staging_uploads
= rsrc
->max_forced_staging_uploads
;
310 rdst
->flags
= rsrc
->flags
;
312 assert(rdst
->vram_usage
== rsrc
->vram_usage
);
313 assert(rdst
->gart_usage
== rsrc
->gart_usage
);
314 assert(rdst
->bo_size
== rsrc
->bo_size
);
315 assert(rdst
->bo_alignment
== rsrc
->bo_alignment
);
316 assert(rdst
->domains
== rsrc
->domains
);
318 si_rebind_buffer(ctx
, dst
, old_gpu_address
);
321 static void si_invalidate_resource(struct pipe_context
*ctx
,
322 struct pipe_resource
*resource
)
324 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
325 struct r600_resource
*rbuffer
= r600_resource(resource
);
327 /* We currently only do anyting here for buffers */
328 if (resource
->target
== PIPE_BUFFER
)
329 (void)r600_invalidate_buffer(rctx
, rbuffer
);
332 static void *r600_buffer_get_transfer(struct pipe_context
*ctx
,
333 struct pipe_resource
*resource
,
335 const struct pipe_box
*box
,
336 struct pipe_transfer
**ptransfer
,
337 void *data
, struct r600_resource
*staging
,
340 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
341 struct r600_transfer
*transfer
;
343 if (usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
)
344 transfer
= slab_alloc(&rctx
->pool_transfers_unsync
);
346 transfer
= slab_alloc(&rctx
->pool_transfers
);
348 transfer
->b
.b
.resource
= NULL
;
349 pipe_resource_reference(&transfer
->b
.b
.resource
, resource
);
350 transfer
->b
.b
.level
= 0;
351 transfer
->b
.b
.usage
= usage
;
352 transfer
->b
.b
.box
= *box
;
353 transfer
->b
.b
.stride
= 0;
354 transfer
->b
.b
.layer_stride
= 0;
355 transfer
->b
.staging
= NULL
;
356 transfer
->offset
= offset
;
357 transfer
->staging
= staging
;
358 *ptransfer
= &transfer
->b
.b
;
362 static void *r600_buffer_transfer_map(struct pipe_context
*ctx
,
363 struct pipe_resource
*resource
,
366 const struct pipe_box
*box
,
367 struct pipe_transfer
**ptransfer
)
369 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
370 struct r600_resource
*rbuffer
= r600_resource(resource
);
373 assert(box
->x
+ box
->width
<= resource
->width0
);
375 /* From GL_AMD_pinned_memory issues:
377 * 4) Is glMapBuffer on a shared buffer guaranteed to return the
378 * same system address which was specified at creation time?
380 * RESOLVED: NO. The GL implementation might return a different
381 * virtual mapping of that memory, although the same physical
384 * So don't ever use staging buffers.
386 if (rbuffer
->b
.is_user_ptr
)
387 usage
|= PIPE_TRANSFER_PERSISTENT
;
389 /* See if the buffer range being mapped has never been initialized,
390 * in which case it can be mapped unsynchronized. */
391 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
392 TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
)) &&
393 usage
& PIPE_TRANSFER_WRITE
&&
394 !rbuffer
->b
.is_shared
&&
395 !util_ranges_intersect(&rbuffer
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
)) {
396 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
399 /* If discarding the entire range, discard the whole resource instead. */
400 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
&&
401 box
->x
== 0 && box
->width
== resource
->width0
) {
402 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
405 /* If a buffer in VRAM is too large and the range is discarded, don't
406 * map it directly. This makes sure that the buffer stays in VRAM.
408 bool force_discard_range
= false;
409 if (usage
& (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
410 PIPE_TRANSFER_DISCARD_RANGE
) &&
411 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
412 /* Try not to decrement the counter if it's not positive. Still racy,
413 * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
414 rbuffer
->max_forced_staging_uploads
> 0 &&
415 p_atomic_dec_return(&rbuffer
->max_forced_staging_uploads
) >= 0) {
416 usage
&= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
417 PIPE_TRANSFER_UNSYNCHRONIZED
);
418 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
419 force_discard_range
= true;
422 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
&&
423 !(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
424 TC_TRANSFER_MAP_NO_INVALIDATE
))) {
425 assert(usage
& PIPE_TRANSFER_WRITE
);
427 if (r600_invalidate_buffer(rctx
, rbuffer
)) {
428 /* At this point, the buffer is always idle. */
429 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
431 /* Fall back to a temporary buffer. */
432 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
436 if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
437 ((!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
438 PIPE_TRANSFER_PERSISTENT
))) ||
439 (rbuffer
->flags
& RADEON_FLAG_SPARSE
))) {
440 assert(usage
& PIPE_TRANSFER_WRITE
);
442 /* Check if mapping this buffer would cause waiting for the GPU.
444 if (rbuffer
->flags
& RADEON_FLAG_SPARSE
||
445 force_discard_range
||
446 si_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
447 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
448 /* Do a wait-free write-only transfer using a temporary buffer. */
450 struct r600_resource
*staging
= NULL
;
452 u_upload_alloc(ctx
->stream_uploader
, 0,
453 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
),
454 rctx
->screen
->info
.tcc_cache_line_size
,
455 &offset
, (struct pipe_resource
**)&staging
,
459 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
460 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
461 ptransfer
, data
, staging
, offset
);
462 } else if (rbuffer
->flags
& RADEON_FLAG_SPARSE
) {
466 /* At this point, the buffer is always idle (we checked it above). */
467 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
470 /* Use a staging buffer in cached GTT for reads. */
471 else if (((usage
& PIPE_TRANSFER_READ
) &&
472 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
473 (rbuffer
->domains
& RADEON_DOMAIN_VRAM
||
474 rbuffer
->flags
& RADEON_FLAG_GTT_WC
)) ||
475 (rbuffer
->flags
& RADEON_FLAG_SPARSE
)) {
476 struct r600_resource
*staging
;
478 assert(!(usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
));
479 staging
= (struct r600_resource
*) pipe_buffer_create(
480 ctx
->screen
, 0, PIPE_USAGE_STAGING
,
481 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
));
483 /* Copy the VRAM buffer to the staging buffer. */
484 rctx
->dma_copy(ctx
, &staging
->b
.b
, 0,
485 box
->x
% R600_MAP_BUFFER_ALIGNMENT
,
486 0, 0, resource
, 0, box
);
488 data
= si_buffer_map_sync_with_rings(rctx
, staging
,
489 usage
& ~PIPE_TRANSFER_UNSYNCHRONIZED
);
491 r600_resource_reference(&staging
, NULL
);
494 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
496 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
497 ptransfer
, data
, staging
, 0);
498 } else if (rbuffer
->flags
& RADEON_FLAG_SPARSE
) {
503 data
= si_buffer_map_sync_with_rings(rctx
, rbuffer
, usage
);
509 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
510 ptransfer
, data
, NULL
, 0);
513 static void r600_buffer_do_flush_region(struct pipe_context
*ctx
,
514 struct pipe_transfer
*transfer
,
515 const struct pipe_box
*box
)
517 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
518 struct r600_resource
*rbuffer
= r600_resource(transfer
->resource
);
520 if (rtransfer
->staging
) {
521 struct pipe_resource
*dst
, *src
;
523 struct pipe_box dma_box
;
525 dst
= transfer
->resource
;
526 src
= &rtransfer
->staging
->b
.b
;
527 soffset
= rtransfer
->offset
+ box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
529 u_box_1d(soffset
, box
->width
, &dma_box
);
531 /* Copy the staging buffer into the original one. */
532 ctx
->resource_copy_region(ctx
, dst
, 0, box
->x
, 0, 0, src
, 0, &dma_box
);
535 util_range_add(&rbuffer
->valid_buffer_range
, box
->x
,
536 box
->x
+ box
->width
);
539 static void r600_buffer_flush_region(struct pipe_context
*ctx
,
540 struct pipe_transfer
*transfer
,
541 const struct pipe_box
*rel_box
)
543 unsigned required_usage
= PIPE_TRANSFER_WRITE
|
544 PIPE_TRANSFER_FLUSH_EXPLICIT
;
546 if ((transfer
->usage
& required_usage
) == required_usage
) {
549 u_box_1d(transfer
->box
.x
+ rel_box
->x
, rel_box
->width
, &box
);
550 r600_buffer_do_flush_region(ctx
, transfer
, &box
);
554 static void r600_buffer_transfer_unmap(struct pipe_context
*ctx
,
555 struct pipe_transfer
*transfer
)
557 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
558 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
560 if (transfer
->usage
& PIPE_TRANSFER_WRITE
&&
561 !(transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
))
562 r600_buffer_do_flush_region(ctx
, transfer
, &transfer
->box
);
564 r600_resource_reference(&rtransfer
->staging
, NULL
);
565 assert(rtransfer
->b
.staging
== NULL
); /* for threaded context only */
566 pipe_resource_reference(&transfer
->resource
, NULL
);
568 /* Don't use pool_transfers_unsync. We are always in the driver
570 slab_free(&rctx
->pool_transfers
, transfer
);
573 static void si_buffer_subdata(struct pipe_context
*ctx
,
574 struct pipe_resource
*buffer
,
575 unsigned usage
, unsigned offset
,
576 unsigned size
, const void *data
)
578 struct pipe_transfer
*transfer
= NULL
;
582 u_box_1d(offset
, size
, &box
);
583 map
= r600_buffer_transfer_map(ctx
, buffer
, 0,
584 PIPE_TRANSFER_WRITE
|
585 PIPE_TRANSFER_DISCARD_RANGE
|
591 memcpy(map
, data
, size
);
592 r600_buffer_transfer_unmap(ctx
, transfer
);
595 static const struct u_resource_vtbl r600_buffer_vtbl
=
597 NULL
, /* get_handle */
598 r600_buffer_destroy
, /* resource_destroy */
599 r600_buffer_transfer_map
, /* transfer_map */
600 r600_buffer_flush_region
, /* transfer_flush_region */
601 r600_buffer_transfer_unmap
, /* transfer_unmap */
604 static struct r600_resource
*
605 r600_alloc_buffer_struct(struct pipe_screen
*screen
,
606 const struct pipe_resource
*templ
)
608 struct r600_resource
*rbuffer
;
610 rbuffer
= MALLOC_STRUCT(r600_resource
);
612 rbuffer
->b
.b
= *templ
;
613 rbuffer
->b
.b
.next
= NULL
;
614 pipe_reference_init(&rbuffer
->b
.b
.reference
, 1);
615 rbuffer
->b
.b
.screen
= screen
;
617 rbuffer
->b
.vtbl
= &r600_buffer_vtbl
;
618 threaded_resource_init(&rbuffer
->b
.b
);
621 rbuffer
->bind_history
= 0;
622 rbuffer
->TC_L2_dirty
= false;
623 util_range_init(&rbuffer
->valid_buffer_range
);
627 static struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
628 const struct pipe_resource
*templ
,
631 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
632 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
634 if (templ
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
635 rbuffer
->b
.b
.flags
|= R600_RESOURCE_FLAG_UNMAPPABLE
;
637 si_init_resource_fields(sscreen
, rbuffer
, templ
->width0
, alignment
);
639 if (templ
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
640 rbuffer
->flags
|= RADEON_FLAG_SPARSE
;
642 if (!si_alloc_resource(sscreen
, rbuffer
)) {
646 return &rbuffer
->b
.b
;
649 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
655 struct pipe_resource buffer
;
657 memset(&buffer
, 0, sizeof buffer
);
658 buffer
.target
= PIPE_BUFFER
;
659 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
661 buffer
.usage
= usage
;
662 buffer
.flags
= flags
;
663 buffer
.width0
= size
;
666 buffer
.array_size
= 1;
667 return si_buffer_create(screen
, &buffer
, alignment
);
670 static struct pipe_resource
*
671 si_buffer_from_user_memory(struct pipe_screen
*screen
,
672 const struct pipe_resource
*templ
,
675 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
676 struct radeon_winsys
*ws
= sscreen
->ws
;
677 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
679 rbuffer
->domains
= RADEON_DOMAIN_GTT
;
681 rbuffer
->b
.is_user_ptr
= true;
682 util_range_add(&rbuffer
->valid_buffer_range
, 0, templ
->width0
);
683 util_range_add(&rbuffer
->b
.valid_buffer_range
, 0, templ
->width0
);
685 /* Convert a user pointer to a buffer. */
686 rbuffer
->buf
= ws
->buffer_from_ptr(ws
, user_memory
, templ
->width0
);
692 rbuffer
->gpu_address
= ws
->buffer_get_virtual_address(rbuffer
->buf
);
693 rbuffer
->vram_usage
= 0;
694 rbuffer
->gart_usage
= templ
->width0
;
696 return &rbuffer
->b
.b
;
699 static struct pipe_resource
*si_resource_create(struct pipe_screen
*screen
,
700 const struct pipe_resource
*templ
)
702 if (templ
->target
== PIPE_BUFFER
) {
703 return si_buffer_create(screen
, templ
, 256);
705 return si_texture_create(screen
, templ
);
709 void si_init_screen_buffer_functions(struct si_screen
*sscreen
)
711 sscreen
->b
.resource_create
= si_resource_create
;
712 sscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
713 sscreen
->b
.resource_from_user_memory
= si_buffer_from_user_memory
;
716 void si_init_buffer_functions(struct si_context
*sctx
)
718 sctx
->b
.b
.invalidate_resource
= si_invalidate_resource
;
719 sctx
->b
.b
.transfer_map
= u_transfer_map_vtbl
;
720 sctx
->b
.b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
721 sctx
->b
.b
.transfer_unmap
= u_transfer_unmap_vtbl
;
722 sctx
->b
.b
.texture_subdata
= u_default_texture_subdata
;
723 sctx
->b
.b
.buffer_subdata
= si_buffer_subdata
;