src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                    struct pb_buffer *buf,
  35                                    enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  38                 return true;
  39         }
  40         if (radeon_emitted(ctx->dma.cs, 0) &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  42                 return true;
  43         }
  44         return false;
  45 }
  46
  47 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                     struct r600_resource *resource,
  49                                     unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  55
  56         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  57                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  58         }
  59
  60         if (!(usage & PIPE_TRANSFER_WRITE)) {
  61                 /* have to wait for the last write */
  62                 rusage = RADEON_USAGE_WRITE;
  63         }
  64
  65         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
  66             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  67                                              resource->buf, rusage)) {
  68                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  69                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  70                         return NULL;
  71                 } else {
  72                         ctx->gfx.flush(ctx, 0, NULL);
  73                         busy = true;
  74                 }
  75         }
  76         if (radeon_emitted(ctx->dma.cs, 0) &&
  77             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  78                                              resource->buf, rusage)) {
  79                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  80                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  81                         return NULL;
  82                 } else {
  83                         ctx->dma.flush(ctx, 0, NULL);
  84                         busy = true;
  85                 }
  86         }
  87
  88         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  89                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  90                         return NULL;
  91                 } else {
  92                         /* We will be wait for the GPU. Wait for any offloaded
  93                          * CS flush to complete to avoid busy-waiting in the winsys. */
  94                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  95                         if (ctx->dma.cs)
  96                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  97                 }
  98         }
  99
 100         /* Setting the CS to NULL will prevent doing checks we have done already. */
 101         return ctx->ws->buffer_map(resource->buf, NULL, usage);
 102 }
 103
 104 void si_init_resource_fields(struct r600_common_screen *rscreen,
 105                              struct r600_resource *res,
 106                              uint64_t size, unsigned alignment)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109
 110         res->bo_size = size;
 111         res->bo_alignment = alignment;
 112         res->flags = 0;
 113         res->texture_handle_allocated = false;
 114         res->image_handle_allocated = false;
 115
 116         switch (res->b.b.usage) {
 117         case PIPE_USAGE_STREAM:
 118                 res->flags = RADEON_FLAG_GTT_WC;
 119                 /* fall through */
 120         case PIPE_USAGE_STAGING:
 121                 /* Transfers are likely to occur more often with these
 122                  * resources. */
 123                 res->domains = RADEON_DOMAIN_GTT;
 124                 break;
 125         case PIPE_USAGE_DYNAMIC:
 126                 /* Older kernels didn't always flush the HDP cache before
 127                  * CS execution
 128                  */
 129                 if (rscreen->info.drm_major == 2 &&
 130                     rscreen->info.drm_minor < 40) {
 131                         res->domains = RADEON_DOMAIN_GTT;
 132                         res->flags |= RADEON_FLAG_GTT_WC;
 133                         break;
 134                 }
 135                 /* fall through */
 136         case PIPE_USAGE_DEFAULT:
 137         case PIPE_USAGE_IMMUTABLE:
 138         default:
 139                 /* Not listing GTT here improves performance in some
 140                  * apps. */
 141                 res->domains = RADEON_DOMAIN_VRAM;
 142                 res->flags |= RADEON_FLAG_GTT_WC;
 143                 break;
 144         }
 145
 146         if (res->b.b.target == PIPE_BUFFER &&
 147             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 148                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 149                 /* Use GTT for all persistent mappings with older
 150                  * kernels, because they didn't always flush the HDP
 151                  * cache before CS execution.
 152                  *
 153                  * Write-combined CPU mappings are fine, the kernel
 154                  * ensures all CPU writes finish before the GPU
 155                  * executes a command stream.
 156                  */
 157                 if (rscreen->info.drm_major == 2 &&
 158                     rscreen->info.drm_minor < 40)
 159                         res->domains = RADEON_DOMAIN_GTT;
 160         }
 161
 162         /* Tiled textures are unmappable. Always put them in VRAM. */
 163         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 164             res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 165                 res->domains = RADEON_DOMAIN_VRAM;
 166                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 167                          RADEON_FLAG_GTT_WC;
 168         }
 169
 170         /* Displayable and shareable surfaces are not suballocated. */
 171         if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 172                 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 173         else
 174                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 175
 176         /* If VRAM is just stolen system memory, allow both VRAM and
 177          * GTT, whichever has free space. If a buffer is evicted from
 178          * VRAM to GTT, it will stay there.
 179          *
 180          * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 181          * placements even with a low amount of stolen VRAM.
 182          */
 183         if (!rscreen->info.has_dedicated_vram &&
 184             (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
 185             res->domains == RADEON_DOMAIN_VRAM) {
 186                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 187                 res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
 188         }
 189
 190         if (rscreen->debug_flags & DBG_NO_WC)
 191                 res->flags &= ~RADEON_FLAG_GTT_WC;
 192
 193         /* Set expected VRAM and GART usage for the buffer. */
 194         res->vram_usage = 0;
 195         res->gart_usage = 0;
 196
 197         if (res->domains & RADEON_DOMAIN_VRAM)
 198                 res->vram_usage = size;
 199         else if (res->domains & RADEON_DOMAIN_GTT)
 200                 res->gart_usage = size;
 201 }
 202
 203 bool si_alloc_resource(struct r600_common_screen *rscreen,
 204                        struct r600_resource *res)
 205 {
 206         struct pb_buffer *old_buf, *new_buf;
 207
 208         /* Allocate a new resource. */
 209         new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
 210                                              res->bo_alignment,
 211                                              res->domains, res->flags);
 212         if (!new_buf) {
 213                 return false;
 214         }
 215
 216         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 217          * NULL. This should prevent crashes with multiple contexts using
 218          * the same buffer where one of the contexts invalidates it while
 219          * the others are using it. */
 220         old_buf = res->buf;
 221         res->buf = new_buf; /* should be atomic */
 222
 223         if (rscreen->info.has_virtual_memory)
 224                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 225         else
 226                 res->gpu_address = 0;
 227
 228         pb_reference(&old_buf, NULL);
 229
 230         util_range_set_empty(&res->valid_buffer_range);
 231         res->TC_L2_dirty = false;
 232
 233         /* Print debug information. */
 234         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 235                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 236                         res->gpu_address, res->gpu_address + res->buf->size,
 237                         res->buf->size);
 238         }
 239         return true;
 240 }
 241
 242 static void r600_buffer_destroy(struct pipe_screen *screen,
 243                                 struct pipe_resource *buf)
 244 {
 245         struct r600_resource *rbuffer = r600_resource(buf);
 246
 247         threaded_resource_deinit(buf);
 248         util_range_destroy(&rbuffer->valid_buffer_range);
 249         pb_reference(&rbuffer->buf, NULL);
 250         FREE(rbuffer);
 251 }
 252
 253 static bool
 254 r600_invalidate_buffer(struct r600_common_context *rctx,
 255                        struct r600_resource *rbuffer)
 256 {
 257         /* Shared buffers can't be reallocated. */
 258         if (rbuffer->b.is_shared)
 259                 return false;
 260
 261         /* Sparse buffers can't be reallocated. */
 262         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 263                 return false;
 264
 265         /* In AMD_pinned_memory, the user pointer association only gets
 266          * broken when the buffer is explicitly re-allocated.
 267          */
 268         if (rbuffer->b.is_user_ptr)
 269                 return false;
 270
 271         /* Check if mapping this buffer would cause waiting for the GPU. */
 272         if (si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 273             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 274                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 275         } else {
 276                 util_range_set_empty(&rbuffer->valid_buffer_range);
 277         }
 278
 279         return true;
 280 }
 281
 282 /* Replace the storage of dst with src. */
 283 void si_replace_buffer_storage(struct pipe_context *ctx,
 284                                  struct pipe_resource *dst,
 285                                  struct pipe_resource *src)
 286 {
 287         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 288         struct r600_resource *rdst = r600_resource(dst);
 289         struct r600_resource *rsrc = r600_resource(src);
 290         uint64_t old_gpu_address = rdst->gpu_address;
 291
 292         pb_reference(&rdst->buf, rsrc->buf);
 293         rdst->gpu_address = rsrc->gpu_address;
 294         rdst->b.b.bind = rsrc->b.b.bind;
 295         rdst->flags = rsrc->flags;
 296
 297         assert(rdst->vram_usage == rsrc->vram_usage);
 298         assert(rdst->gart_usage == rsrc->gart_usage);
 299         assert(rdst->bo_size == rsrc->bo_size);
 300         assert(rdst->bo_alignment == rsrc->bo_alignment);
 301         assert(rdst->domains == rsrc->domains);
 302
 303         rctx->rebind_buffer(ctx, dst, old_gpu_address);
 304 }
 305
 306 void si_invalidate_resource(struct pipe_context *ctx,
 307                             struct pipe_resource *resource)
 308 {
 309         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 310         struct r600_resource *rbuffer = r600_resource(resource);
 311
 312         /* We currently only do anyting here for buffers */
 313         if (resource->target == PIPE_BUFFER)
 314                 (void)r600_invalidate_buffer(rctx, rbuffer);
 315 }
 316
 317 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 318                                       struct pipe_resource *resource,
 319                                       unsigned usage,
 320                                       const struct pipe_box *box,
 321                                       struct pipe_transfer **ptransfer,
 322                                       void *data, struct r600_resource *staging,
 323                                       unsigned offset)
 324 {
 325         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 326         struct r600_transfer *transfer;
 327
 328         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 329                 transfer = slab_alloc(&rctx->pool_transfers_unsync);
 330         else
 331                 transfer = slab_alloc(&rctx->pool_transfers);
 332
 333         transfer->b.b.resource = NULL;
 334         pipe_resource_reference(&transfer->b.b.resource, resource);
 335         transfer->b.b.level = 0;
 336         transfer->b.b.usage = usage;
 337         transfer->b.b.box = *box;
 338         transfer->b.b.stride = 0;
 339         transfer->b.b.layer_stride = 0;
 340         transfer->b.staging = NULL;
 341         transfer->offset = offset;
 342         transfer->staging = staging;
 343         *ptransfer = &transfer->b.b;
 344         return data;
 345 }
 346
 347 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 348                                      unsigned dstx, unsigned srcx, unsigned size)
 349 {
 350         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 351
 352         return rctx->screen->has_cp_dma ||
 353                (dword_aligned && (rctx->dma.cs ||
 354                                   rctx->screen->has_streamout));
 355
 356 }
 357
 358 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 359                                       struct pipe_resource *resource,
 360                                       unsigned level,
 361                                       unsigned usage,
 362                                       const struct pipe_box *box,
 363                                       struct pipe_transfer **ptransfer)
 364 {
 365         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 366         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 367         struct r600_resource *rbuffer = r600_resource(resource);
 368         uint8_t *data;
 369
 370         assert(box->x + box->width <= resource->width0);
 371
 372         /* From GL_AMD_pinned_memory issues:
 373          *
 374          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 375          *        same system address which was specified at creation time?
 376          *
 377          *        RESOLVED: NO. The GL implementation might return a different
 378          *        virtual mapping of that memory, although the same physical
 379          *        page will be used.
 380          *
 381          * So don't ever use staging buffers.
 382          */
 383         if (rbuffer->b.is_user_ptr)
 384                 usage |= PIPE_TRANSFER_PERSISTENT;
 385
 386         /* See if the buffer range being mapped has never been initialized,
 387          * in which case it can be mapped unsynchronized. */
 388         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 389                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 390             usage & PIPE_TRANSFER_WRITE &&
 391             !rbuffer->b.is_shared &&
 392             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 393                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 394         }
 395
 396         /* If discarding the entire range, discard the whole resource instead. */
 397         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 398             box->x == 0 && box->width == resource->width0) {
 399                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 400         }
 401
 402         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 403             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 404                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 405                 assert(usage & PIPE_TRANSFER_WRITE);
 406
 407                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 408                         /* At this point, the buffer is always idle. */
 409                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 410                 } else {
 411                         /* Fall back to a temporary buffer. */
 412                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 413                 }
 414         }
 415
 416         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 417             !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 418             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 419                          PIPE_TRANSFER_PERSISTENT)) &&
 420               r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
 421              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 422                 assert(usage & PIPE_TRANSFER_WRITE);
 423
 424                 /* Check if mapping this buffer would cause waiting for the GPU.
 425                  */
 426                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 427                     si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 428                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 429                         /* Do a wait-free write-only transfer using a temporary buffer. */
 430                         unsigned offset;
 431                         struct r600_resource *staging = NULL;
 432
 433                         u_upload_alloc(ctx->stream_uploader, 0,
 434                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 435                                        rctx->screen->info.tcc_cache_line_size,
 436                                        &offset, (struct pipe_resource**)&staging,
 437                                        (void**)&data);
 438
 439                         if (staging) {
 440                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 441                                 return r600_buffer_get_transfer(ctx, resource, usage, box,
 442                                                                 ptransfer, data, staging, offset);
 443                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 444                                 return NULL;
 445                         }
 446                 } else {
 447                         /* At this point, the buffer is always idle (we checked it above). */
 448                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 449                 }
 450         }
 451         /* Use a staging buffer in cached GTT for reads. */
 452         else if (((usage & PIPE_TRANSFER_READ) &&
 453                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 454                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 455                    rbuffer->flags & RADEON_FLAG_GTT_WC) &&
 456                   r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
 457                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 458                 struct r600_resource *staging;
 459
 460                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 461                 staging = (struct r600_resource*) pipe_buffer_create(
 462                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 463                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 464                 if (staging) {
 465                         /* Copy the VRAM buffer to the staging buffer. */
 466                         rctx->dma_copy(ctx, &staging->b.b, 0,
 467                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 468                                        0, 0, resource, 0, box);
 469
 470                         data = si_buffer_map_sync_with_rings(rctx, staging,
 471                                                                usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 472                         if (!data) {
 473                                 r600_resource_reference(&staging, NULL);
 474                                 return NULL;
 475                         }
 476                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 477
 478                         return r600_buffer_get_transfer(ctx, resource, usage, box,
 479                                                         ptransfer, data, staging, 0);
 480                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 481                         return NULL;
 482                 }
 483         }
 484
 485         data = si_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 486         if (!data) {
 487                 return NULL;
 488         }
 489         data += box->x;
 490
 491         return r600_buffer_get_transfer(ctx, resource, usage, box,
 492                                         ptransfer, data, NULL, 0);
 493 }
 494
 495 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 496                                         struct pipe_transfer *transfer,
 497                                         const struct pipe_box *box)
 498 {
 499         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 500         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 501
 502         if (rtransfer->staging) {
 503                 struct pipe_resource *dst, *src;
 504                 unsigned soffset;
 505                 struct pipe_box dma_box;
 506
 507                 dst = transfer->resource;
 508                 src = &rtransfer->staging->b.b;
 509                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 510
 511                 u_box_1d(soffset, box->width, &dma_box);
 512
 513                 /* Copy the staging buffer into the original one. */
 514                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 515         }
 516
 517         util_range_add(&rbuffer->valid_buffer_range, box->x,
 518                        box->x + box->width);
 519 }
 520
 521 static void r600_buffer_flush_region(struct pipe_context *ctx,
 522                                      struct pipe_transfer *transfer,
 523                                      const struct pipe_box *rel_box)
 524 {
 525         unsigned required_usage = PIPE_TRANSFER_WRITE |
 526                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 527
 528         if ((transfer->usage & required_usage) == required_usage) {
 529                 struct pipe_box box;
 530
 531                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 532                 r600_buffer_do_flush_region(ctx, transfer, &box);
 533         }
 534 }
 535
 536 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 537                                        struct pipe_transfer *transfer)
 538 {
 539         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 540         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 541
 542         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 543             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 544                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 545
 546         r600_resource_reference(&rtransfer->staging, NULL);
 547         assert(rtransfer->b.staging == NULL); /* for threaded context only */
 548         pipe_resource_reference(&transfer->resource, NULL);
 549
 550         /* Don't use pool_transfers_unsync. We are always in the driver
 551          * thread. */
 552         slab_free(&rctx->pool_transfers, transfer);
 553 }
 554
 555 void si_buffer_subdata(struct pipe_context *ctx,
 556                        struct pipe_resource *buffer,
 557                        unsigned usage, unsigned offset,
 558                        unsigned size, const void *data)
 559 {
 560         struct pipe_transfer *transfer = NULL;
 561         struct pipe_box box;
 562         uint8_t *map = NULL;
 563
 564         u_box_1d(offset, size, &box);
 565         map = r600_buffer_transfer_map(ctx, buffer, 0,
 566                                        PIPE_TRANSFER_WRITE |
 567                                        PIPE_TRANSFER_DISCARD_RANGE |
 568                                        usage,
 569                                        &box, &transfer);
 570         if (!map)
 571                 return;
 572
 573         memcpy(map, data, size);
 574         r600_buffer_transfer_unmap(ctx, transfer);
 575 }
 576
 577 static const struct u_resource_vtbl r600_buffer_vtbl =
 578 {
 579         NULL,                           /* get_handle */
 580         r600_buffer_destroy,            /* resource_destroy */
 581         r600_buffer_transfer_map,       /* transfer_map */
 582         r600_buffer_flush_region,       /* transfer_flush_region */
 583         r600_buffer_transfer_unmap,     /* transfer_unmap */
 584 };
 585
 586 static struct r600_resource *
 587 r600_alloc_buffer_struct(struct pipe_screen *screen,
 588                          const struct pipe_resource *templ)
 589 {
 590         struct r600_resource *rbuffer;
 591
 592         rbuffer = MALLOC_STRUCT(r600_resource);
 593
 594         rbuffer->b.b = *templ;
 595         rbuffer->b.b.next = NULL;
 596         pipe_reference_init(&rbuffer->b.b.reference, 1);
 597         rbuffer->b.b.screen = screen;
 598
 599         rbuffer->b.vtbl = &r600_buffer_vtbl;
 600         threaded_resource_init(&rbuffer->b.b);
 601
 602         rbuffer->buf = NULL;
 603         rbuffer->bind_history = 0;
 604         rbuffer->TC_L2_dirty = false;
 605         util_range_init(&rbuffer->valid_buffer_range);
 606         return rbuffer;
 607 }
 608
 609 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 610                                        const struct pipe_resource *templ,
 611                                        unsigned alignment)
 612 {
 613         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 614         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 615
 616         si_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 617
 618         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 619                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 620
 621         if (!si_alloc_resource(rscreen, rbuffer)) {
 622                 FREE(rbuffer);
 623                 return NULL;
 624         }
 625         return &rbuffer->b.b;
 626 }
 627
 628 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 629                                                unsigned flags,
 630                                                unsigned usage,
 631                                                unsigned size,
 632                                                unsigned alignment)
 633 {
 634         struct pipe_resource buffer;
 635
 636         memset(&buffer, 0, sizeof buffer);
 637         buffer.target = PIPE_BUFFER;
 638         buffer.format = PIPE_FORMAT_R8_UNORM;
 639         buffer.bind = 0;
 640         buffer.usage = usage;
 641         buffer.flags = flags;
 642         buffer.width0 = size;
 643         buffer.height0 = 1;
 644         buffer.depth0 = 1;
 645         buffer.array_size = 1;
 646         return si_buffer_create(screen, &buffer, alignment);
 647 }
 648
 649 struct pipe_resource *
 650 si_buffer_from_user_memory(struct pipe_screen *screen,
 651                            const struct pipe_resource *templ,
 652                            void *user_memory)
 653 {
 654         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 655         struct radeon_winsys *ws = rscreen->ws;
 656         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 657
 658         rbuffer->domains = RADEON_DOMAIN_GTT;
 659         rbuffer->flags = 0;
 660         rbuffer->b.is_user_ptr = true;
 661         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 662         util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 663
 664         /* Convert a user pointer to a buffer. */
 665         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 666         if (!rbuffer->buf) {
 667                 FREE(rbuffer);
 668                 return NULL;
 669         }
 670
 671         if (rscreen->info.has_virtual_memory)
 672                 rbuffer->gpu_address =
 673                         ws->buffer_get_virtual_address(rbuffer->buf);
 674         else
 675                 rbuffer->gpu_address = 0;
 676
 677         rbuffer->vram_usage = 0;
 678         rbuffer->gart_usage = templ->width0;
 679
 680         return &rbuffer->b.b;
 681 }