src/gallium/drivers/radeon/r600_cs.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  */
  25
  26 /**
  27  * This file contains helpers for writing commands to commands streams.
  28  */
  29
  30 #ifndef R600_CS_H
  31 #define R600_CS_H
  32
  33 #include "r600_pipe_common.h"
  34 #include "r600d_common.h"
  35
  36 /**
  37  * Add a buffer to the buffer list for the given command stream (CS).
  38  *
  39  * All buffers used by a CS must be added to the list. This tells the kernel
  40  * driver which buffers are used by GPU commands. Other buffers can
  41  * be swapped out (not accessible) during execution.
  42  *
  43  * The buffer list becomes empty after every context flush and must be
  44  * rebuilt.
  45  */
  46 static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
  47                                                  struct r600_ring *ring,
  48                                                  struct r600_resource *rbo,
  49                                                  enum radeon_bo_usage usage,
  50                                                  enum radeon_bo_priority priority)
  51 {
  52         assert(usage);
  53
  54         /* Make sure that all previous rings are flushed so that everything
  55          * looks serialized from the driver point of view.
  56          */
  57         if (!ring->flushing) {
  58                 if (ring == &rctx->rings.gfx) {
  59                         if (rctx->rings.dma.cs) {
  60                                 /* flush dma ring */
  61                                 rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
  62                         }
  63                 } else {
  64                         /* flush gfx ring */
  65                         rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
  66                 }
  67         }
  68         return rctx->ws->cs_add_buffer(ring->cs, rbo->cs_buf, usage,
  69                                       rbo->domains, priority) * 4;
  70 }
  71
  72 static inline void r600_emit_reloc(struct r600_common_context *rctx,
  73                                    struct r600_ring *ring, struct r600_resource *rbo,
  74                                    enum radeon_bo_usage usage,
  75                                    enum radeon_bo_priority priority)
  76 {
  77         struct radeon_winsys_cs *cs = ring->cs;
  78         bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_virtual_address;
  79         unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
  80
  81         if (!has_vm) {
  82                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
  83                 radeon_emit(cs, reloc);
  84         }
  85 }
  86
  87 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
  88 {
  89         assert(reg < R600_CONTEXT_REG_OFFSET);
  90         assert(cs->cdw+2+num <= cs->max_dw);
  91         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
  92         radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
  93 }
  94
  95 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
  96 {
  97         radeon_set_config_reg_seq(cs, reg, 1);
  98         radeon_emit(cs, value);
  99 }
 100
 101 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 102 {
 103         assert(reg >= R600_CONTEXT_REG_OFFSET);
 104         assert(cs->cdw+2+num <= cs->max_dw);
 105         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
 106         radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
 107 }
 108
 109 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 110 {
 111         radeon_set_context_reg_seq(cs, reg, 1);
 112         radeon_emit(cs, value);
 113 }
 114
 115 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 116 {
 117         assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 118         assert(cs->cdw+2+num <= cs->max_dw);
 119         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
 120         radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 121 }
 122
 123 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 124 {
 125         radeon_set_sh_reg_seq(cs, reg, 1);
 126         radeon_emit(cs, value);
 127 }
 128
 129 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 130 {
 131         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 132         assert(cs->cdw+2+num <= cs->max_dw);
 133         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
 134         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 135 }
 136
 137 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 138 {
 139         radeon_set_uconfig_reg_seq(cs, reg, 1);
 140         radeon_emit(cs, value);
 141 }
 142
 143 #endif