src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
  43 {
  44 }
  45
  46 bool r600_common_context_init(struct r600_common_context *rctx,
  47                               struct r600_common_screen *rscreen)
  48 {
  49         util_slab_create(&rctx->pool_transfers,
  50                          sizeof(struct r600_transfer), 64,
  51                          UTIL_SLAB_SINGLETHREADED);
  52
  53         rctx->screen = rscreen;
  54         rctx->ws = rscreen->ws;
  55         rctx->family = rscreen->family;
  56         rctx->chip_class = rscreen->chip_class;
  57         rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
  58
  59         rctx->b.transfer_map = u_transfer_map_vtbl;
  60         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
  61         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
  62         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
  63         rctx->b.memory_barrier = r600_memory_barrier;
  64
  65         r600_init_context_texture_functions(rctx);
  66         r600_streamout_init(rctx);
  67         r600_query_init(rctx);
  68
  69         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
  70                                                                0, PIPE_USAGE_DEFAULT, TRUE);
  71         if (!rctx->allocator_so_filled_size)
  72                 return false;
  73
  74         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
  75                                         PIPE_BIND_INDEX_BUFFER |
  76                                         PIPE_BIND_CONSTANT_BUFFER);
  77         if (!rctx->uploader)
  78                 return false;
  79
  80         return true;
  81 }
  82
  83 void r600_common_context_cleanup(struct r600_common_context *rctx)
  84 {
  85         if (rctx->rings.gfx.cs) {
  86                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
  87         }
  88         if (rctx->rings.dma.cs) {
  89                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
  90         }
  91
  92         if (rctx->uploader) {
  93                 u_upload_destroy(rctx->uploader);
  94         }
  95
  96         util_slab_destroy(&rctx->pool_transfers);
  97
  98         if (rctx->allocator_so_filled_size) {
  99                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 100         }
 101 }
 102
 103 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 104 {
 105         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 106         struct r600_resource *rr = (struct r600_resource *)r;
 107
 108         if (r == NULL) {
 109                 return;
 110         }
 111
 112         /*
 113          * The idea is to compute a gross estimate of memory requirement of
 114          * each draw call. After each draw call, memory will be precisely
 115          * accounted. So the uncertainty is only on the current draw call.
 116          * In practice this gave very good estimate (+/- 10% of the target
 117          * memory limit).
 118          */
 119         if (rr->domains & RADEON_DOMAIN_GTT) {
 120                 rctx->gtt += rr->buf->size;
 121         }
 122         if (rr->domains & RADEON_DOMAIN_VRAM) {
 123                 rctx->vram += rr->buf->size;
 124         }
 125 }
 126
 127 /*
 128  * pipe_screen
 129  */
 130
 131 static const struct debug_named_value common_debug_options[] = {
 132         /* logging */
 133         { "tex", DBG_TEX, "Print texture info" },
 134         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 135         { "compute", DBG_COMPUTE, "Print compute info" },
 136         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 137         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 138
 139         /* shaders */
 140         { "fs", DBG_FS, "Print fetch shaders" },
 141         { "vs", DBG_VS, "Print vertex shaders" },
 142         { "gs", DBG_GS, "Print geometry shaders" },
 143         { "ps", DBG_PS, "Print pixel shaders" },
 144         { "cs", DBG_CS, "Print compute shaders" },
 145
 146         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 147         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 148         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 149
 150         DEBUG_NAMED_VALUE_END /* must be last */
 151 };
 152
 153 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 154 {
 155         return "X.Org";
 156 }
 157
 158 static const char* r600_get_name(struct pipe_screen* pscreen)
 159 {
 160         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 161
 162         switch (rscreen->family) {
 163         case CHIP_R600: return "AMD R600";
 164         case CHIP_RV610: return "AMD RV610";
 165         case CHIP_RV630: return "AMD RV630";
 166         case CHIP_RV670: return "AMD RV670";
 167         case CHIP_RV620: return "AMD RV620";
 168         case CHIP_RV635: return "AMD RV635";
 169         case CHIP_RS780: return "AMD RS780";
 170         case CHIP_RS880: return "AMD RS880";
 171         case CHIP_RV770: return "AMD RV770";
 172         case CHIP_RV730: return "AMD RV730";
 173         case CHIP_RV710: return "AMD RV710";
 174         case CHIP_RV740: return "AMD RV740";
 175         case CHIP_CEDAR: return "AMD CEDAR";
 176         case CHIP_REDWOOD: return "AMD REDWOOD";
 177         case CHIP_JUNIPER: return "AMD JUNIPER";
 178         case CHIP_CYPRESS: return "AMD CYPRESS";
 179         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 180         case CHIP_PALM: return "AMD PALM";
 181         case CHIP_SUMO: return "AMD SUMO";
 182         case CHIP_SUMO2: return "AMD SUMO2";
 183         case CHIP_BARTS: return "AMD BARTS";
 184         case CHIP_TURKS: return "AMD TURKS";
 185         case CHIP_CAICOS: return "AMD CAICOS";
 186         case CHIP_CAYMAN: return "AMD CAYMAN";
 187         case CHIP_ARUBA: return "AMD ARUBA";
 188         case CHIP_TAHITI: return "AMD TAHITI";
 189         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 190         case CHIP_VERDE: return "AMD CAPE VERDE";
 191         case CHIP_OLAND: return "AMD OLAND";
 192         case CHIP_HAINAN: return "AMD HAINAN";
 193         case CHIP_BONAIRE: return "AMD BONAIRE";
 194         case CHIP_KAVERI: return "AMD KAVERI";
 195         case CHIP_KABINI: return "AMD KABINI";
 196         case CHIP_HAWAII: return "AMD HAWAII";
 197         default: return "AMD unknown";
 198         }
 199 }
 200
 201 static float r600_get_paramf(struct pipe_screen* pscreen,
 202                              enum pipe_capf param)
 203 {
 204         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 205
 206         switch (param) {
 207         case PIPE_CAPF_MAX_LINE_WIDTH:
 208         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 209         case PIPE_CAPF_MAX_POINT_WIDTH:
 210         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 211                 if (rscreen->family >= CHIP_CEDAR)
 212                         return 16384.0f;
 213                 else
 214                         return 8192.0f;
 215         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 216                 return 16.0f;
 217         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 218                 return 16.0f;
 219         case PIPE_CAPF_GUARD_BAND_LEFT:
 220         case PIPE_CAPF_GUARD_BAND_TOP:
 221         case PIPE_CAPF_GUARD_BAND_RIGHT:
 222         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 223                 return 0.0f;
 224         }
 225         return 0.0f;
 226 }
 227
 228 static int r600_get_video_param(struct pipe_screen *screen,
 229                                 enum pipe_video_profile profile,
 230                                 enum pipe_video_entrypoint entrypoint,
 231                                 enum pipe_video_cap param)
 232 {
 233         switch (param) {
 234         case PIPE_VIDEO_CAP_SUPPORTED:
 235                 return vl_profile_supported(screen, profile, entrypoint);
 236         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 237                 return 1;
 238         case PIPE_VIDEO_CAP_MAX_WIDTH:
 239         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 240                 return vl_video_buffer_max_size(screen);
 241         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 242                 return PIPE_FORMAT_NV12;
 243         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 244                 return false;
 245         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 246                 return false;
 247         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 248                 return true;
 249         case PIPE_VIDEO_CAP_MAX_LEVEL:
 250                 return vl_level_supported(screen, profile);
 251         default:
 252                 return 0;
 253         }
 254 }
 255
 256 const char *r600_get_llvm_processor_name(enum radeon_family family)
 257 {
 258         switch (family) {
 259         case CHIP_R600:
 260         case CHIP_RV630:
 261         case CHIP_RV635:
 262         case CHIP_RV670:
 263                 return "r600";
 264         case CHIP_RV610:
 265         case CHIP_RV620:
 266         case CHIP_RS780:
 267         case CHIP_RS880:
 268                 return "rs880";
 269         case CHIP_RV710:
 270                 return "rv710";
 271         case CHIP_RV730:
 272                 return "rv730";
 273         case CHIP_RV740:
 274         case CHIP_RV770:
 275                 return "rv770";
 276         case CHIP_PALM:
 277         case CHIP_CEDAR:
 278                 return "cedar";
 279         case CHIP_SUMO:
 280         case CHIP_SUMO2:
 281                 return "sumo";
 282         case CHIP_REDWOOD:
 283                 return "redwood";
 284         case CHIP_JUNIPER:
 285                 return "juniper";
 286         case CHIP_HEMLOCK:
 287         case CHIP_CYPRESS:
 288                 return "cypress";
 289         case CHIP_BARTS:
 290                 return "barts";
 291         case CHIP_TURKS:
 292                 return "turks";
 293         case CHIP_CAICOS:
 294                 return "caicos";
 295         case CHIP_CAYMAN:
 296         case CHIP_ARUBA:
 297                 return "cayman";
 298
 299         case CHIP_TAHITI: return "tahiti";
 300         case CHIP_PITCAIRN: return "pitcairn";
 301         case CHIP_VERDE: return "verde";
 302         case CHIP_OLAND: return "oland";
 303 #if HAVE_LLVM <= 0x0303
 304         default:
 305                 fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
 306                         __func__, family);
 307                 return "SI";
 308 #else
 309         case CHIP_HAINAN: return "hainan";
 310         case CHIP_BONAIRE: return "bonaire";
 311         case CHIP_KABINI: return "kabini";
 312         case CHIP_KAVERI: return "kaveri";
 313         case CHIP_HAWAII: return "hawaii";
 314         default: return "";
 315 #endif
 316         }
 317 }
 318
 319 static int r600_get_compute_param(struct pipe_screen *screen,
 320         enum pipe_compute_cap param,
 321         void *ret)
 322 {
 323         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 324
 325         //TODO: select these params by asic
 326         switch (param) {
 327         case PIPE_COMPUTE_CAP_IR_TARGET: {
 328                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 329                 if (ret) {
 330                         sprintf(ret, "%s-r600--", gpu);
 331                 }
 332                 return (8 + strlen(gpu)) * sizeof(char);
 333         }
 334         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 335                 if (ret) {
 336                         uint64_t *grid_dimension = ret;
 337                         grid_dimension[0] = 3;
 338                 }
 339                 return 1 * sizeof(uint64_t);
 340
 341         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 342                 if (ret) {
 343                         uint64_t *grid_size = ret;
 344                         grid_size[0] = 65535;
 345                         grid_size[1] = 65535;
 346                         grid_size[2] = 1;
 347                 }
 348                 return 3 * sizeof(uint64_t) ;
 349
 350         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 351                 if (ret) {
 352                         uint64_t *block_size = ret;
 353                         block_size[0] = 256;
 354                         block_size[1] = 256;
 355                         block_size[2] = 256;
 356                 }
 357                 return 3 * sizeof(uint64_t);
 358
 359         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 360                 if (ret) {
 361                         uint64_t *max_threads_per_block = ret;
 362                         *max_threads_per_block = 256;
 363                 }
 364                 return sizeof(uint64_t);
 365
 366         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 367                 if (ret) {
 368                         uint64_t *max_global_size = ret;
 369                         /* XXX: This is what the proprietary driver reports, we
 370                          * may want to use a different value. */
 371                         /* XXX: Not sure what to put here for SI. */
 372                         if (rscreen->chip_class >= SI)
 373                                 *max_global_size = 2000000000;
 374                         else
 375                                 *max_global_size = 201326592;
 376                 }
 377                 return sizeof(uint64_t);
 378
 379         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 380                 if (ret) {
 381                         uint64_t *max_local_size = ret;
 382                         /* Value reported by the closed source driver. */
 383                         *max_local_size = 32768;
 384                 }
 385                 return sizeof(uint64_t);
 386
 387         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 388                 if (ret) {
 389                         uint64_t *max_input_size = ret;
 390                         /* Value reported by the closed source driver. */
 391                         *max_input_size = 1024;
 392                 }
 393                 return sizeof(uint64_t);
 394
 395         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 396                 if (ret) {
 397                         uint64_t max_global_size;
 398                         uint64_t *max_mem_alloc_size = ret;
 399                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 400                         /* OpenCL requres this value be at least
 401                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 402                          * I'm really not sure what value to report here, but
 403                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 404                          */
 405                         *max_mem_alloc_size = max_global_size / 4;
 406                 }
 407                 return sizeof(uint64_t);
 408
 409         default:
 410                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 411                 return 0;
 412         }
 413 }
 414
 415 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 416 {
 417         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 418
 419         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 420                         rscreen->info.r600_clock_crystal_freq;
 421 }
 422
 423 static int r600_get_driver_query_info(struct pipe_screen *screen,
 424                                       unsigned index,
 425                                       struct pipe_driver_query_info *info)
 426 {
 427         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 428         struct pipe_driver_query_info list[] = {
 429                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 430                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 431                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 432                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
 433         };
 434
 435         if (!info)
 436                 return Elements(list);
 437
 438         if (index >= Elements(list))
 439                 return 0;
 440
 441         *info = list[index];
 442         return 1;
 443 }
 444
 445 static void r600_fence_reference(struct pipe_screen *screen,
 446                                  struct pipe_fence_handle **ptr,
 447                                  struct pipe_fence_handle *fence)
 448 {
 449         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 450
 451         rws->fence_reference(ptr, fence);
 452 }
 453
 454 static boolean r600_fence_signalled(struct pipe_screen *screen,
 455                                     struct pipe_fence_handle *fence)
 456 {
 457         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 458
 459         return rws->fence_wait(rws, fence, 0);
 460 }
 461
 462 static boolean r600_fence_finish(struct pipe_screen *screen,
 463                                  struct pipe_fence_handle *fence,
 464                                  uint64_t timeout)
 465 {
 466         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 467
 468         return rws->fence_wait(rws, fence, timeout);
 469 }
 470
 471 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 472                                   uint32_t tiling_config)
 473 {
 474         switch ((tiling_config & 0xe) >> 1) {
 475         case 0:
 476                 rscreen->tiling_info.num_channels = 1;
 477                 break;
 478         case 1:
 479                 rscreen->tiling_info.num_channels = 2;
 480                 break;
 481         case 2:
 482                 rscreen->tiling_info.num_channels = 4;
 483                 break;
 484         case 3:
 485                 rscreen->tiling_info.num_channels = 8;
 486                 break;
 487         default:
 488                 return false;
 489         }
 490
 491         switch ((tiling_config & 0x30) >> 4) {
 492         case 0:
 493                 rscreen->tiling_info.num_banks = 4;
 494                 break;
 495         case 1:
 496                 rscreen->tiling_info.num_banks = 8;
 497                 break;
 498         default:
 499                 return false;
 500
 501         }
 502         switch ((tiling_config & 0xc0) >> 6) {
 503         case 0:
 504                 rscreen->tiling_info.group_bytes = 256;
 505                 break;
 506         case 1:
 507                 rscreen->tiling_info.group_bytes = 512;
 508                 break;
 509         default:
 510                 return false;
 511         }
 512         return true;
 513 }
 514
 515 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 516                                        uint32_t tiling_config)
 517 {
 518         switch (tiling_config & 0xf) {
 519         case 0:
 520                 rscreen->tiling_info.num_channels = 1;
 521                 break;
 522         case 1:
 523                 rscreen->tiling_info.num_channels = 2;
 524                 break;
 525         case 2:
 526                 rscreen->tiling_info.num_channels = 4;
 527                 break;
 528         case 3:
 529                 rscreen->tiling_info.num_channels = 8;
 530                 break;
 531         default:
 532                 return false;
 533         }
 534
 535         switch ((tiling_config & 0xf0) >> 4) {
 536         case 0:
 537                 rscreen->tiling_info.num_banks = 4;
 538                 break;
 539         case 1:
 540                 rscreen->tiling_info.num_banks = 8;
 541                 break;
 542         case 2:
 543                 rscreen->tiling_info.num_banks = 16;
 544                 break;
 545         default:
 546                 return false;
 547         }
 548
 549         switch ((tiling_config & 0xf00) >> 8) {
 550         case 0:
 551                 rscreen->tiling_info.group_bytes = 256;
 552                 break;
 553         case 1:
 554                 rscreen->tiling_info.group_bytes = 512;
 555                 break;
 556         default:
 557                 return false;
 558         }
 559         return true;
 560 }
 561
 562 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 563 {
 564         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 565
 566         /* set default group bytes, overridden by tiling info ioctl */
 567         if (rscreen->chip_class <= R700) {
 568                 rscreen->tiling_info.group_bytes = 256;
 569         } else {
 570                 rscreen->tiling_info.group_bytes = 512;
 571         }
 572
 573         if (!tiling_config)
 574                 return true;
 575
 576         if (rscreen->chip_class <= R700) {
 577                 return r600_interpret_tiling(rscreen, tiling_config);
 578         } else {
 579                 return evergreen_interpret_tiling(rscreen, tiling_config);
 580         }
 581 }
 582
 583 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 584                                                   const struct pipe_resource *templ)
 585 {
 586         if (templ->target == PIPE_BUFFER) {
 587                 return r600_buffer_create(screen, templ, 4096);
 588         } else {
 589                 return r600_texture_create(screen, templ);
 590         }
 591 }
 592
 593 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 594                              struct radeon_winsys *ws)
 595 {
 596         ws->query_info(ws, &rscreen->info);
 597
 598         rscreen->b.get_name = r600_get_name;
 599         rscreen->b.get_vendor = r600_get_vendor;
 600         rscreen->b.get_compute_param = r600_get_compute_param;
 601         rscreen->b.get_paramf = r600_get_paramf;
 602         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 603         rscreen->b.get_timestamp = r600_get_timestamp;
 604         rscreen->b.fence_finish = r600_fence_finish;
 605         rscreen->b.fence_reference = r600_fence_reference;
 606         rscreen->b.fence_signalled = r600_fence_signalled;
 607         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 608
 609         if (rscreen->info.has_uvd) {
 610                 rscreen->b.get_video_param = rvid_get_video_param;
 611                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 612         } else {
 613                 rscreen->b.get_video_param = r600_get_video_param;
 614                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 615         }
 616
 617         r600_init_screen_texture_functions(rscreen);
 618
 619         rscreen->ws = ws;
 620         rscreen->family = rscreen->info.family;
 621         rscreen->chip_class = rscreen->info.chip_class;
 622         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 623
 624         if (!r600_init_tiling(rscreen)) {
 625                 return false;
 626         }
 627         util_format_s3tc_init();
 628         pipe_mutex_init(rscreen->aux_context_lock);
 629
 630         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 631                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 632                                                                                 PIPE_BIND_CUSTOM,
 633                                                                                 PIPE_USAGE_STAGING,
 634                                                                                 4096);
 635                 if (rscreen->trace_bo) {
 636                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 637                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 638                 }
 639         }
 640
 641         return true;
 642 }
 643
 644 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 645 {
 646         pipe_mutex_destroy(rscreen->aux_context_lock);
 647         rscreen->aux_context->destroy(rscreen->aux_context);
 648
 649         if (rscreen->trace_bo) {
 650                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 651                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 652         }
 653
 654         rscreen->ws->destroy(rscreen->ws);
 655         FREE(rscreen);
 656 }
 657
 658 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 659 {
 660         struct tgsi_parse_context parse;
 661
 662         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 663                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 664                 return ~0;
 665         }
 666         return parse.FullHeader.Processor.Processor;
 667 }
 668
 669 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 670                           const struct tgsi_token *tokens)
 671 {
 672         /* Compute shader don't have tgsi_tokens */
 673         if (!tokens)
 674                 return (rscreen->debug_flags & DBG_CS) != 0;
 675
 676         switch (tgsi_get_processor_type(tokens)) {
 677         case TGSI_PROCESSOR_VERTEX:
 678                 return (rscreen->debug_flags & DBG_VS) != 0;
 679         case TGSI_PROCESSOR_GEOMETRY:
 680                 return (rscreen->debug_flags & DBG_GS) != 0;
 681         case TGSI_PROCESSOR_FRAGMENT:
 682                 return (rscreen->debug_flags & DBG_PS) != 0;
 683         case TGSI_PROCESSOR_COMPUTE:
 684                 return (rscreen->debug_flags & DBG_CS) != 0;
 685         default:
 686                 return false;
 687         }
 688 }
 689
 690 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 691                               unsigned offset, unsigned size, unsigned value)
 692 {
 693         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 694
 695         pipe_mutex_lock(rscreen->aux_context_lock);
 696         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 697         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 698         pipe_mutex_unlock(rscreen->aux_context_lock);
 699 }