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r600g,radeonsi: Assert that there's enough space after flushing
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* Flush if there's not enough space. */
111 if ((num_dw + ctx->rings.dma.cs->cdw) > RADEON_MAX_CMDBUF_DWORDS) {
112 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
113 assert((num_dw + ctx->rings.dma.cs->cdw) <= RADEON_MAX_CMDBUF_DWORDS);
114 }
115 }
116
117 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 }
120
121 void r600_preflush_suspend_features(struct r600_common_context *ctx)
122 {
123 /* Disable render condition. */
124 ctx->saved_render_cond = NULL;
125 ctx->saved_render_cond_cond = FALSE;
126 ctx->saved_render_cond_mode = 0;
127 if (ctx->current_render_cond) {
128 ctx->saved_render_cond = ctx->current_render_cond;
129 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
130 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
131 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
132 }
133
134 /* suspend queries */
135 ctx->nontimer_queries_suspended = false;
136 if (ctx->num_cs_dw_nontimer_queries_suspend) {
137 r600_suspend_nontimer_queries(ctx);
138 ctx->nontimer_queries_suspended = true;
139 }
140
141 ctx->streamout.suspended = false;
142 if (ctx->streamout.begin_emitted) {
143 r600_emit_streamout_end(ctx);
144 ctx->streamout.suspended = true;
145 }
146 }
147
148 void r600_postflush_resume_features(struct r600_common_context *ctx)
149 {
150 if (ctx->streamout.suspended) {
151 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
152 r600_streamout_buffers_dirty(ctx);
153 }
154
155 /* resume queries */
156 if (ctx->nontimer_queries_suspended) {
157 r600_resume_nontimer_queries(ctx);
158 }
159
160 /* Re-enable render condition. */
161 if (ctx->saved_render_cond) {
162 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
163 ctx->saved_render_cond_cond,
164 ctx->saved_render_cond_mode);
165 }
166 }
167
168 static void r600_flush_from_st(struct pipe_context *ctx,
169 struct pipe_fence_handle **fence,
170 unsigned flags)
171 {
172 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
173 unsigned rflags = 0;
174
175 if (flags & PIPE_FLUSH_END_OF_FRAME)
176 rflags |= RADEON_FLUSH_END_OF_FRAME;
177
178 if (rctx->rings.dma.cs) {
179 rctx->rings.dma.flush(rctx, rflags, NULL);
180 }
181 rctx->rings.gfx.flush(rctx, rflags, fence);
182 }
183
184 static void r600_flush_dma_ring(void *ctx, unsigned flags,
185 struct pipe_fence_handle **fence)
186 {
187 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
188 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
189
190 if (!cs->cdw) {
191 return;
192 }
193
194 rctx->rings.dma.flushing = true;
195 rctx->ws->cs_flush(cs, flags, fence, 0);
196 rctx->rings.dma.flushing = false;
197 }
198
199 bool r600_common_context_init(struct r600_common_context *rctx,
200 struct r600_common_screen *rscreen)
201 {
202 util_slab_create(&rctx->pool_transfers,
203 sizeof(struct r600_transfer), 64,
204 UTIL_SLAB_SINGLETHREADED);
205
206 rctx->screen = rscreen;
207 rctx->ws = rscreen->ws;
208 rctx->family = rscreen->family;
209 rctx->chip_class = rscreen->chip_class;
210
211 if (rscreen->family == CHIP_HAWAII)
212 rctx->max_db = 16;
213 else if (rscreen->chip_class >= EVERGREEN)
214 rctx->max_db = 8;
215 else
216 rctx->max_db = 4;
217
218 rctx->b.transfer_map = u_transfer_map_vtbl;
219 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
220 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
221 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
222 rctx->b.memory_barrier = r600_memory_barrier;
223 rctx->b.flush = r600_flush_from_st;
224
225 LIST_INITHEAD(&rctx->texture_buffers);
226
227 r600_init_context_texture_functions(rctx);
228 r600_streamout_init(rctx);
229 r600_query_init(rctx);
230 cayman_init_msaa(&rctx->b);
231
232 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
233 0, PIPE_USAGE_DEFAULT, TRUE);
234 if (!rctx->allocator_so_filled_size)
235 return false;
236
237 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
238 PIPE_BIND_INDEX_BUFFER |
239 PIPE_BIND_CONSTANT_BUFFER);
240 if (!rctx->uploader)
241 return false;
242
243 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
244 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
245 r600_flush_dma_ring,
246 rctx, NULL);
247 rctx->rings.dma.flush = r600_flush_dma_ring;
248 }
249
250 return true;
251 }
252
253 void r600_common_context_cleanup(struct r600_common_context *rctx)
254 {
255 if (rctx->rings.gfx.cs) {
256 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
257 }
258 if (rctx->rings.dma.cs) {
259 rctx->ws->cs_destroy(rctx->rings.dma.cs);
260 }
261
262 if (rctx->uploader) {
263 u_upload_destroy(rctx->uploader);
264 }
265
266 util_slab_destroy(&rctx->pool_transfers);
267
268 if (rctx->allocator_so_filled_size) {
269 u_suballocator_destroy(rctx->allocator_so_filled_size);
270 }
271 }
272
273 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
274 {
275 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
276 struct r600_resource *rr = (struct r600_resource *)r;
277
278 if (r == NULL) {
279 return;
280 }
281
282 /*
283 * The idea is to compute a gross estimate of memory requirement of
284 * each draw call. After each draw call, memory will be precisely
285 * accounted. So the uncertainty is only on the current draw call.
286 * In practice this gave very good estimate (+/- 10% of the target
287 * memory limit).
288 */
289 if (rr->domains & RADEON_DOMAIN_GTT) {
290 rctx->gtt += rr->buf->size;
291 }
292 if (rr->domains & RADEON_DOMAIN_VRAM) {
293 rctx->vram += rr->buf->size;
294 }
295 }
296
297 /*
298 * pipe_screen
299 */
300
301 static const struct debug_named_value common_debug_options[] = {
302 /* logging */
303 { "tex", DBG_TEX, "Print texture info" },
304 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
305 { "compute", DBG_COMPUTE, "Print compute info" },
306 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
307 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
308 { "info", DBG_INFO, "Print driver information" },
309
310 /* shaders */
311 { "fs", DBG_FS, "Print fetch shaders" },
312 { "vs", DBG_VS, "Print vertex shaders" },
313 { "gs", DBG_GS, "Print geometry shaders" },
314 { "ps", DBG_PS, "Print pixel shaders" },
315 { "cs", DBG_CS, "Print compute shaders" },
316
317 /* features */
318 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
319 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
320 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
321 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
322 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
323 { "notiling", DBG_NO_TILING, "Disable tiling" },
324 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
325 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
326 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
327
328 DEBUG_NAMED_VALUE_END /* must be last */
329 };
330
331 static const char* r600_get_vendor(struct pipe_screen* pscreen)
332 {
333 return "X.Org";
334 }
335
336 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
337 {
338 return "AMD";
339 }
340
341 static const char* r600_get_name(struct pipe_screen* pscreen)
342 {
343 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
344
345 switch (rscreen->family) {
346 case CHIP_R600: return "AMD R600";
347 case CHIP_RV610: return "AMD RV610";
348 case CHIP_RV630: return "AMD RV630";
349 case CHIP_RV670: return "AMD RV670";
350 case CHIP_RV620: return "AMD RV620";
351 case CHIP_RV635: return "AMD RV635";
352 case CHIP_RS780: return "AMD RS780";
353 case CHIP_RS880: return "AMD RS880";
354 case CHIP_RV770: return "AMD RV770";
355 case CHIP_RV730: return "AMD RV730";
356 case CHIP_RV710: return "AMD RV710";
357 case CHIP_RV740: return "AMD RV740";
358 case CHIP_CEDAR: return "AMD CEDAR";
359 case CHIP_REDWOOD: return "AMD REDWOOD";
360 case CHIP_JUNIPER: return "AMD JUNIPER";
361 case CHIP_CYPRESS: return "AMD CYPRESS";
362 case CHIP_HEMLOCK: return "AMD HEMLOCK";
363 case CHIP_PALM: return "AMD PALM";
364 case CHIP_SUMO: return "AMD SUMO";
365 case CHIP_SUMO2: return "AMD SUMO2";
366 case CHIP_BARTS: return "AMD BARTS";
367 case CHIP_TURKS: return "AMD TURKS";
368 case CHIP_CAICOS: return "AMD CAICOS";
369 case CHIP_CAYMAN: return "AMD CAYMAN";
370 case CHIP_ARUBA: return "AMD ARUBA";
371 case CHIP_TAHITI: return "AMD TAHITI";
372 case CHIP_PITCAIRN: return "AMD PITCAIRN";
373 case CHIP_VERDE: return "AMD CAPE VERDE";
374 case CHIP_OLAND: return "AMD OLAND";
375 case CHIP_HAINAN: return "AMD HAINAN";
376 case CHIP_BONAIRE: return "AMD BONAIRE";
377 case CHIP_KAVERI: return "AMD KAVERI";
378 case CHIP_KABINI: return "AMD KABINI";
379 case CHIP_HAWAII: return "AMD HAWAII";
380 case CHIP_MULLINS: return "AMD MULLINS";
381 default: return "AMD unknown";
382 }
383 }
384
385 static float r600_get_paramf(struct pipe_screen* pscreen,
386 enum pipe_capf param)
387 {
388 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
389
390 switch (param) {
391 case PIPE_CAPF_MAX_LINE_WIDTH:
392 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
393 case PIPE_CAPF_MAX_POINT_WIDTH:
394 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
395 if (rscreen->family >= CHIP_CEDAR)
396 return 16384.0f;
397 else
398 return 8192.0f;
399 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
400 return 16.0f;
401 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
402 return 16.0f;
403 case PIPE_CAPF_GUARD_BAND_LEFT:
404 case PIPE_CAPF_GUARD_BAND_TOP:
405 case PIPE_CAPF_GUARD_BAND_RIGHT:
406 case PIPE_CAPF_GUARD_BAND_BOTTOM:
407 return 0.0f;
408 }
409 return 0.0f;
410 }
411
412 static int r600_get_video_param(struct pipe_screen *screen,
413 enum pipe_video_profile profile,
414 enum pipe_video_entrypoint entrypoint,
415 enum pipe_video_cap param)
416 {
417 switch (param) {
418 case PIPE_VIDEO_CAP_SUPPORTED:
419 return vl_profile_supported(screen, profile, entrypoint);
420 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
421 return 1;
422 case PIPE_VIDEO_CAP_MAX_WIDTH:
423 case PIPE_VIDEO_CAP_MAX_HEIGHT:
424 return vl_video_buffer_max_size(screen);
425 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
426 return PIPE_FORMAT_NV12;
427 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
428 return false;
429 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
430 return false;
431 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
432 return true;
433 case PIPE_VIDEO_CAP_MAX_LEVEL:
434 return vl_level_supported(screen, profile);
435 default:
436 return 0;
437 }
438 }
439
440 const char *r600_get_llvm_processor_name(enum radeon_family family)
441 {
442 switch (family) {
443 case CHIP_R600:
444 case CHIP_RV630:
445 case CHIP_RV635:
446 case CHIP_RV670:
447 return "r600";
448 case CHIP_RV610:
449 case CHIP_RV620:
450 case CHIP_RS780:
451 case CHIP_RS880:
452 return "rs880";
453 case CHIP_RV710:
454 return "rv710";
455 case CHIP_RV730:
456 return "rv730";
457 case CHIP_RV740:
458 case CHIP_RV770:
459 return "rv770";
460 case CHIP_PALM:
461 case CHIP_CEDAR:
462 return "cedar";
463 case CHIP_SUMO:
464 case CHIP_SUMO2:
465 return "sumo";
466 case CHIP_REDWOOD:
467 return "redwood";
468 case CHIP_JUNIPER:
469 return "juniper";
470 case CHIP_HEMLOCK:
471 case CHIP_CYPRESS:
472 return "cypress";
473 case CHIP_BARTS:
474 return "barts";
475 case CHIP_TURKS:
476 return "turks";
477 case CHIP_CAICOS:
478 return "caicos";
479 case CHIP_CAYMAN:
480 case CHIP_ARUBA:
481 return "cayman";
482
483 case CHIP_TAHITI: return "tahiti";
484 case CHIP_PITCAIRN: return "pitcairn";
485 case CHIP_VERDE: return "verde";
486 case CHIP_OLAND: return "oland";
487 case CHIP_HAINAN: return "hainan";
488 case CHIP_BONAIRE: return "bonaire";
489 case CHIP_KABINI: return "kabini";
490 case CHIP_KAVERI: return "kaveri";
491 case CHIP_HAWAII: return "hawaii";
492 case CHIP_MULLINS:
493 #if HAVE_LLVM >= 0x0305
494 return "mullins";
495 #else
496 return "kabini";
497 #endif
498 default: return "";
499 }
500 }
501
502 static int r600_get_compute_param(struct pipe_screen *screen,
503 enum pipe_compute_cap param,
504 void *ret)
505 {
506 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
507
508 //TODO: select these params by asic
509 switch (param) {
510 case PIPE_COMPUTE_CAP_IR_TARGET: {
511 const char *gpu;
512 const char *triple;
513 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
514 triple = "r600--";
515 } else {
516 triple = "amdgcn--";
517 }
518 switch(rscreen->family) {
519 /* Clang < 3.6 is missing Hainan in its list of
520 * GPUs, so we need to use the name of a similar GPU.
521 */
522 #if HAVE_LLVM < 0x0306
523 case CHIP_HAINAN:
524 gpu = "oland";
525 break;
526 #endif
527 default:
528 gpu = r600_get_llvm_processor_name(rscreen->family);
529 break;
530 }
531 if (ret) {
532 sprintf(ret, "%s-%s", gpu, triple);
533 }
534 /* +2 for dash and terminating NIL byte */
535 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
536 }
537 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
538 if (ret) {
539 uint64_t *grid_dimension = ret;
540 grid_dimension[0] = 3;
541 }
542 return 1 * sizeof(uint64_t);
543
544 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
545 if (ret) {
546 uint64_t *grid_size = ret;
547 grid_size[0] = 65535;
548 grid_size[1] = 65535;
549 grid_size[2] = 1;
550 }
551 return 3 * sizeof(uint64_t) ;
552
553 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
554 if (ret) {
555 uint64_t *block_size = ret;
556 block_size[0] = 256;
557 block_size[1] = 256;
558 block_size[2] = 256;
559 }
560 return 3 * sizeof(uint64_t);
561
562 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
563 if (ret) {
564 uint64_t *max_threads_per_block = ret;
565 *max_threads_per_block = 256;
566 }
567 return sizeof(uint64_t);
568
569 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
570 if (ret) {
571 uint64_t *max_global_size = ret;
572 uint64_t max_mem_alloc_size;
573
574 r600_get_compute_param(screen,
575 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
576 &max_mem_alloc_size);
577
578 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
579 * 1/4 of the MAX_GLOBAL_SIZE. Since the
580 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
581 * make sure we never report more than
582 * 4 * MAX_MEM_ALLOC_SIZE.
583 */
584 *max_global_size = MIN2(4 * max_mem_alloc_size,
585 rscreen->info.gart_size +
586 rscreen->info.vram_size);
587 }
588 return sizeof(uint64_t);
589
590 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
591 if (ret) {
592 uint64_t *max_local_size = ret;
593 /* Value reported by the closed source driver. */
594 *max_local_size = 32768;
595 }
596 return sizeof(uint64_t);
597
598 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
599 if (ret) {
600 uint64_t *max_input_size = ret;
601 /* Value reported by the closed source driver. */
602 *max_input_size = 1024;
603 }
604 return sizeof(uint64_t);
605
606 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
607 if (ret) {
608 uint64_t *max_mem_alloc_size = ret;
609
610 /* XXX: The limit in older kernels is 256 MB. We
611 * should add a query here for newer kernels.
612 */
613 *max_mem_alloc_size = 256 * 1024 * 1024;
614 }
615 return sizeof(uint64_t);
616
617 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
618 if (ret) {
619 uint32_t *max_clock_frequency = ret;
620 *max_clock_frequency = rscreen->info.max_sclk;
621 }
622 return sizeof(uint32_t);
623
624 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
625 if (ret) {
626 uint32_t *max_compute_units = ret;
627 *max_compute_units = rscreen->info.max_compute_units;
628 }
629 return sizeof(uint32_t);
630
631 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
632 if (ret) {
633 uint32_t *images_supported = ret;
634 *images_supported = 0;
635 }
636 return sizeof(uint32_t);
637 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
638 break; /* unused */
639 }
640
641 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
642 return 0;
643 }
644
645 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
646 {
647 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
648
649 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
650 rscreen->info.r600_clock_crystal_freq;
651 }
652
653 static int r600_get_driver_query_info(struct pipe_screen *screen,
654 unsigned index,
655 struct pipe_driver_query_info *info)
656 {
657 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
658 struct pipe_driver_query_info list[] = {
659 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
660 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
661 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
662 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}},
663 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
664 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES},
665 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
666 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
667 {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}},
668 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}},
669 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}},
670 {"GPU-load", R600_QUERY_GPU_LOAD, {100}}
671 };
672 unsigned num_queries;
673
674 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
675 num_queries = Elements(list);
676 else
677 num_queries = 8;
678
679 if (!info)
680 return num_queries;
681
682 if (index >= num_queries)
683 return 0;
684
685 *info = list[index];
686 return 1;
687 }
688
689 static void r600_fence_reference(struct pipe_screen *screen,
690 struct pipe_fence_handle **ptr,
691 struct pipe_fence_handle *fence)
692 {
693 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
694
695 rws->fence_reference(ptr, fence);
696 }
697
698 static boolean r600_fence_signalled(struct pipe_screen *screen,
699 struct pipe_fence_handle *fence)
700 {
701 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
702
703 return rws->fence_wait(rws, fence, 0);
704 }
705
706 static boolean r600_fence_finish(struct pipe_screen *screen,
707 struct pipe_fence_handle *fence,
708 uint64_t timeout)
709 {
710 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
711
712 return rws->fence_wait(rws, fence, timeout);
713 }
714
715 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
716 uint32_t tiling_config)
717 {
718 switch ((tiling_config & 0xe) >> 1) {
719 case 0:
720 rscreen->tiling_info.num_channels = 1;
721 break;
722 case 1:
723 rscreen->tiling_info.num_channels = 2;
724 break;
725 case 2:
726 rscreen->tiling_info.num_channels = 4;
727 break;
728 case 3:
729 rscreen->tiling_info.num_channels = 8;
730 break;
731 default:
732 return false;
733 }
734
735 switch ((tiling_config & 0x30) >> 4) {
736 case 0:
737 rscreen->tiling_info.num_banks = 4;
738 break;
739 case 1:
740 rscreen->tiling_info.num_banks = 8;
741 break;
742 default:
743 return false;
744
745 }
746 switch ((tiling_config & 0xc0) >> 6) {
747 case 0:
748 rscreen->tiling_info.group_bytes = 256;
749 break;
750 case 1:
751 rscreen->tiling_info.group_bytes = 512;
752 break;
753 default:
754 return false;
755 }
756 return true;
757 }
758
759 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
760 uint32_t tiling_config)
761 {
762 switch (tiling_config & 0xf) {
763 case 0:
764 rscreen->tiling_info.num_channels = 1;
765 break;
766 case 1:
767 rscreen->tiling_info.num_channels = 2;
768 break;
769 case 2:
770 rscreen->tiling_info.num_channels = 4;
771 break;
772 case 3:
773 rscreen->tiling_info.num_channels = 8;
774 break;
775 default:
776 return false;
777 }
778
779 switch ((tiling_config & 0xf0) >> 4) {
780 case 0:
781 rscreen->tiling_info.num_banks = 4;
782 break;
783 case 1:
784 rscreen->tiling_info.num_banks = 8;
785 break;
786 case 2:
787 rscreen->tiling_info.num_banks = 16;
788 break;
789 default:
790 return false;
791 }
792
793 switch ((tiling_config & 0xf00) >> 8) {
794 case 0:
795 rscreen->tiling_info.group_bytes = 256;
796 break;
797 case 1:
798 rscreen->tiling_info.group_bytes = 512;
799 break;
800 default:
801 return false;
802 }
803 return true;
804 }
805
806 static bool r600_init_tiling(struct r600_common_screen *rscreen)
807 {
808 uint32_t tiling_config = rscreen->info.r600_tiling_config;
809
810 /* set default group bytes, overridden by tiling info ioctl */
811 if (rscreen->chip_class <= R700) {
812 rscreen->tiling_info.group_bytes = 256;
813 } else {
814 rscreen->tiling_info.group_bytes = 512;
815 }
816
817 if (!tiling_config)
818 return true;
819
820 if (rscreen->chip_class <= R700) {
821 return r600_interpret_tiling(rscreen, tiling_config);
822 } else {
823 return evergreen_interpret_tiling(rscreen, tiling_config);
824 }
825 }
826
827 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
828 const struct pipe_resource *templ)
829 {
830 if (templ->target == PIPE_BUFFER) {
831 return r600_buffer_create(screen, templ, 4096);
832 } else {
833 return r600_texture_create(screen, templ);
834 }
835 }
836
837 bool r600_common_screen_init(struct r600_common_screen *rscreen,
838 struct radeon_winsys *ws)
839 {
840 ws->query_info(ws, &rscreen->info);
841
842 rscreen->b.get_name = r600_get_name;
843 rscreen->b.get_vendor = r600_get_vendor;
844 rscreen->b.get_device_vendor = r600_get_device_vendor;
845 rscreen->b.get_compute_param = r600_get_compute_param;
846 rscreen->b.get_paramf = r600_get_paramf;
847 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
848 rscreen->b.get_timestamp = r600_get_timestamp;
849 rscreen->b.fence_finish = r600_fence_finish;
850 rscreen->b.fence_reference = r600_fence_reference;
851 rscreen->b.fence_signalled = r600_fence_signalled;
852 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
853 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
854
855 if (rscreen->info.has_uvd) {
856 rscreen->b.get_video_param = rvid_get_video_param;
857 rscreen->b.is_video_format_supported = rvid_is_format_supported;
858 } else {
859 rscreen->b.get_video_param = r600_get_video_param;
860 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
861 }
862
863 r600_init_screen_texture_functions(rscreen);
864
865 rscreen->ws = ws;
866 rscreen->family = rscreen->info.family;
867 rscreen->chip_class = rscreen->info.chip_class;
868 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
869
870 if (!r600_init_tiling(rscreen)) {
871 return false;
872 }
873 util_format_s3tc_init();
874 pipe_mutex_init(rscreen->aux_context_lock);
875 pipe_mutex_init(rscreen->gpu_load_mutex);
876
877 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
878 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
879 PIPE_BIND_CUSTOM,
880 PIPE_USAGE_STAGING,
881 4096);
882 if (rscreen->trace_bo) {
883 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
884 PIPE_TRANSFER_UNSYNCHRONIZED);
885 }
886 }
887
888 if (rscreen->debug_flags & DBG_INFO) {
889 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
890 printf("family = %i\n", rscreen->info.family);
891 printf("chip_class = %i\n", rscreen->info.chip_class);
892 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
893 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
894 printf("max_sclk = %i\n", rscreen->info.max_sclk);
895 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
896 printf("max_se = %i\n", rscreen->info.max_se);
897 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
898 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
899 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
900 printf("has_uvd = %i\n", rscreen->info.has_uvd);
901 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
902 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
903 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
904 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
905 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
906 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
907 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
908 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
909 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
910 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
911 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
912 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
913 }
914 return true;
915 }
916
917 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
918 {
919 r600_gpu_load_kill_thread(rscreen);
920
921 pipe_mutex_destroy(rscreen->gpu_load_mutex);
922 pipe_mutex_destroy(rscreen->aux_context_lock);
923 rscreen->aux_context->destroy(rscreen->aux_context);
924
925 if (rscreen->trace_bo) {
926 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
927 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
928 }
929
930 rscreen->ws->destroy(rscreen->ws);
931 FREE(rscreen);
932 }
933
934 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
935 const struct tgsi_token *tokens)
936 {
937 /* Compute shader don't have tgsi_tokens */
938 if (!tokens)
939 return (rscreen->debug_flags & DBG_CS) != 0;
940
941 switch (tgsi_get_processor_type(tokens)) {
942 case TGSI_PROCESSOR_VERTEX:
943 return (rscreen->debug_flags & DBG_VS) != 0;
944 case TGSI_PROCESSOR_GEOMETRY:
945 return (rscreen->debug_flags & DBG_GS) != 0;
946 case TGSI_PROCESSOR_FRAGMENT:
947 return (rscreen->debug_flags & DBG_PS) != 0;
948 case TGSI_PROCESSOR_COMPUTE:
949 return (rscreen->debug_flags & DBG_CS) != 0;
950 default:
951 return false;
952 }
953 }
954
955 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
956 unsigned offset, unsigned size, unsigned value,
957 bool is_framebuffer)
958 {
959 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
960
961 pipe_mutex_lock(rscreen->aux_context_lock);
962 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
963 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
964 pipe_mutex_unlock(rscreen->aux_context_lock);
965 }