src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
  43 {
  44         /* The number of dwords we already used in the DMA so far. */
  45         num_dw += ctx->rings.dma.cs->cdw;
  46         /* Flush if there's not enough space. */
  47         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
  48                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  49         }
  50 }
  51
  52 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
  53 {
  54 }
  55
  56 void r600_preflush_suspend_features(struct r600_common_context *ctx)
  57 {
  58         /* Disable render condition. */
  59         ctx->saved_render_cond = NULL;
  60         ctx->saved_render_cond_cond = FALSE;
  61         ctx->saved_render_cond_mode = 0;
  62         if (ctx->current_render_cond) {
  63                 ctx->saved_render_cond = ctx->current_render_cond;
  64                 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
  65                 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
  66                 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
  67         }
  68
  69         /* suspend queries */
  70         ctx->nontimer_queries_suspended = false;
  71         if (ctx->num_cs_dw_nontimer_queries_suspend) {
  72                 r600_suspend_nontimer_queries(ctx);
  73                 ctx->nontimer_queries_suspended = true;
  74         }
  75
  76         ctx->streamout.suspended = false;
  77         if (ctx->streamout.begin_emitted) {
  78                 r600_emit_streamout_end(ctx);
  79                 ctx->streamout.suspended = true;
  80         }
  81 }
  82
  83 void r600_postflush_resume_features(struct r600_common_context *ctx)
  84 {
  85         if (ctx->streamout.suspended) {
  86                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
  87                 r600_streamout_buffers_dirty(ctx);
  88         }
  89
  90         /* resume queries */
  91         if (ctx->nontimer_queries_suspended) {
  92                 r600_resume_nontimer_queries(ctx);
  93         }
  94
  95         /* Re-enable render condition. */
  96         if (ctx->saved_render_cond) {
  97                 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
  98                                           ctx->saved_render_cond_cond,
  99                                           ctx->saved_render_cond_mode);
 100         }
 101 }
 102
 103 static void r600_flush_from_st(struct pipe_context *ctx,
 104                                struct pipe_fence_handle **fence,
 105                                unsigned flags)
 106 {
 107         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 108         unsigned rflags = 0;
 109
 110         if (flags & PIPE_FLUSH_END_OF_FRAME)
 111                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 112
 113         if (rctx->rings.dma.cs) {
 114                 rctx->rings.dma.flush(rctx, rflags, NULL);
 115         }
 116         rctx->rings.gfx.flush(rctx, rflags, fence);
 117 }
 118
 119 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 120                                 struct pipe_fence_handle **fence)
 121 {
 122         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 123         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 124
 125         if (!cs->cdw) {
 126                 return;
 127         }
 128
 129         rctx->rings.dma.flushing = true;
 130         rctx->ws->cs_flush(cs, flags, fence, 0);
 131         rctx->rings.dma.flushing = false;
 132 }
 133
 134 bool r600_common_context_init(struct r600_common_context *rctx,
 135                               struct r600_common_screen *rscreen)
 136 {
 137         util_slab_create(&rctx->pool_transfers,
 138                          sizeof(struct r600_transfer), 64,
 139                          UTIL_SLAB_SINGLETHREADED);
 140
 141         rctx->screen = rscreen;
 142         rctx->ws = rscreen->ws;
 143         rctx->family = rscreen->family;
 144         rctx->chip_class = rscreen->chip_class;
 145         rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
 146
 147         rctx->b.transfer_map = u_transfer_map_vtbl;
 148         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
 149         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 150         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 151         rctx->b.memory_barrier = r600_memory_barrier;
 152         rctx->b.flush = r600_flush_from_st;
 153
 154         r600_init_context_texture_functions(rctx);
 155         r600_streamout_init(rctx);
 156         r600_query_init(rctx);
 157         cayman_init_msaa(&rctx->b);
 158
 159         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 160                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 161         if (!rctx->allocator_so_filled_size)
 162                 return false;
 163
 164         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 165                                         PIPE_BIND_INDEX_BUFFER |
 166                                         PIPE_BIND_CONSTANT_BUFFER);
 167         if (!rctx->uploader)
 168                 return false;
 169
 170         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 171                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
 172                                                          r600_flush_dma_ring,
 173                                                          rctx, NULL);
 174                 rctx->rings.dma.flush = r600_flush_dma_ring;
 175         }
 176
 177         return true;
 178 }
 179
 180 void r600_common_context_cleanup(struct r600_common_context *rctx)
 181 {
 182         if (rctx->rings.gfx.cs) {
 183                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 184         }
 185         if (rctx->rings.dma.cs) {
 186                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 187         }
 188
 189         if (rctx->uploader) {
 190                 u_upload_destroy(rctx->uploader);
 191         }
 192
 193         util_slab_destroy(&rctx->pool_transfers);
 194
 195         if (rctx->allocator_so_filled_size) {
 196                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 197         }
 198 }
 199
 200 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 201 {
 202         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 203         struct r600_resource *rr = (struct r600_resource *)r;
 204
 205         if (r == NULL) {
 206                 return;
 207         }
 208
 209         /*
 210          * The idea is to compute a gross estimate of memory requirement of
 211          * each draw call. After each draw call, memory will be precisely
 212          * accounted. So the uncertainty is only on the current draw call.
 213          * In practice this gave very good estimate (+/- 10% of the target
 214          * memory limit).
 215          */
 216         if (rr->domains & RADEON_DOMAIN_GTT) {
 217                 rctx->gtt += rr->buf->size;
 218         }
 219         if (rr->domains & RADEON_DOMAIN_VRAM) {
 220                 rctx->vram += rr->buf->size;
 221         }
 222 }
 223
 224 /*
 225  * pipe_screen
 226  */
 227
 228 static const struct debug_named_value common_debug_options[] = {
 229         /* logging */
 230         { "tex", DBG_TEX, "Print texture info" },
 231         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 232         { "compute", DBG_COMPUTE, "Print compute info" },
 233         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 234         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 235
 236         /* features */
 237         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 238
 239         /* shaders */
 240         { "fs", DBG_FS, "Print fetch shaders" },
 241         { "vs", DBG_VS, "Print vertex shaders" },
 242         { "gs", DBG_GS, "Print geometry shaders" },
 243         { "ps", DBG_PS, "Print pixel shaders" },
 244         { "cs", DBG_CS, "Print compute shaders" },
 245
 246         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 247         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 248         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 249
 250         DEBUG_NAMED_VALUE_END /* must be last */
 251 };
 252
 253 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 254 {
 255         return "X.Org";
 256 }
 257
 258 static const char* r600_get_name(struct pipe_screen* pscreen)
 259 {
 260         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 261
 262         switch (rscreen->family) {
 263         case CHIP_R600: return "AMD R600";
 264         case CHIP_RV610: return "AMD RV610";
 265         case CHIP_RV630: return "AMD RV630";
 266         case CHIP_RV670: return "AMD RV670";
 267         case CHIP_RV620: return "AMD RV620";
 268         case CHIP_RV635: return "AMD RV635";
 269         case CHIP_RS780: return "AMD RS780";
 270         case CHIP_RS880: return "AMD RS880";
 271         case CHIP_RV770: return "AMD RV770";
 272         case CHIP_RV730: return "AMD RV730";
 273         case CHIP_RV710: return "AMD RV710";
 274         case CHIP_RV740: return "AMD RV740";
 275         case CHIP_CEDAR: return "AMD CEDAR";
 276         case CHIP_REDWOOD: return "AMD REDWOOD";
 277         case CHIP_JUNIPER: return "AMD JUNIPER";
 278         case CHIP_CYPRESS: return "AMD CYPRESS";
 279         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 280         case CHIP_PALM: return "AMD PALM";
 281         case CHIP_SUMO: return "AMD SUMO";
 282         case CHIP_SUMO2: return "AMD SUMO2";
 283         case CHIP_BARTS: return "AMD BARTS";
 284         case CHIP_TURKS: return "AMD TURKS";
 285         case CHIP_CAICOS: return "AMD CAICOS";
 286         case CHIP_CAYMAN: return "AMD CAYMAN";
 287         case CHIP_ARUBA: return "AMD ARUBA";
 288         case CHIP_TAHITI: return "AMD TAHITI";
 289         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 290         case CHIP_VERDE: return "AMD CAPE VERDE";
 291         case CHIP_OLAND: return "AMD OLAND";
 292         case CHIP_HAINAN: return "AMD HAINAN";
 293         case CHIP_BONAIRE: return "AMD BONAIRE";
 294         case CHIP_KAVERI: return "AMD KAVERI";
 295         case CHIP_KABINI: return "AMD KABINI";
 296         case CHIP_HAWAII: return "AMD HAWAII";
 297         case CHIP_MULLINS: return "AMD MULLINS";
 298         default: return "AMD unknown";
 299         }
 300 }
 301
 302 static float r600_get_paramf(struct pipe_screen* pscreen,
 303                              enum pipe_capf param)
 304 {
 305         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 306
 307         switch (param) {
 308         case PIPE_CAPF_MAX_LINE_WIDTH:
 309         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 310         case PIPE_CAPF_MAX_POINT_WIDTH:
 311         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 312                 if (rscreen->family >= CHIP_CEDAR)
 313                         return 16384.0f;
 314                 else
 315                         return 8192.0f;
 316         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 317                 return 16.0f;
 318         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 319                 return 16.0f;
 320         case PIPE_CAPF_GUARD_BAND_LEFT:
 321         case PIPE_CAPF_GUARD_BAND_TOP:
 322         case PIPE_CAPF_GUARD_BAND_RIGHT:
 323         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 324                 return 0.0f;
 325         }
 326         return 0.0f;
 327 }
 328
 329 static int r600_get_video_param(struct pipe_screen *screen,
 330                                 enum pipe_video_profile profile,
 331                                 enum pipe_video_entrypoint entrypoint,
 332                                 enum pipe_video_cap param)
 333 {
 334         switch (param) {
 335         case PIPE_VIDEO_CAP_SUPPORTED:
 336                 return vl_profile_supported(screen, profile, entrypoint);
 337         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 338                 return 1;
 339         case PIPE_VIDEO_CAP_MAX_WIDTH:
 340         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 341                 return vl_video_buffer_max_size(screen);
 342         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 343                 return PIPE_FORMAT_NV12;
 344         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 345                 return false;
 346         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 347                 return false;
 348         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 349                 return true;
 350         case PIPE_VIDEO_CAP_MAX_LEVEL:
 351                 return vl_level_supported(screen, profile);
 352         default:
 353                 return 0;
 354         }
 355 }
 356
 357 const char *r600_get_llvm_processor_name(enum radeon_family family)
 358 {
 359         switch (family) {
 360         case CHIP_R600:
 361         case CHIP_RV630:
 362         case CHIP_RV635:
 363         case CHIP_RV670:
 364                 return "r600";
 365         case CHIP_RV610:
 366         case CHIP_RV620:
 367         case CHIP_RS780:
 368         case CHIP_RS880:
 369                 return "rs880";
 370         case CHIP_RV710:
 371                 return "rv710";
 372         case CHIP_RV730:
 373                 return "rv730";
 374         case CHIP_RV740:
 375         case CHIP_RV770:
 376                 return "rv770";
 377         case CHIP_PALM:
 378         case CHIP_CEDAR:
 379                 return "cedar";
 380         case CHIP_SUMO:
 381         case CHIP_SUMO2:
 382                 return "sumo";
 383         case CHIP_REDWOOD:
 384                 return "redwood";
 385         case CHIP_JUNIPER:
 386                 return "juniper";
 387         case CHIP_HEMLOCK:
 388         case CHIP_CYPRESS:
 389                 return "cypress";
 390         case CHIP_BARTS:
 391                 return "barts";
 392         case CHIP_TURKS:
 393                 return "turks";
 394         case CHIP_CAICOS:
 395                 return "caicos";
 396         case CHIP_CAYMAN:
 397         case CHIP_ARUBA:
 398                 return "cayman";
 399
 400         case CHIP_TAHITI: return "tahiti";
 401         case CHIP_PITCAIRN: return "pitcairn";
 402         case CHIP_VERDE: return "verde";
 403         case CHIP_OLAND: return "oland";
 404 #if HAVE_LLVM <= 0x0303
 405         default:
 406                 fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
 407                         __func__, family);
 408                 return "SI";
 409 #else
 410         case CHIP_HAINAN: return "hainan";
 411         case CHIP_BONAIRE: return "bonaire";
 412         case CHIP_KABINI: return "kabini";
 413         case CHIP_KAVERI: return "kaveri";
 414         case CHIP_HAWAII: return "hawaii";
 415         case CHIP_MULLINS:
 416 #if HAVE_LLVM >= 0x0305
 417                 return "mullins";
 418 #else
 419                 return "kabini";
 420 #endif
 421         default: return "";
 422 #endif
 423         }
 424 }
 425
 426 static int r600_get_compute_param(struct pipe_screen *screen,
 427         enum pipe_compute_cap param,
 428         void *ret)
 429 {
 430         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 431
 432         //TODO: select these params by asic
 433         switch (param) {
 434         case PIPE_COMPUTE_CAP_IR_TARGET: {
 435                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 436                 if (ret) {
 437                         sprintf(ret, "%s-r600--", gpu);
 438                 }
 439                 return (8 + strlen(gpu)) * sizeof(char);
 440         }
 441         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 442                 if (ret) {
 443                         uint64_t *grid_dimension = ret;
 444                         grid_dimension[0] = 3;
 445                 }
 446                 return 1 * sizeof(uint64_t);
 447
 448         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 449                 if (ret) {
 450                         uint64_t *grid_size = ret;
 451                         grid_size[0] = 65535;
 452                         grid_size[1] = 65535;
 453                         grid_size[2] = 1;
 454                 }
 455                 return 3 * sizeof(uint64_t) ;
 456
 457         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 458                 if (ret) {
 459                         uint64_t *block_size = ret;
 460                         block_size[0] = 256;
 461                         block_size[1] = 256;
 462                         block_size[2] = 256;
 463                 }
 464                 return 3 * sizeof(uint64_t);
 465
 466         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 467                 if (ret) {
 468                         uint64_t *max_threads_per_block = ret;
 469                         *max_threads_per_block = 256;
 470                 }
 471                 return sizeof(uint64_t);
 472
 473         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 474                 if (ret) {
 475                         uint64_t *max_global_size = ret;
 476                         /* XXX: This is what the proprietary driver reports, we
 477                          * may want to use a different value. */
 478                         /* XXX: Not sure what to put here for SI. */
 479                         if (rscreen->chip_class >= SI)
 480                                 *max_global_size = 2000000000;
 481                         else
 482                                 *max_global_size = 201326592;
 483                 }
 484                 return sizeof(uint64_t);
 485
 486         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 487                 if (ret) {
 488                         uint64_t *max_local_size = ret;
 489                         /* Value reported by the closed source driver. */
 490                         *max_local_size = 32768;
 491                 }
 492                 return sizeof(uint64_t);
 493
 494         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 495                 if (ret) {
 496                         uint64_t *max_input_size = ret;
 497                         /* Value reported by the closed source driver. */
 498                         *max_input_size = 1024;
 499                 }
 500                 return sizeof(uint64_t);
 501
 502         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 503                 if (ret) {
 504                         uint64_t max_global_size;
 505                         uint64_t *max_mem_alloc_size = ret;
 506                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 507                         /* OpenCL requres this value be at least
 508                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 509                          * I'm really not sure what value to report here, but
 510                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 511                          */
 512                         *max_mem_alloc_size = max_global_size / 4;
 513                 }
 514                 return sizeof(uint64_t);
 515
 516         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 517                 if (ret) {
 518                         uint32_t *max_clock_frequency = ret;
 519                         *max_clock_frequency = rscreen->info.max_sclk;
 520                 }
 521                 return sizeof(uint32_t);
 522
 523         default:
 524                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 525                 return 0;
 526         }
 527 }
 528
 529 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 530 {
 531         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 532
 533         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 534                         rscreen->info.r600_clock_crystal_freq;
 535 }
 536
 537 static int r600_get_driver_query_info(struct pipe_screen *screen,
 538                                       unsigned index,
 539                                       struct pipe_driver_query_info *info)
 540 {
 541         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 542         struct pipe_driver_query_info list[] = {
 543                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 544                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 545                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 546                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
 547                 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
 548                 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
 549                 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
 550                 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
 551         };
 552
 553         if (!info)
 554                 return Elements(list);
 555
 556         if (index >= Elements(list))
 557                 return 0;
 558
 559         *info = list[index];
 560         return 1;
 561 }
 562
 563 static void r600_fence_reference(struct pipe_screen *screen,
 564                                  struct pipe_fence_handle **ptr,
 565                                  struct pipe_fence_handle *fence)
 566 {
 567         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 568
 569         rws->fence_reference(ptr, fence);
 570 }
 571
 572 static boolean r600_fence_signalled(struct pipe_screen *screen,
 573                                     struct pipe_fence_handle *fence)
 574 {
 575         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 576
 577         return rws->fence_wait(rws, fence, 0);
 578 }
 579
 580 static boolean r600_fence_finish(struct pipe_screen *screen,
 581                                  struct pipe_fence_handle *fence,
 582                                  uint64_t timeout)
 583 {
 584         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 585
 586         return rws->fence_wait(rws, fence, timeout);
 587 }
 588
 589 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 590                                   uint32_t tiling_config)
 591 {
 592         switch ((tiling_config & 0xe) >> 1) {
 593         case 0:
 594                 rscreen->tiling_info.num_channels = 1;
 595                 break;
 596         case 1:
 597                 rscreen->tiling_info.num_channels = 2;
 598                 break;
 599         case 2:
 600                 rscreen->tiling_info.num_channels = 4;
 601                 break;
 602         case 3:
 603                 rscreen->tiling_info.num_channels = 8;
 604                 break;
 605         default:
 606                 return false;
 607         }
 608
 609         switch ((tiling_config & 0x30) >> 4) {
 610         case 0:
 611                 rscreen->tiling_info.num_banks = 4;
 612                 break;
 613         case 1:
 614                 rscreen->tiling_info.num_banks = 8;
 615                 break;
 616         default:
 617                 return false;
 618
 619         }
 620         switch ((tiling_config & 0xc0) >> 6) {
 621         case 0:
 622                 rscreen->tiling_info.group_bytes = 256;
 623                 break;
 624         case 1:
 625                 rscreen->tiling_info.group_bytes = 512;
 626                 break;
 627         default:
 628                 return false;
 629         }
 630         return true;
 631 }
 632
 633 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 634                                        uint32_t tiling_config)
 635 {
 636         switch (tiling_config & 0xf) {
 637         case 0:
 638                 rscreen->tiling_info.num_channels = 1;
 639                 break;
 640         case 1:
 641                 rscreen->tiling_info.num_channels = 2;
 642                 break;
 643         case 2:
 644                 rscreen->tiling_info.num_channels = 4;
 645                 break;
 646         case 3:
 647                 rscreen->tiling_info.num_channels = 8;
 648                 break;
 649         default:
 650                 return false;
 651         }
 652
 653         switch ((tiling_config & 0xf0) >> 4) {
 654         case 0:
 655                 rscreen->tiling_info.num_banks = 4;
 656                 break;
 657         case 1:
 658                 rscreen->tiling_info.num_banks = 8;
 659                 break;
 660         case 2:
 661                 rscreen->tiling_info.num_banks = 16;
 662                 break;
 663         default:
 664                 return false;
 665         }
 666
 667         switch ((tiling_config & 0xf00) >> 8) {
 668         case 0:
 669                 rscreen->tiling_info.group_bytes = 256;
 670                 break;
 671         case 1:
 672                 rscreen->tiling_info.group_bytes = 512;
 673                 break;
 674         default:
 675                 return false;
 676         }
 677         return true;
 678 }
 679
 680 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 681 {
 682         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 683
 684         /* set default group bytes, overridden by tiling info ioctl */
 685         if (rscreen->chip_class <= R700) {
 686                 rscreen->tiling_info.group_bytes = 256;
 687         } else {
 688                 rscreen->tiling_info.group_bytes = 512;
 689         }
 690
 691         if (!tiling_config)
 692                 return true;
 693
 694         if (rscreen->chip_class <= R700) {
 695                 return r600_interpret_tiling(rscreen, tiling_config);
 696         } else {
 697                 return evergreen_interpret_tiling(rscreen, tiling_config);
 698         }
 699 }
 700
 701 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 702                                                   const struct pipe_resource *templ)
 703 {
 704         if (templ->target == PIPE_BUFFER) {
 705                 return r600_buffer_create(screen, templ, 4096);
 706         } else {
 707                 return r600_texture_create(screen, templ);
 708         }
 709 }
 710
 711 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 712                              struct radeon_winsys *ws)
 713 {
 714         ws->query_info(ws, &rscreen->info);
 715
 716         rscreen->b.get_name = r600_get_name;
 717         rscreen->b.get_vendor = r600_get_vendor;
 718         rscreen->b.get_compute_param = r600_get_compute_param;
 719         rscreen->b.get_paramf = r600_get_paramf;
 720         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 721         rscreen->b.get_timestamp = r600_get_timestamp;
 722         rscreen->b.fence_finish = r600_fence_finish;
 723         rscreen->b.fence_reference = r600_fence_reference;
 724         rscreen->b.fence_signalled = r600_fence_signalled;
 725         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 726
 727         if (rscreen->info.has_uvd) {
 728                 rscreen->b.get_video_param = rvid_get_video_param;
 729                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 730         } else {
 731                 rscreen->b.get_video_param = r600_get_video_param;
 732                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 733         }
 734
 735         r600_init_screen_texture_functions(rscreen);
 736
 737         rscreen->ws = ws;
 738         rscreen->family = rscreen->info.family;
 739         rscreen->chip_class = rscreen->info.chip_class;
 740         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 741
 742         if (!r600_init_tiling(rscreen)) {
 743                 return false;
 744         }
 745         util_format_s3tc_init();
 746         pipe_mutex_init(rscreen->aux_context_lock);
 747
 748         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 749                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 750                                                                                 PIPE_BIND_CUSTOM,
 751                                                                                 PIPE_USAGE_STAGING,
 752                                                                                 4096);
 753                 if (rscreen->trace_bo) {
 754                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 755                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 756                 }
 757         }
 758
 759         return true;
 760 }
 761
 762 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 763 {
 764         pipe_mutex_destroy(rscreen->aux_context_lock);
 765         rscreen->aux_context->destroy(rscreen->aux_context);
 766
 767         if (rscreen->trace_bo) {
 768                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 769                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 770         }
 771
 772         rscreen->ws->destroy(rscreen->ws);
 773         FREE(rscreen);
 774 }
 775
 776 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 777 {
 778         struct tgsi_parse_context parse;
 779
 780         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 781                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 782                 return ~0;
 783         }
 784         return parse.FullHeader.Processor.Processor;
 785 }
 786
 787 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 788                           const struct tgsi_token *tokens)
 789 {
 790         /* Compute shader don't have tgsi_tokens */
 791         if (!tokens)
 792                 return (rscreen->debug_flags & DBG_CS) != 0;
 793
 794         switch (tgsi_get_processor_type(tokens)) {
 795         case TGSI_PROCESSOR_VERTEX:
 796                 return (rscreen->debug_flags & DBG_VS) != 0;
 797         case TGSI_PROCESSOR_GEOMETRY:
 798                 return (rscreen->debug_flags & DBG_GS) != 0;
 799         case TGSI_PROCESSOR_FRAGMENT:
 800                 return (rscreen->debug_flags & DBG_PS) != 0;
 801         case TGSI_PROCESSOR_COMPUTE:
 802                 return (rscreen->debug_flags & DBG_CS) != 0;
 803         default:
 804                 return false;
 805         }
 806 }
 807
 808 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 809                               unsigned offset, unsigned size, unsigned value)
 810 {
 811         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 812
 813         pipe_mutex_lock(rscreen->aux_context_lock);
 814         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 815         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 816         pipe_mutex_unlock(rscreen->aux_context_lock);
 817 }